W6811IRG - Winbond Electronics

Publication Release Date: September, 2005

- 1 - Revision A12

W6811

SINGLE-CHANNEL VOICEBAND CODEC

(5V Analog, 3V Digital)

Data Sheet

W6811

Publication Release Date: September, 2005

- 2 - Revision A12

1. GENERAL DESCRIPTION

The W6811 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law

companding. The device is compliant with the ITU G.712 specification. It operates off of separated

analog (5V) and digital (3V) power supplies and is available in 24-pin PDIP, SOG, SSOP, and TSSOP

package options. Functions performed include digitization and reconstruction of voice signals, and

band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712

specification. W6811 performance is specified over the industrial temperature range of –40°C to

+85°C.

The W6811 includes an on-chip precision voltage reference and an additional power amplifier,

capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is

fully differential, reducing noise and improving the power supply rejection ratio. The data transfer

protocol supports both long-frame and short-frame synchronous communications for PCM applications,

and IDL and GCI communications for ISDN applications. W6811 accepts seven master clock rates

between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the division

ratio for the required internal clock.

2. FEATURES

• Power supply:

 Analog 4.5 – 5.5V

 Digital 2.7 – 3.3V

• Typical power dissipation of 25 mW,

power-down mode of 0.5 W

• Fully-differential analog circuit design

• On-chip precision reference of 1.575 V for

a 0 dBm TLP at 600 Ω

• Push-pull power amplifiers with external

gain adjustment with 300 Ω load capability

• Seven master clock rates of 256 kHz to

4.096 MHz

• Pin-selectable -Law and A-Law

companding (compliant with ITU G.711)

• CODEC A/D and D/A filtering compliant

with ITU G.712

• Industrial temperature range (–40°C to

+85°C)

• Four packages: 24-pin PDIP, SOG, SSOP,

and TSSOP

• Pb-Free / RoHS package options available

APPLICATIONS

• Digital Telephone Systems

• Central Office Equipment (Gateways,

Switches, Routers)

• PBX Systems (Gateways, Switches)

• PABX/SOHO Systems

• Local Loop card

• SOHO Routers

• VoIP Terminals

• Enterprise Phones

• ISDN Terminals

• Analog line cards

• Digital Voice Recorders

W6811

Publication Release Date: September, 2005

- 3 - Revision A12

3. BLOCK DIAGRAM

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

& 4096 kHz

MCLK

256 kHz

8 kHz

512 kHz

Pre - scaler

DDA

SSA

Power Conditioning

Voltage reference V

PUI

G.712 CODEC

G.711

/A -Law

PAO+

PAO-

PAI

AI+

AI-

/A-Law

Tra

mit

Int

erf

ace

cei

Int

erf

ace

FST

BCLKT

PCMT

FSR

BCLKR

PCMR

REF

256 kHz,

512 kHz,

1536 kHz,

1544 kHz,

2048 kHz,

2560 kHz

& 4096 kHz

MCLK

256 kHz

8 kHz

Pre - Saler

Power Conditioning

Voltage reference V

G.712 CODEC

G.711

/A -Law

/A-Law

G.712 CODEC

G.711

/A -Law

/A-Law

Transmit

PCM

Interface

Receive

PCM

Interface

BCLKT

BCLKR

DDD

SSD

W6811

Publication Release Date: September, 2005

- 4 - Revision A12

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION ................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION............................................................................................................ 9

7.1. Transmit Path............................................................................................................................. 9

7.2. Receive Path............................................................................................................................ 10

7.3. Power Management................................................................................................................. 11

7.3.1. Analog Supply ................................................................................................................ 11

7.3.2. Digital Supply ................................................................................................................. 11

7.3.3. Analog Ground Reference Bypass................................................................................. 11

7.3.4. Analog Ground Reference Voltage Output .................................................................... 11

7.4. PCM Interface .......................................................................................................................... 11

7.4.1. Long Frame Sync ........................................................................................................... 12

7.4.2. Short Frame Sync .......................................................................................................... 12

7.4.3. GCI Interface .................................................................................................................. 12

7.4.4. IDL Interface................................................................................................................... 13

7.4.5. System Timing................................................................................................................ 13

8. TIMING DIAGRAMS.......................................................................................................................... 14

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21

9.1. Absolute Maximum Ratings .................................................................................................... 21

9.2. Operating Conditions .............................................................................................................. 21

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22

10.1. General Parameters............................................................................................................... 22

10.2. Analog Signal Level and Gain Parameters............................................................................ 23

10.3. Analog Distortion and Noise Parameters............................................................................... 24

10.4. Analog Input and Output Amplifier Parameters ..................................................................... 25

10.5. Digital I/O ............................................................................................................................... 27

10.5.1. µ-Law Encode Decode Characteristics........................................................................ 27

10.5.2. A-Law Encode Decode Characteristics........................................................................ 28

10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 29

10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 29

11. TYPICAL APPLICATION CIRCUIT .................................................................................................30

12. PACKAGE SPECIFICATION .......................................................................................................... 32

12.1. 24L TSSOP – 4.4X7.8mm .....................................................................................................32

12.2. 24L SOP – 300mil.................................................................................................................. 33

12.3. 24L SSOP – 209mil ............................................................................................................... 34

12.4. 24L PDIP – 300 mil ................................................................................................................ 35

13. ORDERING INFORMATION........................................................................................................... 36

14. VERSION HISTORY ....................................................................................................................... 37

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Publication Release Date: September, 2005

- 5 - Revision A12

5. PIN CONFIGURATION

PDIP/SOP/SSOP/TSSOP

VAG

AI+

AI-

/A-Law

VSSA

FST

PCMT

BCLKT

MCLK

VSSD

REF

PAI

PAO

PAO+

DDA

FSR

PCMI

BCLKR

PUI

DDD

VAG

AI+

AI-

VSSA

MCLK

VSSD

REF

PAI

PAO

PAO+

DDA

FSR

PCMR

BCLKR

PUI

DDD

AI+ 23

AI-22

AO 21

/A 20

SSA

FSX 16

PCMO 15

BCLKT 14

MCLK 13

1 VREF

2 RO-

3 PAI

4 PAO-

5 PAO+

6 VDDA

9 FSR

10 PCMI

11 BCLKR

12 PUI

SSD

178 VDDD

C 187 NC

187

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Publication Release Date: September, 2005

- 6 - Revision A12

6. PIN DESCRIPTION

Name

No.

VDD

*Functionality

VREF 1 A This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be

decoupled to VSSA through a 0.1 μF ceramic decoupling capacitor. No

external loads should be tied to this pin.

RO- 2 A Inverting output of the receive smoothing filter. This pin can typically drive a 2

kΩ load to 1.575 volt peak referenced to the analog ground level.

PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the VAG

voltage.

PAO- 4 A Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt

peak referenced to the VAG voltage level.

PAO+ 5 A Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575

Volt peak referenced to the VAG voltage level.

VDDA 6 A Analog power supply. This pin should be decoupled to VSSA with a 0.1μF

ceramic capacitor.

NC 7 Not Connected

VDDD 8 D

Digital power supply. This pin should be decoupled to VSSD with a 0.1μF

ceramic capacitor. For correct operation, VDDD value should always be lower

than VDDA.

FSR 9 D 8 kHz Frame Sync input for the PCM receive section. This pin also selects

channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to

the FST pin when transmit and receive are synchronous operations.

PCMR 10 D PCM input data receive pin. The data needs to be synchronous with the FSR

and BCLKR pins.

BCLKR 11 D PCM receive bit clock input pin. This pin also selects the interface mode. The

GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected

when this pin is tied to VDDD. This pin can also be tied to the BCLKT when

transmit and receive are synchronous operations.

PUI 12 D Power up input signal. When this pin is tied to VDDD, the part is powered up.

When tied to VSSD, the part is powered down.

MCLK 13 D System master clock input. Possible input frequencies are 256 kHz, 512 kHz,

1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better

performance, it is recommended to have the MCLK signal synchronous and

aligned to the FST signal. This is a requirement in the case of 256 and 512

kHz frequencies.

BCLKT 14 D PCM transmit bit clock input pin.

PCMT 15 D PCM output data transmit pin. The output data is synchronous with the FST

and BCLKT pins.

FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data

bytes.

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Name

No.

VDD

*Functionality

VSSD 17 D This is the digital supply ground. This pin should be connected to 0V.

NC 18 Not Connected

VSSA 19 A This is the analog supply ground. This pin should be connected to 0V.

μ/A-Law 20 D Compander mode select pin. μ-Law companding is selected when this pin is

tied to VDDD. A-Law companding is selected when this pin is tied to VSSD.

AO 21 A Analog output of the first gain stage in the transmit path.

AI- 22 A Inverting input of the first gain stage in the transmit path.

AI+ 23 A Non-inverting input of the first gain stage in the transmit path.

VAG 24 A Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for

all-analog signal processing. This pin should be decoupled to VSSA with a

0.01μF capacitor. This pin becomes high impedance when the chip is

powered down.

* These columns represent whether the pin Is driven by Analog (‘A’) or Digital (‘D’) power supply.

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7. FUNCTIONAL DESCRIPTION

W6811 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies

with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete μ-

Law and A-Law compander. The μ-Law and A-Law companders are designed to comply with the

specifications of the ITU-T G.711 recommendation.

The block diagram in section 3 shows the main components of the W6811. The chip consists of a

PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.

The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample

rate with the external frame sync frequency. The power conditioning block provides the internal power

supply for the digital and the analog section, while the voltage reference block provides a precision

analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in

section 3.

Figure 7.1 The W6811 Signal Path

PAO+

PAO

/A-

Cont

AI+

AI -

/A-

Cont

RO -

7.1. TRANSMIT PATH

The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain

setting (see application examples in section 11). The device has an input operational amplifier whose

output is the input to the encoder section. If the input amplifier is not required for operation it can be

powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or

the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The

input amplifier can be powered down by connecting the AI+ pin to VDDA or VSSA. The AO pin is selected

as an input when AI+ is tied to VDDA and the AI- pin is selected as an input when AI+ is tied to VSSA

(see Table 7.1).

AntAnt -Aliasi

Filter

= 3400

-Aliasi

Filter

C= 200

High

Pas

Filt

Smooth

Filter

Smooth

VAG

Control

/A-

Control

+ -

- +

PAI

Ant

AntHigh Pass -Aliasing

Filter

Aliasing

Filter

Smoothing

Filter Filter Filter Filter

Smoothing

Receive Path

Transmit Path

D/A

Converter

A/D

Converter

C= 3400Hz

C= 200Hz

W6811

Publication Release Date: September, 2005

- 9 - Revision A12

AI+ Input Amplifier Input

VDDA Powered Down AO

1.2 to VDDA-1.2 Powered Up AI+, AI-

VSSA Powered Down AI-

Table 7.1 Input Amplifier Modes of operation

When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the

analog ground voltage VAG.

The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent

aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low

pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed

according to the recommendations in the G.712 ITU-T specification. From the output of the high pass

filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with

either μ-Law or A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin.

The compression format can be selected according to Table 7.2.

μ/A-Law Pin Format

VSSA A-Law

VDDA μ-Law

Table 7.2. Pin-selectable Compression Format

The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the

data rate supplied by the external bit clock BCLKT.

7.2. RECEIVE PATH

The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of

expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a

low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.

A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is

buffered to provide the receive output signal RO-. The RO- output can be externally connected to the

PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By

using external resistors (see section 11 for examples), various gain settings of this output amplifier can

be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to

VDDA.

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7.3. POWER MANAGEMENT

7.3.1. Analog Supply

The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is

connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 μF ceramic

capacitor.

7.3.2. Digital Supply

The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is

connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 μF ceramic

capacitor.

7.3.3. Analog Ground Reference Bypass

The system has an internal precision voltage reference which generates the 2.5V mid-supply analog

ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 μF ceramic

capacitor.

7.3.4. Analog Ground Reference Voltage Output

The analog ground reference voltage is available for external reference at the VAG pin. This voltage

needs to be decoupled to VSSA through a 0.01 μF ceramic capacitor. The analog ground reference

voltage is generated from the voltage on the VREF pin and is also used for the internal signal

processing.

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of

operation of the interface are shown in Table 7.3.

BCLKR FSR Interface Mode

64 kHz to 4.096

MHz

8 kHz Long or Short Frame Sync

VSSD VSSD ISDN GCI with active channel B1

VSSD VDDD ISDN GCI with active channel B2

VDDD VSSD ISDN IDL with active channel B1

VDDD VDDD ISDN IDL with active channel B2

Table 7.3 PCM Interface mode selections

7.4.1. Long Frame Sync

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR

or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame

sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on

the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is

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held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame

Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125

μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will

become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is

being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync

signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The

internal decision logic will determine whether the next frame sync is a long or a short frame sync,

based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be HIGH

impedance for two frame sync cycles after every power down state. More detailed timing information

can be found in the interface timing section.

7.4.2. Short Frame Sync

The W6811 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH

for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the

bit-clock, the W6811 starts clocking out the data on the PCMT pin, which will also change from high to

low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway

through the LSB. The Short Frame Sync operation of the W6811 is based on an 8-bit data word.

When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling

edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the

next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus

collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down

state. More detailed timing information can be found in the interface timing section.

7.4.3. General Circuit Interface (GCI)

The GCI interface mode is selected when the BCLKR pin is connected to VSSD for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface

consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects

channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data

clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.

The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted

consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is

transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.

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7.4.4. Interchip Digital Link (IDL)

The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame

sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface

consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR

pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the

first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK

cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after

the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK

after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the

IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not

used for data transmission and also in the time slot of the unused channels. For more timing

information, see the timing section.

7.4.5. System Timing

The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz

master clock rates. The system clock is supplied through the master clock input MCLK and can be

derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and an

8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for

the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811

will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW.

When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame

Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become

low impedance.

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8. TIMING DIAGRAMS

FST

BCLKT

D7 D6 D5 D4 D3 D2 D1PCM T

MSB LSB

THID TBCK

TBCKH TBCKL

TFS

TFTFH

TFTRS

TFTRH

THID

TBDTD

TFDTD

01 23 45 7 8 0 1

MSB LSB

FSR

BCLKR

TBCK

D6 D5 D4 D3 D2 D1 D0PCM R D7

TDRH

TDRS

TBCKH TBCKL

TFS

TFRFH

TFRRS

TFRRH

01 2 3 45 6 7 8 0 1

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFA L L

TFSL

Figure 8.1 Long Frame Sync PCM Timing

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SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

TFSL FST / FSR Minimum LOW Width 1TBCK sec

1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT 0 Falling Edge to FST Rising

Edge Hold Time

20 --- --- ns

TFTRS FST Rising Edge to BCLKT 1 Falling

edge Setup Time

80 --- --- ns

TFTFH BCLKT 2 Falling Edge to FST Falling

Edge Hold Time

50 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay

Time

--- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT

Delay Time

--- --- 60 ns

THID Delay Time from the Later of FST

Falling Edge, or

BCLKT 8 Falling Edge to PCMT Output

High Impedance

10 --- 60 ns

TFRRH BCLKR 0 Falling Edge to FSR Rising

Edge Hold Time

20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 1 Falling

edge Setup Time

80 --- --- ns

TFRFH BCLKR 2 Falling Edge to FSR Falling

Edge Hold Time

50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge

Setup Time

0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling

Edge

50 --- --- ns

Table 8.1 Long Frame Sync PCM Timing Parameters

1 TFSL must be at least ≥ TBCK

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D7 D6 D5 D4 D3 D2 D1

MSB LSB

TBCK

TBCKH TBCK L

TFS

TFTRS

TFTRH

THID

TBDTD

01 2 3 45 6 7 8 01

FST

BCLKT

PCM T

TBDTD

TFTFH

-1

TFTFS

MSB LSB

TBCK

D6 D5 D4 D3 D2 D1 D0D7

TDRH

TDRS

TBCKH TBCK L

TFS

TFRRS

TFRRH

01 2 3 45 6 7 8 01

FSR

BCLKR

PCM R

TFRFH

-1

TFRFS

MCLK

TFTRHM TFTRSM TMCKH TMCKL

TMCK

TRISE TFA LL

Figure 8.2 Short Frame Sync PCM Timing

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SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

1/TBCK BCLKT, BCLKR Frequency 64 --- 4096 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT –1 Falling Edge to FST Rising Edge Hold

Time

20 --- --- ns

TFTRS FST Rising Edge to BCLKT 0 Falling edge Setup

Time

80 --- --- ns

TFTFH BCLKT 0 Falling Edge to FST Falling Edge Hold Time 50 --- --- ns

TFTFS FST Falling Edge to BCLKT 1 Falling Edge Setup

Time

50 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns

THID Delay Time from BCLKT 8 Falling Edge to PCMT

Output High Impedance

10 --- 60 ns

TFRRH BCLKR –1 Falling Edge to FSR Rising Edge Hold

Time

20 --- --- ns

TFRRS FSR Rising Edge to BCLKR 0 Falling edge Setup

Time

80 --- --- ns

TFRFH BCLKR 0 Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns

TFRFS FSR Falling Edge to BCLKR 1 Falling Edge Setup

Time

50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge Setup Time 0 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns

Table 8.2 Short Frame Sync PCM Timing Parameters

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FST

BCLKT

PCM T

PCM R

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

TFS

TFSRH

TFSFH

TFSRS

TBDTD TBDTD TBDTD TBDTD

THID

TDRS TDRS

TDRH TDRH

BCH = 0

B1 Channel

BCH = 1

B2 Channel

MSB

LSB

TBCK

TBCKH TBCK L

-1

Figure 8.3 IDL PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 256 --- 4096 kHz

TBCKH BCLKT HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT LOW Pulse Width 50 --- --- ns

TFSRH BCLKT –1 Falling Edge to FST Rising

Edge Hold Time

20 --- --- ns

TFSRS FST Rising Edge to BCLKT 0 Falling edge

Setup Time

60 --- --- ns

TFSFH BCLKT 0 Falling Edge to FST Falling Edge

Hold Time

20 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay

Time

10 --- 60 ns

THID Delay Time from the BCLKT 8 Falling

Edge (B1 channel) or BCLKT 18 Falling

Edge (B2 Channel) to PCMT Output High

Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Falling Edge Setup

Time

20 --- --- ns

TDRH PCMR Hold Time from BCLKT Falling

Edge

75 --- --- ns

Table 8.3 IDL PCM Timing Parameters

W6811

Publication Release Date: September, 2005

- 18 - Revision A12

FST

BCLKT

PCM T

PCM R

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

TFS

TFDTD TBDTD TBDTD TBDTD

THID

TDRS TDRS

TDRH TDRH

BCH = 0

B1 Channel

BCH = 1

B2 Channel

MSB

LSB

TFSRH

TFSFH

TFSRS

TBCK

TBCKH TBCK L

234567891011121314151617181920212223242526272829303132333410

Figure 8.4 GCI PCM Timing

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFST FST Frequency --- 8 --- kHz

1/TBCK BCLKT Frequency 512 --- 6176 kHz

TBCKH BCLKT HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT LOW Pulse Width 50 --- --- ns

TFSRH BCLKT 0 Falling Edge to FST Rising Edge Hold

Time

20 --- --- ns

TFSRS FST Rising Edge to BCLKT 1 Falling edge Setup

Time

60 --- --- ns

TFSFH BCLKT 1 Falling Edge to FST Falling Edge Hold

Time

20 --- --- ns

TFDTD FST Rising Edge to Valid PCMT Delay Time --- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time --- --- 60 ns

THID Delay Time from the BCLKT 16 Falling Edge (B1

channel) or BCLKT 32 Falling Edge (B2 Channel) to

PCMT Output High Impedance

10 --- 50 ns

TDRS Valid PCMR to BCLKT Rising Edge Setup Time 20 --- --- ns

TDRH PCMR Hold Time from BCLKT Rising Edge --- --- 60 ns

Table 8.4 GCI PCM Timing Parameters

W6811

Publication Release Date: September, 2005

- 19 - Revision A12

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TMCK Master Clock Frequency --- 256

512

1536

1544

2048

2560

4096

--- kHz

TMCKH / TMCK MCLK Duty Cycle for 256 kHz Operation 45% 55%

TMCKH Minimum Pulse Width HIGH for MCLK(512 kHz

or Higher)

50 --- --- ns

TMCKL Minimum Pulse Width LOW for MCLK (512 kHz

or Higher)

50 --- --- ns

TFTRHM MCLK falling Edge to FST Rising Edge Hold

Time

50 --- --- ns

TFTRSM FST Rising Edge to MCLK Falling edge Setup

Time

50 --- --- ns

TRISE Rise Time for All Digital Signals --- --- 50 ns

TFALL Fall Time for All Digital Signals --- --- 50 ns

Table 8.5 General PCM Timing Parameters

W6811

Publication Release Date: September, 2005

- 20 - Revision A12

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition Value

Junction temperature 1500C

Storage temperature range -650C to +1500C

Voltage Applied to any pin Analog

Digital

(VSSA - 0.3V) to (VDDA + 0.3V)

(VSSD - 0.3V) to (VDDD + 0.3V)

Voltage applied to any pin Analog

(Input current limited to +/-20 mA) Digital

(VSSA – 1.0V) to (VDDA + 1.0V)

(VSSD – 1.0V) to (VDDD + 1.0V)

VDDA - VSSA ; VDDD - VSSD -0.5V to +6V

VDDD – VDDA

2< 0.3V

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

2. At any time, the digital power supply should not be higher the 0.3V from the analog power supply.

9.2. OPERATING CONDITIONS

Condition Value

Industrial operating temperature -400C to +850C

Analog supply voltage (VDDA) +4.5V to +5.5V

Digital supply voltage (VDDD) +2.7V to +3.3V

Ground voltage (VSSA, VSSD) 0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

W6811

Publication Release Date: September, 2005

- 21 - Revision A12

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

Symbo

Parameters Conditions Min (2) Typ (1) Max (2) Units

VIL Input LOW Voltage 0.5 V

VIH Input HIGH Voltage 2.2 V

VOL PCMT Output LOW Voltage IOL = 1.6 mA 0.4 V

VOH PCMT Output HIGH Voltage IOL = -1.6 mA VDDD – 0.5 V

IDDA

IDDD

VDDA Current (Operating) -ADC+DAC PUI = 1

FSX running MCLK

running

5.5

1000

μA

ISBA

ISBD

VCCA Current (Standby)

PUI = 1

FSX = 0 MCLK running 200

0.2

500

100

μA

IPDA

IPDD

VCCA Current (Power Down)

VCCD Current (Power Down)

PUI = 0

200

500

IIL Input Leakage Current VSSD<VIN<VDDD +/-10

μA

IOL PCMT Output Leakage Current VSSA<PCMT<VDDA

High Z State

+/-10

μA

CIN Digital Input Capacitance 10 pF

COUT PCMT Output Capacitance PCMT High Z 15 pF

1. Typical values: TA = 25°C , VDDA = 5.0 V, VDDD = 3.0 V

2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

W6811

Publication Release Date: September, 2005

- 22 - Revision A12

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz;

FST=FSR=8kHz Synchronous operation.

TRANSMIT

(A/D)

RECEIVE

(D/A)

UNIT PARAMETER SYM. CONDITION TYP.

MIN. MAX. MIN. MAX.

Absolute Level LABS 0 dBm0 = 0dBm @ 600Ω 1.096 --- --- --- --- VPK

Max. Transmit

Level

TXMAX 3.17 dBm0 for μ-Law

3.14 dBm0 for A-Law

1.579

1.573

---

VPK

Absolute Gain

(0 dBm0 @

1020 Hz;

TA=+25°C)

GABS 0 dBm0 @ 1020 Hz;

TA=+25°C

0 -0.25 +0.25 -0.25 +0.25 dB

Absolute Gain

variation with

Temperature

GABST TA=0°C to TA=+70°C

TA=-40°C to TA=+85°C

0 -0.03

-0.05

+0.03

+0.05

-0.03

-0.05

+0.03

+0.05

Frequency

Response,

Relative to

0dBm0 @

1020 Hz

GRTV 15 Hz

50 Hz

60 Hz

200 Hz

300 to 3000 Hz

3300 Hz

3400 Hz

3600 Hz

4000 Hz

4600 Hz to 100 kHz

---

-1.0

-0.20

-0.35

-0.8

---

-40

-30

-26

-0.4

+0.15

-14

-32

-0.5

-0.20

-0.35

-0.8

---

+0.15

-14

-30

Gain Variation

vs. Level Tone

(1020 Hz

relative to –10

dBm0)

GLT +3 to –40 dBm0

-40 to –50 dBm0

-50 to –55 dBm0

---

-0.3

-0.6

-1.6

+0.3

+0.6

+1.6

-0.2

-0.4

-1.6

+0.2

+0.4

+1.6

W6811

Publication Release Date: September, 2005

- 23 - Revision A12

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz;

FST=FSR=8kHz Synchronous operation.

TRANSMIT (A/D) RECEIVE (D/A) PARAMETER SYM. CONDITION

MIN. TYP. MA

MIN. TYP. MAX.

UNIT

Total Distortion vs.

Level Tone (1020 Hz,

μ-Law, C-Message

Weighted)

DLTμ+3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

---

dBC

Total Distortion vs.

Level Tone (1020 Hz,

A-Law, Psophometric

Weighted)

DLTA +3 dBm0

0 dBm0 to -30 dBm0

-40 dBm0

-45 dBm0

---

dBp

Spurious Out-Of-Band

at RO- (300 Hz to

3400 Hz @ 0dBm0)

DSPO 4600 Hz to 7600 Hz

7600 Hz to 8400 Hz

8400 Hz to 100000

---

-30

-40

-30

Spurious In-Band (700

Hz to 1100 Hz @

0dBm0)

DSPI 300 to 3000 Hz ---

--- -47

---

--- -47

Intermodulation

Distortion (300 Hz to

3400 Hz –4 to –21

dBm0

DIM Two tones

--- --- -41 --- --- -41 dB

Crosstalk (1020 Hz @

0dBm0)

DXT --- --- -75 --- --- -75 dBm0

Absolute Group Delay τABS 1200 Hz --- --- 360 --- --- 240 μsec

Group Delay Distortion

(relative to group

delay @ 1200 Hz)

τD500 Hz

600 Hz

1000 Hz

2600 Hz

2800 Hz

---

750

380

130

750

---

750

370

120

750

μsec

Idle Channel Noise NIDL μ-Law; C-message

A-Law; Psophometric

---

-68

---

-78

dBrnc0

dBm0p

W6811

Publication Release Date: September, 2005

- 24 - Revision A12

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

AI Input Offset Voltage VOFF,AI AI+, AI- --- --- ±25 mV

AI Input Current IIN,AI AI+, AI- --- ±0.1 ±1.0 μA

AI Input Resistance RIN,AI AI+, AI- to VAG 10 --- --- MΩ

AI Input Capacitance CIN,AI AI+, AI- --- --- 10 pF

AI Common Mode Input

Voltage Range

VCM,AI AI+, AI- 1.2 --- VDDA-1.2 V

AI Common Mode Rejection

Ratio

CMRRTI AI+, AI- --- 60 --- dB

AI Amp Gain Bandwidth

Product

GBWTI AO, RLD≥10kΩ --- 2150 --- kHz

AI Amp DC Open Loop Gain GTI AO, RLD≥10kΩ --- 95 --- dB

AI Amp Equivalent Input

Noise

NTI C-Message

Weighted

--- -24 --- dBrnC

AO Output Voltage Range VTG RLD=10kΩ to VAG

RLD=2kΩ to VAG

0.5

1.0

---

VDDA-0.5

VDDA-1.0

Load Resistance RLDTGRO AO, RO to VAG 2 --- ---

kΩ

Load Capacitance CLDTGRO AO, RO --- --- 100 pF

AO & RO Output Current IOUT1 0.5 ≤AO,RO-≤

VDDA-0.5

±1.0 --- --- mA

RO- Output Resistance RRO- RO-, 0 to 3400

--- 1 ---

RO- Output Offset Voltage VOFF,RO- RO- to VAG --- --- ±25 mV

Analog Ground Voltage VAG Relative to VSSA 2.429 2.5 2.573 V

VAG Output Resistance RVAG Within ±25mV

change

--- 2.5 12.5

Power Supply Rejection Ratio

(0 to 100 kHz to VDDA, C-

message)

PSRR Transmit

Receive

---

dBC

PAI Input Offset Voltage VOFF,PAI PAI --- ---

±20 mV

PAI Input Current IIN,PAI PAI ---

±0.05 ±1.0 μA

PAI Input Resistance RIN,PAI PAI to VAG 10 --- --- MΩ

PAI Amp Gain Bandwidth

Product

GBWPI PAO- no load --- 1000 --- kHz

W6811

Publication Release Date: September, 2005

- 25 - Revision A12

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

Output Offset Voltage VOFF,PO PAO+ to PAO- --- --- ±50 mV

Load Resistance RLDPO PAO+, PAO-

differentially

300 --- --- Ω

Load Capacitance CLDPO PAO+, PAO-

differentially

--- --- 1000 pF

PO Output Current IOUTPO 0.5 ≤AO,RO-≤

VDDA-0.5

±10.0 --- --- mA

PO Output Resistance RPO PAO+ to PAO- --- 1 --- Ω

PO Differential Gain GPO RLD=300Ω,

+3dBm0, 1 kHz,

PAO+ to PAO-

-0.2 0 +0.2 dB

PO Differential Signal to

Distortion C-Message

weighted

DPO ZLD=300Ω

ZLD=100nF +

100Ω

ZLD=100nF + 20Ω

---

dBC

PO Power Supply Rejection

Ratio (0 to 25 kHz to VDDA,

Differential out)

PSRRPO 0 to 4 kHz

4 to 25 kHz

---

W6811

Publication Release Date: September, 2005

- 26 - Revision A12

10.5. DIGITAL I/O

10.5.1. μ-Law Encode Decode Chatacteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 0 0 0 0 0 0 8031

1 0 0 0 1 1 1 1 4191

1 0 0 1 1 1 1 1 2079

1 0 1 0 1 1 1 1 1023

1 0 1 1 1 1 1 1 495

1 1 0 0 1 1 1 1 231

1 1 0 1 1 1 1 1 99

1 1 1 0 1 1 1 1 33

1 1 1 1 1 1 1 0 2

1 1 1 1 1 1 1 1 0

8159

7903

4319

4063

2143

2015

1055

991

511

479

239

223

103

Notes:

Sign bit = 0 for negative values, sign bit = 1 for positive values

W6811

Publication Release Date: September, 2005

- 27 - Revision A12

10.5.2. A-Law Encode Decode Characteristics

Digital Code

D7 D6 D5 D4 D3 D2 D1 D0

Normalized

Encode

Decision

Levels

Sign Chord Chord Chord Step Step Step Step

Normalized

Decode

Levels

1 0 1 0 1 0 1 0 4032

1 0 1 0 0 1 0 1 2112

1 0 1 1 0 1 0 1 1056

1 0 0 0 0 1 0 1 528

1 0 0 1 0 1 0 1 264

1 1 1 0 0 1 0 1 132

1 1 1 0 0 1 0 1 66

1 1 0 1 0 1 0 1 1

4096

3968

2048

1088

1024

544

512

272

256

136

128

Notes:

1. Sign bit = 0 for negative values, sign bit = 1 for positive values

2. Digital code includes inversion of all even number bits

W6811

Publication Release Date: September, 2005

- 28 - Revision A12

10.5.3. PCM Codes for Zero and Full Scale

μ-Law A-Law

Level Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

+ Full Scale 1 000 0000 1 010 1010

+ Zero 1 111 1111 1 101 0101

- Zero 0 111 1111 0 101 0101

- Full Scale 0 000 0000 0 010 1010

10.5.4. PCM Codes for 0dBm0 Output

μ-Law A-Law

Sample Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

Sign bit

(D7)

Chord bits

(D6,D5,D4)

Step bits

(D3,D2,D1,D0)

1 0 001 1110 0 011 0100

2 0 000 1011 0 010 0001

3 0 000 1011 0 010 0001

4 0 001 1110 0 011 0100

5 1 001 1110 1 011 0100

6 1 000 1011 1 010 0001

7 1 000 1011 1 010 0001

8 1 001 1110 1 011 0100

W6811

Publication Release Date: September, 2005

- 29 - Revision A12

11. TYPICAL APPLICATION CIRCUIT

POWER CONTROL

1.0 uF

W6811

819

VDDA

VSSD

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

VDDDVSSA

1.0 uF

PCM IN

27K

DIFFERENTIAL

AUDIO IN

2.048 MHz

Bit Clock

27K

0.1 uF

27K

0.1 uF

27K

PCM OUT27K

+5VDC +3VDC

0.01 uF

0.1 uF

8 KHz Frame Sy nc

DIFFERENTIAL

AUDIO OUT

RL > 150 ohms

MODE SELECT

Figure 11.1 Typical circuit for Differential Analog I/O’s

PCM OUT1.0 uF

8 KHz Frame Sy nc

W6811

819

VDDA

VSSD

PUI

u/A

FST

BCLKT

PCMT

MCLK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

VDDDVSSA

27K

0.1 uF

+3VDC

PCM IN

1.0 uF

0.1 uF

0.01 uF

AUDIO IN

27K

AUDIO OUT

RL > 150

ohms

27K

2.048 MHz

Bit Clock

100 uF

+5VDC

27K

0.1 uF

AUDIO OUT

RL > 2K ohms

POWER CONTROL

MODE SELECT

Figure 11.2 Typical circuit for Single Ended Analog I/O’s

W6811

Publication Release Date: September, 2005

- 30 - Revision A12

100pF3.9K

MICROPHONE

0.1 uF

1.0 uF+

62K

1.5K 1K

1.0 uF

0.1 uF

1.5K

2.048 MHz

Bit Clock

W6811

819

VDDA

VSSD

PUI

u/A

FST

BCLKT

PCMT

MC LK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

VDDDVSSA

POWER CONTROL

+5VD C

0.01 uF

27K

100pF

SPEAKER

8 KHz Frame Sy nc

0.1 uF

PCM OUT

3.9K

ELECTRET

PCM IN

62K

MODE SELECT

22 uF

+3VDC

27K

Figure 11.3 Handset Interface

0.1 uF PCM IN

W6811

819

VDDA

VSSD

PUI

u/A

FST

BCLKT

PCMT

MCLK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

VDDDVSSA

PCM OUT

600 OHM 1:1

27K

0.01 uF

2.048 MHz

Bit Clock

TRANSFORMER

0.1 uF

27K

0.1 uF

8 KHz Frame Sy nc

1.0 uF

27K

+5VDC

POWER CONTROL

27K

600

+3VDC

MODE SELECT

B1/B2 SELECT

Figure 11.4 Transformer Interface Circuit in GCI mode

W6811

Publication Release Date: September, September, 2005

- 31 - Revision A12

12. PACKAGE SPECIFICATION

12.1. 24L TSSOP - 4.4X7.8MM

PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS

DIMENSION IN MM DIMENSION IN INCH

SYMBOL MIN NOM MAX MIN NOM MAX

A 1.20 0.043

A1 0.05 0.15 0.002 0.006

A2 0.80 0.90 1.05 0.031 0.035 0.041

L 0.50 0.60 0.75 0.020 0.024 0.030

E 6.40 BSC. 0.252 BSC.

HE 4.30 4.40 4.50 0.169 0.173 0.177

D 7.70 7.80 7.90 0.303 0.307 0.311

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.008

L1 1.0 REF. 0.039 REF

e 0.65 BSC. 0.026 BSC

01 0 8 0 8

W6811

Publication Release Date: September, September, 2005

- 32 - Revision A12

12.2. 24L SOP-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

DIMENSIONS IN MM DIMENSIONS IN INCH

SYMBOL MIN MAX MIN MAX

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

b 0.33 0.51 0.013 0.020

c 0.23 0.32 0.009 0.013

E 7.40 7.60 0.291 0.299

D 12.60 13.00 0.946 0.512

e 1.27 BSC. 0.050 BSC.

HE10.00 1065 0.394 0.419

Y 0.10 0.004

L 0.40 1.27 0.016 0.050

0 0 8 0 8

SEATING PLANE

0.25

GAUGE PLANE

SEATING PLANE

W6811

Publication Release Date: September, September, 2005

- 33 - Revision A12

12.3. 24L SSOP-209 MIL

SHRINK SMALL OUTLINE PACKAGE

DIMENSIONS

W6811

Publication Release Date: September, September, 2005

- 34 - Revision A12

12.4. 24L PDIP – 300 MIL

PLASTIC DUAL INLINE PACKAGE DIMENSIONS

DIMENSION IN MM DIMENSION IN INCH

SYMBOL MIN NOM MAX MIN NOM MAX

A 4.45 0.175

A1 0.25 0.010

A2 3.18 3.30 3.43 0.125 0.130 0.135

B 0.41 0.46 0.56 0.016 0.018 0.022

B1 1.47 1.52 1.63 0.058 0.060 0.064

c 0.20 0.25 0.36 0.008 0.010 0.014

D 31.95 32.26 1.258 1.270

E 7.37 7.62 7.87 0.290 0.300 0.310

E1 6.43 6.55 6.68 0.253 0.258 0.263

e1 2.29 2.54 2.79 0.090 0.100 0.110

L 3.05 3.30 3.56 0.120 0.130 0.140

á 0° 15° 0° 15°

eA8.38 8.89 9.40 0.330 0.350 0.370

S 2.29 0.090

Base Plane

Mounting Plane

W6811

Publication Release Date: September, September, 2005

- 35 - Revision A12

13. ORDERING INFORMATION

Winbond Part Number Description

Product Family

W6811 Product

W6811I _ _

Package Material:

Blank = Standard Package

G = Pb-free (RoHS) Package

Package Type:

W = 24-Lead Plastic Thin Small Outline Package (TSSOP) Type 1

S = 24-Lead Plastic Small Outline Package (SOG/SOP)

R = 24-Lead Plastic Small Outline Package (SSOP)

E = 24-Lead Plastic Dual Inline Package (PDIP)

When ordering W6811 series devices, please refer to the following part numbers.

Part Number

W6811IW

W6811IS

W6811IR

W6811IE

W6811IWG

W6811ISG

W6811IRG

W6811IEG

W6811

Publication Release Date: September, September, 2005

- 36 - Revision A12

14. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A7 August 9,

2002

Preliminary

A8 September

26, 2002

A9 October

10, 2002

A10 October

23, 2003

34 Changed the package dimension of the SSOP24 package

A11 April 2005 41 Add Important Notice

A12 September,

2005

11, 12

29, 30

Added reference to Pb-free RoHS packaging

Capitalized logic HIGH/LOW

Extended conditions on Table 10.2.

Extended conditions on Table 10.3.

Corrected Idle Channel Noise min/max and units.

Improved Application Diagrams

Added G package ordering code

W6811

Publication Release Date: September, September, 2005

- 37 - Revision A12

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control instruments,

airplane or spaceship instruments, transportation instruments, traffic signal instruments,

combustion control instruments, or for other applications intended to support or sustain life.

Further more, Winbond products are not intended for applications wherein failure of Winbond

products could result or lead to a situation wherein personal injury, death or severe property

or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III 2727 North First Street, San Jose, 27F, 299 Yan An W. Rd. Shanghai,

Science-Based Industrial Park, CA 95134, U.S.A. 200336 China

Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999

TEL: 886-3-5770066 FAX: 1-408-5441798 FAX: 86-21-62356998

FAX: 886-3-5665577 http://www.winbond-usa.com/

http://www.winbond.com.tw/

Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG, 3-7-18 Unit 9-15, 22F, Millennium City,

Neihu District, Shinyokohama Kohoku-ku, No. 378 Kwun Tong Rd.,

Taipei, 114, Taiwan Yokohama, 222-0033 Kowloon, Hong Kong

TEL: 886-2-81777168 TEL: 81-45-4781881 TEL: 852-27513100

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