LTC3810
31
3810fc
is less than fO, current is sunk continuously, pulling down
the PLL/LPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLL/LPF
pin is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor CLP holds the voltage. The LTC3810 MODE/SYNC
pin must be driven from a low impedance source such as
a logic gate located close to the pin.
The loop fi lter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The fi lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10kΩ and CLP is 0.01μF
to 0.1μF.
Pin Clearance/Creepage Considerations
The LTC3810 is available in the G28 package which
has 0.0106" spacing between adjacent pins. To
maximize PC board trace clearance between high volt-
age pins, the LTC3810 has three unconnected pins
between all adjacent high voltage and low voltage
pins, providing 4(0.0106") = 0.042" clearance which
will be suffi cient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3810 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
effi ciency to drop at high output currents. In continuous
mode the average output current fl ows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the resistances of L and the board traces to obtain
the DC I2R loss. For example, if RDS(ON) = 0.01Ω and
RL = 0.005Ω, the loss will range from 15mW to 1.5W
as the output current varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is signifi cant
at input voltages above 20V and can be estimated from
the second term of the PMAIN equation found in the Power
MOSFET Selection section. When transition losses are
signifi cant, effi ciency can be improved by lowering the
frequency and/or using a top MOSFET(s) with lower
CRSS at the expense of higher RDS(ON).
3. INTVCC/DRVCC current. This is the sum of the MOSFET
driver and control currents. Control current is typically
about 3mA and driver current can be calculated by: IGATE
= f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are
the gate charges of the top and bottom MOSFETs. This
loss is proportional to the supply voltage that INTVCC/
DRVCC is derived from, i.e., VIN for the external NMOS
linear regulator, VOUT for the internal EXTVCC regula-
tor, or VEXT when an external supply is connected to
INTVCC/DRVCC.
4. CIN loss. The input capacitor has the diffi cult job of fi l-
tering the large RMS input current to the regulator. It
must
have a very low ESR to minimize the AC I2R loss
and suffi cient capacitance to prevent the RMS current
from
causing additional upstream losses in fuses or
batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss. When
making adjustments to improve effi ciency, the input cur-
rent is the best indicator of changes in effi ciency. If you
make a change and the input current decreases, then the
effi ciency has increased. If there is no change in input
current, then there is no change in effi ciency.
APPLICATIONS INFORMATION