© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 8
1Publication Order Number:
MC10E016/D
MC10E016, MC100E016
5.0VECL8‐Bit
Synchronous Binary Up
Counter
Description
The MC10E/100E016 is a high-speed synchronous, presettable,
cascadable 8-bit binary counter. Architecture and operation are the
same as the MC10H016 in the MECL 10H™family, extended to
8-bits, as shown in the logic symbol.
The counter features internal feedback of TC, gated by the TCLD
(terminal count load) pin. When TCLD is LOW (or left open, in which
case it is pulled LOW by the internal pull-downs), the TC feedback is
disabled, and counting proceeds continuously, with TC going LOW to
indicate an all-one state. When TCLD is HIGH, the TC feedback
causes the counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter. The Qn outputs do not need to
be terminated for the count function to operate properly. To minimize
noise and power, unused Q outputs should be left unterminated.
The 100 series contains temperature compensation.
Features
•700 MHz Min. Count Frequency
•1000 ps CLK to Q, TC
•Internal TC Feedback (Gated)
•8-Bit
•Fully Synchronous Counting and TC Generation
•Asynchronous Master Reset
•PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
•These Devices are Pb-Free, Halogen Free and are RoHS Compliant
MARKING DIAGRAM*
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
PLCC−28
FN SUFFIX
CASE 776−02
MCxxxE016G
AWLYYWW
1
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*For additional marking information, refer to
Application Note AND8002/D.
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
ORDERING INFORMATION
Device Package Shipping
MC10E016FNG PLCC−28
(Pb-Free)
37 Units/Tube
MC10E016FNR2G 500 Tape & Reel
MC100E016FNR2G
MC100E016FNG
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
PLCC−28
(Pb-Free)
37 Units/Tube
500 Tape & Reel
MC10E016, MC100E016
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2
1
MR
CLK
TCLD
VEE
NC
P0
P1
26
27
28
2
3
4
25 24 23 22 21 20 1
918
17
16
15
14
13
12
115678910
PE CE P7P6P5VCCO TC
Q7
Q6
VCC
Q5
Q4
Q3
P2P3P4VCCO Q0Q1Q2
VCCO
Figure 1. 28-Lead Pinout Assignment (Top View)
All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN FUNCTION
P0 −P7
Q0−Q7
CE
PE
MR
CLK
TC
TCLD
NC
VCC, VCCO
VEE
ECL Parallel Data (Preset) Inputs
ECL Data Outputs
ECL Count Enable Control Input
ECL Parallel Load Enable Control Input
ECL Master Reset
ECL Clock
ECL Terminal Count Output
ECL TC−Load Control Input
No Connect
Positive Supply
Negative Supply
Figure 2. 8-Bit Binary Counter Logic Counter
Note that this diagram is provided for understanding of
logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally
without incurring a full gate delay.
P1
SLAVEMASTER
5
TC
Q1
Q0
P7
Q6
Q5
Q4
Q3
Q2
Q1
CEQ0
BIT 1
CE
Q0
Q0M
Q0M
BIT 0
PE
TCLD
CE
PO
MR
CLK
BIT 7
BITS 2-6
Q7
Table 2. FUNCTION TABLE
FUNCTION CE PE TCLD MR CLK
Load Parallel (Pn to Qn) X L X L Z
Continuous Count L H L L Z
Count; Load Parallel on TC = LOW L H H L Z
Hold H H X L Z
Masters Respond, Slaves Hold X X X L ZZ
Reset (Qn : = LOW, TC : = HIGH) X X X H X
Z = clock pulse (low to high);
ZZ = clock pulse (high to low)
MC10E016, MC100E016
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3
Table 3. EXPANDED FUNCTION TABLE
Function PE CE MR TCLD CLK P7−P4 P3 P2 P1 P0 Q7−Q4 Q3 Q2 Q1 Q0 TC
Load L X L X Z H H H L L H H H L L H
Count HLL L Z X XXXX H HHLHH
HLL L Z X XXXX H HHHLH
HLL L Z X XXXX H HHHHL
HLL L Z X XXXX L LLLLH
Load L XL X Z H HHL L H HHL LH
Hold HHL X Z X XXXX H HHL LH
HHL X Z X XXXX H HHL LH
Load On HLL H Z H LHHL H HHLHH
Terminal H LL H Z H LHHL H HHHLH
Count HLL H Z H LHHL H HHHHL
HLL H Z H LHHL H LHHLH
HLL H Z H LHHL H LHHHH
HLL H Z H LHHL H HLLLH
Reset X X H X X X X X X X L L L L L H
Table 4. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 50 kW
Internal Input Pullup Resistor 50 kW
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
PLCC−28
Pb-Free Pkg
Level 3
Flammability Rating
Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 592 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC10E016, MC100E016
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4
Table 5. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 8 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
6
−6
V
Iout Output Current Continuous
Surge
50
100
mA
TAOperating Temperature Range 0 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board PLCC−28 22 to 26 °C/W
Tsol Wave Solder (Pb-Free) 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 6. 10E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1))
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 151 181 151 181 151 181 mA
VOH Output HIGH Voltage (Note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV
VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV
VIH Input HIGH Voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV
VIL Input LOW Voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.3 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
MC10E016, MC100E016
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5
Table 7. 10E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 151 181 151 181 151 181 mA
VOH Output HIGH Voltage (Note 2) −1020 −930 −840 −980 −895 −810 −910 −815 −720 mV
VOL Output LOW Voltage (Note 2) −1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
VIH Input HIGH Voltage −1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV
VIL Input LOW Voltage −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.065 0.3 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 8. 100E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1))
Symbol Characteristic
0°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 151 181 151 181 174 208 mA
VOH Output HIGH Voltage (Note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV
VOL Output LOW Voltage (Note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV
VIH Input HIGH Voltage 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV
VIL Input LOW Voltage 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
MC10E016, MC100E016
www.onsemi.com
6
Table 9. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 151 181 151 181 174 208 mA
VOH Output HIGH Voltage (Note 2) −1025 −950 −880 −1025 −950 −880 −1025 −950 −880 mV
VOL Output LOW Voltage (Note 2) −1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
VIH Input HIGH Voltage −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
VIL Input LOW Voltage −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.3 0.5 0.25 0.5 0.2 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 10. AC CHARACTERISTICS (VCCx= 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 1))
0°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fMAX Maximum Toggle Frequency 700 700 700 MHz
fCOUNT Maximum Count Frequency 700 900 700 900 700 900 MHz
tPLH, tPHL Propagation Delay to Output
CLK to Q
MR to Q
CLK to TC
MR to TC
500
500
500
500
725
775
775
775
900 500 725
775
775
775
900 500 725
775
775
775
900
ps
tsSetup Time (to CLK +) ps
tsSetup Time (to CLK +)
Pn
CE
PE
TCLD
150
600
600
500
−30
400
400
300
150
600
600
500
−30
400
400
300
150
600
600
500
−30
400
400
300
ps
thHold Time (to CLK +)
Pn
CE
PE
TCLD
350
400
0
100
100
200
200
−300
350
400
0
100
100
200
200
−300
350
400
0
100
100
200
200
−300
tRR Reset Recovery Time 900 700 900 700 900 700 ps
tPW Minimum Pulse Width
CLK, MR 400 400 400
ps
tJITTER Random Clock Jitter (RMS) < 1 < 1 < 1 ps
tr, tfRise/Fall Times (20−80%) 200 510 700 200 510 700 200 510 700 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
MC10E016, MC100E016
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7
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output
and count enable input (CE) greatly facilitate the cascading
of E016 devices. Two E016s can be cascaded without the
need for external gating, however for counters wider than 16
bits external OR gates are necessary for cascade
implementations.
Figure 3 below pictorially illustrates the cascading of 4
E016s to build a 32-bit high frequency counter. Note the
E101 gates used to OR the terminal count outputs of the
lower order E016s to control the counting operation of the
higher order bits. When the terminal count of the preceding
device (or devices) goes low (the counter reaches an all 1s
state) the more significant E016 is set in its count mode and
will count one binary digit upon the next positive clock
transition. In addition, the preceding devices will also count
one bit thus sending their terminal count outputs back to a
high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an E016 in the chain to count, all of the lower
order terminal count outputs must be in the low state. The bit
width of the counter can be increased or decreased by simply
adding or subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC
output and the necessary setup time of the CE input and the
propagation delay through the OR gate controlling it (for
16-bit counters the limitation is only the TC propagation
delay and the CE setup time). Figure 3 shows EL01 gates
used to control the count enable inputs, however, if the
frequency of operation is lower a slower, ECL OR gate can
be used. Using the worst case guarantees for these
parameters from the ECLinPS data book, the maximum
count frequency for a greater than 16-bit counter is 500 MHz
and that for a 16-bit counter is 625 MHz.
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Figure 3. 32-Bit Cascaded E016 Counter
EL01
CLOCK
P0 -> P7
TC
CLK
P0 -> P7
TCCLK
EL01
P0 -> P7
TC
CLK
P0 -> P7
MSB
E016
PE
CE
Q0 -> Q7Q0 -> Q7 Q0 -> Q7
E016
PE
CE
Q0 -> Q7
E016
PE
CE
LSB
E016
PE
CE
LO
LOAD
TCCLK
MC10E016, MC100E016
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8
APPLICATIONS INFORMATION (continued)
Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads
the data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.
H
L
H
HLLLHHHH
TC
PE
CE
TCLD
CLK
P7 P6 P4 P3 P2 P1 P0P5
Q7 Q6 Q4 Q3 Q2 Q1 Q0Q5
Figure 4. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 − 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the E016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
Table 11. Preset Values for Various Divide Ratios
Divide
Ratio
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
2 H H H H H H H L
3 H HHHHHLH
4 H HHHHHL L
5 H HHHHLHH
w w •••••••
w••••••••
112 HLLHLLLL
113 HL L LHHHH
114 HL L LHHHL
• • •••••••
• • •••••••
254 L LLLLLHL
255 L LLLLLLH
256 L L L L L L L L
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed multiple E016s can be cascaded in a manner similar
to that already discussed. When E016s are cascaded to build
larger dividers the TCLD pin will no longer provide a means
for loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must
be used for multiple E016 divider chains.
•••
PE
•••
•••
Clock
TC
Load
DIVIDE BY 113
Load1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111
Figure 5. Divide by 113 E016 Programmable Divider Waveforms
MC10E016, MC100E016
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9
APPLICATIONS INFORMATION (continued)
E016
MSB
CLK TC
PECE
E016
CLK TC
PECE
E016
CLK TC
PECE
EL01
EL01
EL01
CLOCK
Q0 -> Q7
PO -> P7
Q0 -> Q7
PO -> P7
Q0 -> Q7
PO -> P7
Q0 -> Q7
PO -> P7
LO
E016
LSB
CLK TC
PECE
Figure 6. 32-Bit Cascaded E016 Programmable Divider
OUT
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EL01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EL01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant E016 must also feed the CE
input of the most significant E016. If the two TC outputs
were OR tied the cascaded count operation would not
operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning
single-ended outputs, thus VCC noise can become
significant in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise can
negatively impact the maximum frequency of operation of
the device. Since the device does not need to have the Q
outputs terminated to count properly, it is recommended that
if the outputs are not going to be used in the rest of the system
they should be left unterminated. In addition, if only a subset
of the Q outputs are used in the system only those outputs
should be terminated. Not terminating the unused outputs
will not only cut down the VCC noise generated but will also
save in total system power dissipation. Following these
guidelines will allow designers to either be more aggressive
in their designs or provide them with an extra margin to the
published data book specifications.
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
MC10E016, MC100E016
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10
PACKAGE DIMENSIONS
28 LEAD PLLC
FN SUFFIX
CASE 776−02
ISSUE F
−N−
−M−
−L−
V
WD
D
Y BRK
28 1
VIEW S
S
L-M
S
0.010 (0.250) N S
T
S
L-M
M
0.007 (0.180) N S
T
0.004 (0.100)
G1
GJ
C
Z
R
E
A
SEATING
PLANE
S
L-M
M
0.007 (0.180) N S
T
−T−
B
S
L-M
S
0.010 (0.250) N S
T
S
L-M
M
0.007 (0.180) N S
T
U
S
L-M
M
0.007 (0.180) N S
T
Z
G1X
VIEW D−D
S
L-M
M
0.007 (0.180) N S
T
K1
VIEW S
H
K
FS
L-M
M
0.007 (0.180) N S
T
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.485 0.495 12.32 12.57
B0.485 0.495 12.32 12.57
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.021 0.33 0.53
G0.050 BSC 1.27 BSC
H0.026 0.032 0.66 0.81
J0.020 --- 0.51 ---
K0.025 --- 0.64 ---
R0.450 0.456 11.43 11.58
U0.450 0.456 11.43 11.58
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y--- 0.020 --- 0.50
Z2 10 2 10
G1 0.410 0.430 10.42 10.92
K1 0.040 --- 1.02 ---
__ __
MC10E016, MC100E016
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11
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