S6AP413A 4ch DC/DC Converter with I2C Interface and Internal SW FETs S6AP413A contains 3ch buck DC/DC converter and 1ch buck-boost DC/DC converter. S6AP413A can supply the main power line in several systems by using only its chip. The current mode control is adopted for the DC/DC converter, and it is possible to use the small chip inductor with the high switching frequency operation which contains internal switching FETs. S6AP413A contains the output setting resistor and the phase compensation circuit, and contributes to reduce the number of external components and its mount area. Also it contains the CTL input pin which can control the ON/OFF for each DC/DC converter, the Power Good signal 2 output pin and I C communication interface, therefore it is easy to design the power supply sequence. It is possible to tune in the 2 output voltage exactly using the I C communication. Features Operating input voltage range: 2.5V to 5.5V (Maximum rating: 6.5V) Output voltage setting range: DD1*:0.7V to 1.32V (20mV/step) DD2*:1.2V to 1.95V (50mV/step) DD3*:2.8Vto 3.5V (100mV/step) DD4*:0.7V to 1.32V (20mV/step) Maximum output current: DD1:2A, DD2:1.2A, DD3:0.6A, DD4:2A Internal switching FETs, output voltage setting resistor, phase compensation circuit and output discharge resistor (all DC/DC converters) Buck-boost DC/DC converter is seamless to change operation mode Soft start time setting range: 1 ms to 16 ms (approximately 1ms/step) Switching frequency for the DC/DC converter: 3 MHz Communication interface: I2C (ON/OFF, Output voltage, Soft start time) Internal PFM/PWM auto switching mode Each DC/DC converter Power Good function (open drain) Several protection functions: Under voltage lockout (UVLO), Over current protection (OCP), Thermal shut down (TSD) Small package: QFN32 (5mm x 5mm x 0.71mm, 0.5mm pitch) *: DD1, DD2, DD3, and DD4: DC/DC converter blocks 1,2,3,4 Applications Network equipment, Factory automation, Security system, Surveillance camera, Electrical music instrument, Multi-function printer, Scanner, Printer, Copy machine, Home appliances, Data storage (HDD, SSD), Mobile equipment for Li+ battery (1 cell) Cypress Semiconductor Corporation Document Number: 002-08448 Rev.*A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 26, 2016 S6AP413A Contents 1. Application Circuit Example ............................................................................................................................................ 4 2. Recommended Application Specification ....................................................................................................................... 5 3. Pin Configuration .............................................................................................................................................................. 8 4. Pin Descriptions ................................................................................................................................................................ 9 5. Block Diagram ................................................................................................................................................................. 10 6. Absolute Maximum Ratings ........................................................................................................................................... 11 7. Recommended Operating Conditions ........................................................................................................................... 12 8. Electrical Characteristics ............................................................................................................................................... 13 8.1 Reference Control Block.............................................................................................................................................. 13 8.2 DD1 ............................................................................................................................................................................. 14 8.3 DD2 ............................................................................................................................................................................. 15 8.4 DD3 ............................................................................................................................................................................. 16 8.5 DD4 ............................................................................................................................................................................. 17 8.6 Digital Block................................................................................................................................................................. 18 9. Operation Mode List ....................................................................................................................................................... 19 10. State Transition Diagram................................................................................................................................................ 20 11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3, CTL4) .......................................................... 21 12. Turning ON and OFF Sequence (AVCC CTLMAINCTL1CTL2 CTL3 CTL4) ............................................... 22 2 13. Turning ON and OFF Sequence (AVCCCTLMAINI C) ........................................................................................... 23 14. CTL Pin Threshold Voltage ............................................................................................................................................ 24 15. Protection Operation Sequence..................................................................................................................................... 25 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit ..................................................... 26 17. DD Soft Start Operation .................................................................................................................................................. 27 18. Discharge Operation ....................................................................................................................................................... 28 19. PG Function ..................................................................................................................................................................... 29 2 20. I CInterface ...................................................................................................................................................................... 30 2 20.1 Structure of I CInterface .............................................................................................................................................. 30 20.2 Definition of Signal Lines ............................................................................................................................................. 30 20.3 Validity of Data ............................................................................................................................................................ 31 20.4 Definition of Start and Stop Condition.......................................................................................................................... 31 20.5 ACK Signal .................................................................................................................................................................. 32 2 20.6 I C Interface Input Timing ............................................................................................................................................ 33 20.7 Slave Address ............................................................................................................................................................. 34 2 20.8 Bit Structure of Data on I C Interface .......................................................................................................................... 35 2 21. Structure of I C Interface and Data ................................................................................................................................ 37 21.1 About DD1, DD4Output Voltage Setting ...................................................................................................................... 38 21.2 About DD2 Output Voltage Setting .............................................................................................................................. 39 21.3 About DD3 Output Voltage Setting .............................................................................................................................. 40 21.4 About Soft Start Time .................................................................................................................................................. 41 21.5 DC/DC Operation Mode .............................................................................................................................................. 42 21.6 ON/OFF for DC/DC ..................................................................................................................................................... 43 21.7 About Error Monitor ..................................................................................................................................................... 44 21.8 About Power Good Monitor ......................................................................................................................................... 45 22. I/O Pin Equivalent Circuit Diagram ................................................................................................................................ 46 23. Measurement Circuit for Characteristics of General Operation ................................................................................. 49 24. Reference Data ................................................................................................................................................................ 51 25. Ordering Information ...................................................................................................................................................... 63 26. Preset Code List .............................................................................................................................................................. 64 Document Number: 002-08448 Rev.*A Page 2 of 69 S6AP413A 27. Layout .............................................................................................................................................................................. 65 28. Package Dimensions ...................................................................................................................................................... 66 29. Major Changes ................................................................................................................................................................ 67 Document History ................................................................................................................................................................. 68 Document Number: 002-08448 Rev.*A Page 3 of 69 S6AP413A 1. Application Circuit Example Figure 1. Application Circuit Document Number: 002-08448 Rev.*A Page 4 of 69 S6AP413A 2. Recommended Application Specification [Input Voltage Range] 2.5 Input Voltage Vin(V) Typ Max 3.3 5.5 (Ta=+25C) DD1 VO1 1.2 % Document Number: 002-08448 Rev.*A Discharge Resistance (k) Soft-start Time (ms) Min Mode Max Output Capacitance Max 0.708 0.729 0.749 0.769 0.789 0.810 0.830 0.850 0.870 0.891 0.911 (*1) 0.931 0.951 0.972 0.992 1.012 (*1) 1.032 1.052 1.073 1.093 1.113 (*1) 1.133 1.154 1.174 1.194 1.214 (*1) 1.235 1.255 1.275 1.295 1.316 1.336 Inductor(H) Typ 0.700 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880 0.900 (*1) 0.920 0.940 0.960 0.980 1.000 (*1) 1.020 1.040 1.060 1.080 1.100 (*1) 1.120 1.140 1.160 1.180 1.200 (*1) 1.220 1.240 1.260 1.280 1.300 1.320 Switching Frequency(MH z) Min 0.692 0.711 0.731 0.751 0.771 0.790 0.810 0.830 0.850 0.869 0.889 (*1) 0.909 0.929 0.948 0.968 0.988 (*1) 1.008 1.028 1.047 1.067 1.087 (*1) 1.107 1.126 1.146 1.166 1.186 (*1) 1.205 1.225 1.245 1.265 1.284 1.304 Limit Current(mA) Output Voltage (V) Output Current(mA) Accuracy Symbol Channel [Output specification] 1 to 16ms 2000 (2400) Buck (synchro nous rectificati on) C-mode 3.0 1.0 22 At the time of 1.0V setting, the details are cf. Contents 17 5.0 Remarks Min Built-in SWFET Built-in output setting resistor s Built-in phase compe nsation circuit Page 5 of 69 VO3 1.8 % 2.74 (*1) 2.84 2.94 (*1) 3.04 3.14 3.23 (*1) 3.33 2.80 (*1) 2.90 3.00 (*1) 3.10 3.20 3.30 (*1) 3.40 2.86 (*1) 2.96 3.06 (*1) 3.16 3.26 3.37 (*1) 3.47 3.43 (*1) 3.50 (*1) 3.57 (*1) Document Number: 002-08448 Rev.*A Mode Soft-start Time (ms) 1.973 Output Capacitance 1.950 Min Inductor(H) 1.927 Max Switching Frequency(MH z) Max 1.214 (*1) 1.265 1.316 1.366 (*1) 1.417 1.467 1.518 (*1) 1.569 1.619 1.670 1.720 1.771 1.822 (*1) 1.872 1.923 Limit Current(mA) Typ 1.200 (*1) 1.250 1.300 1.350 (*1) 1.400 1.450 1.500 (*1) 1.550 1.600 1.650 1.700 1.750 1.800 (*1) 1.850 1.900 Output Current(mA) Accuracy 1.2 % Min 1.186 (*1) 1.235 1.284 1.334 (*1) 1.383 1.433 1.482 (*1) 1.531 1.581 1.630 1.680 1.729 1.778 (*1) 1.828 1.877 Remarks DD3 VO2 Output Voltage (V) Discharge Resistance (k) DD2 Symbol Channel S6AP413A 5.0 Built-in SWFE T Built-in output setting resistor s Built-in phase compe nsation circuit 5.0 Built-in SWFE T Built-in output setting resistor s Built-in phase compe nsation circuit 1 to 16ms 1200 (15 00) Buck (synchronou s rectification) C-mode 3.0 1. 0 10 At the time of 1.8V settin g, the detail s are cf. Conte nts 17 1 to16m s 600 (75 0) Buck-boost (synchronou s rectification) C-mode 3.0 1. 0 22 At the time of 3.3V settin g, the detail s are cf. Conte nts 17 Page 6 of 69 DD4 VO4 1.2 % 0.720 0.729 0.731 0.740 0.749 0.751 0.760 0.769 0.771 0.780 0.789 0.790 0.800 0.810 0.810 0.820 0.830 0.830 0.840 0.850 0.850 0.860 0.870 0.869 0.889 (*1) 0.909 0.880 0.900 (*1) 0.920 0.891 0.911( *1) 0.931 0.929 0.940 0.951 0.948 0.960 0.972 0.968 0.988 (*1) 1.008 0.980 1.000 (*1) 1.020 0.992 1.012 (*1) 1.032 1.028 1.040 1.052 1.047 1.060 1.073 1.067 1.087 (*1) 1.107 1.080 1.100 (*1) 1.120 1.093 1.113 (*1) 1.133 1.126 1.140 1.154 1.146 1.160 1.174 1.166 1.186 (*1) 1.205 1.180 1.200 (*1) 1.220 1.194 1.214 (*1) 1.235 1.225 1.240 1.255 1.245 1.260 1.275 1.265 1.280 1.295 1.284 1.300 1.316 1 to16ms 2000 (2400) Buck (synchr onous rectificat ion) C-mode 3.0 1. 0 22 At the time of 1.8V setting, the details are cf. Content s 17 5.0 Remarks Discharge Resistance (k) Mode Min Soft-start Time (ms) 0.711 Max Output Capacitance Max 0.708 Inductor(H) Typ 0.700 Switching Frequency(MH z) Min 0.692 Limit Current(mA) Output Voltage (V) Output Current(mA) Accuracy Symbol Channel S6AP413A Built-in SWFE T Built-in output setting resistor s Built-in phase compe nsation circuit 1.304 1.320 1.336 *1:default(It is selectable with the default output voltage) Document Number: 002-08448 Rev.*A Page 7 of 69 S6AP413A 3. Pin Configuration VO3 PG4 PG3 PG2 PG1 AVCC VREF18 CTLMAIN (TOP VIEW) 32 31 30 29 28 27 26 25 LX3-2 1 24 IN1 PGND3 2 23 PVCC1 LX3-1 3 22 LX1 PVCC3 4 21 PGND1 PVCC2 5 20 PGND4 LX2 6 19 LX4 PGND2 7 18 PVCC4 IN2 8 17 IN4 top view 14 15 16 DVCC CTL3 13 SDA CTL2 12 SCL 11 GND 10 CTL4 9 CTL1 EP(Exposed Pad) (WNT032) Document Number: 002-08448 Rev.*A Page 8 of 69 S6AP413A 4. Pin Descriptions Block DD1 Buck DD2 Buck DD3 Buck-boos t DD4 Buck CTL Unuse d DD1 Unuse d DD2 Unused DD3 Unused DD4 Unus ed 2 IC DD1 output voltage feedback Pulldown Resis tor - GND - - - - - DD1output block power supply - AVCC - - - - 22 28 O O DD1 inductor connection DD1 Power Good output - Open GND - - - - 21 O DD1 output block ground - GND - - - - 8 I DD2 output voltage feedback - - GND - - - 5 - DD2 output block power supply - - AVCC - - - 6 29 O O DD2 inductor connection DD2 Power Good output - - Open GND - - - 7 - DD2 output block ground - - GND - - - 4 - - - - AVCC - - 32 3 1 30 O O O O Power supply for DD3 output block Output voltage for DD3 DD3 inductor connection1 DD3 inductor connection2 Output for DD3 Power Good - - - GND Open Open GND - - 2 - Ground for DD3 output block - - - GND - - 17 - DD4 output voltage feedback - - - - GND - 18 - DD4 output block power supply - - - - AVCC - 19 31 O O DD4 inductor connection DD4 Power Good output - - - - Open GND - 20 - DD4 output block ground - - - - GND - 25 I Exist - - - - - 9 10 11 12 I I I I Exist Exist Exist Exist Open - Open - Open - Open - DVCC 16 I - - - - - GND SCL SDA 14 15 I I/O Exist - - - - Open Open AVCC 27 - - - - - - - 26 O Output reference voltage - - - - - - 13 EP - Ground for reference voltage Ground for reference voltage - - - - - - Pin Name Pin Num ber I/O IN1 PVCC 1 LX1 PG1 PGND 1 IN2 PVCC 2 LX2 PG2 PGND 2 PVCC 3 VO3 LX3-1 LX3-2 PG3 PGND 3 IN4 PVCC 4 LX4 PG4 PGND 4 CTLM AIN CTL1 CTL2 CTL3 CTL4 24 I 23 2 IC Reference control VREF1 8 GND GND Document Number: 002-08448 Rev.*A Description Control for reference voltage output DD1 control DD2 control DD3control DD4 control 2 Power supply for I C communication 2 Clock for I C communication 2 Data for I C communication Power supply for reference voltage Page 9 of 69 S6AP413A 5. Block Diagram IN1 PVCC1 <<DD1>> VCC:2.5V to 5.5V L Priority A VCC VCC VCC A PWM Logic Control ErrAMP ctl1 ICOMP VREF18 LX1 AST UVLO LV CNV POR PGND1 SLP CMP DAC PG1 cs1 mode clk scp1 PVCC4 D IN4 <<DD4>> L Priority VCC VCC VCC ctl4 D PWM Logic Control ICOMP LX4 AST UVLO VREF18 LV CNV POR DAC PGND4 SLP CMP PG4 cs4 IN2 mode clk scp4 PVCC2 <<DD2>> L Priority B VCC VCC VCC ErrAMP ctl2 VREF18 B LX2 PWM Logic Control ICOMP AST UVLO LV CNV POR PGND2 SLP CMP DAC PG2 cs2 scp2 mode clk PVCC3 <<DD3>> L Priority VCC VCC VCC ErrAMP ctl3 VREF18 PWM Logic Control ICOMP LX3-1 AST UVLO LV CNV POR SLP CMP DAC VO3 LX3-2 AST PGND3 PG3 cs3 mode xclk scp3 VREF18 DVCC SCL Logic Control SDA Output Voltage Ajuster AVCC CTL1 ctl1 CTL2 ctl2 CTL3 Common Block Logic Control CTLMAIN VREF BGR ctl3 Under Voltage Locked-Out CTL4 Thermal Shut Down VREF18 mode scp* (1.8V) Short Circuit Protection (Timer & Latch) Soft Start Control cs* OSC cIK CT RT xclk GND Document Number: 002-08448 Rev.*A Page 10 of 69 S6AP413A 6. Absolute Maximum Ratings Parameter Symbol LX voltage VVCC1 VVCC2 VCTL1 VCTL2 VLOGIC VPG VOUT VLX Permission loss PD Maximum junction temperature Storage temperature Tjmax TSTG Power supply voltage Terminal voltage Rating Condition AVCC,PVCC input voltage DVCC input voltage CTL1, CTL2, CTL3 input voltage CTLMAIN input voltage SDA,SCL input voltage PG1, PG2, PG3, PG4 drain voltage IN1, IN2, IN3, IN4 input voltage LX1, LX2, LX3, LX4 voltage Ta+25C Thermal resistance(ja):(29.2C /W(*1)) - Unit Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1.0 Max 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 V V V V V V V V 0 3420 mW -55 +125 +125 C C *1: When the IC is mounted on 74mm x 74mm four-layer square epoxy board. IC is mounted on a four-layer epoxy board, which terminal bias, and the IC's thermal pad is connected to the epoxy board. WARNING: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Figure 2. Power Dissipation vs. Operation Ambient Temperature Power dissipation vs. Operation ambient temperature 4000 3500 3000 Pd [mW] 2500 2000 1500 1000 500 0 -40 -20 0 20 40 60 80 100 Temperature[C] Document Number: 002-08448 Rev.*A Page 11 of 69 S6AP413A 7. Recommended Operating Conditions Parameter Symbol Condition Value Typ Min Unit Max 1. Reference control block Power supply voltage Output current for reference voltage Operating temperature VVCC IREF Ta AVCC VREF18 - 2.5 -1 -30 3.3 +25 5.5 0 +85 V mA C 2.5 3.3 5.5 V 0 0 - AVCC 5.5 V V 2. DC/DC channel Power supply voltage VVCC Input voltage PG input voltage VOUT VPG PVCC1, PVCC2, PVCC3, PVCC4 IN1,IN2 PG1, PG2, PG3, PG4 VCTL VMODE CTL1, CTL 2, CTL3, mode CTLMAIN 0 - AVCC V VVCC VLOGIC DVCC SDA,SCL 1.70 0 - 3.50 DVCC V V 3. Input block Input voltage 2 4. I C communication block Power supply voltage Input voltage WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-08448 Rev.*A Page 12 of 69 S6AP413A 8. Electrical Characteristics 8.1 Reference Control Block (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V, Ta = +25C, unless otherwise noted.) Parameter Symbol Condition 1. Reference voltage VVREF2 VVREF3 VREF18 pin = 0mA AVCC pin = 2.5V to 5.5V VREF18 pin = 0mA 1.773 1.800 1.827 V 1.768 1.800 1.832 V VREF18 pin =0mA to -1mA 1.768 1.800 1.832 V 2.156 - 2.20 0.20(*1) 2.244 - V V 0.9 1 1.1 ms 125(*2) 150 - C AVCC x0.7 - AVCC V 0 - 0.4 V 2.5 3.3 4.7 A - - 1 A - 1(*1) - M 2. Under voltage lockout Threshold voltage Hysteresis width [ VCC UVLO ] VTH VH AVCC rising - 3. Over current protection Timer [ OCP ] tOCP1 DD1, DD2, DD3, DD4 4. Thermal shut down Stop temperature [ TSD ] TTSDH - 5. Input block (CTL,mode,CTLMAIN) Input voltage VIH Input voltage VIL Input current ICTLH IMODEH ICTLL IMODEL Input pull-down resistor Unit Max [ VREF18 ] VVREF1 Output voltage Value Typ Min RP [ CTL,CTLMAIN ] CTL1, CTL2, CTL3, CTL4 pin CTLMAIN pin CTL1, CTL2, CTL3, CTL4 pin CTLMAIN pin CTL1, CTL2, CTL3, CTL4 pin = 3.3V CTLMAIN pin = 3.3V CTL1, CTL2, CTL3, CTL4 pin = 0V CTLMAIN pin = 0V CTL1, CTL2, CTL3, CTL4 pin CTLMAIN pin 6. Consumption current (DC/DC converter block) IVCCS1 CTL1, CTL2, CTL3, CTL4 pin = 0V CTLMAIN pin = 0V - 0 1.0 A IVCCS2 CTL1, CTL2, CTL3, CTL4 pin = 0V CTLMAIN pin =3.3V - 30 45 A DD1,DD2,DD3,DD4=ON, All DD are 0mA IVCC 450 670 (operation mode: PFM/PWM mode) DD1,DD2,DD3,DD4=ON, All DD are 0mA IVCC 18 27 (operation mode: Fixed PWM mode) *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. Power supply current A mA *2: No production tested, ensure by design. Document Number: 002-08448 Rev.*A Page 13 of 69 S6AP413A 8.2 DD1 (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25C, unless otherwise noted.) Parameter Symbol Condition 1. DC/DC converter block Value Typ Min Unit Max [ DD1 ] Output voltage VOUT IOUT = -10mA, Output voltage setting: 1.0V Input stability VLINE IOUT = -10mA, PVCC1= 2.5V to 5.5V -5 - +5 mV Load stability VLOAD IOUT = -1mA to -4000mA (Fixed PWM mode) -10 - +10 mV Load stability VLOAD IOUT = -1mA to -4000mA (PFM/PWM mode) -10 - +15 mV IN1 input impedance RIN IN1 = 2.0V - 190(*1) - k RPMOS LX1 = -30mA - 120(*1) - m RNMOS LX1 = 30mA - 80(*1) - m ILEAK LX1 = 0V -3 - - A ILEAK LX1 = 3.3V - - 3 A ILIMIT L=1.0H 2400(*2) - - mA IPFM L=1.0H - 100(*1) - mA RDIS Tss fOSC Soft start time setting: 1ms - 0.9 2.7 5(*1) 1 3.0 1.1 3.3 k ms MHz SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr Leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Soft start time Switching frequency 0.988 1.000 1.012 V *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08448 Rev.*A Page 14 of 69 S6AP413A 8.3 DD2 (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25C, unless otherwise noted.) Parameter Symbol Condition 2. DC/DC converter block Unit Max [ DD2 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD IN2 input impedance RIN SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Soft start time Switching frequency Value Typ Min IOUT = -10mA, Output voltage setting:1.8V IOUT = -10mA PVCC2= 2.5V to 5.5V IOUT = -1mA to -1200mA (Fixed PWM mode) IOUT = -1mA to -1200mA (PFM/PWM mode) 1.778 1.800 1.822 V -5 - +5 mV -10 - +10 mV -10 - +20 mV IN2 = 2.0V - 150(*1) - k RPMOS LX2 = -30mA - 190(*1) - m RNMOS LX2 = 30mA - 135(*1) - m ILEAK LX2 = 0V -3 - - A ILEAK LX2 = 3.3V - - 3 A ILIMIT L=1.0H 1500(*2) - - mA IPFM L=1.0H - 65(*1) - mA RDIS Tss fOSC Soft start time setting:1ms - 0.9 2.7 5(*1) 1 3.0 1.1 3.3 k ms MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08448 Rev.*A Page 15 of 69 S6AP413A 8.4 DD3 (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25C, unless otherwise noted.) Parameter Symbol 3. DC/DC converter block Value Typ Min Unit Max [ DD3 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD VO3 impedance RVo3 SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr leakage current SW PMOS-Tr leakage current SW NMOS-Tr leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Soft start time Switching frequency Condition IOUT = -10mA, Output voltage setting:3.3V IOUT = -10mA, PVCC3= 2.5V to 5.5V IOUT = -1mA to -600mA (Fixed PWM mode) IOUT = -1mA to -600mA (PFM/PWM mode) 3.241 3.300 3.359 V -5 - +5 mV -10 - +10 mV -10 - +15 mV VO3= 2.0V - 550(*1) - k RPMOS LX3-1 = -30mA - 115(*1) - m RNMOS LX3-1 = 30mA - 140(*1) - m RPMOS LX3-2 = -30mA - 155(*1) - m RNMOS LX3-2 = 30mA - 220(*1) - m ILEAK LX3-1 = 0V -3 - - A ILEAK LX3-1 = 3.3V - - 1 A ILEAK LX3-2 = 0V -3 - - A ILEAK LX3-2 = 3.3V - - 1 A ILIMIT L=1.0H 1000(*2) - - mA IPFM L=1.0H - 200(*1) - mA RDIS Tss fOSC Soft start time setting:1ms - 0.9 2.7 5(*1) 1 3.0 1.1 3.3 k ms MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08448 Rev.*A Page 16 of 69 S6AP413A 8.5 DD4 (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25C, unless otherwise noted.) Parameter Symbol 4. DC/DC converter block Condition Value Typ Min Unit Max [ DD4 ] Output voltage VOUT IOUT = -10mA, Output voltage setting: 1.0V 0.988 1.000 1.012 V Input stability VLINE IOUT = -10mA, PVCC4 = 2.5V to 5.5V -5 - +5 mV Load stability VLOAD IOUT = -1mA to -4000mA (Fixed PWM mode) -10 - +10 mV Load stability VLOAD IOUT = -1mA to -4000mA (PFM/PWM mode) -10 - +15 mV IN4 input impedance RIN IN4 = 2.0V - 190(*1) - k RPMOS LX4 = -30mA - 120(*1) - m RNMOS LX4 = 30mA - 80(*1) - m ILEAK LX4 = 0V -3 - - A ILEAK LX4 = 3.3V - - 3 A ILIMIT L=1.0H 2300(*2) - - mA IPFM L=1.0H - 75(*1) - mA RDIS Tss fOSC Soft start time setting: 1ms - 0.9 2.7 5(*1) 1 3.0 1.1 3.3 k ms MHz SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr Leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Soft start time Switching frequency *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08448 Rev.*A Page 17 of 69 S6AP413A 8.6 Digital Block (AVCC = PVCC1=PVCC2=PVCC3=PVCC4= 3.3V supply, PGND1=PGND2=PGND3=PGND4=GND = 0V. Ta = +25C, unless otherwise noted.) Parameter Symbol Condition 1. Power Good block Unit Max [ Power Good ] Output voltage VOL PG1, PG2, PG3, PG4 Output current IOL PG1, PG2, PG3, PG4 Low voltage detection VTH Power on detection VTH IN1, IN2, IN4 = falling VO3 = falling IN1, IN2, IN4 = rising VO3 = rising 2 IOL = 1mA - - 0.4 V 1 - - mA - V - V - Vo0.90 (*1) Vo0.93 (*1) 2 2. I C block [I C] VIH SCL,SDA DVCC x0.7 - DVCC V VIL SCL,SDA 0 - DVCC x0.3 V - - 10 A -10 - - A 3 - 0.4 - V mA Input voltage IIH Input current IIL Output voltage Output current Value Typ Min VOL IOL SCL,SDA DVCC = 3.3V SCL,SDA DVCC = 3.3V SDA IOL = 3mA SDA *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. Document Number: 002-08448 Rev.*A Page 18 of 69 S6AP413A 9. Operation Mode List Table 1. Operation Mode List CTL signal Operation Block 2 Mode CTLMAIN (external) 2 CTL1 (external/I C) 2 CTL2 (external/I C) 2 CTL3 (external/I C) 2 CTL4 (external/I C) Reference Digital DD1 DD2 DD3 DD4 Stand-by L L L L L OFF OFF OFF OFF OFF OFF Stand-by2 H L L L L ON ON OFF OFF OFF OFF Normal H H/L(*1) H/L(*1) H/L(*1) H/L(*1) ON ON ON/OFF ON/OFF ON/OFF ON/OFF Error Detection H X X X X ON ON OFF OFF OFF OFF I Ccommunicati on I Ccommunication disable enable enable enable Protection operating Thermal shut down (TSD) Over current protection(OCP) Not available Not available available (*2) Not available Not available available (*2) 2 *1: normal mode means that CTLMAIN pin is "H" level and each DD CTL pin is "H" level *2: This state is after each err detection. Error state will release, when the power supply voltage or CTLMAIN pin will turn off and on. 2 Priority of the External CTL Pin and I C Communication CTL1, CTL2, CTL3, CTL4 (External) CTLMAIN (External) H H H H L H H L L X 30h Resistor 2 (I C) 1 0 1 0 disable Relevant Channel ON ON ON OFF OFF Notes: 2 * The I C communication is valid after the reference control block and digital block activation setting the external CTLMAIN pin to "H" level. 2 * Please attention below note about ON/OFF control of DD1, DD2,DD3, DD4 by I C communication. 2 When each DD control is turned off by I C communication and external CTL pin remains "H" level, DCDC converter keep operating. Document Number: 002-08448 Rev.*A Page 19 of 69 S6AP413A 10. State Transition Diagram Stand-by (1) (2) Stand-by 2 (3) (2) (4) General (6) (5) Error detection (1) External CTLMAIN pin is "H" level. (2) External CTLMAIN pin is "L" level. (3) External CTL pin or I C communication "relevant CH_ON" (4) External CTL pin or I C communication "relevant CH_OFF" (5) Error detection (TSD, OCP 1ms continuation) (6) Turning on the power supply again (equal to or less than uvlo_vcc rest voltage) or setting CTLMAIN to "L" level 2 2 Document Number: 002-08448 Rev.*A Page 20 of 69 S6AP413A 11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3, CTL4) AVCC PVCC* AVCC=2.0V AVCC=2.2V CTLMAIN CTL* 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) 93% Discharge 93% Discharge 93% Discharge 93% Discharge DD1 PG1 DD2 PG2 DD3 PG3 DD4 PG4 UVLO release to DD* activation Soft-start time Time till start (*1) Typ : (820)s Max : TBD s *1: PVCC1, PVCC2, PVCC3, PVCC4 *2: CTL1, CTL2, CTL3, CTL4 *3: DD1, DD2, DD3, DD4 *4: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08448 Rev.*A Page 21 of 69 S6AP413A 12. Turning ON and OFF Sequence (AVCC CTLMAINCTL1CTL2 CTL3 CTL4) AVCC PVCC* 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) CTL1 Discharge 93% DD1 PG1=CTL2 Discharge 93% DD2 PG2=CTL3 Discharge 93% DD3 PG3=CTL4 93% Discharge DD4 PG4 UVLO release to DD* activation Soft-start time Time till start (*1) Typ : (820)s Max : TBD s *1: PVCC1, PVCC2, PVCC3, PVCC4 *2: DD1, DD2, DD3, DD4 *3: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08448 Rev.*A Page 22 of 69 S6AP413A 13. Turning ON and OFF Sequence (AVCCCTLMAINI2C) AVCC PVCC* 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) I2C(DD ON/OFF) OFF ON OFF ctl* (IC internal signal) 93% Discharge 93% Discharge 93% Discharge 93% Discharge DD1 PG1 DD2 PG2 DD3 PG3 DD4 PG4 UVLO release to DD* activation Soft-start time Time till start (*1) Typ : (820)s Max : TBD s *1: PVCC1, PVCC2, PVCC3, PVCC4 *2: CTL1, CTL2, CTL3 *3: DD1, DD2, DD3 *4: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08448 Rev.*A Page 23 of 69 S6AP413A 14. CTL Pin Threshold Voltage The input circuit structure for the CTL(*1) pin is the Schmitt trigger style, and the threshold voltage shows the hysteresis characteristics when CTL(*1) OFF to ON and ON to OFF. (See "CTL (*1) Pin Equivalent Circuit Diagram" below.) Also, the threshold voltage level depends on the VCC pin voltage. Moreover, make sure to input either the "H" level (>"VCCx0.7"V) or "L" level (<0.4V) to the CTL(*1)pin when in use. Figure 3. CTL (*1) Pin Equivalent Circuit Diagram AVCC The CTL threshold voltage shows the hysteresis characteristics. ESD protection element CTL* ESD protection element GND *1: CTLMAIN, CTL1, CTL2, CTL3, CTL4 Document Number: 002-08448 Rev.*A Page 24 of 69 S6AP413A 15. Protection Operation Sequence Over Current Protection (DD channel) The DD channel monitors the peak current of FET at any time during the operation. When the DD output becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress. When one of each DD channel stops operation by over current protection, all DD channels stop operation. Thermal Shut Down If the temperature at the junction part reaches +150C, the thermal shutdown protection circuit turns all channels off. Error Detection Sequence Figure 4. Error Detection Sequence DD1,DD2,DD3,DD4 The whole IC Normal operation Normal operation Over current detection Thermal shutdown protection Voltage drop No 1ms Continue for 1ms? Yes Error detection mode Error signal output (I2C address 40h) Error Detection Mode Release It is necessary to turn the power supply turning on again, or to turn CTLMAIN turning on again to release the error detection mode. Document Number: 002-08448 Rev.*A Page 25 of 69 S6AP413A 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit Operation Whilst Under Protection Channel Under Voltage Lockout Protection (UVLO) Over Current Protection (OCP) Operating condition: Chip temperature increment Operating condition: After about 1ms progress in the over current condition DD1,DD2,DD3, DD4 Error output (address 40h) Discharge - Thermal Shutdown Protection (TSD) Operating condition: Input voltage drop Process during protection operation: DD1, DD2, DD3, DD4 stop Process during protection operation: DD1, DD2, DD3, DD4 stop Recovery condition: Input voltage rise Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted UVLO operates only when CTLMAIN is "H" (at VREF18 output). Write "1" when detecting OCP No change Process during protection operation: DD1, DD2, DD3, DD4 stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted Only when CTLMAIN is in the "H" state and CTL(*1) is in the "H" state, or when DD(*2) in operating 2 condition by I C, will operate. Write "1" when detecting TSD Thermal shutdown protection (TSD) operation during over current protection timer operation When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal shutdown protection has priority. Operation when releasing under voltage lockout protection (UVLO) 2 * DD1,DD2,DD3,DD4: Activation following the condition for CTL(*1) pin or I C Note: 2 * When VREF18 decreases at the time of UVLO operation, I C register is reset, and all DD does OFF. It is necessary to let you do ON by CTL(*1) pin and communication again to let DD have ON." *1: CTL1, CTL2, CTL3, CTL4 *2: DD1, DD2, DD3, DD4 Document Number: 002-08448 Rev.*A Page 26 of 69 S6AP413A 17. DD Soft Start Operation The soft-start operation for DD1, DD2, DD3 and DD4 is enabled in order to prevent the rush current during the DD activation. The 2 soft-start time can be controlled by I C. About output voltage changing option, soft start time is showed by follow equation. Tss=Tslp x Vset/Vdef (ms) Tss: soft start time Tslp: slope coefficient of soft start Vset: output voltage setting Vdef: DD1=1.0, DD2=1.8, DD3=3.3, DD4=1.0 Figure 5. DD Soft Start Output voltage2 setting value Output voltage1 setting value Output voltage3 setting value Soft-start time Channel ON/OFF signal (internal signal) t Document Number: 002-08448 Rev.*A Page 27 of 69 S6AP413A 18. Discharge Operation DD Channel When executing the DD OFF operation at the channel ON/OFF signal, the DC/DC smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load) toff(s) 2.3 xR_DIS xCOUT (F) Note: * See the table in Electrical Characteristics for the discharge resistor value. Figure 6. Discharge Function IN(*1) A Resistor for discharge R1 PVCC(*2) A Error Amp R2 LX(*3) Cout Reference voltage DAC PGND(*4) Channel ON/OFF Cont. *1: IN1, IN2, IN3, IN4 *2: PVCC1, PVCC2, PVCC3, PVCC4 *3: LX1, LX2, LX3, LX4 *4: PGND1, PGND2, PGND3, PGND4 Document Number: 002-08448 Rev.*A Page 28 of 69 S6AP413A 19. PG Function The following pins for each channel Power Good output are prepared. PG1 It is the pin for DD1 Power Good output. When the output voltage exceeds 93% of the setting value at the DD1 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD1 OFF mode. PG2 It is the pin for DD2 Power Good output. When the output voltage exceeds 93% of the setting value at the DD2 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD2 OFF mode. PG3 It is the pin for DD3 Power Good output. When the output voltage exceeds 93% of the setting value at the DD3 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD3 OFF mode. PG4 It is the pin for DD4 Power Good output. When the output voltage exceeds 93% of the setting value at the DD4 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD4 OFF mode. Document Number: 002-08448 Rev.*A Page 29 of 69 S6AP413A 20. I2CInterface 2 20.1 Structure of I C Interface 2 The I C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a SDA (serial data line). This bus is connected to multiple devices; Master: device to generate the clock signal and to control the data transfer (CPU and so on) Slave: device that an address is specified by a master. This IC is set as the slave and has no function to be the master. Each device is defined due to the communication direction as described below. Transmitter: device to send data to bus Receiver: device to receive data from bus The IC has the function both transmitter and receiver. SCL SDA transmitter receiver receiver maser transmitter slave1 slave2 The IC defines the followings; Write: data is transmitted from master and the IC receives data Read: The IC transmits data and master receives data. 20.2 Definition of Signal Lines SCL and SDA are connected to the power supply by the pull-up resistor. The output circuit is the open Drain output. When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state. Note: 2 * SCL and SDA pins adopt a different ESD protection system from standard I C specification because of ESD enhancement (See 22.I/O Pin Equivalent Circuit Diagram). When the power supply is in the bus line, do not shut off the power supply for an IC (DVCC). I2C bus line power supply R R Pull Up SCL SDA input Inside of IC Document Number: 002-08448 Rev.*A input output Page 30 of 69 S6AP413A 20.3 Validity of Data Data has the following characteristics; * Change when SCL is the "L" level * Valid if the state is kept while SCL is the "H" level. SCL SDA data state data change data state The SDA signal change means the start or stop condition when SCL is the "H" level. 20.4 Definition of Start and Stop Condition The start and stop conditions are output from the master and shows start and stop of communications to the slave. * Start: SDA changes from "H" to "L" when SCL is "H". * Stop: SDA changes from "L" to "H" when SCL is "H". SCL SDA S start condition Document Number: 002-08448 Rev.*A P stop condition Page 31 of 69 S6AP413A 20.5 ACK Signal This is a signal to confirm the data reception during communication. The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master generates. * A transmitter keeps SDA output "open H" in SCL9clk. * A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 calk ; When data was received: SDA output "L" (ACK) When no data was received: SDA output "open H" (NACK) However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the stop condition reception waiting state from the master. SCL from master SDA by transmitter 1 8 bit0 bit7 9 H hold 10 bit0 NACK SDA by receiver ACK Document Number: 002-08448 Rev.*A Page 32 of 69 S6AP413A 2 20.6 I C Interface Input Timing (Within recommended operating conditions) Value Parameter Symbol SCL=100kHz Min SCL clock frequency Start condition hold time Restart condition setup time Stop condition setup time Stop to Start bus open time SCL "L" time SCL "H" time SCL/SDA rising time SCL/SDA falling time Data hold time Data setup time SCL/SDA capacitor load fSCL tHD:start tSU:start tSU:stop tbuf tLow tHigh tr tf tHD:data tSU:data Cb 4.0 4.7 4.0 4.7 4.7 4.0 0.0 0.25 - Max 100 1.0 0.3 400 SCL=400kHz Min 0.6 0.6 0.6 1.3 1.3 0.6 0.0 0.10 - Unit Max 400 0.3 0.3 400 kHz s s s s s s s s s s pF VIH/VIL level reference 2 Conform to I C bus specifications S tr tf tHigh tLow Sr P SCL tbuf SDA tHD:start Document Number: 002-08448 Rev.*A tSU:data tHD:data tSU:start tSU:stop Page 33 of 69 S6AP413A 20.7 Slave Address 2 This is a slave address when communicating with the I C interface. The slave address of this IC is set by the first seven bits as shown below. The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will be written from the master to the slave. The bit "1" shows that the master reads information from the slave. This does not support the general call address. slave address S T A R T 0 1 MSB Document Number: 002-08448 Rev.*A 0 1 1 0 0 R/W LSB A C K S T O P Page 34 of 69 S6AP413A 2 20.8 Bit Structure of Data on I C Interface 1. Writing Data to Register and Reading Data The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB). S T A R T No. A C K slave address 1 2 3 4 5 6 7 8 register address 1 S 0 1 0 1 1 0 0 W A C K 2 3 4 5 6 7 8 0 0 0 0 0 0 1 0 S A T C O K P data 1 2 3 4 5 6 7 8 a b c d e f g h P register data address 00 H 01 H 02 H 03 H 04 H : : D07 D06 D05 D04 D03 D02 D01 D00 a b c d e f g h Output the "stop" condition after sending the Write data. : Signal which a master sends, Document Number: 002-08448 Rev.*A : Signal which this IC sends Page 35 of 69 S6AP413A 2 2. I C Interface Data Format 2 About I C Communication 1. 2. 3. 4. When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting. If a non-existing register address is specified, data is not written to a register. Output the "stop" condition after sending the write data. <Write (W)> S T A R T slave address A C K register address A C K data S A T C O K P S 0 1 0 1 1 0 0 W P Write is allowed per one address. (Sequential writing is not allowed.) Send register address and data as one unit. : Signal which a master sends, : Signal which this IC sends <Read(R)> S T A R T A C K slave address register address S T A A C R K T S 0 1 0 1 1 0 0 W slave address A C K S 0 1 0 1 1 0 0 R data S A T C O K P P Read is allowed per one address. Be sure to perform read by specifying the register addresses. (Sequential reading is not allowed.) : Signal which a master sends, Document Number: 002-08448 Rev.*A : Signal which this IC sends Page 36 of 69 S6AP413A 21. Structure of I2C Interface and Data Table 2. Register map Addr ess Data Writing Timing d03 d02 d01 d00 Defa ult D04 D03 D02 D01 D00 0FH ACK 0 0 D03 D02 D01 D00 0CH ACK 0 0 0 0 D02 D01 D00 05H ACK 0 0 0 D04 D03 D02 D01 D00 0FH ACK 10H 0 0 0 0 D03 D02 D01 D00 00H ACK 11H 0 0 0 0 D03 D02 D01 D00 00H ACK 12H 0 0 0 0 D03 D02 D01 D00 00H ACK 13H 0 0 0 0 D03 D02 D01 D00 00H ACK DD operation mode 20H 0 0 0 0 D03 D02 D01 D00 00H ACK ON/OFF 30H 0 0 0 0 D03 D02 D01 D00 00H ACK Error 40H 0 0 0 D04 D03 D02 D01 D00 00H - PG 50H 0 0 0 0 D03 D02 D01 D00 00H - For test For test EXH FXH - - - - - - - - - - Output voltage d07 d06 d05 00H 0 0 0 01H 0 0 02H 0 03H d04 Soft start Remarks DD1 output voltage setting DD2 output voltage setting DD3 output voltage setting DD4 output voltage setting DD1 soft-start time setting DD2 soft-start time setting DD3 soft-start time setting DD4 soft-start time setting DD operation mode setting "0": Fixed PWM mode, "1":PFM/PWM mode DD output ON/OFF setting "0":Output OFF / "1":Output ON DD error state monitoring register (read only) "0":Normal / "1":Error detection DD PG state monitoring register (read only) "0":Non-output / "1":output Disabled Disabled Note: * Address FXH and address EXH are for test. Do not write/read FXH and EXH. Document Number: 002-08448 Rev.*A Page 37 of 69 S6AP413A 21.1 About DD1, DD4 Output Voltage Setting Address 00H DD1 is allocated as resisters for the DC/DC output voltage setting. Address 03H DD4 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD1 is controlled by writing data to address 00H. The DC/DC output voltage setting of DD4 is controlled by writing data to address 03 H. Data S T A R T 0 0 0 D04 D03 MSB D02 D01 D00 LSB A C K S T O P address00H: For DD1 output voltage setting address03H: For DD4 output voltage setting D04 to D00: Set the output voltage DD1, DD4 Output Voltage Setting Table Data Output Voltage (V) Data Output Voltage (V) 00H 0.700 10H 1.020 01H 0.720 11H 1.040 02H 0.740 12H 1.060 03H 0.760 13H 1.080 04H 0.780 14H 1.100 (*1) 05H 0.800 15H 1.120 06H 0.820 16H 1.140 07H 0.840 17H 1.160 08H 0.860 18H 1.180 09H 0.880 19H 1.200 (*1) 0AH 0.900 (*1) 1AH 1.220 0BH 0.920 1BH 1.240 0CH 0.940 1CH 1.260 0DH 0.960 1DH 1.280 1EH 1FH 1.300 1.320 0EH 0.980 0FH 1.000 (*1) *1: Preset value Document Number: 002-08448 Rev.*A Page 38 of 69 S6AP413A 21.2 About DD2 Output Voltage Setting Address 01H DD2 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD2 is controlled by writing data to address 01 H. Data S T A R T 0 0 MSB 0 0 D03 D02 D01 D00 LSB A C K S T O P address01H: For DD2 output voltage setting D03 to D00: Set the output voltage DD2 Output Voltage Setting Table 00H Output Voltage(V) 1.200 (*1) 01H 1.250 02H 1.300 03H 1.350 (*1) 04H 1.400 05H 1.450 06H 1.500 (*1) 07H 1.550 08H 1.600 09H 1.650 0AH 1.700 0BH 1.750 0CH 1.800 (*1) 0DH 1.850 0EH 1.900 Data 0FH 1.950 *1: Preset value Document Number: 002-08448 Rev.*A Page 39 of 69 S6AP413A 21.3 About DD3 Output Voltage Setting Address 02H DD3 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD3 is controlled by writing data to address 02 H. Data S T A R T 0 0 MSB 0 0 0 D02 D01 D00 LSB A C K S T O P address02H: For DD3 output voltage setting D02 to D00: Set the output voltage DD3 Output Voltage Setting Table Data Output Voltage(V) 00H 2.80 (*1) 01H 2.90 02H 3.00 (*1) 03H 3.10 04H 3.20 05H 3.30 (*1) 06H 3.40 07H 3.50 (*1) *1: Preset value Document Number: 002-08448 Rev.*A Page 40 of 69 S6AP413A 21.4 About Soft Start Time Addresses 10H to 12H are allocated as registers for the soft start time control. The soft start time control is controlled by writing data to addresses 10 H to 12H. Data S T A R T 0 0 0 0 MSB D03 D02 D01 D00 LSB A C K S T O P address10H: For DD1 soft start time setting address11H: For DD2 soft start time setting address12H: For DD3 soft start time setting address13H: For DD4 soft start time setting D03 to D00: Set the soft start time Tss=Tslp x Vset/Vdef (ms) Tss: soft start time Tslp: slope coefficient of soft start: refer to follow table Vset: output voltage setting Vdef: DD1=1.0, DD2=1.8, DD3= 3.3, DD4=1.0 Soft Start Time Setting 00H Data Tslp 1.0 01H 2.0 02H 3.0 03H 4.0 04H 5.0 05H 6.0 06H 7.0 07H 8.0 08H 9.0 09H 10.0 0AH 11.0 0BH 12.0 0CH 13.0 0DH 14.0 0EH 15.0 0FH *1: Preset value Remarks DD1,DD2,DD3,DD4 (*1) 16.0 Document Number: 002-08448 Rev.*A Page 41 of 69 S6AP413A 21.5 DC/DC Operation Mode Address 20H is allocated as a register for the DC/DC operation mode control. The DC/DC operation mode is controlled by writing data to address 20 H. Data S T A R T 0 0 0 0 D03 D02 MSB D01 D00 LSB A C K S T O P address20H: For DC/DC operation mode setting D01 to D00: Set the DC/DC operation mode Address Bit 20H D00 20H D01 20H D02 20H D03 Description 0: DD1 Fixed PWM (*1) 1: DD1 PFM/PWM 0: DD2 Fixed PWM (*1) 1: DD2 PFM/PWM 0: DD3 Fixed PWM (*1) 1: DD3 PFM/PWM 0: DD4 Fixed PWM (*1) 1: DD4 PFM/PWM *1: Preset value Document Number: 002-08448 Rev.*A Page 42 of 69 S6AP413A 21.6 ON/OFF for DC/DC Address 30H is allocated as a register for the DC/DC ON/OFF. The DC/DC ON/OFF is controlled by writing data to address 30H. Data S T A R T 0 0 0 0 D03 D02 MSB D01 D00 LSB A C K S T O P address30H: For DC/DC ON/OFF D02 to D00: Set ON/OFF for DC/DC Address Bit 30H D00 30H D01 30H D02 30H D03 Description 0: DD1 output OFF (*1) 1: DD1 output ON 0: DD2 output OFF (*1) 1: DD2 output ON 0: DD3 output OFF (*1) 1: DD3 output ON 0: DD4 output OFF (*1) 1: DD4 output ON *1: Preset value Document Number: 002-08448 Rev.*A Page 43 of 69 S6AP413A 21.7 About Error Monitor Address 40H is allocated as error status monitor of each DC/DC output and thermal shut down. Address 40H is read only resistor. Data S T A R T 0 0 0 D04 D03 D02 MSB D01 D00 LSB A C K S T O P address40H: For error monitor of each DC/DC output and thermal shut down D04 to D00: read only resistor. (Not allowed write resistor) Address Bit 40H D00 40H D01 40H D02 40H D03 40H D04 Description 0: DD1 OCP non detection (*1) 1: DD1 OCP detection 0: DD2 OCP non detection (*1) 1: DD2 OCP detection 0: DD3 OCP non detection (*1) 1: DD3 OCP detection 0: DD4 OCP non detection (*1) 1: DD4 OCP detection 0: TSD non detection (*1) 1: TSD detection *1: Preset value Document Number: 002-08448 Rev.*A Page 44 of 69 S6AP413A 21.8 About Power Good Monitor Address 50H is allocated as output monitor of each DC/DC output. Address 50H is read only resistor. Data S T A R T 0 0 0 0 D03 D02 MSB D01 D00 LSB A C K S T O P address50H: For output monitor of each DC/DC output. Detection level is over 93% of DCDC output voltage setting. D04 to D00: read only resistor. (Not allowed write resistor) Address Bit 50H D00 50H D01 50H D02 50H D03 Description 0: DD1 non output (*1) 1: DD1 output 0: DD2 non output (*1) 1: DD2 output 0: DD3 non output (*1) 1: DD3 output 0: DD4 non output (*1) 1: DD4 output *1: Preset value Document Number: 002-08448 Rev.*A Page 45 of 69 S6AP413A 22. I/O Pin Equivalent Circuit Diagram <<AVCC>> AVCC ESD protection element GND <<VREF18>> AVCC VREF18 GND <<IN1,IN2,IN4,LX1,LX2,LX4,PGND1,PGND2,PGND4>> AVCC IN* GND IN*: IN1, IN2, IN4 LX*: LX1, LX2, IN4 PGND*: PGND1, PGND2, PGN4 Document Number: 002-08448 Rev.*A LX* PGND* Page 46 of 69 S6AP413A <<PVCC1,PVCC2,PVCC4> AVCC PVCC*: PVCC1, PVCC2, PVCC4 LX*: LX1, LX2, LX4 PGND*: PGND1, PGND2, PGND4 PVCC* LX* PGND* GND <<IN3,PGND3 > IN3 GND PGND3 <<PVCC3,LX3-1,LX3-2,VO3>> AVCC PVCC3 LX3-1 VO3 LX3-2 PGND3 GND Document Number: 002-08448 Rev.*A Page 47 of 69 S6AP413A <<CTL*>> AVCC <<PG*>> AVCC PG*: PG1, PG2, PG3, PG4 PG* CTL* GND CTL*: CTLMAIN, CTL1, CTL2, CTL3, CTL4 GND <<SCL>> <<SDA>> DVCC DVCC SCL SDA GND Document Number: 002-08448 Rev.*A GND Page 48 of 69 S6AP413A 23. Measurement Circuit for Characteristics of General Operation S6AP413A Input Voltage: 2.5V to 5.5V C1 0.1mF AVCC IN1 L1 LX1 C2 4.7mF C7 47mF PVCC1 PGND1 R1 100kW CTL1 PG1 PG1 C3 4.7mF PVCC2 IN2 LX2 CTL2 L2 C8 22mF PGND2 C4 4.7mF DD1:1.0V Io(max):2000mA PVCC3 DD2:1.80V Io(max):1200mA R2 100kW PG2 PG2 LX3-1 CTL3 L3 C5 4.7mF PVCC4 LX3-2 VO3 C9 33mF CTL4 PGND3 3.3V R3 100kW PG3 CTLMAIN DVCC IN4 SCL SDA LX4 PG3 L4 SCL SDA PGND4 PG4 VREF18 DD3:3.30V Io(max):600mA C10 47mF DD4:1.0V Io(max):2000mA R4 100kW PG4 GND C6 1.0mF Document Number: 002-08448 Rev.*A Page 49 of 69 S6AP413A Table 3. Parts list Symbol L1 L2 L3 L4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 R1 R2 R3 R4 Parts Inductor Inductor Inductor Inductor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Resistor Resistor Resistor Resistor TOKO : TOKO, INC. TDK : TDK Corporation SSM : SUSUMU CO., LTD. Document Number: 002-08448 Rev.*A Part Number 1276AS-H-1R0M 1276AS-H-1R0M 1276AS-H-1R0M 1276AS-H-1R0M C1608X5R1H104K C1608X5R1V475K C1608X5R1V475K C1608X5R1V475K C1608X5R1V475K C2012X5R1A336M C2012X5R1A476M C1608X5R1A226M C2012X5R1A336M C2012X5R1A476M RR0816P-104-D RR0816P-104-D RR0816P-104-D RR0816P-104-D Specifications 1.0H 1.0H 1.0H 1.0H 0.1F 4.7F 4.7F 4.7F 4.7F 1.0F 47F 22F 33F 47F 100k 100k 100k 100k Vendor TOKO TOKO TOKO TOKO TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK SSM SSM SSM SSM Page 50 of 69 S6AP413A 24. Reference Data Inductor and capacitor value refer to section 26. DCDC Convertor Efficiency Data DD1,DD4 Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.2V setting 90 80 80 70 70 Efficiency[%] 100 90 Efficiency[%] 100 60 50 40 30 20 0 0.00001 50 40 30 20 Fixed PWM 10 60 0.001 0.1 Load current[A] 0 0.00001 10 Input voltage = 5.5V, Vo = 1.0V setting 80 70 70 Efficiency[%] 90 80 Efficiency[%] 100 90 60 50 40 30 0 0.00001 0.001 0.1 Load current[A] 10 50 40 30 Fixed PWM 10 PFM/PWM 0.001 0.1 Load current[A] 60 20 Fixed PWM 10 PFM/PWM Input voltage = 5.5V, Vo = 1.2V setting 100 20 Fixed PWM 10 PFM/PWM 0 0.00001 10 PFM/PWM 0.001 0.1 Load current[A] 10 DD2 Input voltage = 3.3V, Vo = 1.8V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input Voltage = 3.3V, Vo = 1.5V setting 60 50 40 30 20 0 0.00001 Document Number: 002-08448 Rev.*A 40 30 Fixed PWM 10 PFM/PWM 0.001 0.1 Load current[A] 50 20 Fixed PWM 10 60 10 0 0.00001 PFM/PWM 0.001 0.1 Load current[A] 10 Page 51 of 69 S6AP413A DD2 Input voltage = 5.5V, Vo = 1.5V setting Input Voltage = 5.5V, Vo = 1.8V setting 90 80 80 70 70 Efficiency[%] 100 90 Efficiency[%] 100 60 50 40 30 50 40 30 20 20 Fixed PWM 10 0 0.00001 60 0.001 0.1 Load current[A] Fixed PWM 10 PFM/PWM 0 0.00001 10 PFM/PWM 0.001 0.1 Load current[A] 10 DD3 Input Voltage = 5.5V, Vo = 3.3V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input voltage = 3.3V, Vo = 3.3V setting 60 50 40 30 20 50 40 30 20 Fixed PWM PFM/PWM 10 0 0.00001 60 0.001 0.1 Load current[A] Document Number: 002-08448 Rev.*A Fixed PWM PFM/PWM 10 10 0 0.00001 0.001 0.1 Load current[A] 10 Page 52 of 69 S6AP413A DCDC Convertor Regulation Data DD1,DD4 Input voltage = 3.3V, Vo = 1.0V setting Input voltage = 3.3V, Vo=1.2V setting 1.220 1.020 1.215 Output voltage[V] Output voltage[V] 1.015 1.010 1.005 1.000 0.995 0.990 Fixed PWM 0.985 PFM/PWM 1.210 1.205 1.200 1.195 1.190 Fixed PWM 1.185 PFM/PWM 1.180 0.980 0.0 0.5 1.0 1.5 0.0 2.0 1.020 1.220 1.015 1.215 1.010 1.210 1.005 1.000 0.995 0.985 PFM/PWM 1.5 2.0 Input voltage = 5.5V, Vo = 1.2V setting Output voltage[V] Output voltage[V] Input voltage = 5.5V, Vo = 1.0V setting 0.990 1.0 Load current[A] Load current[A] Fixed PWM 0.5 1.205 1.200 1.195 1.190 Fixed PWM 1.185 PFM/PWM 1.180 0.980 0.0 0.5 1.0 1.5 Load current[A] 0.0 2.0 0.5 1.0 1.5 Load current[A] 2.0 DD2 Input voltage = 3.3V, Vo = 1.8V setting 1.520 1.820 1.515 1.815 1.510 1.810 Output voltage[V] Output voltage[V] Input Voltage = 3.3V, Vo = 1.5V setting 1.505 1.500 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 1.805 1.800 1.795 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] Document Number: 002-08448 Rev.*A 1.2 0.0 0.4 0.8 Load current[A] 1.2 Page 53 of 69 S6AP413A DD2 Input Voltage = 5.5V, Vo = 1.8V setting 1.520 1.820 1.515 1.815 1.510 1.810 Output voltage[V] Output voltage[V] Input voltage = 5.5V, Vo = 1.5V setting 1.505 1.500 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 1.805 1.800 1.795 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] 1.2 0.0 0.4 0.8 Load current[A] 1.2 DD3 Input Voltage = 5.5V, Vo = 3.3V setting 3.320 3.320 3.315 3.315 3.310 3.310 Output voltage[V] Output voltage[V] Input voltage = 3.3V, Vo = 3.3V setting 3.305 3.300 3.295 3.290 Fixed PWM 3.285 PFM/PWM 3.280 3.305 3.300 3.295 3.290 Fixed PWM 3.285 PFM/PWM 3.280 0.0 0.2 0.4 Load current[A] Document Number: 002-08448 Rev.*A 0.6 0.0 0.2 0.4 Load current[A] 0.6 Page 54 of 69 S6AP413A DCDC Convertor Output Ripple Voltage DD1, DD4 Input voltage = 3.3V, Vo = 1.0V setting Load current = 0mA , Fixed PWM 10mV/div,0.5s/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , Fixed PWM 10mV/div,0.5s/div Input voltage = 3.3V, Vo = 1.0V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , PFM/PWM 10mV/div,2ms/div Document Number: 002-08448 Rev.*A Input voltage = 3.3V, Vo=1.0V setting Load current = 2000mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 2000mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo=1.0V setting Load current = 2000mA,PFM/PWM 10mV/div,0.5s/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 2000mA,PFM/PWM 10mV/div, 0.5s/div Page 55 of 69 S6AP413A DD2 Input voltage = 3.3V, Vo = 1.8V setting Load current = 0mA , Fixed PWM 10mV/div,0.5s/div Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo = 1.8V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div Document Number: 002-08448 Rev.*A Input voltage = 3.3V, Vo=1.8V setting Load current = 1200mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.8V setting Load current =1200mA, Fixed PWM 10mV/div,0.5s/div Input voltage = 3.3V, Vo=1.8V setting Load current =1200mA,PFM/PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.8V setting Load current = 1200mA,PFM/PWM 10mV/div,0.5s/div Page 56 of 69 S6AP413A DD3 Input voltage = 3.3V, Vo = 3.3V setting Load current = 0mA , Fixed PWM 10mV/div,0.5s/div Input voltage = 5.5V, Vo = 3.3V setting Load current = 0mA , Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo = 3.3V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , PFM/PWM 10mV/div, 2ms/div Document Number: 002-08448 Rev.*A Input voltage = 3.3V, Vo=3.3V setting Load current = 600mA, Fixed PWM 10mV/div,0.5s/div Input voltage = 5.5V, Vo = 3.3V setting Load current =600mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo=3.3V setting Load current = 600mA,PFM/PWM 10mV/div,0.5s/div Input voltage = 3.3V, Vo =3.3V setting Load current = 600mA,PFM/PWM 10mV/div, 0.5s/div Page 57 of 69 S6AP413A DCDC Convertor Enable/disable DD1,DD4(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = 2000mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.0ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 500ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD1,DD4(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = 2000mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.0ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 500ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = 1200mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.02ms Vo(1V/div) Vo(1V/div) 200us/div 200ms 50ms/div IIN(500mA/div) IIN(40mA/div) Document Number: 002-08448 Rev.*A Page 58 of 69 S6AP413A DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = 1200mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.03ms Vo(1V/div) Vo(1V/div) 200us/div 204ms 50ms/div IIN(500mA/div) IIN(40mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 0.99ms Vo(2V/div) 200us/div Vo(2V/div) 255ms 100ms/div IIN(500mA/div) IIN(40mA/div) DD3 (PFM/PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 1.0ms Vo(2V/div) Vo(2V/div) 200us/div 255ms 100ms/div IIN(500mA/div) IIN(40mA/div) Document Number: 002-08448 Rev.*A Page 59 of 69 S6AP413A DCDC Convertor Load Transient DD1(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = from 0mA to 2000mA per 10us Input voltage = 3.3V, Vo=1.0V setting Load current = from 2000mA to 0mA per 10us Vo1(30mV/div) offset1.0V 40.5mV Vo1(100mV/div) offset1.000V 43.3mV 10us 10us Io(2.0A/div) Io(1.0A/div) DD1(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = from 0mA to 2000mA per 10us Vo1(30mV/div) offset1.0V Input voltage = 3.3V, Vo=1.0V setting Load current = from 2000mA to 0mA per 10us Vo1(30mV/div) offset1.0V 40.5mV 42.9mV 50ms 10us Io(1.0A/div) Io(1.0A/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = from 0mA to 1200mA per 10us Vo2(50mV/div) offset1.8V Input voltage = 3.3V, Vo=1.8V setting Load current = from 1200mA to 0mA per 10us 54.1mV Vo1(50mV/div) offset1.8V 54.8mV 10us 10us Io(1.0A/div) Io(1.0A/div) Document Number: 002-08448 Rev.*A Page 60 of 69 S6AP413A DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = from 0mA to 1200mA per 10us Input voltage = 3.3V, Vo=1.8V setting Load current = from 1200mA to 0mA per 10us 57.1mV Vo2(50mV/div) offset1.8V Vo1(50mV/div) offset1.8V 54.0mV 10ms 10us Io(1.0A/div) Io(1.0A/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Vo3(50mV/div) offset3.3V Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting Vo3(50mV/div) offset3.3V 57.1mV 67.4mV 10us 10us Io(500mA/div) Io(500mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Vo3(50mV/div) offset3.3V Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting Vo3(100mV/div) offset3.3V 81.7mV 84.1mV 20ms 10us Io(500mA/div) Io(500mA/div) Document Number: 002-08448 Rev.*A Page 61 of 69 S6AP413A DCDC Convertor DVFS Function DD1 (Fixed PWM) Input voltage = 3.3V, 2 Vo =from 0.7V to 1.32V setting by I C Input voltage = 3.3V 2 Vo =from 1.32V to 0.7V setting by I C SCL (2V/div) SCL (2V/div) PG (5V/div) PG (5V/div) Vo1 (200mV/div) offset0.7V Document Number: 002-08448 Rev.*A 100us Vo1 (200mV/div) offset0.7V 100us Page 62 of 69 S6AP413A 25. Ordering Information Table 4. Ordering Information Part Number S6AP413A18GN1C000 S6AP413A19GN1C000 S6AP413A1AGN1C000 S6AP413A1BGN1C000 S6AP413A28GN1C000 S6AP413A29GN1C000 S6AP413A2AGN1C000 S6AP413A2BGN1C000 S6AP413A38GN1C000 S6AP413A39GN1C000 S6AP413A3AGN1C000 S6AP413A3BGN1C000 S6AP413A5AGN1C000 S6AP413A5BGN1C000 S6AP413A69GN1C000 S6AP413A6AGN1C000 S6AP413A6BGN1C000 S6AP413A79GN1C000 S6AP413A7AGN1C000 S6AP413A7BGN1C000 S6AP413A9AGN1C000 S6AP413A9BGN1C000 S6AP413AAAGN1C000 S6AP413AABGN1C000 S6AP413ABAGN1C000 S6AP413ABBGN1C000 S6AP413ADBGN1C000 S6AP413AEBGN1C000 S6AP413AFBGN1C000 Package Remarks 32-pin plastic QFN (WNT032) Document Number: 002-08448 Rev.*A Page 63 of 69 S6AP413A 26. Preset Code List Preset Code DD1 Output Voltage Preset Code Value DD2 Output Voltage Preset Code Value 18 19 1A 1B 28 29 2A 2B 38 39 3A 3B 59 5A 5B 69 6A 6B 79 7A 7B 9A 9B AA AB BA BB DB EB FB 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 0.90V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.00V 1.10V 1.10V 1.10V 1.10V 1.10V 1.10V 1.20V 1.20V 1.20V 1.35V 1.35V 1.35V 1.35V 1.50V 1.50V 1.50V 1.50V 1.80V 1.80V 1.80V 1.80V 1.35V 1.35V 1.35V 1.50V 1.50V 1.50V 1.80V 1.80V 1.80V 1.35V 1.35V 1.50V 1.50V 1.80V 1.80V 1.35V 1.50V 1.80V Document Number: 002-08448 Rev.*A DD3 Output Voltage Preset Code Value 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V 3.30V DD3 Output Voltage Preset Code Value 0.90V 1.00V 1.10V 1.20V 0.90V 1.00V 1.10V 1.20V 0.90V 1.00V 1.10V 1.20V 1.00V 1.10V 1.20V 1.00V 1.10V 1.20V 1.00V 1.10V 1.20V 1.10V 1.20V 1.10V 1.20V 1.10V 1.20V 1.20V 1.20V 1.20V Page 64 of 69 S6AP413A 27. Layout Consider the points listed below and do the layout design. * Provide the ground plane as much as possible on the IC mounted face. GND and PGNDx provide the through hole proximal to GND and PGNDx pins of IC, and connect it with GND of internal layer. * Provide the power plane as much as possible to lower impedance of VCC. * Play the most attention to the loop composed of input capacitor (CPVCCx) and SWFET. Input capacitor (CPVCCx) connected with PVCCx should be placed close to the pin as much as possible to make the current loop as small as possible. Also connect the GND pin of the input capacitor with PGNDx. * Output capacitor (CVO3) connected with VO3 should be placed close to the pin as much as possible. Also connect the GND pin of the output capacitor with PGND3. * GND pins of the switching system parts provide the through hole at the proximal place, and connect it with GND of internal layer. * By-pass capacitor (CVREF, CAVCC) connected with VREF and AVCC should be placed close to the pin as much as possible. Also connect the GND pin of the by-pass capacitor with GND of internal layer in the proximal through-hole. * Pull the feedback line to be connected to the INx pin of the IC separately from near the output capacitor pin, whenever possible. Consider the line connected with INx pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. * There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with inductor). Switching system parts: Input capacitor (CPVCCx), Inductor (L), Output capacitor(CVOx) Note: * x: Each channel number Figure 7. Layout Example Layout example of switching components 1 Layout example of IC CPVCC1 GND PVCC4 PGND4 PVCC1 PGND1 CPVCC4 PGNDx PVCCx CPVCCx CVREF VREF Through Hole L AVCC CAVCC GND (Top View) CVOx Output voltage VO3 feedback PVCC2 PVCC3 PGND3 PGND2 VO3 GND 1pin CPVCC3 CVO3 To the LX3-2 pin PVCC3 CPVCC2 PGND3 L Surfase Layer Output voltage VOx feedback Layout example of switching components 2 EP(Exposed Pad) CVO3 To the LXx pin CPVCC3 Inner Layer To the LX3-1 pin Document Number: 002-08448 Rev.*A GND Page 65 of 69 S6AP413A 28. Package Dimensions Document Number: 002-08448 Rev.*A Page 66 of 69 S6AP413A 29. Major Changes Spansion Publication Number: S6AP413A_DS405-00019 Page Section Revision 0.1 Revision 1.0 26. Measurement Circuit for 52 Characteristics of General Operation 65 28. Ordering Information Descriptions Initial release Preliminary Full production Revised the Parts number of Component list 1278AS-H-1R0M 1276AS-H-1R0M Revised the Part number of Ordering Information NOTE: Please see "Document History" about later revised information. Document Number: 002-08448 Rev.*A Page 67 of 69 S6AP413A Document History 2 Document Title: S6AP413A 4ch DC/DC Converter with I C Interface and Internal SW FETs Document Number: 002-08448 Revision ECN Orig. of Change Submission Date Description of Change ** - TAOA 12/26/2014 Migrated to Cypress and assigned document number 002-08448. No change to document contents or format. *A 5146815 TAOA 02/26/2016 Updated to Cypress format. Document Number: 002-08448 Rev.*A Page 68 of 69 S6AP413A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. 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Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as cri tical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-08448 Rev.*A February 26, 2016 Page 69 of 69