Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
2A, Ultra Low Dropout (0.24V Typical) Linear Regulator
Features
•Ultra Low Dropout
- 0.24V (typical) at 2A Output Current
•0.8V Reference Voltage
•High Output Accuracy
- ±1.5% Over Line, Load, and Temperature Range
•Fast Transient Response
•Adjustable Output Voltage
•Power-On-Reset Monitoring on Both VCNTL and
VIN Pins
•Internal Soft-Start
•Current-Limit and Short Current-Limit Protections
•Thermal Shutdown with Hysteresis
•Open-Drain VOUT Voltage Indicator (POK)
•Low Shutdown Quiescent Current ( < 30µA )
•Shutdown/Enable Control Function
•Simple TDFN3x3-10 Package with Exposed Pad
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
The APL5620 is a 2A ultra low dropout linear regulator.
The IC needs two supply voltages, one is a control volt-
age (VCNTL) for the control circuitry, the other is a main
supply Voltage (VIN) for power conversion, to reduce power
dissipation and provide extremely low dropout voltage.
The APL5620 integrates many functions. A Power-On-Re-
set (POR) circuit monitors both supply voltages on VCNTL
and VIN pins to prevent erroneous operations. The func-
tions of thermal shutdown and current-limit protect the
device against thermal and current over-loads. A POK
indicates that the output voltage status with a delay time
set internally. It can control other converter for power
sequence. The APL5620 can be enabled by other power
systems. Pulling and holding the EN voltage below 0.4V
shuts off the output.
The APL5620 is available in a TDFN3x3-10 package
which features small size as TDFN3x3-10 and an Ex-
posed Pad to reduce the junction-to-case resistance to
extend power range of applications.
•Motherboards, VGA Cards
•Notebook PCs
•Add-in Cards
Simplified Application Circuit
Pin Configuration
VCNTL
VOUT
VIN
GND
VOUT
VCNTL
POK VIN
EN
Enable EN
POK
APL5620
FB
Optional
8 VIN
TDFN3x3-10
VOUT 2
VOUT 3
FB 4
VOUT 1
POK 5 6 EN
9 VIN
7 VIN
10 VCNTL
GND
(Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw2
Ordering and Marking Information
Symbol Parameter Rating Unit
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 6 V
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 6 V
VOUT VOUT to GND Voltage -0.3 ~ VIN+0.3 V
POK to GND Voltage -0.3 ~ 7
EN, FB to GND Voltage -0.3 ~ VCNTL+0.3 V
PD Power Dissipation Internally Limited W
TJ Maximum Junction Temperature 150 οC
TSTG Storage Temperature Range -65 ~ 150 οC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 οC
Absolute Maximum Ratings (Note 1)
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2)
TDFN3x3-10
50 oC/W
θJC Junction-to-Case Resistance in Free Air (Note 3)
TDFN3x3-10
6 oC/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Measured Point
PCB Copper
8
7
6
9
10
3
4
5
2
1
APL5620
Handling Code
Temperature Range
Package Code
Package Code
QB : TDFN3x3-10
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
APL5620 QB : APL
5620
XXXXX XXXXX - Date Code
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw3
Recommended Operating Conditions
Symbol Parameter Range Unit
VCNTL VCNTL Supply Voltage 3.0 ~ 5.5 V
VIN VIN Supply Voltage 1.2 ~ 5.5 V
VOUT VOUT Output Voltage (when VCNTL-VOUT>1.7V) 0.8 ~ VIN - VDROP V
IOUT VOUT Output Current 0 ~ 2 A
R2 FB to GND 1k ~ 24k Ω
IOUT = 2A at 25% nominal VOUT 8 ~ 770
IOUT = 1A at 25% nominal VOUT 8 ~ 1400
COUT VOUT Output Capacitance
IOUT = 0.5A at 25% nominal VOUT 8 ~ 1700
µF
ESRCOUT ESR of VOUT Output Capacitor 0 ~ 200 mΩ
TA Ambient Temperature -40 ~ 85 οC
TJ Junction Temperature -40 ~ 125 οC
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.8V, VOUT=1.2V, and TA=-40~85oC, unless
otherwise specified. Typical values are at TJ=25oC.
APL5620
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVCNTL VCNTL Supply Current EN=VCNTL, IOUT=0A - 1.0 1.5 mA
ISD VCNTL Supply Current at Shutdown
EN=GND - 20 30 µA
VIN Supply Current at Shutdown EN=GND, VIN=5.5V - - 1 µA
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold 2.5 2.7 2.9 V
VCNTL POR Hysteresis - 0.4 - V
Rising VIN POR Threshold 0.8 0.9 1.0
VIN POR Hysteresis - 0.5 - V
OUTPUT VOLTAGE
VREF Reference Voltage FB=VOUT, IOUT=10mA, TJ=25°C 0.792
0.8 0.808
V
Output Voltage Accuracy IOUT=0~2A, TJ=-40~125oC -1.5
- +1.5
%
Load Regulation IOUT=0A~2A - 0.06
0.25
%
Line Regulation IOUT=10mA, VCNTL=3.0~5.5V -0.15
- +0.15
%/V
VOUT Pull-Low Resistance VCNTL=3.3V, VEN=0V, VOUT<0.8V - 85 - Ω
FB Input Current VFB=0.8V -100
- 100
nA
DROPOUT VOLTAGES
TJ=25oC - 0.26
0.32
VOUT=2.5V
TJ=-40~125oC
- - 0.44
TJ=25oC - 0.25
0.30
VDROP VIN-to-VOUT Dropout Voltage VCNTL=4.5V,
IOUT=2A VOUT=1.8V
TJ=-40~125oC
- - 0.41
V
Note 3: Please refer to the typical application circuit.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw4
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.8V, VOUT=1.2V, and TA=-40~85oC, unless
otherwise specified. Typical values are at TJ=25oC.
Electrical Characteristics (Cont.)
APL5620
Symbol Parameter Test Conditions Min. Typ. Max.
Unit
DROPOUT VOLTAGES (CONT.)
TJ=25oC - 0.24 0.29
VDROP VIN-to-VOUT Dropout Voltage VCNTL=4.5V,
IOUT=2A VOUT=1.2V
TJ=-40~125oC
- - 0.39 V
PROTECTIONS
TJ=25οC 3.0 3.6 4.3
ILIM Current-Limit Level TJ=-40~125οC 2.5 - - A
ISHORT Short Current-Limit Level VFB<0.2V - 0.8 - A
Short Current-Limit Blanking Time
From beginning of soft-start 0.6 1.6 - ms
TSD Thermal Shutdown Temperature TJ rising - 170 - oC
Thermal Shutdown Hysteresis - 50 - oC
ENABLE AND SOFT-START
EN Logic High Threshold Voltage
VEN rising 0.5 0.8 1.1 V
EN Hysteresis - 80 - mV
EN Pull-High Current EN=GND - 5 - µA
TSS Soft-Start Interval 0.3 0.6 1 ms
POWER-OK AND DELAY
VTHPOK Rising POK Threshold Voltage VFB rising 90 92 94 %
POK Threshold Hysteresis - 8 - %
POK Pull-Low Voltage POK sinks 5mA - 0.25 0.4 V
POK Denounce Interval VFB<falling POK voltage threshold - 10 - µs
POK Delay Time From VFB =VTHPOK to rising edge of the
VPOK 1 2 4 ms
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw5
Typical Operating Characteristics
Current-Limit, ILIM (A)
-50 -25 0 25 50 75 100 125
VOUT = 1.2V
VCNTL = 5V
VCNTL = 3.3V
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
Current-Limit vs.
Junction Temperature
Junction Temperature (oC)
Short Current-Limit, ISHORT (mA)
Junction Temperature (oC)
VCNTL = 5V
VCNTL = 3.3V
500
550
600
650
700
750
800
850
900
-50 -25 0 25 50 75 100 125
Short Current-Limit vs.
Junction Temperature
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
VCNTL = 5V
VOUT = 1.2V
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
Dropout Voltage vs. Output Current
0
50
100
150
200
250
300
350
400
00.5 11.5 2
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
00.5 11.5 2
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
VCNTL = 3.3V
VOUT = 1.2V
Dropout Voltage vs. Output Current
0
50
100
150
200
250
300
350
400
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
VCNTL = 5V
VOUT = 1.8V
Dropout Voltage vs. Output Current
0
50
100
150
200
250
300
350
400
00.5 11.5 2
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
VCNTL = 3.3V
VOUT = 1.5V
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
Dropout Voltage vs. Output Current
0
50
100
150
200
250
300
350
400
450
00.5 11.5 2
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
VCNTL = 5V
VOUT = 2.5V
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
Dropout Voltage vs. Output Current
00.5 11.5 2
0
50
100
150
200
250
300
350
400
450
Junction Temperature (oC)
-50 -25 0 25 50 75 100
Reference Voltage, VREF (V)
125
Reference Voltage vs.
Junction Temperature
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
Power Supply Rejection Ratio (dB)
Frequency (Hz)
VIN Power Supply Rejection
Ratio (PSRR)
100 1000 10000 100000 100000
VCNTL=5V
VIN=1.55V
VINPK-PK=50mV
VOUT=1.2V
IOUT=2A
COUT=10µF
-50
-40
-30
-20
-10
0
Power Supply Rejection Ratio (dB)
Frequency (Hz)
VCNTL Power Supply Rejection
Ratio (PSRR)
1000 10000 100000 1000000
VCNTL=4.6~5.4V
VIN=1.5V
VOUT=1.2V
IOUT=2A
CIN=COUT=10µF
-80
-70
-60
-50
-40
-30
-20
-10
0
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw7
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
CH1: VOUT, 50mV/Div, AC
CH4: IOUT, 1A/Div, DC
TIME: 20µs/Div
COUT=10µF, CIN=10µF
Load Transient Response
IOUT
VOUT
1
4
IOUT=10mA to 2A to 10mA (rise / fall time = 1µs)
Over Current Protection
IOUT
1
4
CH4: IOUT, 1A/Div, DC
TIME: 0.2ms/Div
COUT=10µF, CIN=10µF, IOUT=1A to 3.4A
VOUT
CH1: VOUT, 1V/Div, DC
Power Off
VCNTL
VIN
VOUT
VPOK
1
4
2
3
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
TIME: 10ms/Div
COUT=10µF, CIN=10µF, RL=0.6Ω
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
Power On
VCNTL
VIN
VOUT
VPOK
1
4
2
3
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
TIME: 5ms/Div
COUT=10µF, CIN=10µF, RL=0.6Ω
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw8
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
TIME: 5µs/Div
COUT=10µF, CIN=10µF, RL=0.6Ω
Shutdown
IOUT
VEN
1
4
2
3
VOUT
VPOK
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
TIME: 0.5ms/Div
COUT=10µF, CIN=10µF, RL=0.6Ω
Enable
1
4
2
3
IOUT
VEN
VOUT
VPOK
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw9
Pin Description
PIN
NO. NAME FUNCTION
1,2,3 VOUT Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is
required for stability and improving transient response. The output voltage is programmed by the
resistor-divider connected to FB pin. The VOUT can provide 2A (max.) load current to loads.
During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET.
4 FB Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback
voltage of the regulator.
5 POK Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output
voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the
Power-OK voltage window.
6 EN
Active-high enable control pin. Applying and holding the voltage on this pin below the enable
voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start
process. When left this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and
enables the regulator.
7,8,9 VIN Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is
usually connected near this pin to filter the voltage noise and improve transient response. The
voltage on this pin is monitored for Power-On-Reset purpose
10 VCNTL Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V
recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the
voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose.
Exposed Pad
GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Block Diagram
Thermal
Shutdown
GND
VOUT
VIN
EN
VCNTL
POK
90%
VREF
FB
Delay
0.8V
Control Logic
and
Soft-Start
VCNTL
5µA
Enable
POR
POR
Error Amplifier
Power-On-
Reset
(POR)
PWOK
Current-Limit
and
Short Current-Limit
Soft-Start
Enable
VREF
0.8V
ISEN
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw10
Typical Application Circuit
10µF: GRM31MR60J106KE19 Murata
VCNTL
VOUT
CCNTL
1µFVIN
+1.8V
GND
VOUT
VCNTL
POK VIN
CIN
10µF
COUT
10µF
EN
Enable EN
POK
R3
5.1kΩ7,8,9
1,2,3
10
Exposed
Pad
6
5
APL5620
R1
12kΩ
C1
(Optional)
FB 4
R2
24kΩ
(X5R/X7R Recommended)
(+5V is preferred)
(X5R/X7R Recommended)
+1.2V / 2A
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw11
Function Description
Power-On-Reset
A Power-On-Reset (POR) circuit monitors both of supply
voltages on VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
after both of the supply voltages exceed their rising POR
voltage thresholds during powering on. The POR func-
tion also pulls low the POK voltage regardless of the
output status when one of the supply voltages falls below
its falling POR voltage threshold.
Internal Soft-Start
An internal soft-start function controls rise rate of the out-
put voltage to limit the current surge during start-up. The
typical soft-start interval is about 0.6ms.
Output Voltage Regulation
An error amplifier working with a temperature-compen-
sated 0.8V reference and an output NMOS regulates out-
put to the preset voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast tran-
sient response and less load regulation. It compares the
reference with the feedback voltage and amplifies the dif-
ference to drive the output NMOS which provides load
current from VIN to VOUT.
Current-Limit Protection
The APL5620 monitors the current flowing through the
output NMOS and limits the maximum current to prevent
load and APL5620 from damaging during current over-
load conditions.
Short Current-Limit Protection
The short current-limit function reduces the current-limit
level down to 0.8A (typical) when the voltage on FB pin
falls below 0.2V (typical) during current overload or short-
circuit conditions.
The short current-limit function is disabled for success-
ful start-up during soft-start.
Thermal Shutdown
A thermal shutdown circuit limits the junction tempera-
ture of APL5620. When the junction temperature exceeds
+170oC, a thermal sensor turns off the output NMOS, al-
lowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start pro-
cess after the junction temperature cools by 50oC, result-
ing in a pulsed output during continuous thermal over-
load conditions. The thermal shutdown is designed with
a 50oC hysteresis to lower the average junction tempera-
ture during continuous thermal overload conditions, ex-
tending lifetime of the device.
For normal operation, the device power dissipation should
be externally limited so that junction temperatures will
not exceed +125οC.
Enable Control
The APL5620 has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Fol-
lowing a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle. When
left open, this pin is pulled up by an internal current source
(5µA typical) to enable normal operation. It’s not neces-
sary to use an external transistor to save cost.
Power-OK and Delay
The APL5620 indicates the status of the output voltage by
monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK voltage thresh-
old (VTHPOK), an internal delay function starts to work. At the
end of the delay time, the IC turns off the internal NMOS of
the POK to indicate that the output is ok. As the VFB falls
and reaches the falling Power-OK voltage threshold, the
IC turns on the NMOS of the POK ( after a debounce time
of 10µs typical ).
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw12
Application Information
........... (V)
Power Sequencing
The power sequencing of VIN and VCNTL is not neces-
sary to be concerned. However, do not apply a voltage to
VOUT for a long time when the main voltage applied at
VIN does not present. The reason is the internal parasitic
diode from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
Output Capacitor
The APL5620 requires a proper output capacitor to main-
tain stability and improve transient response. The output
capacitor selection is dependent upon ESR (equivalent
series resistance) and capacitance of the output capacitor
over the operating temperature.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as output capacitors.
During load transients, the output capacitors which is de-
pending on the stepping amplitude and slew rate of load
current, are used to reduce the slew rate of the current
seen by the APL5620 and help the device to minimize the
variations of output voltage for good transient response.
For the applications with large stepping load current, the
low-ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the load
and ground pins as close as possible and the imped-
ance of the layout must be minimized.
Input Capacitor
The APL5620 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the para-
sitic inductor from the voltage sources or other bulk ca-
pacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors
can all be used as an input capacitor of VIN. For most
applications, the recommended input capacitance of VIN
is 10µF at least. However, if the drop of the input voltage
Setting The Output Voltage
The output voltage is programmed by the resistor divider
connected to FB pin. The preset output voltage is calcu-
lated by the following equation :
+⋅=R2
R1
10.8 VOUT
where R1 is the risistor connected from VOUT to FB with
Kelvin sensing connection and R2 is the risistor con-
nected from FB to GND. A bypass capacitor(C1) may be
connected with R1 in parallel to improve load transient
response and stability.
is not cared, the input capacitance can be less than 10µF.
More capacitance reduces the variations of the supply
voltage on VIN pin.
Layout Consideration (See Figure 1)
1. Please solder the Exposed Pad on the system ground
pad on the top-layer of PCBs. The ground pad must
have wide size to conduct heat into the ambient air
through the system ground plane and PCB as a heat
sink.
2. Please place the input capacitors for VIN and VCNTL
pins near the pins as close as possible for decoupling
high-frequency ripples.
3. Ceramic decoupling capacitors for load must be placed
near the load as close as possible for ecoupling high-
frequency ripples.
4. To place APL5620 and output capacitors near the load
reduces parasitic resistance and inductance for excel-
lent load transient response.
5. The negative pins of the input and output capacitors
and the GND pad must be connected to the ground
plane of the load.
6. Large current paths, shown by bold lines on the figure
1, must have wide tracks.
7. Place the R1, R2, and C1 (option) near the APL5620 as
close as to avoid noise coupling.
8. Connect the ground of the R2 to the GND pad by using
a dedicated track.
9. Connect the one pin of the R1 to the load for Kelvin
sensing.
10. Connect one pin of the C1 (option) to the VOUT pin for
reliable feedback compensation.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw13
Figure 1.
Thermal Consideration
The TDFN3x3-10 is a cost-effective package featuring a
small size and a bottom exposed pad to minimize the
thermal resistance of the package, being applicable to
high current applications. The exposed pad must be sol-
dered to the top-layer ground plane. It is recommended
to connect the top-layer ground pad to the internal ground
plan by using vias. The copper of the ground plane on the
top-layer conducts heat into the PCB and ambient air.
Please enlarge the area of the top-layer pad and the
ground plane to reduce the case-to-ambient resistance
(θCA).
Application Information (Cont.)
Layout Consideration (See Figure 1) (Cont.)
VCNTL
VOUT
CCNTL
VIN
GND
VOUT
VCNTLVIN
CIN
COUT
APL5620
R1
C1
(Optional)
FB
R2
Load
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw14
Package Information
TDFN3x3-10
0.70
0.069
0.028
0.002
0.50 BSC 0.020 BSC
0.20 0.008
K
2.90 3.10 0.114 0.122
2.90 3.10 0.114 0.122
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.18 0.30
2.20 2.70
0.05
1.40
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN3x3-10
0.30 0.50
1.75
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.087 0.106
0.055
0.012 0.020
Note : 1. Followed from JEDEC MO-229 VEED-5.
Pin 1 Corner
e
LK E2
D2 A1
A3
b
A
E
Pin 1
D
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw15
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
TDFN3x3-10 Tape & Reel 3000
Devices Per Unit
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN3x3-10
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
(mm)
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw16
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw17
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.3 - Aug., 2010
APL5620
www.anpec.com.tw18
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
