16-Bit, 250 kSPS, Unipolar/Bipolar
Programmable Input PulSAR
®
ADC
Data Sheet
AD7610
Rev. A
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FEATURES
Multiple pins/software programmable input ranges:
5 V, 10 V, ±5 V, ±10 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput: 250 kSPS
16-bit resolution with no missing codes
INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
SNR: 94 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C;
On-chip temperature sensor
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
90 mW @ 250 kSPS
10 mW @ 1 kSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
FUNCTIONAL BLOCK DIAGRAM
16
CLOCK
AD7610
DGNDDVDD
AVDD
AGND
REF REFGND
IN+
PD
RESET
CNVST
PDBUF
REFBUFIN
PDREF REF
TEMP
D[15:0]
BUSY
RD
CS
OB/2C
OGND
OVDD
BYTESWAP
SER/PAR
REF
AMP
SWITCHED
CAP DAC
VCC VEE
BIPOLAR TEN
IN–
SERIAL
CONFIGURATION
PORT
PARALLEL
INTERFACE
SERIAL
DATAPORT
CONTROL LOGIC AND
CALI BRATI ON CIRCUITRY
06395-001
Figure 1.
GENERAL DESCRIPTION
The AD7610 is a 16-bit charge redistribution successive approxi-
mation register (SAR), architecture analog-to-digital converter
(ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage
process. The device is configured through hardware or via a
dedicated write only serial configuration port for input range
and operating mode. The AD7610 contains a high speed 16-bit
sampling ADC, an internal conversion clock, an internal reference
(and buffer), error correction circuits, and both serial and parallel
system interface ports. A falling edge on CNVST samples the
analog input on IN+ with respect to a ground sense, IN−. The
AD7610 features four different analog input ranges: 0 V to 5 V, 0 V
to 1 0 V, ±5 V, and ±10 V. Power consumption is scaled linearly
with throughput. The device is available in Pb-free 48-lead, low-
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from −40°C to
+85°C.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
Type
100 kSPS to
250 kSPS
500 kSPS to
570 kSPS
800 kSPS to
1000 kSPS
>1000
kSPS
Pseudo
Differential
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
True Bipolar AD7610
AD7663
AD7665 AD7612
AD7671
AD7951
True
Differential
AD7675 AD7676 AD7677 AD7621
AD7622
AD7623
18-Bit, True
Differential
AD7678 AD7679 AD7674 AD7641
AD7643
Multichannel/
Simultaneous
AD7654
AD7655
AD7610 Data Sheet
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Overview ...................................................................................... 16
Converter Operation .................................................................. 16
Transfer Functions...................................................................... 17
Typical Connection Diagram ................................................... 18
Analog Inputs .............................................................................. 19
Voltage Reference Input/Output .............................................. 20
Power Supplies ............................................................................ 21
Conversion Control ................................................................... 22
Interfaces.......................................................................................... 23
Digital Interface .......................................................................... 23
Parallel Interface ......................................................................... 23
Serial Interface ............................................................................ 24
Master Serial Interface ............................................................... 24
Slave Serial Interface .................................................................. 26
Hardware Configuration ........................................................... 28
Software Configuration ............................................................. 28
Microprocessor Interfacing ....................................................... 29
Application Information ................................................................ 30
Layout Guidelines....................................................................... 30
Evaluating Performance ............................................................ 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
12/12—Rev. 0 to Rev. A
Added Exposed Pad Note ................................................................ 8
Changes to Power Sequencing Section ........................................ 23
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
10/06—Revision 0: Initial Version
Data Sheet AD7610
Rev. A | Page 3 of 32
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V
V
IN+
− V
IN−
= 0 V to 10 V
−0.1
+10.1
V
VIN+ − VIN− = ±5 V −5.1 +5.1 V
VIN+ − VIN− = ±10 V −10.1 +10.1 V
V
IN−
to AGND
−0.1
+0.1
V
Analog Input CMRR fIN = 100 kHz 75 dB
Input Current
V
IN
= ±5 V, ±10 V @ 250 kSPS
100
1
µA
Input Impedance See Analog Inputs section
THROUGHPUT SPEED
Complete Cycle 4 μs
Throughput Rate
250
kSPS
DC ACCURACY
Integral Linearity Error2
−1.5
±0.75
+1.5
LSB3
No Missing Codes2 16 Bits
Differential Linearity Error2 −1 +1.5 LSB
Transition Noise
0.55
LSB
Zero Error (Unipolar or Bipolar) −35 +35 LSB
Zero Error Temperature Drift
±1
ppm/°C
Bipolar Full-Scale Error −50 +50 LSB
Unipolar Full-Scale Error −70 +70 LSB
Full-Scale Error Temperature Drift
±1
ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB
AC ACCURACY
Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB4
V
IN
= 0 V to 10 V, ±5 V, f
IN
= 2 kHz, −60 dB
94
dB
VIN = ±10 V, fIN = 2 kHz, −60 dB 94.5 dB
Signal-to-Noise Ratio VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz 92 93 dB
V
IN
= ±5 V, ±10 V, f
IN
= 2 kHz
94
dB
VIN = 0 V to 5 V, fIN = 20 kHz 93.5 dB
Signal-to-(Noise + Distortion) (SINAD)
V
IN
= ±5 V, f
IN
= 2 kHz
92.5
dB
VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz 93 dB
VIN = ±10 V, fIN = 2 kHz 93.5 dB
Total Harmonic Distortion
f
IN
= 2 kHz
−107
dB
Spurious-Free Dynamic Range fIN = 2 kHz 107 dB
–3 dB Input Bandwidth
V
IN
= 0 V to 5 V
650
kHz
Aperture Delay 2 ns
Aperture Jitter
5
ps rms
Transient Response Full-scale step 500 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 4.965 5.000 5.035 V
Temperature Drift
–40°C to +85°C
±3
ppm/°C
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time
C
REF
= 22 µF
10
ms
REFERENCE BUFFER
PDREF = high
REFBUFIN Input Voltage Range 2.4 2.5 2.6 V
AD7610 Data Sheet
Rev. A | Page 4 of 32
Parameter
Conditions/Comments
Min
Typ
Max
Unit
EXTERNAL REFERENCE
PDREF = PDBUF = high
Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain
250 kSPS throughput
30
µA
TEMPERATURE PIN
Voltage Output
@ 25°C
311
mV
Temperature Sensitivity 1 mV/°C
Output Resistance
4.33
kΩ
DIGITAL INPUTS
Logic Levels
V
IL
−0.3
+0.6
V
VIH 2.1 OVDD + 0.3 V
I
IL
−1
+1
µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format
Parallel or serial 16-bit
Pipeline Delay5
V
OL
I
SINK
= 500 µA
0.4
V
VOH ISOURCE = –500 µA OVDD − 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.756 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD
2.7
5.25
V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V
Operating Current
7, 8
@ 250 kSPS throughput
AVDD
With Internal Reference
8
mA
With Internal Reference Disabled 6.3 mA
DVDD 3.3 mA
OVDD
0.3
mA
VCC VCC = 15 V, with internal reference buffer 1.4 mA
VCC = 15 V
0.8
mA
VEE VEE = −15 V 0.7 mA
Power Dissipation @ 250 kSPS throughput
With Internal Reference
PDREF = PDBUF = low
90
110
mW
With Internal Reference Disabled PDREF = PDBUF = high 70 90 mW
In Power-Down Mode
9
PD = high
10
µW
TEMPERATURE RANGE10
Specified Performance
T
MIN
to T
MAX
−40
+85
°C
1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Conversion results are available immediately after completed conversion.
6 4.75 V or VREF – 0.1 V, whichever is larger.
7 Tested in parallel reading mode.
8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
9 With all digital inputs forced to OVDD.
10 Consult sales for extended temperature range.
Data Sheet AD7610
Rev. A | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width t1 10 ns
Time Between Conversions t2 4 μs
CNVST Low to BUSY High Delay t3 35 ns
BUSY High (Except Master Serial Read After Convert) t4 1.45 μs
Aperture Delay
t
5
2
ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7 1.45 μs
Acquisition Time t8 380 ns
RESET Pulse Width t9 10 ns
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay t10 1.41 μs
DATA Valid to BUSY Low Delay t11 20 ns
Bus Access Request to DATA Valid
t
12
40
ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES1 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
t
14
10
ns
CS Low to Internal SDCLK Valid Delay1 t15 10 ns
CS Low to SDOUT Delay t16 10 ns
CNVST Low to SYNC Delay, Read During Convert t17 560 ns
SYNC Asserted to SDCLK First Edge Delay t18 3 ns
Internal SDCLK Period2 t19 30 45 ns
Internal SDCLK High2 t20 15 ns
Internal SDCLK Low2 t21 10 ns
SDOUT Valid Setup Time2 t22 4 ns
SDOUT Valid Hold Time2 t23 5 ns
SDCLK Last Edge to SYNC Delay2 t24 5 ns
CS High to SYNC HI-Z
t
25
10
ns
CS High to Internal SDCLK HI-Z t26 10 ns
CS High to SDOUT HI-Z t27 10 ns
BUSY High in Master Serial Read After Convert2 t28 See Table 4
CNVST Low to SYNC Delay, Read After Convert t29 1.31 μs
SYNC Deasserted to BUSY Low Delay t30 25 ns
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1 (See Figure 42,
Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time t31 5 ns
External SDCLK Active Edge to SDOUT Delay t32 2 18 ns
SDIN/SCIN Setup Time t33 5 ns
SDIN/SCIN Hold Time t34 5 ns
External SDCLK/SCCLK Period t35 25 ns
External SDCLK/SCCLK High t36 10 ns
External SDCLK/SCCLK Low
t
37
10
ns
1 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial mode read after convert mode.
AD7610 Data Sheet
Rev. A | Page 6 of 32
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns
Internal SDCLK Period Minimum t19 30 60 120 240 ns
Internal SDCLK Period Maximum t19 45 90 180 360 ns
Internal SDCLK High Minimum t20 15 30 60 120 ns
Internal SDCLK Low Minimum t21 10 25 55 115 ns
SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns
SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns
BUSY High Width Maximum t28 2.25 3.00 4.40 7.30 μs
NOTES
1. IN SERI AL I NT ERFACE MODES, THE SYNC, S CLK, AND
SDO UT ARE DEFINED WI TH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
1.6mA I
OL
500µA I
OH
1.4V
TO OUTPUT
PIN
C
L
60pF
0
6395-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
2V
2V
0.8V0.8V
2V
tDELAY tDELAY
06395-003
Figure 3. Voltage Reference Levels for Timing
Data Sheet AD7610
Rev. A | Page 7 of 32
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,
REFGND to AGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD
−0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V
VEE to GND +0.3 V to −16.5 V
Digital Inputs −0.3 V to OVDD +0.3 V
PDREF, PDBUF
2
±20 mA
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 125°C
Storage Temperature Range −65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 See the Analog Inputs section.
2 See the Voltage Reference Input section.
3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
AD7610 Data Sheet
Rev. A | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
VEE
VCC
IN–
REFGND
REF
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SDCLK
D10/SYNC
D11/RDERROR
AGND
AVDD
AGND
BYTESWAP
OB/2C
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
OGND
OGND
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D15/SCCS
D14/SCCLK
D13/SCIN
D12/HW/SW
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19
20 21 22 23 24
PIN 1
AD7610
TOP VI EW
(No t t o Scal e)
06395-004
NOTES
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), T HE EXPOSED
PAD SHOULD BE CONNECTED T O VE E . THIS CONNECT IO N IS NO T
REQ UIRED T O ME E T THE E LECTRICAL PE RFORM ANCE S .
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to
AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and
OGND voltages should be at the same potential.
2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on
D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5 OB/2C DI2 Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7, 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
8 SER/PAR DI Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and
the remaining data bits are high impedance outputs.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of
SER/PAR.
11, 12 D[2:3] or DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data
clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
EXT/INT
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or
external (slave) serial data clock for the AD7610 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
Data Sheet AD7610
Rev. A | Page 9 of 32
Pin No. Mnemonic Type1 Description
14 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D6 or DI/O In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
16 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select
the read mode. See the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable
in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-
chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3
V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied
from AVDD.
20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital
ground ideally at the same potential as AGND and OGND.
21 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first,
from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode).
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22 D9 or DI/O In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the
logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of
the INVSCLK pin.
23 D10 or DO In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used
as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT
output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT
output is valid.
24 D11 or DO In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current conversion is
complete, the current data is lost and RDERROR is pulsed high.
25 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
HW/SW
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by
hardware or software. See the Hardware Configuration section and Software Configuration section.
When HW/SW = low, the AD7610 is configured through software using the serial configuration register.
When HW/SW = high, the AD7610 is configured through dedicated hardware input pins.
26 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to serially write in, MSB first, the configuration data into the serial configuration register. The
data on this input is latched with SCCLK. See the Software Configuration section.
AD7610 Data Sheet
Rev. A | Page 10 of 32
Pin No. Mnemonic Type1 Description
27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is
used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state
of the INVSCLK pin. See the Software Configuration section.
28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus.
SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input enables the serial configuration port. See the Software Configuration section.
29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low,
RDC = low) the busy time changes according to Table 4.
30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V Low Low
0 V to 10 V Low High
±5 V High Low
±10 V High High
31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also
used to gate the external clock in slave serial mode (not used for serial programmable port).
33 RESET DI Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET
resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the Digital
Interface section. If not used, this pin can be tied to OGND.
34 PD DI2 Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions
are inhibited after the current one is completed. The digital interface remains active during power down.
35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates
a conversion.
36 BIPOLAR DI2 Input Range Select. See description for Pin 30.
37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V
on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the
internal reference and buffer. See the Reference Decoupling section.
38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI Analog Input. Referenced to IN−.
45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF =
low). See the Temperature Sensor section.
46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,
PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section.
47 PDREF DI Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
48 PDBUF DI Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
49 EPAD3 NC Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered
to VEE.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2 In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
3 LFCSP_VQ package only.
Data Sheet AD7610
Rev. A | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
1.5
–1.5 065536
INL (LSB)
CODE
16384 32768 49152
1.0
0.5
0
–0.5
–1.0
06395-005
Figure 5. Integral Nonlinearity vs. Code
250
0
–1.0 1.0
NUMBER OF UNIT S
INL DISTRIBUTION (LSB)
50
100
150
200
–0.6–0.4–0.2 0 0.2 0.4 0.6 0.8
–0.8
NEGATIVE INL
POSITIVE I NL
06395-006
Figure 6. Integral Nonlinearity Distribution (296 Devices)
250000
07FFF 8006
COUNTS
CODE IN HEX
8000 8001 8002 8003 8004 8005
200000
150000
100000
50000
0 0 40 0
27510 22202
211404 σ = 0.44
06395-007
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center
CODE
DNL ( LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5 016384 32768 49152 65536
06395-008
Figure 8. Differential Nonlinearity vs. Code
180
0
–1.0 1.0
NUMBER OF UNIT S
DNL DIST RIBUT ION ( LSB)
20
60
100
140
–0.6 –0.4 –0.2 00.2 0.4 0.6 0.8
–0.8
NEGATI VE DNL
POSIT I VE DNL
40
80
120
160
06395-009
Figure 9. Differential Nonlinearity Distribution (296 Devices)
COUNTS
CODE IN HEX
8007
8006
8000 8001 8002 8003 8004 8005
140000
0
120000
100000
80000
60000
40000
20000
σ = 0.51
0 0 0 0
169
1072
127179 132700
06395-010
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition
AD7610 Data Sheet
Rev. A | Page 12 of 32
0
–160
AMPLITUDE (dB OF FULL SCALE)
0125
FRE QUENCY ( kHz ) 10025 50 75
–20
–40
–60
–80
–100
–120
–140
f
S
= 250kSPS
f
IN
= 19.95kHz
SNR = 93. 4dB
THD = –107dB
SF DR = 114dB
SI NAD = 93dB
06395-011
Figure 11. FFT 20 kHz
80
82
84
86
88
90
92
94
96
110 100
14.4
14.6
14.8
15.0
15.2
15.4
15.6
15.8
16.0
ENO B ( Bits)
SNR
SINAD
ENOB
FRE QUENCY ( kHz )
SNR, S INAD (d B)
06395-012
Figure 12. SNR, SINAD, and ENOB vs. Frequency
96
90
–55 125
SNR (dB)
TEMPERATURE (°C)
93
92
91
94
95
–35 –15 525 45 65 85 105
VI N = 0V TO 5V
VI N = 0V TO 10V
VI N = ± 5V
VI N = ± 10V
06395-013
Figure 13. SNR vs. Temperature
93.0
93.5
94.0
94.5
95.0
–60 –50 –40 –30 –20 –10 0
SNR
SINAD
±10V
±5V
INPUT LEVEL (d B)
SNR, S INAD REF E RRE D TO FULL SCALE (dB)
0V T O 10V
0V T O 5V
06395-014
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
–130
–120
–110
–100
–90
–80
–70
110 100
60
70
80
90
100
110
120
SF DR ( dB)
SFDR
SECOND
HARMONIC
THIRD
HARMONIC
FRE QUENCY ( kHz )
THD, HARMO NICS ( dB)
THD
06395-015
Figure 15. THD, Harmonics, and SFDR vs. Frequency
96
90
–55 125
SI NAD ( dB)
TEMPERATURE (°C)
93
92
91
94
95
–35 –15 525 45 65 85 105
VI N = 0V TO 5V
VI N = 0V TO 10V
VI N = ± 5V
VI N = ± 10V
06395-016
Figure 16. SINAD vs. Temperature
Data Sheet AD7610
Rev. A | Page 13 of 32
–96
–124
–55 125
THD ( dB)
TEMPERATURE (°C)
–108
–112
–116
–104
–100
–35 –15 525 45 65 85 105
–120
VI N = 0V TO 5V
VI N = 0V TO 10V
VI N = ± 5V
VI N = ± 10V
06395-017
Figure 17. THD vs. Temperature
–5
–4
–3
–2
–1
0
1
2
3
4
5
–55 –35 –15 525 45 65 85
105 125
ZE RO ERRO R
POSIT I VE F S ERROR
NEGATIVE FS ERROR
TEMPERATURE (°C)
ZE RO ERRO R, F ULL S CALE E RROR (L S B)
06395-018
Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature
60
00 8
NUMBER OF UNIT S
REF E RE NCE DRIFT (ppm/° C)
10
20
30
40
50
1234567
06395-019
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
126
108
–55 125
SF DR ( dB)
TEMPERATURE (°C)
120
118
116
122
124
–35 –15 525 45 65 85 105
VI N = 0V TO 5V
VI N = 0V TO 10V
VI N = ± 5V
VI N = ± 10V
114
112
110
06395-020
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
4.996
4.998
5.000
5.002
5.004
5.006
5.008
5.010
5.012
TEMPERATURE (°C)
VREF (V)
–55 –35 –15 525 45 65 85 105 125
06395-021
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
100000
0.001 1000000
OP E RATING CURRENTS (µA)
SAMPLING RATE (SPS)
100
10
10 100 1000 10000 100000
1000
1
0.1
0.01
10000
PDREF = PDBUF = HI GH
OVDD
AVDD
DVDD
VCC +15V
VEE –15V
ALL MODES
06395-022
Figure 22. Operating Currents vs. Sample Rate
AD7610 Data Sheet
Rev. A | Page 14 of 32
0
100
200
300
400
500
600
700
TEMPERATURE (°C)
PO WER-DOW N OPERATI NG CURRENT S ( nA)
–55 –35 –15 525 45 65 85 105
PD = PDBUF = P DRE F = HI GH
VEE = –15V
VCC = +15V
DVDD
OVDD
AVDD
06395-023
Figure 23. Power-Down Operating Currents vs. Temperature
0
5
10
15
20
25
30
35
40
45
50
050 100 150 200
C
L
(pF)
t
12
DELAY (ns)
OV DD = 2.7V @ 25°C
OV DD = 2.7V @ 85°C
OV DD = 5V @ 85°C
OV DD = 5V @ 25°C
06395-024
Figure 24. Typical Delay vs. Load Capacitance CL
Data Sheet AD7610
Rev. A | Page 15 of 32
TERMINOLOGY
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital con-
verter with N bits of resolution, the LSB expressed in volts is
N
INp-p maxV
LSB 2
)(
)V( =
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive full-
scale. The point used as negative full-scale occurs a ½ LSB before
the first code transition. Positive full-scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is meas-
ured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
Unipolar Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Full-Scale Error
The last transition (from 111…10 to 111…11) should occur for
an analog voltage 1½ LSB below the nominal full-scale. The full-
scale error is the deviation in LSB (or % of full-scale range) of
the actual level of the last transition from the ideal level and
includes the effect of the offset error. Closely related is the gain
error (also in LSB or % of full-scale range), which does not
include the effects of the offset error.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
The time required for the AD7610 to achieve its rated accuracy
after a full-scale step function is applied to its input.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
6
10
C25
((
Cppm/ ×
×°
=° )T–T()(V
)MinV–)MaxV
)(TCV
MIN
MAX
REF
REFREF
REF
where:
VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX.
VREF (25°C) = VREF at 25°C.
TMAX = +85°C.
TMIN = –40°C.
AD7610 Data Sheet
Rev. A | Page 16 of 32
THEORY OF OPERATION
IN+
REF
REFGND
LSB
MSB
32,768C
IN–
16,384C 4C 2C CC
65,536C
CNVST
COMP
SW
B
SW
A
SWITCHES
CONTROL
CONTROL
LOGIC
BUSY
OUTPUT
CODE
06395-025
Figure 25. ADC Simplified Schematic
OVERVIEW
The AD7610 is a very fast, low power, precise, 16-bit analog-to-
digital converter (ADC) using successive approximation capacitive
digital-to-analog converter (CDAC) architecture.
The AD7610 can be configured at any time for one of four input
ranges with inputs in parallel and serial hardware modes or by a
dedicated write only, SPI-compatible interface via a configure-
tion register in serial software mode. The AD7610 uses Analog
Device’s patented iCMOS high voltage process to accommodate
0 to 5 V, 0 to 10 V, ±5 V, and ±10 V input ranges without the use
of conventional thin films. Only one acquisition cycle, t8, is required
for the inputs to latch to the correct configuration. Resetting or
power cycling is not required for reconfiguring the ADC.
The AD7610 is capable of converting 250,000 samples per
second (250 kSPS) and power consumption scales linearly with
throughput making it useful for battery powered systems.
The AD7610 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
For unipolar input ranges, the AD7610 typically requires three
supplies; VCC, AVDD (which can supply DVDD), and OVDD
which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic.
For bipolar input ranges, the AD7610 requires the use of the
additional VEE supply.
The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP
7 mm × 7 mm packages that combine space savings with flexi-
bility. In addition, the AD7610 can be configured as either a
parallel or serial SPI-compatible interface.
CONVERTER OPERATION
The AD7610 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 16 binary weighted capacitors, which are connected
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST input goes low. When the conversion phase begins, SW+
and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the inputs (IN+
and IN−) captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between REFGND and REF, the comparator input varies by
binary weighted voltage steps (VREF/2, VREF/4 through VREF/65536).
The control logic toggles these switches, starting with the MSB
first, in order to bring the comparator back into a balanced
condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
Data Sheet AD7610
Rev. A | Page 17 of 32
TRANSFER FUNCTIONS
Using the OB/2C digital input or via the configuration register,
the AD7610 offers two output codings: straight binary and twos
complement. See Figure 26 and Table 7 for the ideal transfer char-
acteristic and digital output codes for the different analog input
ranges, VIN. Note that when using the configuration register, the
OB/2C input is a don’t care and should be tied to either high or low.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE ( S t raight Binary)
ANALOG INPUT
+FS R – 1.5 L S B
+FS R – 1 LSB–FS R + 1 LSB
–FSR
–FS R + 0.5 L S B
06395-026
Figure 26. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
VREF = 5 V Digital Output Code
Description VIN = 5 V VIN = 10 V VIN = ±5 V VIN = ±10 V Straight Binary Twos Complement
FSR −1 LSB 4.999924 V 9.999847 V +4.999847 V +9.999695 V 0xFFFF1 0x7FFF1
FSR − 2 LSB
4.999847 V
9.999695 V
+4.999695 V
+9.999390 V
0xFFFE
0x7FFE
Midscale + 1 LSB 2.500076 V 5.000153 V +152.6 µV +305.2 µV 0x8001 0x0001
Midscale 2.5 V 5.000000 V 0 V 0 V 0x8000 0x0000
Midscale − 1 LSB 2.499924 V 4.999847 V −152.6 µV −305.2 µV 0x7FFF 0xFFFF
−FSR + 1 LSB 76.3 µV 152.6 µV −4.999847 V −9.999695 V 0x0001 0x8001
−FSR 0 V 0 V −5 V −10 V 0x00002 0x80002
1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND).
2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND).
AD7610 Data Sheet
Rev. A | Page 18 of 32
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7610 using the internal reference, serial data and serial configuration interfaces.
Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.
RD CS
100nF 100nF
AVDD
10µF 100nF
AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SDCLK
RESETPD
REFBUFIN
D
CLOCK
AD7610
MICROCONVERTER/
MICROPROCESSOR/
DSP
ANALOG
SUPPLY (+5V)
OVDD
DIGITAL
SUPPLY (+5V)
IN+
IN–
NOTE 5
ANALOG
INPUT +
C
C
2.7nF
U1
NOTE 1
SER/PAR
OB/2C
REFGND
REF
PDBUF
PDREF
100nF
NOTE 3
NOTE 4
NOTE 3
NOTE 7
10µF
50Ω
10µF
C
REF
22µF
NOTES
1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
ANALOG
INPUT–
NOTE 2
VCC
VEE
10µF 100nF
+7V TO +15.75V
SUPPLY
10µF 100nF
–7V TO –15.75V
SUPPLY
NOTE 6
HW/SW
SCCS
SCCLK
SCIN
BIPOLAR
TEN
SERIAL
PORT 1
SERIAL
PORT 2
DIGITAL
INTERFACE
SUPPLY
(+2.5V, +3.3V, OR +5V)
0
6395-027
15Ω
10Ω
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
Data Sheet AD7610
Rev. A | Page 19 of 32
ANALOG INPUTS
Input Range Selection
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 Volt range)
inputs. See Table 6 for pin details and the Hardware
Configuration section and Software Configuration section for
programming the mode selection with either pins or configuration
register. Note that when using the configuration register, the
BIPOLAR and TEN inputs are don’t cares and should be tied to
either high or low.
Input Structure
Figure 28 shows an equivalent circuit for the input structure of
the AD7610.
D1 R
IN
C
IN
D2
IN+ OR IN–
VEE
VCC
C
PIN
AGND
D3
D4
AVDD
0 TO 5
V
RANGE O NLY
0
6395-028
Figure 28. AD7610 Simplified Analog Input
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and to
start conducting current. These diodes can handle a forward-
biased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short circuit current is <100 mA.
Note that D3 and D4 are only used in the 0 V to 5 V range to
allow for additional protection in applications that are switching
from the higher voltage ranges.
This analog input structure allows the sampling of the differential
signal between IN+ and IN−. By using this differential input,
small signals common to both inputs are rejected as shown in
Figure 29, which represents the typical CMRR over frequency.
For instance, by using IN− to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.
100
01 10000
CMRR (d B)
FREQUENCY ( kHz )
10 100 1000
90
80
70
60
50
40
30
20
10
06395-029
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of Capacitor CPIN and the network formed by
the series connection of RIN and CIN. CPIN is primarily the pin
capacitance. RIN is typically 5 kΩ and is a lumped component
comprised of serial resistors and the on resistance of the switches.
CIN is primarily the ADC sampling capacitor and depending on
the input range selected is typically 48 pF in the 0 V to 5 V range,
typically 24 pF in the 0 V to 10 V and ±5 V ranges and typically
12 pF in the ±10 V range. During the conversion phase, when
the switches are opened, the input impedance is limited to CPIN.
Since the input impedance of the AD7610 is very high, it can be
directly driven by a low impedance source without gain error.
To further improve the noise filtering achieved by the AD7610
analog input circuit, an external, one-pole RC filter between the
amplifier’s outputs and the ADC analog inputs can be used, as
shown in Figure 27. However, large source impedances signifi-
antly affect the ac performance, especially total harmonic
distortion (THD). The maximum source impedance depends
on the amount of THD that can be tolerated. The THD degrades
as a function of the source impedance and the maximum input
frequency.
AD7610 Data Sheet
Rev. A | Page 20 of 32
DRIVER AMPLIFIER CHOICE
Although the AD7610 is easy to drive, the driver amplifier must
meet the following requirements:
• For multichannel, multiplexed applications, the driver
amplifier and the AD7610 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). For the amplifier, settling at 0.1% to
0.01% is more commonly specified. This differs significantly
from the settling time at a 16-bit level and should be verified
prior to driver selection. The AD8021 op amp combines ultra-
low noise and high gain bandwidth and meets this settling
time requirement even when used with gains of up to 13.
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7610. The noise coming from
the driver is filtered by the external 1-pole low-pass filter
as shown in Figure 27. The SNR degradation due to the
amplifier is
( )
π
+
=
−2
3
2
2
log20
N
dB
NADC
NADC
LOSS
NefV
V
SNR
where:
VNADC is the noise of the ADC, which is:
20
10
22
SNR
INp-p
NADC
V
V=
f–3dB is the cutoff frequency of the input filter (3.9 MHz).
N is the noise factor of the amplifier (+1 in buffer
configuration).
eN is the equivalent input voltage noise density of the op
amp, in nV/√Hz.
• The driver needs to have a THD performance suitable to
that of the AD7610. Figure 15 shows the THD vs. frequency
that the driver should exceed.
The AD8021 meets these requirements and is appropriate for
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in appli-
cations where high frequency (above 100 kHz) performance is not
required. In applications with a gain of 1, an 82 pF compensation
capacitor is required. The AD8610 is an option when low bias
current is needed in low frequency applications.
Since the AD7610 uses a large geometry, high voltage input
switch, the best linearity performance is obtained when using
the amplifier at its maximum full power bandwidth. Gaining
the amplifier to make use of the more dynamic range of the
ADC results in increased linearity errors. For applications
requiring more resolution, the use of an additional amplifier
with gain should precede a unity follower driving the AD7610.
See Table 8 for a list of recommended op amps.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-x 12 V supply, very low noise, low distortion,
low power, low frequency
AD829 ±15 V supplies, very low noise, low frequency
AD8021 ±12 V supplies, very low noise, high frequency
AD8022 ±12 V supplies, very low noise, high
frequency, dual
AD8610/AD8620 ±13 V supplies, low bias current, low
frequency, single/dual
VOLTAGE REFERENCE INPUT/OUTPUT
The AD7610 allows the choice of either a very low temperature
drift internal voltage reference, an external reference or an external
buffered reference.
The internal reference of the AD7610 provides excellent perfor-
mance and can be used in almost all applications. However, the
linearity performance is guaranteed only with an external reference.
Data Sheet AD7610
Rev. A | Page 21 of 32
Internal Reference (REF = 5 V)
(PDREF = Low, PDBUF = Low)
To use the internal reference, the PDREF and PDBUF inputs
must be low. This enables the on-chip band gap reference, buffer,
and TEMP sensor resulting in a 5.00 V reference on the REF pin.
The internal reference is temperature-compensated to 5.000 V
±35 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C. This typical drift characteristic is shown in Figure 19.
External 2.5 V Reference and Internal Buffer (REF = 5 V)
(PDREF = High, PDBUF = Low)
To use an external reference with the internal buffer, PDREF
should be high and PDBUF should be low. This powers down
the internal reference and allows the 2.5 V reference to be applied
to REFBUFIN producing 5 V on the REF pin. The internal ref-
erence buffer is useful in multiconverter applications since a
buffer is typically required in these applications.
External 5 V Reference (PDREF = High, PDBUF = High)
To use an external reference directly on the REF pin, PDREF
and PDBUF should both be high. PDREF and PDBUF power
down the internal reference and the internal reference buffer,
respectively. For improved drift performance, an external ref-
erence such as the ADR445 or ADR435 is recommended.
Reference Decoupling
Whether using an internal or external reference, the AD7610
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs. This
decoupling depends on the choice of the voltage reference, but
usually consists of a low ESR capacitor connected to REF and
REFGND with minimum parasitic inductance. A 22 µF (X5R,
1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor)
is appropriate when using either the internal reference or the
ADR445/ADR435 external reference.
The placement of the reference decoupling is also important to
the performance of the AD7610. The decoupling capacitor should
be mounted on the same side as the ADC right at the REF pin
with a thick PCB trace. The REFGND should also connect to
the reference decoupling capacitor with the shortest distance
and to the analog ground plane with several vias.
For applications that use multiple AD7610 or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external 2.5 V reference voltage.
The voltage reference temperature coefficient (TC) directly
impacts full scale; therefore, in applications where full-scale
accuracy matters, care must be taken with the TC. For instance, a
±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C.
Temperature Sensor
When the internal reference is enabled (PDREF = PDBUF =
low), the on-chip temperature sensor output (TEMP) is enabled
and can be use to measure the temperature of the AD7610. To
improve the calibration accuracy over the temperature range, the
output of the TEMP pin is applied to one of the inputs of the
analog switch (such as ADG779), and the ADC itself is used to
measure its own temperature. This configuration is shown in
Figure 30.
ADG779
C
C
ANALO G INP UT
AD7610
IN+ TEMPERATURE
SENSOR
TEMP
06395-030
Figure 30. Use of the Temperature Sensor
POWER SUPPLIES
The AD7610 uses five sets of power supply pins:
AVDD: analog 5 V core supply
VCC: analog high voltage positive supply
VEE: high voltage negative supply
DVDD: digital 5 V core supply
OVDD: digital input/output interface supply
Core Supplies
The AVDD and DVDD supply the AD7610 analog and digital
cores respectively. Sufficient decoupling of these supplies is
required consisting of at least a 10 F capacitor and 100 nF on
each supply. The 100 nF capacitors should be placed as close as
possible to the AD7610. To reduce the number of supplies needed,
the DVDD can be supplied through a simple RC filter from the
analog supply, as shown in Figure 27.
High Voltage Supplies
The high voltage bipolar supplies, VCC and VEE are required
and must be at least 2 V larger than the maximum input, VIN.
For example, if using the bipolar 10 V range, the supplies should
be ±12 V minimum. Sufficient decoupling of these supplies is
also required consisting of at least a 10 F capacitor and 100 nF
on each supply. For unipolar operation, the VEE supply can be
grounded with some slight THD performance degradation.
Digital Output Supply
The OVDD supplies the digital outputs and allows direct interface
with any logic working between 2.3 V and 5.25 V. OVDD should
be set to the same level as the system interface. Sufficient decou-
pling is required consisting of at least a 10 F capacitor and 100 nF
with the 100 nF placed as close as possible to the AD7610.
AD7610 Data Sheet
Rev. A | Page 22 of 32
Power Sequencing
The AD7610 requires sequencing of the AVDD and DVDD
supplies. AVDD should come up prior to or simultaneously
with DVDD. This can be achieved using the configuration in
Figure 27 or sequencing the supplies in that manner. The
other supplies can be sequenced as desired as long as absolute
maximum ratings are observed. The AD7610 is very insensitive
to power supply variations on AVDD over a wide frequency
range, as shown in Figure 31.
80
30 110000
PSRR ( dB)
FRE QUENCY ( kHz )
10 100 1000
75
70
60
55
50
45
40
65
35
INT REF
EXT REF
06395-031
Figure 31. AVDD PSRR vs. Frequency
Power Dissipation vs. Throughput
The AD7610 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power savings when the conversion rate is reduced (see Figure 32).
This feature makes the AD7610 ideal for very low power, battery-
operated applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails (that is, OVDD and OGND).
1000
111000000
POWER DISSIPATI O N (mW)
SAMPLING RATE (kSPS)
100
10
10 100 1000 10000 100000
PDREF = PDBUF = HI GH
06395-032
Figure 32. Power Dissipation vs. Sample Rate
Power Down
Setting PD = high powers down the AD7610, thus reducing
supply currents to their minimums as shown in Figure 23. When
the ADC is in power down, the current conversion (if any) is
completed and the digital bus remains active. To further reduce
the digital supply currents, drive the inputs to OVDD or OGND.
Power down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a
don’t care and should be tied to either high or low.
CONVERSION CONTROL
The AD7610 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion. Detailed
timing diagrams of the conversion process are shown in Figure 33.
Once initiated, it cannot be restarted or aborted, even by the
power-down input, PD, until the conversion is complete. The
CNVST signal operates independently of CS and RD signals.
BUSY
MODE CONVERT ACQUIREACQUIRE CONVERT
CNVST
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
06395-033
Figure 33. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot, undershoot, or ringing.
The CNVST trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 27.
Data Sheet AD7610
Rev. A | Page 23 of 32
INTERFACES
DIGITAL INTERFACE
The AD7610 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7610
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
the OB/2C input pin, both twos complement or straight binary
coding can be used.
Two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7610
in multicircuit applications and is held low in a single AD7610
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7610. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7610 and clears
the data bus and configuration register. See Figure 34 for the
RESET timing details.
RESET
DATA
BUS
BUSY
CNVST
t
8
t
9
06395-034
Figure 34. RESET Timing
PARALLEL INTERFACE
The AD7610 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 35 details the timing for this mode.
t
1
BUSY
DATA
BUS PREVIO US CONVERS ION DATA NEW DATA
CNVST
CS = RD = 0
t
10
t
4
t
11
t
3
06395-035
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the conver-
sion, it is recommended that it is read only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CURRENT
CONVERSION
t13
t12
BUSY
DATA
BUS
RD
CS
06395-036
Figure 36. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t13
t12
t3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t4
t1
06395-037
Figure 37. Slave Parallel Data Timing for Reading (Read During Convert)
AD7610 Data Sheet
Rev. A | Page 24 of 32
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, when BYTESWAP is low, the LSB byte
is output on D[7:0] and the MSB is output on D[15:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped; the
LSB is output on D[15:8] and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0]. This interface
can be used in both master and slave parallel reading modes.
CS
RD
BYTESWAP
PI NS D[ 15: 8]
PI NS D[ 7: 0] HI-Z
HI-Z HIG H BY TE LOW BYTE
LOW BYTE HIGH BYT E HI-Z
HI-Z
t12 t12 t13
06395-038
Figure 38. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7610 has a serial interface (SPI-compatible) multiplexed
on the data pins D[15:2]. The AD7610 is configured to use the
serial interface when SER/PAR is held high.
Data Interface
The AD7610 outputs 16 bits of data, MSB first, on the SDOUT pin.
This data is synchronized with the 16 clock pulses provided on
the SDCLK pin. The output data is valid on both the rising and
falling edge of the data clock.
Serial Configuration Interface
The AD7610 can be configured through the serial configuration
register only in serial mode as the serial configuration pins are
also multiplexed on the data pins D[15:12]. See the Hardware
Configuration section and Software Configuration section for
more information.
MASTER SERIAL INTERFACE
The pins multiplexed on D[10:2] and used for the master serial
interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC,
INVSCLK, RDC, SDOUT, SDCLK and SYNC.
Internal Clock (SER/PAR = High, EXT/INT = Low)
The AD7610 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/INT pin is held low. The
AD7610 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK, and the SYNC signals
can be inverted, if desired using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data can
be read during the following conversion or after each conver-
sion. Figure 39 and Figure 40 show detailed timing diagrams of
these two modes.
Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low, allows the read after conversion mode.
Since the AD7610 is limited to 250kSPS and the time between
conversions, t2 = 4µs, this mode is the most recommended
serial mode. Unlike the other serial modes, the BUSY signal
returns low after the 16 data bits are pulsed out and not at the
end of the conversion phase, resulting in a longer BUSY width
(See Table 4 for BUSY timing specifications). The
DIVSCLK[1:0] inputs control the SDCLK period and SDOUT
data rate. As a result, the maximum throughput can only be
achieved in two of the DIVSCLK[1:0] settings. In this mode, the
AD7610 generates a discontinuous SDCLK however, a fixed
period and hosts supporting both SPI and serial ports can also
be used.
Read During Convert (RDC = High)
Setting RDC = high, allows the master read (previous conver-
sion result) during conversion mode. In this mode, the serial
clock and data toggle at appropriate instances, minimizing
potential feed through between digital activity and critical
conversion decisions. In this mode, the SDCLK period changes
since the LSBs require more time to settle and the SDCLK is
derived from the SAR conver-sion cycle. In this mode, the
AD7610 generates a discontinuous SDCLK of two different
periods and the host should use an SPI interface.
Data Sheet AD7610
Rev. A | Page 25 of 32
BUSY
SYNC
SDCLK
SDOUT
123 141516
D15 D14 D2 D1 D0
X
RDC/SDI N = 0 INVS CLK = I NV SYNC = 0
CNVST
CS, RD EXT/INT = 0
t
16
t
15
t
22
t
23
t
21
t
19
t
18
t
20
t
14
t
29
t
28
t
26
t
27
t
24
t
25
t
30
t
3
06395-039
Figure 39. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0 RDC/SDI N = 1 INVSCLK = I NVSYNC = 0
D15 D14 D2 D1 D0X
123 141516
BUSY
SYNC
SDCLK
SDOUT
CNVST
CS, RD
t27
t26
t24
t25
t23
t22
t18
t15
t14
t16
t17
t19
t20 t21
t3
t1
06395-040
Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7610 Data Sheet
Rev. A | Page 26 of 32
SLAVE SERIAL INTERFACE
The pins multiplexed on D[11:4] used for slave serial interface are:
EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK and RDERROR.
External Clock (SER/PAR = High, EXT/INT = High)
Setting the EXT/INT = high allows the AD7610 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The external
serial clock is gated by CS. When CS and RD are both low, the
data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally low
when inactive. For detailed timing diagrams, see Figure 42 and
Figure 43.
While the AD7610 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is par-
ticularly important during the last 475 ns of the conversion phase
because the AD7610 provides error correction circuitry that can
correct for an improper bit decision made during the first part
of the conversion phase. For this reason, it is recommended that
any external clock provided, is a discontinuous clock that transi-
tions only when BUSY is low, or, more importantly, that it does
not transition during the last 475 ns of BUSY high.
External Discontinuous Clock Data Read After
Conversion
Since the AD7610 is limited to 250 kSPS, the time between con-
versions, t4 = 4 μs, and the conversion time, t7 = 1.45 μs. This
makes the read after conversion mode the most recommended
serial slave mode since the time to read the data is t4 − t7. Figure 42
shows the detailed timing diagrams for this method. After a
conversion is complete, indicated by BUSY returning low, the
conversion result can be read while both CS and RD are low.
Data is shifted out MSB first with 16 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
Daisy-Chain Feature
Also in the read after convert mode, the AD7610 provides a daisy-
chain feature for cascading multiple converters together using the
serial data input, SDIN, pin. This feature is useful for reducing
component count and wiring connections when desired, for
instance, in isolated multiconverter applications. See Figure 42
for the timing details.
An example of the concatenation of two devices is shown in
Figure 41. Simultaneous sampling is possible by using a common
CNVST signal. Note that the SDIN input is latched on the opposite
edge of SDCLK used to shift out the data on SDOUT (SDCLK
falling edge when INVSCLK = low). Therefore, the MSB of the
upstream converter follows the LSB of the down-stream converter
on the next SDCLK cycle. In this mode, the 40 MHz SDCLK
rate cannot be used since the SDIN to SDCLK setup time, t33, is
less than the minimum time specified. (SDCLK to SDOUT delay,
t32, is the same for all converters when simultaneously sampled).
For proper operation, the SDCLK edge for latching SDIN (or ½
period of SDCLK) needs to be:
3332
SDCLK ttt +=
2/1
Or the max SDCLK frequency needs to be:
)(2
1
3332
SDCLK tt
f+
=
If not using the daisy-chain feature, the SDIN input should be
tied either high or low.
SCLK
SDOUTRDC/SDIN
AD7610
#1
(DOWNSTREAM)
AD7610
#2
(UPSTREAM)
BUSY
OUT
BUSYBUSY
DATA
OUT
SCLK
RDC/SDIN SDOUT
SCL K IN
CNVST IN
CNVST
CS
CNVST
CS
CS I N
06395-041
Figure 41. Two AD7610 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
Figure 43 shows the detailed timing diagrams for this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both the rising
and falling edge of the clock. The 16 bits have to be read before
the current conversion is complete; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
The daisy-chain feature should not be used in this mode since
digital activity occurs during the second half of the SAR
conversion phase likely resulting in performance degradation.
Data Sheet AD7610
Rev. A | Page 27 of 32
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion has been
initiated. This method allows the full throughput and the use of
a slower SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode
and 13 MHz in impulse mode can be used.
SDIN
SDOUT D0
1 2 3 15 16
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 4
D2 D1
17 18
SER/ P AR = 1 RD = 0
14
D15 D14 D13 X15 X14
19
X0
X2 X1
X15 X14 X13 Y15 Y14
t
31
t
31
X*
t
32
t
16
t
33
t
34
t
37
t
35
t
36
*A DISCO NTI NUOUS SDCL K IS RE COMMENDE D.
06395-042
Figure 42. Slave Serial Data Timing for Reading (Read After Convert)
S
DOUT D0
123
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK 15
D1
SER/ P AR = 1 RD = 0
16
D15 D14 DATA = SDIN
t
31
t
31
t
32
t
16
t
37
t
35
t
36
CNVST
X*
X* X* X* X* X*
t
27
*A DISCO NTI NUO US S DCLK IS RECOMMENDED.
06395-043
Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
AD7610 Data Sheet
Rev. A | Page 28 of 32
HARDWARE CONFIGURATION
The AD7610 can be configured at any time with the dedicated
hardware pins BIPOLAR, TEN, OB/2C, and PD for parallel mode
(SER/PAR = low) or serial hardware mode (SER/ PAR = high,
HW/SW = high). Programming the AD7610 for input range
configuration can be done before or during conversion. Like
the RESET input, the ADC requires at least one acquisition
time to settle as indicated in Figure 44. See Table 6 for pin descrip-
tions. Note that these inputs are high impedance when using
the software configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[15:12] used for software configu-
ration are: HW/SW, SCIN, SCCLK, and SCCS. The AD7610 is
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See Table 9 for details of each bit in the configuration register.
The SCP can only be used in serial software mode selected with
SER/PAR = high and HW/SW = low since the port is multiplexed
on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 45 for timing details. SCIN is clocked into the con-
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the start bit. The 9th
SPPCLK edge updates the register and allows the new settings to be
used. As indicated in the timing diagram, at least one acquisition
time is required from the 9th SCCLK edge. Bits [4:3] and [1:0] are
reserved bits and are not written to while the SCP is being
updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7610 is not busy convert-
ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not
attainable because the time required for SCP access is (t31+ 9 × 1/
SCCLK +t8) minimum. If the full throughput is required, the
SCP can be written to during conversion, however it is not
recommended to write to the SCP during the last 475 ns of
conversion (BUSY = high) or performance degradation can
result. In addition, the SCP can be accessed in both serial
master and serial slave read during and read after convert modes.
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
Table 9. Configuration Register Description
Bit Name Description
8 START START bit. With the SCP enabled (SCCS = low),
when START is high, the first rising edge of SCCLK
(INVSCLK = low) begins to load the register with
the new configuration.
7
BIPOLAR
Input Range Select. Used in conjunction with Bit 6,
TEN, per the following:
Input Range
BIPOLAR
TEN
0 V to 5 V Low Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V High High
6
TEN
Input Range Select. See Bit 7, BIPOLAR.
5 PD Power Down.
PD = Low, normal operation.
PD = High, power down the ADC. The SCP is
accessible while in power down. To power up the
ADC, write PD = low on the next configuration
setting.
4 RSV Reserved.
3 RSV Reserved.
2 OB/2C Output Coding
OB/2C = Low, use twos complement output.
OB/2C = High, use straight binary output.
1
RSV
Reserved.
0 RSV Reserved.
WARP,
IMPULSE
BUSY
HW/SW = 0
CNVST
BIPOLAR,
TEN
t
8
SER/PAR = 0, 1PD = 0
t
8
06395-044
Figure 44. Hardware Configuration Timing
Data Sheet AD7610
Rev. A | Page 29 of 32
SCIN
SCCLK
X
START TEN
12 3 67
BUSY
HW/SW = 0 INV S CLK = 0
CNVST
SCCS
4
PD
5
BIPOLAR
XOB/2C X
89
SER/PAR = 1
BIP = 0 OR 1
TE N = 0 OR 1
IMPULSE = 0 OR 1
WARP = 0 OR 1 PD = 0
t
31
t
33
t
34
X
t
35
t
36
t
37
t
31
t
8
06395-045
Figure 45. Serial Configuration Port Timing
MICROPROCESSOR INTERFACING
The AD7610 is ideally suited for traditional dc measurement appli-
cations supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The AD7610 is
designed to interface with a parallel 8-bit or 16-bit wide inter-
face, or with a general-purpose serial port or I/O ports on a micro-
controller. A variety of external buffers can be used with the
AD7610 to prevent digital noise from coupling into the ADC.
SPI Interface
The AD7610 is compatible with SPI and QSPI digital hosts
and DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/
ADSP-219x. Figure 46 shows an interface diagram between the
AD7610 and the SPI-equipped ADSP-219x. To accommodate
the slower speed of the DSP, the AD7610 acts as a slave device, and
data must be read after conversion. This mode also allows the
daisy-chain feature. The convert command could be initiated
in response to an internal timer interrupt.
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps allowing it to read an ADC
result in less than 1 µs. When a higher sampling rate is desired,
use one of the parallel interface modes.
BUSY
CS
SDOUT
SCLK
CNVST
AD7610*
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
06395-046
Figure 46. Interfacing the AD7610 to SPI Interface
AD7610 Data Sheet
Rev. A | Page 30 of 32
APPLICATION INFORMATION
LAYOUT GUIDELINES
While the AD7610 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To facil-
itate the use of ground planes that can be easily separated, design
the printed circuit board that houses the AD7610 so that the
analog and digital sections are separated and confined to certain
areas of the board. Digital and analog ground planes should be
joined in only one place, preferably underneath the AD7610, or
as close as possible to the AD7610. If the AD7610 is in a system
where multiple devices require analog-to-digital ground connect-
ions, the connections should still be made at one point only, a
star ground point, established as close as possible to the AD7610.
To prevent coupling noise onto the die, avoid radiating noise,
and to reduce feedthrough:
• Do not run digital lines under the device.
• Do run the analog ground plane under the AD7610.
• Do shield fast switching signals, like CNVST or clocks, with
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
• Avoid crossover of digital and analog signals.
• Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough through
the board.
The power supply lines to the AD7610 should use as large a trace as
possible to provide low impedance paths and reduce the effect of
glitches on the power supply lines. Good decoupling is also
important to lower the impedance of the supplies presented to
the AD7610, and to reduce the magnitude of the supply spikes.
Decoupled ceramic capacitors, typically 100 nF, should be placed
on each of the power supplies pins, AVDD, DVDD, and OVDD,
VCC, and VEE. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding ground
pins. Additionally, low ESR 10 µF capacitors should be located
in the vicinity of the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7610 can be either a separate supply
or come from the analog supply, AVDD, or from the digital
interface supply, OVDD. When the system digital supply is noisy,
or fast switching digital signals are present, and no separate supply
is available, it is recommended to connect the DVDD digital supply
to the analog supply AVDD through an RC filter, and to connect
the system supply to the interface digital supply OVDD and the
remaining digital circuitry. See Figure 27 for an example of this
configuration. When DVDD is powered from the system supply,
it is useful to insert a bead to further reduce high frequency spikes.
The AD7610 has four different ground pins: REFGND, AGND,
DGND, and OGND.
• REFGND senses the reference voltage and, because it carries
pulsed currents, should be a low impedance return to the
reference.
• AGND is the ground to which most internal ADC analog
signals are referenced; it must be connected with the least
resistance to the analog ground plane.
• DGND must be tied to the analog or digital ground plane
depending on the configuration.
• OGND is connected to the digital system ground.
The layout of the decoupling of the reference voltage is important.
To minimize parasitic inductances, place the decoupling capacitor
close to the ADC and connect it with short, thick traces.
EVALUATING PERFORMANCE
A recommended layout for the AD7610 is outlined in the EVAL-
AD7610EDZ evaluation board documentation. The evaluation
board package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from a PC via the EVAL-CED1Z.
Data Sheet AD7610
Rev. A | Page 31 of 32
OUTLINE DIMENSIONS
COMP LI ANT TO JEDE C S TANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD P ITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
RO TAT E D 9 0° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 S Q
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
COM PLI ANT T O JEDE C STANDARDS M O - 220- VKKD -2
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.80 MAX
0.65 TY P
5.50 REF
COPLANARITY
0.08
0.20 R E F
1.00
0.85
0.80 0.05 MA X
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.25 M IN
7.10
7.00 S Q
6.90
6.85
6.75 SQ
6.65
06-05-2012-A
FOR PROPER CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATION AND
FUNCTION DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes Temperature Range Package Description Package Option
AD7610BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7610BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD7610BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
AD7610BSTZ-RL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48
EVAL-AD7610EDZ 2 Evaluation Board
EVAL-CED1Z 3 Converter Evaluation and Development Board
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the ED designators.
AD7610 Data Sheet
Rev. A | Page 32 of 32
NOTES
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06395-0-12/12(A)
