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Sleep and Ultra-Low-Power Modes
The devices feature a sleep mode and an ultra-low-
power mode in which the internal p-channel isolation
MOSFET is kept on and the buck regulator is off. In sleep
mode, the LED driver output (LED) pulse width modu-
lates the LED current with a 25% duty cycle. The peak
LED current (ILED) is set by an external resistor R SL. To
enable sleep mode, apply a falling edge to SL with ULP
disconnected or high impedance. Sleep mode can only
be entered from wake mode.
Ultra-low-power mode allows the devices to reduce
power consumption lower than sleep mode, while main-
taining the power signature of the IEEE standard. The
ultra-low-power-mode enable input ULP is internally held
high with a 50kω pullup resistor to the internal 5V bias of
the device. To enable ultra-low-power mode, apply a fall-
ing edge to SL with ULP = LOW. Ultra-low-power mode
can only be entered from wake mode.
To exit from sleep mode or ultra-low-power mode and
resume normal operation, apply a falling edge on the
wake-mode enable input (WK).
Thermal-Shutdown Protection
If the devices’ die temperature reaches 151°C, an over-
temperature fault is generated and the device shuts
down. The die temperature must cool down below
+135°C to remove the overtemperature fault condition.
After a thermal shutdown condition clears, the device is
reset.
WAD Description
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
devices feature wall power adapter detection.
The wall power adapter is connected from WAD to PGND.
The devices detect the wall power adapter when the volt-
age from WAD to PGND is greater than 8.8V. When a wall
power adapter is detected, the internal isolation MOSFET
is turned off, classification current is disabled.
Connect the auxiliar power source to WAD, connect a
diode from WAD to VDD, and connect a diode from WAD
to VCC. See the typical application circuit in Figures 3
and 4.
The application circuit must ensure that the auxiliary
power source can provide power to VDD and VCC by
means of external diodes. The voltage on VDD must be
within the VDD voltage range to allow the DC-DC to oper-
ate. To allow operation of the DC-DC converter, the VDD
and VCC voltage must be greater than 8V, on the rising
edge, while on the falling edge the VDD and VCC may fall
down to 7.7V keeping the DC-DC converter on.
Note: When operating solely with a wall power adapter,
the WAD voltage must be able to meet the condition VDD
> 8.8V, that likely results in WAD > 8.8V.
Internal Linear Regulator and Back Bias
An internal voltage regulator provides VDRV to internal
circuitry. The VDRV output is filtered by a 1µF capaci-
tor connected from VDRV to GND. The regulator is for
internal use only and cannot be used to provide power to
external circuits. VDRV can be powered by either VDD or
VAUX, depending on VAUX. The internal regulator is used
for both PD and buck converter operations.
VOUT can be used to back bias the VDRV voltage regu-
lator if VOUT is greater than 4.75V. Back biasing VDRV
increases device efficiency by drawing current from
VOUT instead of VDD. If VOUT is used as back bias,
connect AUX directly to VOUT. In this configuration, the
VDRV source switches from VDD to VAUX after the buck
converter’s output has reached its regulation voltage.
Cable Discharge Event Protection (CDE)
A 70V voltage clamp is integrated to protect the internal
circuits from a cable discharge event.
DC-DC Buck Converter
The DC-DC buck converter uses a PWM, peak current-
mode, fixed-frequency control scheme providing an
easy-to-implement architecture without sacrificing a fast
transient response. The buck converter operates in a
wide input voltage range from 8.8V to 60V and supports
up to 6.49W of output power at 1.3A load. The devices
provide a wide array of protection features including
UVLO, overtemperature shutdown, short-circuit protec-
tion with hiccup runaway current limit, cycle-by-cycle
peak current protection, and cycle-by-cycle output over-
voltage protection, for enhanced performance and reli-
ability. A frequency foldback scheme is implemented to
reduce the switching frequency to half at light loads to
increase the efficiency.
www.maximintegrated.com Maxim Integrated
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MAX5988A/MAX5988B IEEE 802.3af-Compliant, High-Efciency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter