©2012 Integrated Device Technology, Inc.
1
JUNE 2012
DSC-5670/9
Functional Block Diagram
◆◆
◆◆
◆Full hardware support of semaphore signaling between
ports on-chip
◆◆
◆◆
◆Fully asynchronous operation from either port
◆Separate byte controls for multiplexed bus and bus
matching compatibility
◆◆
◆◆
◆Sleep Mode Inputs on both ports
◆◆
◆◆
◆Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
◆◆
◆◆
◆Single 2.5V (±100mV) power supply for core
◆◆
◆◆
◆LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆◆
◆◆
◆Available in a 256-ball Ball Grid Array and 208-ball fine pitch
Ball Grid Array
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆Green parts available, see ordering information
Features
◆◆
◆◆
◆True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆◆
◆◆
◆RapidWrite Mode simplifies high-speed consecutive write
cycles
◆◆
◆◆
◆Dual chip enables allow for depth expansion without
external logic
◆◆
◆◆
◆IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆Busy and Interrupt Flags
◆◆
◆◆
◆On-chip port arbitration logic
HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
IDT70T633/1S
1. Address A18x is a NC for IDT70T631.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
CE
0R
R/
W
R
CE
1R
LB
R
UB
R
512/256K x 18
MEMORY
ARRAY
Address
Decoder
A
18R
(1)
A
0R
Address
Decoder
CE
0L
R/
W
L
CE
1L
LB
L
UB
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
I/O
0L
-I/O
17L
I/O
0R
-I/O
17R
Din_L
ADDR_L
Din_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
CE
0R
CE
1R
5670 drw 01
A
18L
(1)
A
0L
ZZ
CONTROL
LOGIC
ZZ
L(4)
ZZ
R(4)
JTAG
TCK
TRST
TMS
TDI
TDO
INT
L(3)
SEM
L
BUSY
L(2,3)
BUSY
R(2,3)
SEM
R
IN T
R(3)
NOTES:
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous
Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-
TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The IDT70T633/1 has a RapidWrite Mode which allows the designer
to perform back-to-back write operations without pulsing the R/W input
each cycle. This is especially significant at the 10ns cycle times of the
IDT70T633/1, easing design considerations at these high performance
levels.
The 70T633/1 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) remains at 2.5V.
3
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3)
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
70T633/1BC
BC-256(5,6)
256-Pin BGA
Top View
E16
I/O
7R
D16
I/O
8R
C16
I/O
8L
B16
NC
A16
NC
A15
NC
B15
NC
C15
NC
D15
NC
E15
I/O
7L
E14
NC
D14
NC
D13
V
DD
C12
A
6L
C14
OPT
L
B14
NC
A14
A
0L
A12
A
5L
B12
A
4L
C11
BUSY
L
D12
V
DDQR
D11
V
DDQR
C10
SEM
L
B11
NC
A11
INT
L
D8
V
DDQR
C8
NC
A9
CE
1L
D9
C9
LB
L
B9
CE
0L
D10
V
DDQL
C7
A
7L
B8
UB
L
A8
NC
B13
A
1L
A13
A
2L
A10
OE
L
D7
V
DDQR
B7
A
9L
A7
A
8L
B6
A
12L
C6
A
10L
D6
V
DDQL
A5
A
14L
B5
A
15L
C5
A
13L
D5
V
DDQL
A4
B4
A
18L
(4)
C4
A
16L
D4
V
DD
A3
NC
B3
TDO
C3
V
SS
D3
NC
D2
I/O
9R
C2
I/O
9L
B2
NC
A2
TDI
A1
NC
B1
NC
C1
NC
D1
NC
E1
I/O
10R
E2
I/O
10L
E3
NC
E4
V
DDQL
F1
I/O
11L
F2
NC
F3
I/O
11R
F4
V
DDQL
G1
NC
G2
NC
G3
I/O
12L
G4
V
DDQR
H1
NC
H2
I/O
12R
H3
NC
H4
V
DDQR
J1
I/O
13L
J2
I/O
14R
J3
I/O
13R
J4
V
DDQL
K1
NC
K2
NC
K3
I/O
14L
K4
V
DDQL
L1
I/O
15L
L2
NC
L3
I/O
15R
L4
V
DDQR
M1
I/O
16R
M2
I/O
16L
M3
NC
M4
V
DDQR
N1
NC
N2
I/O
17R
N3
NC
N4
V
DD
P1
NC
P2
I/O
17L
P3
TMS
P4
A
16R
R1
NC
R2
NC
R3
TRST
R4
A
18R
(4)
T1
NC
T2
TCK
T3
NC
T4
A
17R
P5
A
13R
R5
A
15R
P12
A
6R
P8
NC
P9
LB
R
R8
UB
R
T8
NC
P10
SEM
R
T11
INT
R
P11
BUSY
R
R12
A
4R
T12
A
5R
P13
A
3R
P7
A
7R
R13
A
1R
T13
A
2R
R6
A
12R
T5
A
14R
T14
A
0R
R14
OPT
R
P14
NC
P15
NC
R15
NC
T15
NC
T16
NC
R16
NC
P16
I/O
0L
N16
NC
N15
I/O
0R
N14
NC
M16
NC
M15
I/O
1L
M14
I/O
1R
L16
I/O
2R
L15
NC
L14
I/O
2L
K16
I/O
3L
K15
NC
K14
NC
J16
I/O
4L
J15
I/O
3R
J14
I/O
4R
H16
I/O
5R
H15
NC
H14
NC
G16
NC
G15
NC
G14
I/O
5L
F16
I/O
6L
F14
I/O
6R
F15
NC
R9
CE
0R
R11
M/S
T6
A
11R
T9
CE
1R
A6
A
11L
B10
R/W
L
C13
A
3L
P6
A
10R
R10
R/W
R
R7
A
9R
T10
OE
R
T7
A
8R
,
E5
V
DD
E6
V
DD
E7
V
SS
E8
V
SS
E9
V
SS
E10
V
SS
E11
V
DD
E12
V
DD
E13
V
DDQR
F5
V
DD
F6
NC
F8
V
SS
F9
V
SS
F10
V
SS
F12
V
DD
F13
V
DDQR
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
SS
G12
V
SS
G13
V
DDQL
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
SS
H13
V
DDQL
J5
ZZ
R
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
ZZ
L
J13
V
DDQR
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
L5
V
DD
L6
NC
L7
V
SS
L8
V
SS
M5
V
DD
M6
V
DD
M7
V
SS
M8
V
SS
N5 N6
V
DDQR
N7
V
DDQL
N8
V
DDQL
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DD
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DD
N9
V
DDQR
N10
V
DDQR
N11
V
DDQL
N12
V
DDQL
K13
V
DDQR
L13
V
DDQL
M13
V
DDQL
N13
V
DD
F7
V
SS
F11
V
SS
5670 drw 02c
,
03/13/03
A
17L
V
DDQL
V
DDQR
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configurations(1,2,3)(con't.)
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
1716
15
1412 13
10
9876543
21 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
NC V
SS
A
4L
INT
L
SEM
L
NCA
8L
A
12L
A
16L
V
SS
NC
OPT
L
A
0L
NC V
SS
NC
NC
A
1L
A
5L
BUSY
L
V
SS
CE
0L
CE
1L
NC
A
9L
A
13L
A
17L
I/O
8L
V
DDQR
V
SS
V
DD QL
I/O
9R
V
DDQR
V
DD
A
2L
A
6
L
R/
W
L
V
SS
UB
L
A
10L
A
14 L
A
18L
(4)
NC
I/O
8R
V
DD
I/O
11L
V
SS
I/O
10L
NC V
DD
A
3L
NC
OE
L
NC
I/O
11R
V
DDQR
I/O
10 R
V
DDQL
NC
NC V
SS
NC V
SS
I/O
12L
NC
V
DD
NC V
DDQR
I/O
12R
V
DD QL
V
DD
V
SS
ZZ
R
NC I/O
14L
V
DDQR
V
DD QL
NC I/O
15R
V
SS
I/O
7R
V
DDQL
I/O
7L
A
15L
A
11L
A
7L
LB
L
I/O
6L
NC V
SS
NC
V
SS
I/O
6R
NC
NC V
DDQL
I/O
5L
NC
V
DD
NC V
SS
I/O
5R
ZZ
L
V
DDQR
I/O
3R
V
DDQL
I/O
4R
V
SS
I/O
4L
V
SS
I/O
3L
NC
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
1R
NC V
SS
NC I/O
15 L
A
16R
A
12R
A
8R
NC V
DD
SEM
R
INT
R
V
DDQR
NC I/O
1L
NC
V
SS
NC I/O
17R
A
17R
A
13R
A
9R
NC
CE
0R
CE
1R
V
DD
V
SS
BUSY
R
V
SS
V
DD
V
SS
V
DDQL
I/O
0R
V
DD QR
NC I/O
17L
V
DDQL
NC
A
18R
(4)
A
14R
A
10R
UB
R
V
SS
NC
NCV
SS
I/O
2R
NC
V
SS
NC V
DD
A
15R
A
11R
A
7R
LB
R
OE
R
M/
S
R/
W
R
V
DDQL
I/O
2L
OPT
R
NC I/O
0L
70T633/1BF
BF-208
(5,6)
208-Ball BGA
Top View
(7)
5670 drw 02b
I/O
13L
I/O
14R
V
SS
I/O
13R
V
SS
I/O
16R
I/O
16L
V
DDQR
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
NC
V
DDQR
V
SS
V
DD
V
SS
NC
V
DD
V
DD
TDO
TDI
TCK
TMS
TRST
V
SS
03/12/03
5
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Pin Names
Left Port Right Port Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables (Input)
R/W
L
R/W
R
Read/Write Enable (Input)
OE
L
OE
R
Output Enable (Input)
A
0L
- A
18L
(1)
A
0R
- A
18R
(1)
Address (Input)
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable (Input)
INT
L
INT
R
Interrupt Flag (Output)
BUSY
L
BUSY
R
Busy Flag (Output)
UB
L
UB
R
Upper Byte Select (Input)
LB
L
LB
R
Lower Byte Select (Input)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(2)
(Input)
OPT
L
OPT
R
Option for selecting V
DDQX
(2,3)
(Input)
ZZ
L
ZZ
R
Sleep Mode Pin
(4)
(Input)
M/SMaster or Slave Select (Input)
(5)
V
DD
Power (2.5V)
(2)
(Input)
V
SS
Ground (0V) (Input)
TDI Test Data Input
TDO Test Data Output
TCK Test Logic Clock (10MHz) (Input)
TMS Test Mode Select (Input)
TRST Reset (Initialize TAP Controller) (Input)
5670 tbl 01
NOTES:
1. Address A18x is a NC for IDT70T631.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master
(M/S=VIH).
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
NOTE:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
Truth Table I—Read/Write and Enable Control(1)
OE SEM CE
0
CE
1
UB LB R/WZZ
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X H H X X X X L High-Z High-Z Deselected–Power Down
X H X L X X X L High-Z High-Z Deselected–Power Down
X H L H H H X L High-Z High-Z Both Bytes Deselected
XHLHHLLLHigh-Z D
IN
Write to Lower Byte
XHLHLHLL D
IN
High-Z Write to Upper Byte
XHLHLLLL D
IN
D
IN
Write to Both Bytes
LHLHHLHLHigh-ZD
OUT
Read Lower Byte
LHLHLHHL D
OUT
High-Z Read Uppe r Byte
LHLHLLHL D
OUT
D
OUT
Read Both Bytes
H H L H L L X L High-Z High-Z Outputs Disabled
X X X X X X X H High-Z High-Z High-Z Sleep Mode
5670 tbl 02
Truth Table II – Semaphore Read/Write Control(1)
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL.
Inputs
(1)
Outputs
Mode
CE
(2)
R/WOE UB LB SEM I/O
1-17
I/O
0
HHL L L LDATA
OUT
DATA
OUT
Read Data in Semaphore Flag
(3)
H↑XXL L X DATA
IN
Write I/O
0
into Semaphore Flag
LXXXX L
______ ______
Not Allowe d
5670 tbl 03
7
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1)
Recommended DC Operating
Conditions with VDDQ at 2.5V
Absolute Maximum Ratings(1)
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be
supplied as indicated above.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Grade
Ambient
Temperature GND V
DD
Commercial 0
O
C to +70
O
C0V2.5V
+
100mV
Industrial -40
O
C to +85
O
C0V2.5V
+
100mV
5670 tbl 04
Symbol Rating Commercial
& Industrial
Unit
V
TERM
(V
DD
)
V
DD
Te rm inal Vo l tag e
with Respect to GND
-0.5 to 3.6 V
V
TERM
(2)
(V
DDQ
)
V
DDQ
Terminal Voltage
with Respect to GND
-0.3 to V
DDQ
+ 0.3 V
V
TE RM
(2)
(INPUTS and I/O's)
Input and I/O Te rminal
Voltage with Respect to GND
-0.3 to V
DDQ
+ 0.3 V
T
BIAS
(3)
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
T
JN
Junction Temperature +150
o
C
I
OUT
(For V
DDQ
=
3.3V) DC Output Current 50 mA
I
OUT
(For V
DDQ
=
2.5V) DC Output Current 40 mA
5670 tbl 07
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
2.4 2.5 2.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage
(Address, Control &
Data I/O Inputs)
(3)
1.7
____
V
DDQ
+ 100mV
(2)
V
V
IH
Input High Voltage
_
JTAG 1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, M/SV
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.7 V
V
IL
Input Low Voltage -
ZZ, OPT, M/S-0.3
(1)
____
0.2 V
5670 tbl 05
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) TQFP ONLY
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 8 pF
C
OUT
(3)
Output Capacitance V
OUT
= 3dV 10.5 pF
5670 tbl 08
Recommended DC Operating
Conditions with VDDQ at 3.3V
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.4 2.5 2.6 V
V
DDQ
I/O Supply Voltage
(3)
3.15 3.3 3.45 V
V
SS
Ground 0 0 0 V
V
IH
Input Hig h Voltage
(Address, Control
&Data I/O Inputs)
(3)
2.0
____
V
DDQ
+ 150mV
(2)
V
V
IH
Input Hig h Voltage
_
JTAG 1.7
____
V
DD
+ 100mV
(2)
V
V
IH
Input High Voltage -
ZZ, OPT, M/SV
DD
- 0.2V
____
V
DD
+ 100mV
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.8 V
V
IL
Input Low Voltage -
ZZ, OPT, M/S-0.3
(1)
____
0.2 V
5670 tbl 06
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
Symbol Parameter Test Conditions
70T633/1S
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
DDQ
= Max., V
IN
= 0V to V
DDQ
___
10 µA
|I
LI
| JTAG & ZZ Input Leakage Current
(1,2)
V
DD =
Max.
,
V
IN
= 0V to V
DD
___
+30 µA
|I
LO
| Output Leakage Current
(1,3)
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DDQ
___
10 µA
V
OL
(3.3V) Output Low Voltage
(1)
I
OL
= +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3.3V) Output High Voltage
(1)
I
OH
= -4mA, V
DDQ
= Min. 2.4
___
V
V
OL
(2.5V) Output Low Voltage
(1)
I
OL
= +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2.5V) Output High Voltage
(1)
I
OH
= -2mA, V
DDQ
= Min. 2.0
___
V
5670 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS".
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ).
4. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
5. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
70T633/1S10
Com'l
& Ind
(6)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Symbol Parameter Test Condition Version Typ.
(4)
Max. Typ.
(4)
Max. Typ.
(4)
Max. Unit
I
DD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(1)
COM'L S 300 405 300 355 225 305 mA
IND S 300 445 300 395
____ ____
I
SB1
(6)
Standby Current
(Both Ports - TTL
Leve l Inputs)
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L S 90 120 75 105 60 85 mA
IND S 90 145 75 130
____ ____
I
SB2
(6)
Standby Current
(One Port - TTL
Leve l Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f = f
MAX
(1)
COM'L S 200 265 180 230 150 200 mA
IND S 200 290 180 255
____ ____
I
SB3
Full Standby Current
(Both Ports - CMOS
Leve l Inputs)
Both Ports CE
L
and
CE
R
> V
DDQ
- 0.2V,
V
IN
> V
DDQ
- 0.2V or V
IN
< 0.2V,
f = 0
(2)
COM'L S 2 10 2 10 2 10 mA
INDS220220
____ ____
I
SB4
(6)
Full Standby Current
(One Port - CMOS
Leve l Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
DDQ
- 0.2V
(5)
,
V
IN
> V
DDQ
- 0.2V or V
IN
< 0.2V,
Active Port, Outputs Disabled,
f = f
MAX
(1)
COM'L S 200 265 180 230 150 200 mA
IND S 200 290 180 255
____ ____
I
ZZ
Sleep Mode Current
(Both Ports - TTL
Leve l Inputs)
ZZ
L =
ZZ
R =
V
IH
f = f
MAX
(1)
COM'L S 2 10 2 10 2 10 mA
INDS220220
____ ____
5670 tbl 10
9
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ = 3.3V/2.5V)
Figure 1. AC Output Test load.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V / GND to 2.5V
2ns Max.
1.5V/1.25V
1.5V/1.25V
Figure 1
5670 tbl 11
1.5V/1.25
50Ω
50Ω
5670 drw 03
10pF
(Tester)
DATA
OUT
,
Figure 3. Typical Output Derating (Lumped Capacitive Load).
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
Symbol Parameter
70T633/1S10
Com'l
& Ind
(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15 ns
t
ACE
Chip Enable Access Time
(3) ____
10
____
12
____
15 ns
t
ABE
Byte Enable Access Time
(3) ____
5
____
6
____
7ns
t
AOE
Output Enable Access Time
____
5
____
6
____
7ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time Chip Enable and Semaphore
(1,2)
3
____
3
____
3
____
ns
t
LZOB
Output Low-Z Time Output Enable and Byte Enable
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
040608ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2) ____
8
____
8
____
12 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)
____
4
____
6
____
8ns
t
SAA
Semaphore Address Access Time 2 10 2 12 2 15 ns
t
SOE
Semaphore Output Enable Access Time
____
5
____
6
____
7ns
5670 tbl 12
Symbol Parameter
70T633/1S10
Com'l
& Ind
(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRI T E CYCLE
t
WC
Write Cycle Time 10
____
12
____
15
____
ns
t
EW
Chip Enable to End-of-Write
(3)
7
____
9
____
12
____
ns
t
AW
Address Valid to End-of-Write 7
____
9
____
12
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 7
____
9
____
12
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 5
____
7
____
10
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
4
____
6
____
8ns
t
OW
Output Active from End-of-Write
(1,2)
3
____
3
____
3
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window 5
____
5
____
5
____
ns
5670 tbl 13
11
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.
5. SEM = VIH.
6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
t
RC
R/W
CE
ADDR
t
AA
OE
UB,LB
5670 drw 06
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA(4)
(6)
.
(1)
t
LZ
/t
LZOB
CE
5670 drw 07
t
PU
I
CC
I
SB
t
PD
50% 50%
.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
NOTES:
1. R/W or CE or UB or LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB,LB
5670 drw 10
(9)
CE or SEM
(9)
(7)
(3)
.
(7)
5670 drw 11
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB,LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
.
.
13
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
RapidWrite Mode Write Cycle
Unlike other vendors' Asynchronous Random Access Memories,
the IDT70T633/1 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
During this new RapidWrite Mode, the end of the write cycle is now
defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles.
Care must be taken to still meet the Write Cycle time (tWC), the time in
which the Address inputs must be stable. Input data setup and hold times
(tDW and tDH) will now be referenced to the ending address transition. In
this RapidWrite Mode the I/O will remain in the Input mode for the duration
of the operations due to R/W being held low. All standard Write Cycle
specifications must be adhered to. However, tAS and tWR are only
applicable when switching between read and write operations. Also,
there are two additional conditions on the Address Inputs that must also
be met to ensure correct address controlled writes. These specifications,
the Allowable Address Skew (tAAS) and the Address Rise/Fall time (tARF),
must be met to use the RapidWrite Mode. If these conditions are not met
there is the potential for inadvertent write operations at random intermediate
locations as the device transitions between the desired write addresses.
5670 drw 08
t
WC
t
WC
t
WC
t
EW
t
WP
t
WZ
t
DH
t
DW
t
DW
t
DW
t
OW
t
WR
ADDRESS
CE or SEM
(6)
BEn
R/W
DATA
IN
DATA
OUT
(2)
(5) (5)
t
DH
t
DH
(4)
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
5670 drw 09
A
0
A
18
t
AAS
t
ARF
t
ARF
(1)
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
NOTE:
1. A17 for IDT70T631.
Symbol Parameter Min Max Unit
t
AAS
Allowable Address Skew for RapidWrite Mode
____
1ns
t
ARF
Address Rise/Fall Time for RapidWrite Mode 1.5
____
V/ns
5670 tbl 14
15
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL, CE0L = CE0R = VIH; CE1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate UB/LB controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
SEM
(1)
5670 drw 12
t
AW
t
EW
I/O
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA VALID
IN
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
Read Cycle
Write Cycle
A
0
-A
2
OE
VALID
(2)
t
SOP
t
SOP
.
t
SOE
SEM
"A"
5670 drw 13
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Symbol Parameter
70T633/1S10
Com'l
& Ind(6)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Unit
Min. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match ____ 10 ____ 12 ____ 15 ns
t
BDA
BUSY Disable Time from Address Not Matched ____ 10 ____ 12 ____ 15 ns
t
BAC
BUSY Access Time from Chip Enable Low ____ 10 ____ 12 ____ 15 ns
t
BDC
BUSY Disable Time from Chip Enable High ____ 10 ____ 12 ____ 15 ns
t
APS
Arbitration Priority Se t-up Time(2) 2.5 ____ 2.5 ____ 2.5 ____ ns
t
BDD
BUSY Disable to Valid Data(3 ) ____ 10 ____ 12 ____ 15 ns
t
WH
Write Hold After BUSY(5) 7____ 9____ 12 ____ ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write(4) 0____ 0____ 0____ ns
t
WH
Write Hold After BUSY(5) 7____ 9____ 12 ____ ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay(1) ____ 14 ____ 16 ____ 20 ns
t
DDD
Write Data Valid to Read Data Delay(1) ____ 14 ____ 16 ____ 20 ns
5670 tbl 15
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2,3)
Symbol Parameter
70T633/1S10
Com'l
& Ind
70T6331S12
Com'l
& Ind
70T633/1S15
Com'l Only
Min. Max. Min. Max. Min. Max.
SLEEP MODE TIMING (ZZx=V
IH
)
t
ZZS
Sleep Mode Set Time 10
____
12
____
15
____
t
ZZR
Sleep Mode Reset Time 10
____
12
____
15
____
t
ZZPD
Sleep Mode Power Down Time
(4)
10
____
12
____
15
____
t
ZZPU
Sleep Mode Power Up Time
(4)
____
0
____
0
____
0
5670 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
4. This parameter is guaranteed by device characterization, but is not production tested.
17
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB only applies to the slave mode.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
5670 drw 14
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
.
5670 drw 15
R/W
"A"
BUSY
"B"
t
WB
(3)
R/W
"B"
t
WH
(1)
(2)
t
WP
.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
18
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1,3,4)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.
4. CE0X = OEX = LBX = UBX = VIL. CE1X = VIH.
5670 drw 16
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"(3)
CE
"B"(3)
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
.
5670 drw 17
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
70T633/1S10
Com'l
& Ind
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Interrup t Set Time
____
10
____
12
____
15 ns
t
INR
Interrup t Reset Time
____
10
____
12
____
15 ns
5670 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
19
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1,4)
Waveform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
5670 drw 18
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"(3)
R/W
"A"
t
AS
t
WC
t
WR
(4) (5)
t
INS
(4)
INT
"B"
(2)
.
5670 drw 19
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"(3)
OE
"B"
t
AS
t
RC
(4)
t
INR
(4)
INT
"B"
(2)
.
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
18L
-A
0L
(5)
INT
L
R/W
R
CE
R
OE
R
A
18R
-A
0R
(5)
INT
R
LLX7FFFFXXXX X L
(2)
Set Right INT
R
Flag
XXX X XXLL7FFFFH
(3)
Reset Right INT
R
Flag
XXX X L
(3)
L L X 7FFFE X Set Left INT
L
Flag
X L L 7FFFE H
(2)
X X X X X Reset Left INT
L
Flag
5670 tb l 17
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
20
Functional Description
The IDT70T633/1 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T633/1 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = HIGH). When a port is enabled, access to the
entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF. The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T631)
is user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 7FFFE and 7FFFF are not used
as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.
Truth Table IV —
Address BUSY Arbitration
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A18 is a NC for IDT70T631. Address comparison will be for A0 - A17.
5. CEX = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2.
3. CE0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Inputs Outputs
Function
CE
L(5)
CE
R(5)
A
0L
-A
18L(4)
A
0R
-A
18R
BUSY
L(1)
BUSY
R(1)
X X NO MATCH H H Normal
HX MATCH H H Normal
XH MATCH H H Normal
LL MATCH (2) (2) Write Inhibit
(3)
5670 tbl 18
Functions D
0
- D
17
Left D
0
- D
17
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
5670 tbl 19
21
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70T633/1 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18
CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and
SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-
chip power down circuitry that permits the respective port to go into standby
mode when not selected.
Systems which can best use the IDT70T633/1 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the hardware
semaphores of the IDT70T633/1, which provide a lockout mechanism
without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T633/1 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70T633/1 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T633/1 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration on a master is based on the chip enable and
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70T633/1 Dual-Port RAMs.
5670 drw 20
MASTER
Dual Port RAM
BUSYR
CE
0
MASTER
Dual Port RAM
BUSYR
SLAVE
Dual Port RAM
BUSYR
SLAVE
Dual Port RAM
BUSYR
CE
1
CE
1
CE
0
A
19
BUSYLBUSYL
BUSYLBUSYL
.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
22
verifies its success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side processor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70T633/1 in a
separate memory space from the Dual-Port RAM array. This address
space is accessed by placing a low input on the SEM pin (which acts as
a chip select for the semaphore flags) and using the other control pins
(Address, CE0, CE1, R/W and LB/UB) as they would be used in accessing
a standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE
signals need to be active. (Please refer to Truth Table II). Furthermore,
the read value is latched into one side’s output register when that side's
semaphore select (SEM, BEn) and output enable (OE) signals go active.
This serves to disallow the semaphore from changing state in the middle
of a read cycle due to a write cycle from the other side.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the opposite side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
If the opposite side semaphore request latch has been written to
zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first request latch. The
opposite side flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
Figure 4. IDT70T633/1 Semaphore Logic
D
5670 drw 21
0DQ
WRITE
D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ
23
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
I
ZZ
I
DD
5670drw22
,
ZZ
t
ZZPD
CE
0
DATA
VALIDAD
DR
ESS
t
ZZR
NonewreadsorwritesallowedNorm
alO
peration
Norm
alOperationSleepM
odeNoreadsorw
ritesallowed
VALIDDATA
AD
DRESS
t
ZZS
t
ZZPU
Timing Waveform of Sleep Mode(1,2)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
24
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
5. JTAG cannot be tested in sleep mode.
JTAG Timing Specifications
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
5670 drw 23
x
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T633/1
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
3
(1)
ns
t
JF
JTAG Clock Fall Time
____
3
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
JTAG Data Output
____
25 ns
t
JDC
JTAG Data Output Hold 0
____
ns
t
JS
JTAG Setup 15
____
ns
t
JH
JTAG Hold 15
____
ns
5670 tbl 20
Sleep Mode
The IDT70T633/1 is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will have the lowest possible power
consumption. The sleep mode timing diagram demonstrates the modes of
operation: Normal Operation, No Read/Write Allowed and Sleep Mode.
For a period of time prior to sleep mode and after recovering from sleep
mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
During sleep mode the RAM automatically deselects itself and discon-
nects its internal buffer. All outputs will remain in high-Z state while in sleep
mode. All inputs are allowed to toggle, but the RAM will not be selected and
will not perform any reads or writes.
25
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field Value Description
Revision Number (31:28) 0x0 Reserved for version number
IDT Device ID (27:12) 0x33B
(1)
Defines IDT part number 70T633
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register
5670 tbl 21
System Interface Parameters
Instruction Code Description
EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.
IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
RESERVED All other codes Several combinations are reserved. Do not use codes other than those
identified above.
5670 tbl 23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
Scan Register Sizes
Register Name Bit Size
Instruction (IR) 4
Bypass (BYR) 1
Identific atio n (IDR) 32
Boundary Scan (BSR) Note (3)
5670 tbl 22
NOTE:
1. Device ID for IDT70T631 is 0x33C.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
26
Ordering Information
NOTES:
1. Green parts available. For specific speeds and packages contact your local sales office.
27
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History:
04/25/03: Initial Datasheet
10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table
Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table
Page 9,11,15, Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only
17&25
Page 10 Added Capacitance Derating Drawing
Page 11,15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables
Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table
Page 12 Added tLZOB to the Waveform of Read Cycles Drawing
Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing
Page 1& 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information
Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms
10/20/03: Page 15 Corrected tARF to 1.5V/ns Min.
04/21/04: Removed Preliminary status from entire datasheet
01/05/06: Page 1 Added green availability to features
Page 27 Added green indicator to ordering information
07/25/08: Page 9 Corrected a typo in the DC Chars table
01/19/09: Page 27 Removed "IDT" from orderable part number
04/20/10: Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01
10/15/11: Page 2,13 Corrected 70T651/9 to 70T633/1
Page 26 Updated ordering information to include tube or tray and tape & reel.
6/18/12 Page 1,2,8,10, Removed 8ns from datasheet to match pricebook.
16,18,26
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
