Datasheet
17/18
BD1Hx500 Series
TSZ02201-0G3G0BD00070-1-2
© 2015 ROHM Co., Ltd. All rights reserved. 2015.04.15 Rev.002
www.rohm.com
TSZ22111・15・001
Operational Notes
1) Absolute Maximum Ratings
Operating the IC over the absolute maximum ratings may damage the IC. In addition, it is impossible to predict all
destructive situations such as short-circuit modes or open circuit modes. Therefore, it is important to consider circuit
protection measures, like adding a fuse, in case the IC is expected to be operated in a special mode exceeding the
absolute maximum ratings.
2) Reverse connection of power supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
3) Power supply line
Design the PCB layout pattern to provide low impedance ground and supply lines. Separate the ground and supply
lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting
the analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of
temperature and aging on the capacitance value when using electrolytic capacitors.
4) GND voltage
The voltage of the ground pin must be the lowest voltage of all pins of the IC at all operating conditions. Ensure that no
pins are at a voltage below the ground pin at any time, even during transient condition.
5) Thermal consideration
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions.
6) Short between pins and mounting errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
7) TSD (Thermal Shut Down)
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn off the IC when the internal
temperature of the IC reaches a 175°C (with 25°C hysteresis). It is not designed to protect the IC from damage or
guarantee its operation. Do not continue to operate the IC after this function is activated. Do not use the IC in
conditions where this function will always be activated.
8) Overcurrent protection circuit (OCP)
The IC incorporates an over-current protection circuit that operates in accordance with the rated output capacity. This
circuit protects the IC from damage when the load becomes shorted. It is also designed to limit the output current
(without latching) in the event of more than 1.45A (Typ) current flow, such as from a large capacitor or other component
connected to the output pin. This protection circuit is effective in preventing damage to the IC in cases of sudden and
unexpected current surges. The IC should not be used in applications where the over current protection circuit will be
activated continuously.
ST (8 PIN) will be set to ‘L (abnormal condition)’ if the current limit state continues to 20μs(Typ). Then, ST (8 PIN) will
be set to ‘H (normal condition)’ if the current limit release until 1.1ms(Typ).
If current limit state continues, generation of heat, degradation, etc. of the IC can be considered. When the state of
overcurrent still flows, compensate by setting the IC in standby mode applications using ST (8 PIN).
9) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
10) Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
11) FIN (HTSOP-J8,HSON 8)
Since it has connected with sub of IC, please connect the heat dissipation metal to external GND potential.
Status of this document
The Japanese version of this document is the formal datasheet. A customer may use this translation version only as
reference to help understand the formal version. If there are any differences, the formal version takes precedence.