Vishay Dale Electronics, Inc. Information Display Products OLED Product Data Sheet OLED SPECIFICATION Model No: OLED-128Y064C-LPP3N00000 SPECIFICATION Module # : Ver: C OLED-128Y064C-LPP3N00000 Global SAP # : O128Y064CLPP3N0000 APPROVED BY: ( FOR CUSTOMER USE ONLY ) PCB VERSION: SALES BY ISSUED DATE: APPROVED BY CHECKED BY DATA: PREPARED BY MODLE NO RECORDS OF REVISION VERSION DATE DOC. FIRST ISSUE REVISED SUMMARY PAGE NO. 0 A B 2011.10.26 2012.01.17 2012.02.20 14 14 C 2012.05.04 14 First issue Add Power Consumption Add Optics Characteristics Add Brightness 1. Module Classification Information OLED -128 1 Y 064 2 3 C L P P 3 N 00000 4 5 6 7 8 9 10 1 BrandVishay Intertechnology, Inc. 2 Horizontal Format: 3 Display TypeNCharacter Type, HGraphic Type ,YTAB Type 4 Vertical Format: 5 Serials code: 6 7 Emitting Color Polarizer 128 columns 64 lines C AAmber RRED BBlue CFull color GGreen WWhite YYellow Green LYellow PWith Polarizer; N: Without Polarizer 8 Display Mode PPassive Matrix ; A: Action Matrix 9 Driver Voltage 3: 3.0 V; 5: 5.0V 10 Touch Panel 11 Serial No. NWithout touch panel; T: With touch panel 00000: Sales code 11 2. General Description Item Dimension Unit 128 x 64 Dots 89.7 x 47.2 x 3.4 (mm) mm Active Area 61.41 x 30.69 (mm) mm Pixel Pitch 0.48 x 0.48 (mm) mm Pixel Size 0.45 x 0.45 (mm) mm 20.5 g Number of Characters Module dimension Weight Display Mode Passive Matrix Display Color Monochrome (Yellow) Drive Duty 1/64 Duty 3. Absolute Maximum Ratings Parameter Symbol Min Max Unit Supply Voltage for Logic VDD -0.3 3.5 V 1,2 Supply Voltage for Display VCC 8 16 V 1,2 Operating Temperature TOP -40 80 C -- TSTG -40 80 C -- Storage Temperature Notes Note 1: All the above voltages are on the basis of "VSS = 0V". Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. "Optics & Electrical Characteristics". If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. 4. Block Diagram 4.1.POWER ON/OFF SEQUENCE &APPLICATION CIRCUIT 3.1.1 POWER ON/OFF SEQUENCE Power ON sequence 1. Power ON VDD ,VDDIO 2. After VDD ,VDDIO become stable , set RES# pin LOW (logic low) for at least 3us(t1) and then HIGH (logic high). 3. After set RES# pin LOW (logic low),wait for at least 3us(t2). Then Power ON Vcc. (1) 4. After Vcc. become stable , send command AFh for display ON. DEG/COM will be ON after 100ms(tAF). ON VDD,VDDIO ON Vcc RES# Send AFh command for display ON VDD,VDDIO GND t1 RES# GND t2 Vcc GND tAF ON SEG/COM OFF Power OFF sequence 1. Send command AEh for display OFF. 2. Power OFF Vcc.(1),(2) 3. Wait for tOFF. Power OFF VDD ,VDDIO. (where Minimum tOFF=80ms,Typical tOFF=100ms) Send command AEh for display OFF OFF VDD,VDDIO OFF Vcc Vcc GND t OFF VDD,VDDIO GND Note: (1) Since an ESD protection circuit is connected between VDD ,VDDIO and Vcc, Vcc becomes lower than VDD and VDD , VDDIO is ON and Vcc is OFF as shown in the dotted line of Vcc in above figures. (2) Vcc should be disabled when it is OFF. 4.2 APPLICATION CIRCUIT U1_a 1 VCC 4 VCC 2 VDD CGOMH D6 3 IREF D5 19 VDD D4 D3 D2 17 BS2 D1 BS1 D0 18 4.7uf C1_a 0.1uf C3_a 4.7uf C2_a D7 D7 5 6 7 8 9 10 11 D6 D5 D4 D3 D2 D1 D0 1M R1_a 20 12 NC E/RD# E/RD# 13 WR# WR# 14 VSS 22 D/C# D/C# 21 15 VSS RES# VSS CS# RES# 16 CS# 4.3 INTERFACE 4.3.1 FUNCTION BLOCK DIAGRAM COG VCC VDD VGOMH IREF E/RD# R/W# D/C# RES# CS# BS1,BS2 D0~D7 VSS 128 columns 12864 X 64 SSD1305 64 rows 4.4 PANEL LAYOUT DIAGRAM C62~C0 S0~S127 C1~C63 SEG&COM Layout Dot Matrixes 4.5 GRAPHIC DISPLAY DATA RAM ADDRESS MAP The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132x64=8448bits COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 0x3Fh 0x3Eh 0x3Dh 0x3Ch 0x3Bh 0x3Ah 0x39h 0x38h 0x37h 0x36h 0x35h 0x34h 0x33h 0x32h 0x31h 0x30h 0x2Fh 0x2Eh 0x2Dh 0x2Ch 0x2Bh 0x2Ah 0x29h 0x28h 0x00h 0x01h 0x02h 0x03h 0x04h 0x05h 0x06h 0x07h 0x08h 0x09h 0x0Ah 0x0Bh 0x0Ch 0x0Dh 0x0Eh 0x0Fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 0x0Fh 0x0Eh 0x0Dh 0x0Ch 0x0Bh 0x0Ah 0x09h 0x08h 0x07h 0x06h 0x05h 0x04h 0x03h 0x02h 0x01h 0x00h 0x30h 0x31h 0x32h 0x33h 0x34h 0x35h 0x36h 0x37h 0x38h 0x39h 0x3Ah 0x3Bh 0x3Ch 0x3Dh 0x3Eh 0x3Fh PAGE 0 PAGE 1 PAGE 2 PAGE 6 PAGE 7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 0x00h 0x83h SEG0 0x01h 0x82h SEG0 0x02h 0x81h SEG0 0x03h 0x80h SEG0 0x7Ch 0x07h SEG0 0x7Dh 0x06h SEG0 0x7Eh 0x05h SEG0 0x7Fh 0x04h SEG0 0x80h 0x03h SEG0 0x81h 0x02h SEG0 0x82h 0x01h SEG0 0x83h 0x00h SEG0 For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. 4.795 5.795 3.400 2.0MAX View Direction Active Area Area Active 128*64 PixelsPixels 128*64 1 NC VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E/RD R/W D/C RES CS FR BS2 BS1 VDDIO VDD VCIR BGGND VBREF NC FB VDDB GDR VSS NC ICSSD1305T7 Double Tape Tesa 4972 22*6*0.05mm 14.50 61.30 69.85 2O.0 22 ?7 .0 Single Tape Teraoka 631S 27*8*0.085mm 36.500 1 31 14.8 0O.5 2.0 .2 ?3 Seal.white 2.0 2.190 82.700 0 O.2 73.00 0 O.2 63.41(VA) 61.41(AA) 30.69(AA) 40.200 0O.2 41.86 0O.2 39.86 32.69(VA) 3.190 5. Contour Drawing 28.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VCC VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 E/RD# R/W# D/C# RES# CS# BS2 BS1 VDD NC VSS VSS P0.5*21=10.5 11.5 0 O.2 2-? 1 .0 Scale 1:2 11.50 0.48 CONTCT SIZE 22 1 0.03 0.5 5.0 0O.5 W=0.3 0.48 0.03 Detail DOTS Scale 1:10 0.3 0 O.05 The non-specified tolerance of dimension is 0.3mm. 6. Interface Pin Function No. 1 Symbol VCC 2 VCOMH 3 IREF 4~11 12 13 D7~D0 E/RD# R/W# 14 D/C# 15 RES# 16 CS# 17 BS2 18 BS1 19 20 21 22 VDD NC VSS VSS Function Power supply for analog circuit. Com Voltage Output. A capacitor should be connected between this pin and VSS. Reference current input pin. A resistor should be connected between this pin and VSS. Data bus. Data read operation is initiated when it's pull low. Data write operation is initiated when it's pull low. Data/ Command control. Pull high for write/read display data. Pull low for write command or read status. Reset signal input. When it's low, initialization of SSD1305 is executed. Chip select input. Communicating Protocol Select These pins are MCU interface selection input. See the following table: 68XX-paralle 80XX-paralle Serial l l BS1 0 1 0 BS2 1 1 0 Power supply for logic circuit. No connection. Ground. Ground. 7. Optics & Electrical Characteristics 7.1INTERFACE TIMING CHART 8080-Series MCU Parallel Interface Timing Characteristics (VDD-VSS=2.4V to 3.5V, VDDIO=VDD,TA=25) Symbol Parameter Min Typ Max tcycle Clock Cycle Time 300 tAS Address Setup Time 10 tAH Address Hold Time 0 tDSW Write Data Setup Time 40 tDHW Write Data Hold Time 7 tDHR Read Data Hold Time 20 tOH Output Disable Time 70 tACC Access Time 140 tPWLR Read Low Time 120 tPWLW Write Low Time 60 tPWHR Read High Time 60 tPWHW Write High Time 60 tR Rise Time 15 tF Fall Time 15 tCS Chip select setup time 0 tCSH Chip select setup hold time to read 0 signal tCSF Chip select setup hold time 20 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8080-seriesparallel interface characteristics (Form 1) Write cycle(Form 1) Write cycle(Form 1) CS# CS# t tcs D/C# D/C# tAS tAH tR tF WR# tAH tAS t tPWLW tDSW D(7:0) tCSH tCSF cs tF CYCLE tPWHW RD# tDHW tR tCYCLE tPWLR tACC tPWHR tDHR D(7:0) tOH Write cycle(Form 2) Write cycle(Form 2) tCYCLE tCYCLE tR CS# tPWLW tP tR CS# tPWHW tCS tPWLR tF tPWHR tCS D/C# D/C# tAS tAH tAH tAS tCSF WR# RD# tDSW tDHW tCSH tACC tDHR D(7:0) D(7:0) tOH 7.2 DC Characteristics Characteristics Supply Voltage for Logic Symbol VDD Condition Min 2.4 Typ 2.7 Max 3.5 Unit V Supply Voltage for Display VCC 14.5 15 15.5 V High Level Input VIH Iout = 100A,3.3MHz 0.8xVDD VDD V Low Level Input VIL Iout = 100A,3.3MHz 0 0.2xVDD V 0.9xVDD VDD V 0 V 90 101 15 17 0.1xVDD mA mA mA mA 10 A 10 A High Level Output VOH Iout =100A,3.3MHZ Low Level Input VOL Iout =100A,3.3MHZ Operating Current for VDD (Panel attached) IDD Note 4 Note 5 Operating Current for VCC (Panel attached) ICC Note 4 Note 5 Sleep Mode Current for VDD Sleep Mode Current for VCC IDD, SLEEP ICC, SLEEP 50% Display Area 297 mW Turn on 100% Display Area Power Consumption 333 mW Turn on Note 3: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer's request. Note 4: VDD = 3.3V, VCC = 13.7V, 50% Display Area Turn on. ( Contrast value =0x80 ) Note 5: VDD = 3.3V, VCC = 13.2V, 100% Display Area Turn on.( Contrast value = 0x80) (Base on 80 nits on 50% checkboard and include DC to DC circuit.) * Software configuration follows Section 4.4 Initialization. Power Consumption 7.3 Optics Characteristics Characteristics Symbol (x) C.I.E. (Yellow) (y) Dark Room Contrast CR Condition Without Polarizer View Angle Brightness Yellow With Polarizer Min 0.44 0.46 Typ Max 0.48 0.52 0.50 0.54 >2000:1 >160 60 80 Unit cd/m2 8. Reliability 8.1 Contents of Reliability Tests Item Conditions Criteria High Temperature Operation 80 ,240hrs Low Temperature Operation -40 ,240hrs The operational High Temperature Storage 80 ,240hrs Low Temperature Storage -40 ,240hrs functions work. 60 ,90% -40 8RH,120 0 High Temperature/Humidity Operation/ Thermal Shock 24cycles 1 hr dwell * The samples used for the above tests do not include polarizer. * No moisture condensation is observed during tests. 8.2 Lifetime Parameter Min Typ Max Unit Condition Notes Operating Life 100,000 Hrs 80 cd/m2, 50% Checkerboard 6 Time Note 6: The average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions. 8.3 Failure Check Standard After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 235C; 5515% RH. 9. Inspection specification NO Item Criterion AQL 01 Electrical Testing 1.1 Missing vertical, horizontal segment, segment contrast defect. 1.2 Missing character , dot or icon. 1.3 Display malfunction. 1.4 No function or no display. 1.5 Current consumption exceeds product specifications. 1.6 Viewing angle defect. 1.7 Mixed product types. 1.8 Contrast defect. 0.65 02 2.1 White and black spots on display 0.25mm, no more Black or than three white or black spots present. white spots (display only) 2.2 Densely spaced: No more than two spots or lines within 3mm 3.1 Round type : As following drawing =( x + y ) / 2 03 04 Black spots, white spots, contaminatio n (non-display) Polarizer bubbles SIZE 0.10 0.10 0.20 0.20 0.25 0.25 3.2 Line type : (As following drawing) Length Width Acceptable Q TY Accept no dense 2 0 Acceptable Q TY Accept no dense W0.02 L3.0 L2.5 --- 0.02W0.03 2 0.03W0.05 0.05W As round type Size 0.20 0.200.50 0.501.00 1.00 Total Q TY 2.5 1 --- If bubbles are visible, judge using black spot specifications, not easy to find, must check in specify direction. 2.5 Acceptable Q TY Accept no dense 3 2 0 3 2.5 2.5 NO 05 Item Scratches Criterion Follow NO.3 Black spots, white spots, contamination Symbols Define: x: Chip length y: Chip width z: Chip thickness k: Seal width t: Glass thickness a: Side length L: Electrode pad length: AQL 6.1 General glass chip : 6.1.1 Chip on panel surface and crack between panels: 06 Chipped glass z: Chip thickness Z1/2t y: Chip width x: Chip length Not over viewing x1/8a area Not exceed 1/3k 1/2tz2t x1/8a If there are 2 or more chips, x is total length of each chip. 6.1.2 Corner crack: z: Chip thickness Z1/2t y: Chip width x: Chip length Not over viewing x1/8a area Not exceed 1/3k 1/2tz2t x1/8a If there are 2 or more chips, x is the total length of each chip. 2.5 NO Item Criterion Symbols : x: Chip length y: Chip width z: Chip thickness k: Seal width t: Glass thickness a: Side length L: Electrode pad length 6.2 Protrusion over terminal : 6.2.1 Chip on electrode pad : y: Chip width x: Chip length y0.5mm x1/8a 6.2.2 Non-conductive portion: 06 AQL z: Chip thickness 0 zt Glass crack 2.5 y: Chip width x: Chip length z: Chip thickness y L x1/8a 0 zt If the chipped area touches the ITO terminal, over 2/3 of the ITO must remain and be inspected according to electrode terminal specifications. If the product will be heat sealed by the customer, the alignment mark not be damaged. 6.2.3 Substrate protuberance and internal crack. y: width y1/3L x: length xa NO 07 08 09 10 11 Item Cracked glass Backlight elements Bezel PCBCOB Soldering Criterion AQL With extensive crack is not acceptable. 2.5 8.1 Illumination source flickers when lit. 8.2 Spots or scratched that appear when lit must be judged. Using Spot, lines and contamination standards. 8.3 Backlight doesn't light or color wrong. 0.65 2.5 9.1 Bezel may not have rust, be deformed or have fingerprints, stains or other contamination. 9.2 Bezel must comply with job specifications. 0.65 2.5 0.65 10.1 COB seal may not have pinholes larger than 0.2mm or contamination. 10.2 COB seal surface may not have pinholes through to the IC. 10.3 The height of the COB should not exceed the height indicated in the assembly diagram. 10.4 There may not be more than 2mm of sealant outside the seal area on the PCB. And there should be no more than three places. 10.5 No oxidation or contamination PCB terminals. 10.6 Parts on PCB must be the same as on the production characteristic chart. There should be no wrong parts, missing parts or excess parts. 10.7 The jumper on the PCB should conform to the product characteristic chart. 10.8 If solder gets on bezel tab pads, LED pad, zebra pad or screw hold pad, make sure it is smoothed down. 2.5 11.1 No un-melted solder paste may be present on the PCB. 11.2 No cold solder joints, missing solder connections, oxidation or icicle. 11.3 No residue or solder balls on PCB. 11.4 No short circuits in components on PCB. 2.5 2.5 2.5 0.65 2.5 2.5 0.65 0.65 2.5 2.5 0.65 NO 12 Item Criterion General appearance 12.1 No oxidation, contamination, curves or, bends on interface Pin (OLB) of TCP. 12.2 No cracks on interface pin (OLB) of TCP. 12.3 No contamination, solder residue or solder balls on product. 12.4 The IC on the TCP may not be damaged, circuits. 12.5 The uppermost edge of the protective strip on the interface pin must be present or look as if it cause the interface pin to sever. 12.6 The residual rosin or tin oil of soldering (component or chip component) is not burned into brown or black color. 12.7 Sealant on top of the ITO circuit has not hardened. 12.8 Pin type must match type in specification sheet. 12.9 Pin loose or missing pins. 12.10 Product packaging must the same as specified on packaging specification sheet. 12.11 Product dimension and structure must conform to product specification sheet. AQL 2.5 0.65 2.5 2.5 2.5 2.5 2.5 0.65 0.65 0.65 0.65 Pattern Check (Display On) in Active Area Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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