High Fidelity, Low Power,
Integrated Stereo Audio Amplifier
Data Sheet SSM6322
Rev. 0 Document Feedback
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FEATURES
Flexible architecture to interface with all digital-to-analog
converters (DACs)
Accepts differential current or voltage input (provides
single-ended voltage output)
High output current drive capability
Greater than 100 mA rms output current
Accurately reproduces large music transients into heavy
loads (16 Ω to 32 Ω)
Excellent audio fidelity
−121 dB total harmonic distortion plus noise (THD + N) at
1 kHz, 2 V rms output with ±5 V supply and 32 Ω load
Low output integrated noise (10 Hz to 22 kHz) of
1.8 μV rms with A-weighted filter
Supply range: ±3.3 V to ±6 V (typical)
Low power operation
Enabled: 60 mW, VCC = +5 V, VEE = −5 V
Disabled/voice select: <30 μA
Low power disable mode with high output impedance
High-Z in power-down mode eliminating voice mode
switch from the high fidelity path
Greater than 87 dB power supply rejection ratio (PSRR) at
20 kHz
Adjustable input common-mode voltage with resistor
programmable reference voltage
1.45 V (typical) with no external components
Capable of two single-pole, low-pass filters in series
2.2 nF maximum input capacitor
Second filter between the GAINx and FILTx pins
Pop and click noise suppression
Signal chain integration supports small printed circuit board
(PCB) area
Compact 4 mm × 4 mm LFCSP package
APPLICATIONS
High fidelity headphone drivers
Mobile phones
Bluetooth speakers and headphones
Gaming notebooks and tablets
A/V receivers
Professional audio equipment
Audio test equipment
Automobile infotainment systems
FUNCTIONAL BLOCK DIAGRAM
SSM6322
GAIN1
VNFB1
REF1
GND1
VEE2
2
VP1
VN1 INPUT VOUT1
OUTPUT
GAIN2
FILT1
FILT2
VP2
VN2
5
6
INPUT VOUT2
VNFB2
OUTPUT
1
22
24 23
18
17
9
REF2
78
13
14
16
SD
SD2
3
4
10
21
GND2
GND3
GND4
11 12
VCC2
VEE1 VCC1
20 19
15
15260-001
Figure 1.
GENERAL DESCRIPTION
The SSM6322 is an integrated, dual-channel audio amplifier
solution that interfaces directly with audio DAC/CODEC,
maximizing the fidelity of high fidelity audio signal chains. The
highly efficient design of the SSM6322 delivers outstanding
audio performance while minimizing power dissipation for
maximum battery life in portable applications.
The SSM6322 features −121 dB THD + N at 1 kHz, along
with very low output noise from 20 Hz to 20 kHz. The low power
operation, high peak output current, and high PSRR make the
SSM6322 an ideal candidate for applications that require high
fidelity audio, high dynamic range, precision, and low power. This
highly integrated drive solution also reduces development time
while reducing board space and minimizing external components.
The SSM6322 is available in a 24-lead LFCSP package. The
SSM6322 operates over the industrial temperature of −40°C to
+85°C.
SSM6322 Data Sheet
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Supply ................................................................................... 3
±3.3 V Supply ................................................................................ 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................8
Test Circuit ...................................................................................... 14
Theory of Operation ...................................................................... 15
Applications Information .............................................................. 16
Headphone Drivers in Mobile Phones .................................... 16
Common-Mode Control Circuit .............................................. 16
Capacitive Load Drive ............................................................... 17
SSM6322 in a Headphone Driver Application ....................... 18
Design Guidelines ...................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/2017—Revision 0: Initial Version
Data Sheet SSM6322
Rev. 0 | Page 3 of 20
SPECIFICATIONS
±5 V SUPPLY
TA = 25°C, reference voltage (VREF) = 0 V, feedback resistor (RF) = gain resistor (RG) = 1 kΩ (see Figure 38), unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Gain Bandwidth RIN1 = 1 kΩ, RIN2 = 1 kΩ (see Figure 38),
output voltage (VOUT) = 0.2 V p-p
25 MHz
Slew Rate Gain = 1, VOUT = 2 V step 18 V/μs
Channel Separation 1 kHz to 10 kHz, input voltage (VIN) = 5 V p-p,
RL = 600 Ω, 32 Ω, 16 Ω
−140 dB
DISTORTION PERFORMANCE
THD + N 1 kHz, VOUT = 2 V rms, low-pass filter = 80 kHz,
RL = 600 Ω
−122 dB
1 kHz, VOUT =2 V rms, low-pass filter = 80 kHz,
RL = 32 Ω
−121 dB
1 kHz, VOUT = 1.6 V rms, low-pass filter =
80 kHz, RL = 16 Ω
−118 dB
Intermodulation Distortion (IMD) SMPTE two-tone, 4:1 (60 Hz and 7 kHz),
gain = 1, VOUT = 2 V rms, RL = 600 Ω, 90 kHz
measurement bandwidth
−125 dB
CCIF two-tone (19 kHz and 20 kHz), gain = 1,
VOUT = 2 V rms, RL = 600 Ω, 90 kHz
measurement bandwidth
−131 dB
NOISE PERFORMANCE
A-Weight Output Noise f = 10 Hz to 22 kHz 1.8 μV rms
Input Voltage Noise f = 10 Hz 5.2 nV/√Hz
f = 100 kHz 3.6 nV/√Hz
Input Current Noise f = 10 Hz 10 pA/√Hz
f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Output Offset Voltage 90 250 μV
Output Offset Voltage Drift 1.5 7.5 μV/°C
Input Bias Current −2.4 −1.8 −1 μA
Input Offset Current 60 320 nA
Open-Loop Gain VOUT = ±2.3 V, RL = 600 Ω 107 120 dB
INPUT CHARACTERISTICS
Input Capacitance 2 pF
Input Common-Mode Voltage Range IDIFF = 3 mA ±1.5 V
Common-Mode Rejection VCM = ±1 V 113 140 dB
VREF1/VREF2
Open Circuit Voltage Referenced to ground 1.45 V
Output Current 15 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each Output RL = 600 Ω ±3.3 ±3.4 V
R
L = 32 Ω ±2.8 ±2.9 V
R
L = 16 Ω ±2.0 ±2.6 V
Output Current RL = 16 Ω, rms voltage (VRMS) = 1.6 V,
THD + N= −118 dB
100 mA rms
Short-Circuit Current RL = 10 Ω; source/sink +240/−190 mA
Closed-Loop Output Impedance 10 Hz to 20 kHz 0.04 Ω
SSM6322 Data Sheet
Rev. 0 | Page 4 of 20
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range ±3.3 to ±6 V
Quiescent Current VSD = VSD2 = VCCx, VREF = 0 V, per channel 3 3.35 mA
−40°C ≤ TA ≤ +85°C 3.1 mA
Quiescent Current Power-Down Mode VSD = 0 V, VSD2 = VCCx, per channel 1.4 mA
V
SD = VSD2 = 0 V, per channel 15 μA
DC Power Supply Rejection Ratio Supply voltage (VSY) = 3.3 V to 5.5 V 115 140 dB
AC Power Supply Rejection Ratio 20 kHz 87 dB
POWER-DOWN INPUTS
Logic High Chip on, referenced to ground >1.5 V
Logic Low Chip off, referenced to ground <0.75 V
±3.3 V SUPPLY
TA = 25°C, VREF = 0 V, RF = RG = 1 kΩ (see Figure 38), unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Gain Bandwidth RIN1 = 1 kΩ, RIN2 = 1 kΩ (see Figure 38), VOUT = 0.2 V p-p 25 MHz
Slew Rate Gain = 1, VOUT = 2 V step 14 V/μs
Channel Separation 1 kHz to 10 kHz, VIN = 1 V p-p, RL = 600 Ω, 32 Ω, and 16 Ω −140 dB
DISTORTION PERFORMANCE
THD + N 1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 600 Ω −116 dB
1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 32 Ω −116 dB
1 kHz, VOUT = 0.9 V rms, low-pass filter = 80 kHz, RL = 16 Ω −111 dB
NOISE PERFORMANCE
A-Weight Output Noise f = 10 Hz to 22 kHz 1.8 μV rms
Input Voltage Noise f = 10 Hz 5.2 nV/√Hz
f = 100 kHz 3.6 nV/√Hz
Input Current Noise f = 10 Hz 10 pA/√Hz
f = 100 kHz 1.2 pA/√Hz
DC PERFORMANCE
Output Offset Voltage 90 250 μV
Output Offset Voltage Drift 1.5 7.5 μV/°C
Input Bias Current −2.4 −1.8 −1 μA
Input Offset Current 60 300 nA
Open-Loop Gain VOUT = ±2.3 V, RL = 600 Ω 106 120 dB
INPUT CHARACTERISTICS
Input Capacitance 2 pF
Input Common-Mode Voltage
Range
Differential current (IDIFF) = 3 mA ±0.3 V
Common-Mode Rejection Common-mode voltage (VCM) = ±0.3 V 109 135 dB
VREF1/VREF2 V
Open Circuit Voltage Referenced to ground 1.45 V
Output Current 15 μA
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each Output RL = 600 Ω ±1.6 ±1.7 V
R
L = 32 Ω ±1.4 ±1.45 V
R
L = 16 Ω ±1.2 ±1.4 V
Output Current RL = 16 Ω, VRMS = 0.9 V, THD + N = −111 dB 56 mA rms
Short-Circuit Current RL = 10 Ω +115/−120 mA
Closed-Loop Output Impedance 10 Hz to 20 kHz 0.04 Ω
Data Sheet SSM6322
Rev. 0 | Page 5 of 20
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range ±3.3 to ±6 V
Quiescent Current VSD = VSD2 = VCCx, VREF = 0 V, per channel 2.9 3.35 mA
−40°C ≤ TA ≤ +85°C 3.0 mA
Quiescent Current Power-Down
Mode
VSD = 0 V, VSD2 = VCCx 1.3 mA
V
SD = VSD2 = 0 V 10 μA
DC Power Supply Rejection Ratio VSY = 3.3 V to 5.5 V 115 140 dB
AC Power Supply Rejection Ratio 20 kHz 85 dB
POWER-DOWN INPUTS
Logic High Chip on, referenced to ground >1.5 V
Logic Low Chip off, referenced to ground <0.75 V
SSM6322 Data Sheet
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage
Single Supply 12.6 V
Dual Supply ±6.3 V
Exposed Pad Voltage −VSY or ground
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to + 85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required. The values in Table 4 were obtained per
JEDEC standard JESD51-12.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
CP-24-15 47 3.3 °C/W
Board layout impacts thermal characteristics, such as θJA. When
proper thermal management techniques are used, a better θJA
value can be achieved.
Although the exposed pad can be left floating, it must be connected
to an external V− plane or ground plane for proper thermal
management.
Maximum Power Dissipation
The maximum safe power dissipation for the SSM6322 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the SSM6322. Exceeding a junction temperature of 175C
for an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality. The power
dissipated in the package (PD) is the sum of the quiescent power
dissipation and the power dissipated in the die due to the
SSM6322 drive at the output.
The quiescent power is the voltage between the supply pins (VS)
times the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power − Load Power)
L
2
OUT
L
OUTS
SS
DR
V
–
R
V
2
V
IVP
Consider the rms output voltages. If RL is referenced to −VSY, as
in single-supply operation, the total drive power is VSY × IOUT. If
the rms signal levels are indeterminate, consider the worst case,
when VOUT = VSY/4 for RL to midsupply.
L
S
SS
DR
/V
IVP
2
4
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
package on a JEDEC standard 4-layer board.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –25 –10 5 20 35 50 65 80
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
15260-002
Figure 2. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION
Data Sheet SSM6322
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
VN2
VP2
GND2
GND1
VP1
VN1
PIN 1
IDENTIFIER
VOUT2
VNFB2
SD2
SD
VNFB1
VOUT1
8
9
10
11
7
FILT2
REF2
GND3
VEE2
12
VCC2
GAIN2
20
19
21
VEE1
VCC1
GND4
22 REF1
23 FILT1
24 GAIN1
SSM6322
TOP VIEW
(Not to Scale)
15260-003
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO A NEGATIVE POWER PLANE (V−)
OR GROUND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VN1 Negative Input of Channel 1 Input Stage.
2 VP1 Positive Input of Channel 1 Input Stage.
3 GND1 Ground 1.
4 GND2 Ground 2.
5 VP2 Positive Input of Channel 2 Input Stage.
6 VN2 Negative Input of Channel 2 Input Stage.
7 GAIN2 Output of Channel 2 Input Stage.
9 FILT2 Positive Input of Channel 2 Output Stage.
9 REF2 Input Common-Mode Voltage of Channel 2 Input Stage.
10 GND3 Ground 3.
11 VEE2 Negative Supply 2. This pin is internally shorted to Pin 20.
12 VCC2 Positive Supply 2. This pin is internally shorted to Pin 19.
13 VOUT2 Output of Channel 2 Output Stage.
14 VNFB2 Negative Feedback of Channel 2 Output Stage.
15 SD2 Shuts Down Power for the Entire Device. This pin is referenced to ground.
16 SD Shuts Down Power for the Output Stage. This pin is referenced to ground.
17 VNFB1 Negative Feedback of Channel 1 Output Stage.
18 VOUT1 Output of Channel 1 Output Stage.
19 VCC1 Positive Supply 1. This pin is internally shorted to Pin 12.
20 VEE1 Negative Supply 1. This pin is internally shorted to Pin 11.
21 GND4 Ground 4.
22 REF1 Input Common-Mode Voltage of Channel 1 Input Stage.
23 FILT1 Positive Input of Channel 1 Output Stage.
24 GAIN1 Output of Channel 1 Input Stage.
EPAD Exposed Pad. Connect the exposed pad to a negative power plane (V−) or ground.
SSM6322 Data Sheet
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
20
10
0
–10
–20
–30
–40
–50
1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
VSY = ±5V
VSD = 5V
AV = 1
RL = 600Ω
CL1 = OPEN
CL1 = 10pF
CL1 = 25pF
CL1 = 150pF
CL1 = 100pF
CL1 = 200pF
15260-004
Figure 4. Frequency Response for Various Capacitive Loads, VSY = ±5 V
20
10
0
–10
–20
–30
–40
–50
1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
SY
= ±3.3V
V
SD
= 3.3V
A
V
= 1
R
L
= 600Ω
CL1 = OPEN
CL1 = 10pF
CL1 = 25pF
CL1 = 150pF
CL1 = 100pF
CL1 = 200pF
15260-005
Figure 5. Frequency Response for Various Capacitive Loads, VSY = ±3.3 V
120
100
80
60
40
20
0
1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
SY
= ±5V
V
SD
= 5V
PSRR+
PSRR–
15260-006
Figure 6. PSRR vs. Frequency, VSY = ±5 V
120
100
80
60
40
20
0
1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
SY
= ±3.3V
V
SD
= 3.3V
PSRR+
PSRR–
15260-007
Figure 7. PSRR vs. Frequency, VSY = ±3.3 V
–
80
–90
–100
–120
–140
–160
–110
–130
–150
–170
–180
20 200 2k 20k
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
V
SY
= ±5V
V
IN
= 5V p-p
80kHz LP FILTER
R
L
= OPEN
R
L
= 600Ω
R
L
= 32Ω
R
L
= 16Ω
15260-008
Figure 8. Channel Separation vs. Frequency, VSY = ±5 V
–
80
–90
–100
–120
–140
–160
–110
–130
–150
–170
–180
20 200 2k 20k
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
V
SY
= ±3.3V
V
IN
= 1V p-p
80kHz LP FILTER
R
L
= OPEN
R
L
= 600Ω
R
L
= 32Ω
R
L
= 16Ω
15260-009
Figure 9. Channel Separation vs. Frequency, VSY = ±3.3 V
Data Sheet SSM6322
Rev. 0 | Page 9 of 20
1
0.1
0.01
0.0001
0.001
0.00001
0.001 0.01 0.1 1
THD + N (%)
AMPLITUDE (V
RMS
)
V
SY
= ±5V, V
SD
= 5V
A
V
= 1
FREQUENCY = 1kHz
80kHz LP FILTER
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-010
Figure 10. THD + N vs. Amplitude, VSY = ±5 V
1
0.1
0.01
0.0001
0.001
0.00001
0.001 0.01 0.1 1
THD + N (%)
AMPLITUDE (V
RMS
)
V
SY
= ±3.3V, V
SD
= 3V
A
V
= 1
FREQUENCY = 1kHz
80kHz LP FILTER
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-011
Figure 11. THD + N vs. Amplitude, VSY = ±3.3 V
1
0.1
0.01
0.0001
0.001
0.00001
0.001 0.01 0.1 1
THD + N (%)
AMPLITUDE (V
RMS
)
V
SY
= ±6V, V
SD
= 6V
A
V
= 1
FREQUENCY = 1kHz
80kHz LP FILTER
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-012
Figure 12. THD + N vs. Amplitude, VSY = ±6 V
0.1
0.01
0.0001
0.001
0.00001
20 200 2k 20k
THD + N (%)
FREQUENCY (Hz)
V
SY
= ±5V
V
SD
= 5V
A
V
= 1
80kHz LP FILTER
R
L
= 16Ω, V
IN
= 1.6V rms
R
L
= 32Ω, V
IN
= 2V rms
R
L
= 600Ω, V
IN
= 2V rms
15260-013
Figure 13. THD + N vs. Frequency, VSY = ±5 V
0.1
0.01
0.0001
0.001
0.00001
20 200 2k 20k
THD + N (%)
FREQUENCY (Hz)
V
SY
= ±3.3V
V
SD
= 3.3V
A
V
= 1
80kHz LP FILTER
R
L
= 16Ω, V
IN
= 0.6V rms
R
L
= 32Ω, V
IN
= 1V rms
R
L
= 600Ω, V
IN
= 1V rms
15260-014
Figure 14. THD + N vs. Frequency, VSY = ±3.3 V
1
0.1
0.01
0.0001
0.001
0.00001
0.01 0.1 1
INTERMODULATION DISTORTION (dB)
V
IN
(V
RMS
)
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-015
Figure 15. SMPTE vs. Input Voltage (VIN), VSY = ±5 V
SSM6322 Data Sheet
Rev. 0 | Page 10 of 20
1
0.1
0.01
0.0001
0.001
0.00001
0.01 0.1 1
INTERMODULATION DISTORTION (dB)
V
IN
(V
RMS
)
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-016
Figure 16. CCIF vs. Input Voltage (VIN), VSY = ±5 V
100
10
1
1 10 100 1k 10k 100k
INPUT VOLTAGE NOISE (nV/
√
Hz)
FREQUENCY (Hz)
VSY = ±5V, VSD = 5V, AV = 10
CH1
CH2
15260-017
Figure 17. Input Voltage Noise vs. Frequency, VSY = ±5 V
100
10
1
1 10 100 1k 10k 100k
INPUT VOLTAGE NOISE (nV/
√
Hz)
FREQUENCY (Hz)
VSY = ±3.3V, VSD = 3.3V, AV = 10
CH1
CH2
15260-018
Figure 18. Input Voltage Noise vs. Frequency, VSY = ±3.3 V
100
10
1
1 10 100 1k 10k 100k
INPUT CURRENT NOISE (pA/
√
Hz)
FREQUENCY (Hz)
RS = 100kΩ
BUFFER AV = 1 ±5V
±3.3V
15260-019
Figure 19. Input Current Noise vs. Frequency
1k
0.01
0.1
1
10
100
0.001
10 100 1k 10k 100k 1M 10M 100M
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
±5V
±3.3V
15260-020
Figure 20. Enabled Output Impedance vs. Frequency
60
10
20
30
40
50
0
–250
250
230
210
190
170
150
130
110
90
70
50
30
10
–10
–30
–50
–70
–90
–130
–110
–150
–170
–190
–210
–230
NUMBER OF UNITS
V
OS
(µV)
V
SY
= ±5V, T
A
= 25°C
600 CHANNELS
MEAN = 42µV
STDEV = 45µV
15260-021
Figure 21. Input Offset Voltage (VOS) Distribution, VSY = ±5 V
Data Sheet SSM6322
Rev. 0 | Page 11 of 20
60
10
20
30
40
50
0
–250
250
230
210
190
170
150
130
110
90
70
50
30
10
–10
–30
–50
–70
–90
–130
–110
–150
–170
–190
–210
–230
NUMBER OF UNITS
V
OS
(µV)
V
SY
= ±3.3V, T
A
= 25°C
600 CHANNELS
MEAN = 42µV
STDEV = 45µV
15260-022
Figure 22. Input Offset Voltage (VOS) Distribution, VSY = ±3.3 V
10
1
0.1
0.001 0.01 100.1 1001 1000
OUTPUT VOLTAGE HIGH TO SUPPLY RAIL (V)
I
LOAD
(mA)
V
SY
= ±5V
+85°C
+25°C
0°C
–40°C
15260-023
Figure 23. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = ±5 V
10
1
0.1
0.001 0.01 100.1 1001 1000
OUTPUT VOLTAGE LOW TO SUPPLY RAIL (V)
I
LOAD
(mA)
V
SY
= ±5V
+85°C
+25°C
0°C
–40°C
15260-024
Figure 24. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
VSY = ±5 V
10
1
0.1
0.001 0.01 100.1 1001 1000
OUTPUT VOLTAGE HIGH TO SUPPLY RAIL (V)
I
LOAD
(mA)
V
SY
= ±3.3V
+85°C
+25°C
0°C
–40°C
15260-025
Figure 25. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = ±3.3 V
10
1
0.1
0.001 0.01 100.1 1001 1000
OUTPUT VOLTAGE LOW TO SUPPLY RAIL (V)
I
LOAD
(mA)
V
SY
= ±3.3V
+85°C
+25°C
0°C
–40°C
15260-026
Figure 26. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) ,
VSY = ±3.3 V
7
1
2
3
4
5
6
0
01.0 4.02.0 5.03.00.5 1.5 4.52.5 5.53.5 6.0
+I
SY
(mA)
V
SY
(V)
V
SY
= 0V TO ±6V
I
SY
= +85°C
I
SY
= +25°C
I
SY
= 0°C
I
SY
= –40°C
15260-027
Figure 27. Positive Supply Current (+ISY) vs. Supply Voltage (VSY)
SSM6322 Data Sheet
Rev. 0 | Page 12 of 20
0
–5
–4
–3
–2
–1
–6
01.0 4.02.0 5.03.00.5 1.5 4.52.5 5.53.5 6.0
–ISY (mA)
VSY (V)
VSY = 0V TO ±6V
ISY = +85°C
ISY = +25°C
ISY = 0°C
ISY = –40°C
15260-028
Figure 28. Supply Current (−ISY) vs. Supply Voltage (VSY)
125
117
119
121
123
115
–40 –15 10 35 60 85
A
VO
(dB)
TEMPERATURE (°C)
A
VO
= ±5V, R
L
= 600Ω
A
VO
= ±3.3V, R
L
= 600Ω
15260-029
Figure 29. Open-Loop Gain (AVO) vs. Temperature
–
1.00
–2.25
–1.50
–2.00
–1.75
–1.25
–2.50
–40 –15 10 35 60 85
I
B
± (µA)
TEMPERATURE (°C)
V
SY
= ±5V
I
B
+
I
B
–
15260-030
Figure 30. Input Bias Current (IB±) vs. Temperature, VSY = ±5 V
–
1.00
–2.25
–1.50
–2.00
–1.75
–1.25
–2.50
–40 –15 10 35 60 85
I
B
± (µA)
TEMPERATURE (°C)
V
SY
= ±3.3V
I
B
+
I
B
–
15260-031
Figure 31. Input Bias Current (IB±) vs. Temperature, VSY = ±3.3 V
4.00
2.75
3.50
3.00
3.25
3.75
2.50
–40 –15 10 35 60 85
V
OH
(V)
TEMPERATURE (°C)
V
SY
= ±5V
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-032
Figure 32. Output Voltage High (VOH) vs. Temperature, VSY = ±5 V
–
2.50
–3.75
–3.00
–3.50
–3.25
–2.75
–4.00
–40 –15 10 35 60 85
V
OL
(V)
TEMPERATURE (°C)
V
SY
= ±5V
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-033
Figure 33. Output Voltage Low (VOL) vs. Temperature, VSY = ±5 V
Data Sheet SSM6322
Rev. 0 | Page 13 of 20
2.00
1.50
1.25
1.75
1.00
–40 –15 10 35 60 85
V
OH
(V)
TEMPERATURE (°C)
V
SY
= ±3.3V
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-034
Figure 34. Output Voltage High (VOH) vs. Temperature, VSY = ±3.3 V
–
1.00
–1.50
–1.75
–1.25
–2.00
–40 –15 10 35 60 85
V
OL
(V)
TEMPERATURE (°C)
V
SY
= ±3.3V
R
L
= 16Ω
R
L
= 32Ω
R
L
= 600Ω
15260-035
Figure 35. Output Voltage Low (VOL) vs. Temperature, VSY = ±3.3 V
6.5
5.9
5.7
6.1
6.3
5.5
–40 –15 10 35 60 85
+I
SY
(mA)
TEMPERATURE (°C)
±5V
±3.3V
15260-036
Figure 36. Supply Current (+ISY) vs. Temperature
–
5.3
–5.6
–5.7
–5.5
–5.4
–5.8
–40 –15 10 35 60 85
–I
SY
(mA)
TEMPERATURE (°C)
±5V
±3.3V
15260-037
Figure 37. Supply Current (−ISY) vs. Temperature
SSM6322 Data Sheet
Rev. 0 | Page 14 of 20
TEST CIRCUIT
15260-138
VEE2 GAIN2 FILT2
VP2
VN2
5
6
INPUT
VOUT2
SD2
VNFB2
OUTPUT
9
REF2
78
13
14
4
10
GND2
GND3
11 12
VCC2
15
SSM6322
499Ω
R
IN1
R
IN2
R
F
R
G
R
L
Figure 38. Test Circuit
Data Sheet SSM6322
Rev. 0 | Page 15 of 20
THEORY OF OPERATION
The SSM6322 is designed using Analog Devices, Inc., proprietary
extra fast complementary bipolar (XFCB) process. The device
features exceptionally low 1/f noise, low power, and load drive
capability. The device combines a classic difference amplifier
configuration with a common-mode loop that maintains a fixed
common-mode input level, regardless of the differential or
common-mode currents going into the device. This combination
results in the DAC operating in optimal conditions to reach the
THD specifications. This configuration of a common-mode
loop and a difference amplifier also has much lower noise and
power consumption than other solutions by eliminating two
additional amplifiers from the signal path.
The output driver has many features including heavy load drive,
multiplexing, and pop click suppression. In both shutdown
conditions, the output is high impedance in the audio band
when the applied external signal is between the supply rails.
An additional shutdown pin is included to power up the input
difference amplifier so that it can settle before any unwanted
signals are applied to the driver. The output driver is capable of
delivering −120 dB THD with a 100 mA peak output current
and a 2 V rms signal.
REF1 and REF2 Pin Voltage
REF1 and REF2 set the input common-mode signal. Internally,
there is a 15 µA current source; by externally adding a resistor,
15 µA of current flows through the resistor to generate a
common-mode voltage. For example, a 51 kΩ resistor and
15 µA current results in a common-mode voltage of 0.765 V.
Shutdown Control
The SSM6322 features two shutdown pins to control different
sections of the device. When SD and SD2 are Logic 1, the entire
device is enabled. When SD is Logic 0 and SD2 is Logic 1, the
input stage is enabled, and the output buffer is disabled. When
SD2 is Logic 0, the entire device is disabled with a quiescent
current of only 15 µA (see Table 6).
Table 6. Disabled Mode and Enabled Mode
Logic Level of the
Shutdown Pins Device Status
SD and SD2 = 1 Entire device is enabled.
SD = 0 and SD2 = 1 Input stage is enabled, and the output
buffer is disabled.
SD2 = 0 Entire device is disabled with a quiescent
current of 15 μA.
SSM6322 Data Sheet
Rev. 0 | Page 16 of 20
APPLICATIONS INFORMATION
HEADPHONE DRIVERS IN MOBILE PHONES
In a headphone driver application, some high performance
audio DACs can be configured as a voltage output or a current
output. Typically, the current output configuration results in the
best THD + N performance.
For a current output configuration, implement an current to
voltage (I to V) circuit to convert the differential current signal
from the R channel and the L channel to the differential voltage
signal, followed by a difference amplifier circuit (see Figure 41).
For a voltage output configuration, the conditioning circuit is a
difference amplifier circuit, which converts the differential
signal from the R channel or L channel to a single-ended signal
(see Figure 39).
Current output audio DACs are typically used to achieve the
best THD + N performance (see Figure 41). Six amplifiers and
many passive components are required to perform current
mode signal conditioning, which consumes more PCB area and
more power. Area consumption and power consumption are
important considerations in mobile phone applications.
R
DAC
V+
V–
DIFFERENTIAL TO
SINGLE-END
VOLTAGE OUTPUT
L
V+
V–
15260-039
Figure 39. Voltage Output DAC Configuration
The SSM6322 is an integrated solution for mobile phone
applications requiring low distortion and noise performance
while directly driving a low impedance load. The device also
saves more PCB area and power than the current discrete
solution.
The SSM6322 contains an additional buffer to support high
current drive capabilities. The buffer is also capable of being
configured in true high-Z mode in the audio band, which is
desirable in some portable applications for the multiplexing of
other signals on the same output port.
COMMON-MODE CONTROL CIRCUIT
The differential output stage of the DAC can be modeled as two
voltage sources, which both have the same amplitude and a 180°
phase difference. RS1 and RS2 are the source resistors of the
voltage source (see Figure 40).
In a typical current output DAC signal chain (see Figure 41),
four amplifiers are configured as an I to V circuit. The non-
inverting inputs are connected to a dc voltage that is the output
common-mode level of the DAC, making the voltage at the I+/I−
terminals a dc signal. This signal makes the voltage drop at two
internal source resistors of the DAC (RS1 and RS2) the same,
which makes the DAC achieve the best distortion performance.
In the SSM6322, the input difference amplifier performs the I to V
conversion.
15260-100
R
G
R
S
1
R
S
2
R
FSSM6322
INPUT
REF2
AUDIO
DAC
GND2
VEE2 VCC2 GAIN2
VP2
VN2
9
4
5
6
11 12 7
Figure 40. Common-Mode Circuit Without Common-Mode Control
R
DAC
I+
I–
DIFFERENTIAL TO
SINGLE-END
ITOV
CURRENT OUTPUT
L
I+
I–
15260-038
Figure 41. Current Output DAC Configuration
Data Sheet SSM6322
Rev. 0 | Page 17 of 20
Assuming there is no common-mode control (see Figure 40),
the signals at the input terminals (VP2/VN2) are ac signals that
have the same amplitude and phase. In addition, the internal
voltage source of the DAC is differential, which makes the
voltage drop at RS1 and RS2 different values. This difference
degrades the performance of the DAC. Simultaneously, from the
amplifier, the ac common-mode signal at two input terminals (VP2
and VN2) generates additional error signal at the output by its
limited ac common-mode rejection ratio (CMRR) performance.
After a common-mode control circuit (indicated by the dashed
outline shown in Figure 42) is included, the signal at the input
terminals (VP2 and VN2) is a dc signal set by the voltage at the
REF2 pin (typically this voltage is the same as the dc common-
mode voltage of the DAC). The voltage drop at RS1 and RS2 in
the DAC is the same. Additionally, the high dc CMRR performance
of the amplifier renders the CMRR error negligible. Both the
DAC and the amplifier have the best performance in this
configuration. The SSM6322 implements the circuit shown
in Figure 42.
R
G
R
S
1
R
S
2
R
F
SSM6322
INPUT
REF2
AUDIO
DAC
GND2
VEE2 VCC2 GAIN2
VP2
VN2
9
4
5
6
11 12 7
15260-101
Figure 42. Common-Mode Circuit with Common-Mode Control
CAPACITIVE LOAD DRIVE
Figure 43 shows the schematic of the output stage for driving
capacitive loads. Figure 44 and Figure 45 show the frequency
response for a gain of 1 at the ±5 V and ±3.3 V power supply
voltages, respectively. The peaking is high with a small
capacitive load. With a 2.2 nF capacitive load (CL), the
frequency response is flat and without peaking.
499Ω
10Ω
600Ω
V
OUT
R
SERIES
V
LOAD
C
L
15260-041
Figure 43. Schematic for Driving Capacitive Loads
20
10
0
–10
–20
–30
–40
–50
1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
SY
= ±5V
V
SD
= 5V
A
V
= 1
R
L
= 600Ω
CL2 = 330pF
CL2 = 470pF
CL2 = 1nF
CL2 = 2.2nF
15260-042
Figure 44. Frequency Response for Driving Capacitive Loads, VSY = ±5 V
20
10
0
–10
–20
–30
–40
–50
1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
SY
= ±3.3V
V
SD
= 3.3V
A
V
= 1
R
L
= 600Ω
CL2 = 330pF
CL2 = 470pF
CL2 = 1nF
CL2 = 2.2nF
15260-043
Figure 45. Frequency Response for Driving Capacitive Loads, VSY = ±3.3 V
SSM6322 Data Sheet
Rev. 0 | Page 18 of 20
SSM6322 IN A HEADPHONE DRIVER APPLICATION
SSM6322 Circuit with Current Output DAC
For an audio DAC with a differential current output, two gain
resistors convert the current to voltage (see Figure 46). The
resistor value is determined by the DAC output full-scale
current and the input stage output range (the output range is
±3 V at a ±5 V supply). Assuming that the DAC single-ended
output current is ±1.5 mA, and that the differential current is
±3 mA, the output of the input stage is ±3 V when using two
1 k gain resistors. The feedback capacitors, in parallel with the
gain resistors, form a single-pole, low-pass filter. The SSM6322
can handle up to a 1 k and 2.2 nF resistor capacitor combination.
Typically, audio DACs generate a dc offset current, which is
converted to an input common-mode voltage at the input of the
SSM6322. The REF1 and REF2 pins of the SSM6322 set the
input common-mode voltage of each channel. The voltage at
the REF1 and REF2 pins is achieved by an internal 15 µA
current source and an external resistor; a 51 kΩ resistor is
suggested to achieve a 0.765 V voltage. A 1 µF capacitor can be
used in parallel with the resistor to remove noise.
A 499 resistor and 1 nF capacitor can be added between the
input stage and output stage for a second single-pole, low-pass
filter, as shown in Figure 46.
For better gain matching and better distortion performance,
all 1 kΩ and 499 Ω resistors must to be of 0.1% tolerance and a
25 ppm/°C temperature coefficient. The 1 nF capacitors must be
NP0 capacitors. There are no specific requirements for the
51 kΩ resistor and the 1 µF capacitor at REF1 and REF2.
SSM6322 Circuit with Voltage Output DAC
For audio DACs that output a differential voltage, four gain
resistors convert the differential voltage to single-ended voltage
(see Figure 47). The feedback capacitors must be in parallel with
the gain resistors to form the single-pole, low-pass filter. As shown
in Figure 47, four 1 k resistors and two 1 nF capacitors are
used to achieve a gain of 1 and a first-order, 159 kHz cutoff
frequency low-pass filter.
For REF1 and REF2, refer to the DAC data sheet for the
common-mode voltage; then, calculate the resistor value at
REF1 and REF2. As shown in Figure 47, a 51 kΩ resistor is
suggested to obtain a 0.765 V voltage.
A 499 resistor and 1 nF capacitor can be added between the
input stage and output stage for a second single-pole, low-pass
filter, as shown in Figure 47.
For better gain matching and better distortion performance, all
1 kΩ and 499 kΩ resistors must be of a 0.1% tolerance and
25ppm/°C temperature coefficent; the 1 nF capacitor must be
NP0 capacitor.
There are no specific requirement for the 51 kΩ resistor and
1 µF capacitor at REF1 and REF2.
1µF
AUDIO
DAC
1nF
1nF
1nF
1kΩ
51kΩ
1kΩ
V
CM
VOUT2
VNFB2
SD2
OUTPUTINPUT
GND3FILT2GAIN2VEE2
VP2
GND2
REF2
VN2
VCC2
499Ω
15
13
14
871211
6
4
9
5
10
SSM6322
15260-044
Figure 46. SSM6322 Circuit with Current Output DAC
1µF
AUDIO
DAC
1nF
1nF
1nF
1kΩ
1kΩ
1kΩ
51kΩ
1kΩ
V
CM
VOUT2
VNFB2
SD2
OUTPUTINPUT
GND3FILT2GAIN2VEE2
VP2
GND2
REF2
VN2
VCC2
499Ω
15
13
14
871211
6
4
9
5
10
SSM6322
15260-045
Figure 47. SSM6322 Circuit with Voltage Output DAC
Data Sheet SSM6322
Rev. 0 | Page 19 of 20
DESIGN GUIDELINES
The performance of the SSM6322 is such that any minor
external interference can destroy the circuit. When using this
device, consider the following:
The sensing ground of the input stage is sensitive to
external interference. In the PCB layout, it is recommended
to refer the sensing ground to the output interface ground
(in high fidelity headphone driver applications, the output
interface is the jack). As shown in Figure 48, the dashed
outline enclosed ground is the input stage sensing ground,
which must be routed directly to the ground of the jack.
Note that Figure 48 only shows one channel; for the other
channel, route the sensing ground to the jack ground
separately.
The SSM6322 circuit is different with a typical current output
DAC signal chain (see Figure 41); there is only one op amp
that performs the differential I to V conversion. The power
across the noninverting grounded resistor is fixed, but the
power across the feedback resistor varies with the output
signal. This variability creates a mismatch between the two
resistors, as well as distortion if the heat cannot be well
dissipated. Low drift (25 ppm/°C) metal film or thin film
resistors are suggested to avoid this situation (see Figure 46).
If there is a resistor between the final output and the
headphone, the resistor must be low drift (25 ppm/°C) and
metal film or thin film to avoid distortion when driving
heavy loads.
Use a low dropout regulator (LDO) as the power supply.
Place the decoupling capacitors (0.1 F and 4.7 F) near
the amplifier power pins. If there is switching power on the
board, keep the switching power circuit and return path far
away from the SSM6322 circuit.
For better heat dissipation, solder the exposed pad of the
LFCSP package to the board pad and, using vias, connect
the exposed pad to a large, solid copper plane at the
opposite side of the board. The copper plane can be
connected to the negative supply plane or ground plane.
Shielding is important in mobile phone applications. To
reach <−100 dB THD + N specifications, even small
interferences can degrade THD + N performance,
particularly when listening to music and browsing the
internet simultaneously. Metal shielding helps prevent
performance degradation.
The maximum input filter capacitor values are 2.2 nF.
15260-046
1µF
AUDIO
DAC
1nF
1nF
1nF
1kΩ
51kΩ
1kΩ
V
CM
VOUT2
SD2
OUTPUTINPUT
GND3FILT2GAIN2VEE2
VP2
GND2
REF2
VN2
VCC2
499Ω
15
13
14
871211
6
4
9
5
10
SSM6322
VNFB2
Figure 48. Sensing Ground of Input Stage
SSM6322 Data Sheet
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
0.80
0.75
0.70
PKG-004273/5069
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8
BOTTOM VIEWTOP VIEW
4.10
4.00 SQ
3.90
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
03-02-2017-A
0.30
0.25
0.18
0.20 MIN
2.70
2.60 SQ
2.50
EXPOSED
PAD
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Package Package Description Package Option Branding
SSM6322ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15 6322A
SSM6322ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15 6322A
SSM6322ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-15 6322A
SSM6322CP-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15260-0-3/17(0)
