SST39VF080-90-4C-EIE - Silicon Storage Technology

EOL Data Sheet

S71146-07-EOL 6/07

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

8 Mbit (x8) Multi-Purpose Flash

SST39LF080 / SST39VF080

FEATURES:

• Organized as 1M x8

• Single Voltage Read and Write Operations

– 3.0-3.6V for SST39LF080

– 2.7-3.6V for SST39VF080

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 12 mA (typical)

– Standby Current: 4 µA (typical)

– Auto Low Power Mode: 4 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Fast Read Access Time:

– 55 ns for SST39LF080

– 70 and 90 ns for SST39VF080

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

15 seconds (typical) for SST39LF/VF080

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 40-lead TSOP (10mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST39LF/VF080 devices are 1M x8 CMOS Multi-Pur-

pose Flash (MPF) manufactured with SST’s proprietary,

high-performance CMOS SuperFlash technology. The

split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39LF080 write (Program or

Erase) with a 3.0-3.6V power supply. The SST39VF080

write (Program or Erase) with a 2.7-3.6V power supply.

They conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39LF/

VF080 devices provide a typical Byte-Program time of 14

µsec. The devices use Toggle Bit or Data# Polling to indi-

cate the completion of Program operation. To protect

against inadvertent write, they have on-chip hardware and

Software Data Protection schemes. Designed, manufac-

tured, and tested for a wide spectrum of applications,

these devices are offered with a guaranteed typical

endurance of 10,000 cycles. Data retention is rated at

greater than 100 years.

The SST39LF/VF080 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during Erase and Program than alter-

native flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. They also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high density, surface mount requirements, the

SST39LF/VF080 are offered in 40-lead TSOP and 48-

ball TFBGA packages. See Figures 1 and 2 for pin

assignments.

SST39LF/VF0803.0 & 2.7V 8Mb (x8) MPF memories

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

The SST39LF/VF080 also have the Auto Low Power

mode which puts the device in a near standby mode after

data has been accessed with a valid Read operation. This

reduces the IDD active read current from typically 15 mA to

typically 4 µA. The Auto Low Power mode reduces the typi-

cal IDD active read current to the range of 1 mA/MHz of

Read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition

used to initiate another Read cycle, with no access time

penalty. Note that the device does not enter Auto Low

Power mode after power-up with CE# held steadily low until

the first address transition or CE# is driven high.

Read

The Read operation of the SST39LF/VF080 is controlled

by CE# and OE#, both have to be low for the system to

obtain data from the outputs. CE# is used for device selec-

tion. When CE# is high, the chip is deselected and only

standby power is consumed. OE# is the output control and

is used to gate data from the output pins. The data bus is in

high impedance state when either CE# or OE# is high.

Refer to the Read cycle timing diagram for further details

(Figure 3).

Byte-Program Operation

The SST39LF/VF080 are programmed on a byte-by-byte

basis. Before programming, the sector where the byte

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load byte address and byte data. During the Byte-

Program operation, the addresses are latched on the falling

edge of either CE# or WE#, whichever occurs last. The

data is latched on the rising edge of either CE# or WE#,

whichever occurs first. The third step is the internal Pro-

gram operation which is initiated after the rising edge of the

fourth WE# or CE#, whichever occurs first. The Program

operation, once initiated, will be completed within 20 µs.

See Figures 4 and 5 for WE# and CE# controlled Program

operation timing diagrams and Figure 16 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any

commands issued during the internal Program operation

are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39LF/VF080 offer both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 4 KByte. The Block-Erase mode

is based on uniform block size of 64 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing waveforms. Any commands issued during the Sector-

or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF/VF080 provide a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 8 for timing diagram,

and Figure 19 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF/VF080 provide two software means to detect

the completion of a write (Program or Erase) cycle, in order

to optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (DQ7) and

Toggle Bit (DQ6). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

internal Program or Erase operation.

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST39LF/VF080 are in the internal Program

operation, any attempt to read DQ7 will produce the com-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 6 for

Data# Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The Toggle Bit is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block-, or Chip-Erase, the Toggle Bit is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle

Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF/VF080 provide both hardware and soft-

ware features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF/VF080 provide the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. The SST39LF/VF080 devices are

shipped with the Software Data Protection permanently

enabled. See Table 4 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to Read mode within TRC.

Common Flash Memory Interface (CFI)

The SST39LF/VF080 also contain the CFI information to

describe the characteristics of the device. In order to enter

the CFI Query mode, the system must load the three-byte

sequence, similar to the Software ID Entry command. The

last byte cycle of this command loads 98H (CFI Query

command) to address 5555H. Once the device enters the

CFI Query mode, the system can read CFI data at the

addresses given in Tables 5 through 7. The system must

write the CFI Exit command to return to Read mode from

the CFI Query mode.

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

Product Identification

The Product Identification mode identifies the device as

SST39LF080 or SST39VF080 and manufacturer as SST.

This mode may be accessed by software operations.

Users may use the Software Product Identification opera-

tion to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same socket. For details, see

Table 4 for software operation, Figure 11 for the Software

ID Entry and Read timing diagram and Figure 18 for the

Software ID Entry command sequence flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read operation.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 13 for timing waveform and Figure 18 for a

flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39LF/VF080 0001H D8H

T1.3 1146

Y-Decoder

I/O Buffers and Data Latches

1146 B1.2

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

Memory

Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 1: Pin Assignments for 40-lead TSOP

FIGURE 2: Pin Assignments for 48-ball TFBGA

A16

A15

A14

A13

A12

A11

WE#

A18

A17

VSS

A19

A10

DQ7

DQ6

DQ5

DQ4

VDD

DQ3

DQ2

DQ1

DQ0

OE#

VSS

CE#

1146 F01.3

Standard Pinout

Top View

Die Up

A14

WE#

A13

A18

A15

A11

A16

A12

A17

A19

DQ5

DQ2

DQ0

A10

DQ3

CE#

DQ6

VDD

OE#

VSS

DQ7

DQ4

DQ1

VSS

1146 48-tfbga P2.2

TOP VIEW (balls facing down)

A B C D E F G H

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the

sector. During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF080

2.7-3.6V for SST39VF080

VSS Ground

NC No Connection Unconnected pins.

T2.4 1146

1. AMS = Most significant address

AMS = A19 for SST39LF/VF080

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or Block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.4 1146

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX350H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry45555H AAH 2AAAH 55H 5555H 98H

Software ID Exit6/

CFI Exit

XXH F0H

Software ID Exit6/

CFI Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.4 1146

1. Address format A14-A0 (Hex),

Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080.

2. WA = Program Byte address

3. SAX for Sector-Erase; uses AMS-A12 address lines

BAX for Block-Erase; uses AMS-A16 address lines

AMS = Most significant address

AMS = A19 for SST39LF/VF080

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0

SST39LF/VF080 Device ID = D8H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080

1. Refer to CFI publication 100 for more details.

Address Data Data

10H 51H Query Unique ASCII string “QRY”

11H 52H

12H 59H

13H 01H Primary OEM command set

14H 07H

15H 00H Address for Primary Extended Table

16H 00H

17H 00H Alternate OEM command set (00H = none exists)

18H 00H

19H 00H Address for Alternate OEM extended Table (00H = none exits)

1AH 00H

T5.4 1146

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF080

Address Data Data

1BH 27H1VDD Min (Program/Erase)

30H1DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 36H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 00H VPP min (00H = no VPP pin)

1EH 00H VPP max (00H = no VPP pin)

1FH 04H Typical time out for Byte-Program 2N µs (24 = 16 µs)

20H 00H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 04H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H 06H Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H 01H Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)

24H 00H Maximum time out for buffer program 2N times typical

25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 01H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

T6.2 1146

1. 0030H for SST39LF080 and 0027H for SST39VF080

TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080

Address Data Data

27H 14H Device size = 2N Bytes (14H = 20; 220 = 1 MByte)

28H 00H Flash Device Interface description; 0000H = x8-only asynchronous interface

29H 00H

2AH 00H Maximum number of bytes in multi-byte write = 2N (00H = not supported)

2BH 00H

2CH 02H Number of Erase Sector/Block sizes supported by device

2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 00H y = 255 + 1 = 256 sectors (00FFH = 255)

2FH 10H

30H 00H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 0FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 00H y = 15 + 1 = 16 blocks (000FH = 15)

33H 00H

34H 01H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.0 1146

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39LF080

Range Ambient Temp VDD

Commercial 0°C to +70°C 3.0-3.6V

OPERATING RANGE FOR SST39VF080

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF080

Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080

See Figures 14 and 15

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

TABLE 8: DC OPERATING CHARACTERISTICS

VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF0801

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT

, at f=1/TRC Min

VDD=VDD Max

Read220 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T8.7 1146

1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C

(room temperature), and VDD = 3V for VF devices. Not 100% tested.

2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T9.1 1146

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T10.0 1146

TABLE 11: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T11.2 1146

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

AC CHARACTERISTICS

TABLE 12: READ CYCLE TIMING PARAMETERS

VDD = 3.0-3.6V FOR SST39LF080 AND 2.7-3.6V FOR SST39VF080

Symbol Parameter

SST39LF080-55 SST39VF080-70 SST39VF080-90

UnitsMin Max Min Max Min Max

TRC Read Cycle Time 55 70 90 ns

TCE Chip Enable Access Time 55 70 90 ns

TAA Address Access Time 55 70 90 ns

TOE Output Enable Access Time 30 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 0 ns

TOLZ1OE# Low to Active Output 0 0 0 ns

TCHZ1CE# High to High-Z Output 15 20 30 ns

TOHZ1OE# High to High-Z Output 15 20 30 ns

TOH1Output Hold from Address Change 0 0 0 ns

T12.4 1146

TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T13.0 1146

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 3: Read Cycle Timing Diagram

FIGURE 4: WE# Controlled Program Cycle Timing Diagram

1146 F02.2

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

1146 F03.2

ADDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 5: CE# Controlled Program Cycle Timing Diagram

FIGURE 6: Data# Polling Timing Diagram

1146 F04.2

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

1146 F05.2

ADDRESS AMS-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 7: Toggle Bit Timing Diagram

FIGURE 8: WE# Controlled Chip-Erase Timing Diagram

1146 F06.2

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

1146 F08.3

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 9: WE# Controlled Block-Erase Timing Diagram

FIGURE 10: WE# Controlled Sector-Erase Timing Diagram

1146 F09.3

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 5055AA 80 AA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

1146 F10.3

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

TSE

TWP

SIX-BYTE CODE FOR SECTOR-ERASE

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 11: Software ID Entry and Read

FIGURE 12: CFI Query Entry and Read

Note: Device ID = D8H for SST39LF/VF080

1146 F11.4

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

Device ID

55AA 90

OE#

CE#

1146 F12.0

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

55AA 98

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 13: Software ID Exit/CFI Exit

1146 F13.0

ADDRESS A14-0

DQ7-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 14: AC Input/Output Reference Waveforms

FIGURE 15: A Test Load Example

1146 F14.1

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1146 F15.1

TO TESTER

TO DUT

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 16: Byte-Program Algorithm

1146 F16.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 17: Wait Options

1146 F17.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 18: Software ID/CFI Command Flowcharts

1146 F18.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: AAH

Address: 5555H

CFI Query Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 98H

Address: 5555H

Wait TIDA

Read CFI data

Load data: AAH

Address: 5555H

Software ID Exit/CFI Exit

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 19: Erase Command Sequence

1146 F19.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

Wait TSCE

Chip erased

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

Wait TSE

Sector erased

to FFH

Load data: AAH

Address: 5555H

Block-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 50H

Address: BAX

Load data: AAH

Address: 5555H

Wait TBE

Block erased

to FFH

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

PRODUCT ORDERING INFORMATION

Valid combinations for SST39LF080

SST39LF080-55-4C-EI SST39LF080-55-4C-B3K

SST39LF080-55-4C-EIE SST39LF080-55-4C-B3KE

Valid combinations for SST39VF080

SST39VF080-70-4C-EI SST39VF080-70-4C-B3K

SST39VF080-70-4C-EIE SST39VF080-70-4C-B3KE

SST39VF080-90-4C-EI SST39VF080-90-4C-B3K

SST39VF080-90-4C-EIE SST39VF080-90-4C-B3KE

SST39VF080-70-4I-EI SST39VF080-70-4I-B3K

SST39VF080-70-4I-EIE SST39VF080-70-4I-B3KE

SST39VF080-90-4I-EI SST39VF080-90-4I-B3K

SST39VF080-90-4I-EIE SST39VF080-90-4I-B3KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E = non-Pb

Package Modifier

I = 40 leads

K = 48 balls

Package Type

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

E = TSOP (type 1, die up, 10mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

Device Density

080 = 8 Mbit

Voltage

L = 3.0-3.6V

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

SST 39 VF 080 - 70 - 4C - B3K E

XX XX XXXX - XXX -XX- XXX X

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

PACKAGING DIAGRAMS

FIGURE 20: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm

SST Package Code: EI

18.50

18.30

20.20

19.80

0.70

0.50

10.10

9.90

0.27

0.17

1.05

0.95

0.15

0.05

0.70

0.50

40-tsop-EI-7

Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

Pin # 1 Identifier

0.50

BSC

1.20

max.

0˚- 5˚

DETAIL

1mm

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39LF080 / SST39VF080

FIGURE 21: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

TABLE 14: REVISION HISTORY

Number Description Date

03 •2002 Data Book May 2002

04 •B3K package no longer offered for SST39LF/VF016

•Part number changes - see page 23 for additional information

•Changes to Table 8 on page 10

– Added footnote for MPF power usage and Typical conditions

– Changed the IALP test onditions

– Clarified the test conditions for Power Supply Current and Read parameters

– Corrected the IDD Read Current from 15 mA to 20 mA

– Corrected the IDD Program and Erase Current from 20 mA to 30 mA

Mar 2003

05 •Removed 16 Mbit parts (SST39LF/VF016); refer to SST39VF1681/1682 (S71243) Aug 2003

06 •2004 Data Book

•Updated B3K package diagram

Nov 2003

07 •End of Life Data Sheet for all devices in S71146 June 2007

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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