1/21
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High Reliability Serial EEPROMs
I2C BUS
BR24□□□□family
BR24T□□□□Series
●Description
BR24T□□□-W series is a serial EEPROM of I2C BUS interface method
●Features
1) Completely conforming to the world standard I2C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 1.7V～5.5V single power source action most suitable for batter y use
4) 1.7V～5.5Vwide limit of action voltage, possible FAST MODE 400KHz action
5) Page write mode useful for initial value write at factory shipment
6) Auto erase and auto end function at data write
7) Low current consumption
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various packages
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●BR24T series
Capacity Bit format Type Power source
Voltage DIP-T8 SOP8 SOP-J8 SSOP-B8 TSSOP-B8 TSSOP-B8J MSOP8 VSON008
X2030
1Kbit 128×8 BR24T01-W 1.7～5.5V ● ● ● ● ● ● ● ●
2Kbit 256×8 BR24T02-W 1.7～5.5V ● ● ● ● ● ● ● ●
4Kbit 512×8 BR24T04-W 1.7～5.5V ● ● ● ● ● ● ● ●
8Kbit 1K×8 BR24T08-W 1.7～5.5V ● ● ● ● ● ● ● ●
16Kbit 2K×8 BR24T16-W 1.7～5.5V ● ● ● ● ● ● ● ●
32Kbit 4K×8 BR24T32-W 1.7～5.5V ● ● ● ● ● ● ● ●
64Kbit 8K×8 BR24T64-W 1.7～5.5V ● ● ● ● ● ● ● ●
128Kbit 16K×8 BR24T128-W 1.7～5.5V ● ● ● ● ● ● ● ●
256Kbit 32K×8 BR24T256-W 1.7～5.5V ● ● ● ● ●
512Kbit 64K×8 BR24T512-W 1.7～5.5V ☆ ☆ ☆ ☆ ☆
1024Kbit 128K×8 BR24T1M-W 1.7～5.5V ☆ ☆ ☆
☆:Developing
No.11001EAT21
Technical Note
2/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Absolute maximum ratings (Ta=25℃) ●Memory cell characteristics (Ta=25℃, Vcc=1.7～
5.5V)
Parameter Symbol Ratings Unit
Impressed voltage VCC -0.3～+6.5 V
Permissible
dissipation Pd
450 (SOP8)*1
mW
450 (SOP-J8)*2
300 (SSOP-B8)*3
330 (TSSOP-B8)*4
310 (TSSOP-B8J)*5
310 (MSOP8) *6
300 (VSON008X2030) *7
800 (DIP-T8)*8
Storage
temperature range Tstg －65～+150 ℃
Action
temperature range Topr －40～+85 ℃
Terminal voltage ‐ -0.3～Vcc+1.0*9 V
Junction
temperature *10 Tjmax 150 ℃
*1,*2 When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
*3,*7 When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
*4 When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
*5, *6 When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
*8 When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
*10 Junction temperature at the storag e condition.
Parameter Limits Unit
Min. Typ. Max
Number of data
rewrite times *1 1,000,000 － － Times
Data hold years *1 40 － － Years
*1Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Ratings Unit
Power source
voltage Vcc 1.7～5.5 V
Input voltage VIN 0～Vcc
●Electrical characteristics
(
Unless otherwise specified, Ta=－40～+85
℃
,
VCC=1.7～5.5V
)
Parameter Symbol Limits Unit Conditions
Min. Typ. Max.
“H” input voltage 1 VIH1 0.7Vcc － Vcc+1.0 V
“L” input voltage 1 VIL1 -0.3*2 － 0.3Vcc V
“L” output voltage 1 VOL1 － － 0.4 V IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
“L” output voltage 2 VOL2 － － 0.2 V IOL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
Input leak current ILI －1 － 1 µA VIN=0～Vcc
Output leak current ILO －1 － 1 µA VOUT=0～Vcc (SDA)
Current consumption
at action
ICC1
－ － 2.0
mA
Vcc=5.5V,fSCL=400kHz,
t
WR=5ms,
Byte write, Page write
BR24T01/02/04/08/16/32/64-W
－ － 2.5 Vcc=5.5V,fSCL=400kHz,
t
WR=5ms,
Byte write, Page write
BR24T128/256-W
－ － 4.5 Vcc=5.5V,fSCL=400kHz,
t
WR=5ms,
Byte write, Page write
BR24T512/1M-W
ICC2
－ － 0.5
mA
Vcc=5.5V,fSCL=400kHz
Random read, current read, sequential read
BR24T01/02/04/08/16/32/64/128/256-W
－ － 2.0 Vcc=5.5V,fSCL=400kHz
Random read, current read, sequential read
BR24T512/1M-W
Standby current ISB
－ － 2.0
µA
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W
－ － 3.0 Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W
○ Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)
Technical Note
3/21
BR24T□□□□Series
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●Action timing characteristics
(Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Parameter Symbol
Limits Unit
Min. Typ. Max.
SCL frequency fSCL － － 400 kHz
Data clock “HIGH“ time tHIGH 0.6 － － µs
Data clock “LOW“ time tLOW 1.2 － － µs
SDA, SCL rise time *1 tR － － 1.0 µs
SDA, SCL fall time *1 tF － － 1.0 µs
Start condition hold time tHD:STA 0.6 － － µs
Start condition setup time tSU:STA 0.6 － － µs
Input data hold time tHD:DAT 0 － － ns
Input data setup time tSU:DAT 100 － － ns
Output data delay time tPD 0.1 － 0.9 µs
Output data hold time tDH 0.1 － － µs
Stop condition setup time tSU:STO 0.6 － － µs
Bus release time before transfer start tBUF 1.2 － － µs
Internal write cycle time tWR － － 5 ms
Noise removal valid period (S DA, SCL terminal) tI － － 0.1 µs
WP hold time tHD:WP 1.0 － － µs
WP setup time tSU:WP 0.1 － － µs
WP valid time tHIGH:WP 1.0 － － µs
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data tim ing refa rence le vel: 0.3×Vcc/ 0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
Fig.1-(e) WP timing at write cancel
SCL
SDA
(input)
SDA
(output)
tR tF tHIGH
tSU:DAT
tLOW tHD:DAT
tDHtPD
tBUF
70%
70%
30%
70% 70%
30% 30%
70% 70%
30%
70% 70%
70%
70%
30%
30%
30%
70% 70%
tSU:STA tHD:STA
START CONDITION
tSU:STO
STOP CONDITION
30%
30%
70%
70%
D0 ACK
tWRwrite data
(n-t h address) START CONDITIONSTOP CON DITION
70%
70%
DATA(1)
D0 ACK
D1
DATA(n)
ACK tWR
30%
70%
STOP CONDITION
tHD:WP
tSU:WP
30%
70%
DATA(1)
D0
D1 ACK
DATA(n)
ACK
tHIGH:WP
70% 70%
tWR
70%
Technical Note
4/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Block diagram
Fig.2 Block diagram
●Pin assignment and description
Terminal
Name Input/
Output BR24T01-W BR24T02-W BR24T04-W BR24T08-W BR24T16-W BR24T32/64/
128/256/512-W BR24T1M-W
A0 Input
Slave address setting Don’t use* Slave address
setting Don’t use*
A1 Input Slave address setting Don’t use* Slave address setting
A2 Input Slave address setting Don’t use* Slave address setting
GND － Reference voltage of all input / output, 0V
SDA Input/
output Serial data input serial data output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc － Connect the power source.
*Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
●Characteristic data (The following values are Typ. ones.)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
H INPUT VOLTAGE : V
IH1
(V)
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLYVOLTAGE : Vcc(V)
INPUT LEAK CURRENT : I
LI
(uA)
0
0.2
0.4
0.6
0.8
1
0123456
L OUTPUT CURRENT : I
OL
(mA)
L OUTPUT VOLTAGE : V
OL2
(V)
0
0.2
0.4
0.6
0.8
1
1.2
0123456
SUPPLY VOLTAGE : Vcc(V)
OUTPUT LEAK CURRENT : I
LO
(uA)
0
0.2
0.4
0.6
0.8
1
0123456
L OUTPUT CURRENT : I
OL
(mA)
L OUTPUT VOLTAGE : V
OL1
(V)
Fig.5 'L' output voltage V
OL1
-I
OL
(Vcc=1.7V)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
L INPUT VOLTAGE : V
IL1
(V)
Fig.6 'L' output voltage V
OL2
-I
OL
(Vcc=2.5V) Fig.7 Input leak current I
LI
(A0,A1,A2,SCL,WP) Fig.8 Output leak current I
LO
(SDA)
Fig.4 'L' input voltage V
IL1
(A0,A1,A2,SCL,SDA,WP)
Fig.3 'H' input voltage V
IH1
(A0,A1,A2,SCL,SDA,WP)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
SPEC
SPEC SPEC
8
7
6
5 4
3
2
1
SDA
SCL
WP
Vcc
GND
A2
A1
A0
Address
decoder Word
address register Data
register
Control circuit
High voltage
generating circuit
P
ower source
voltage detection
8bit
ACK
START STOP
1Kbit～1024Kbit EEPROM array
*1
*1
*2
*2
*2
13bit
14bit
15bit
16bit
17bit
7bit
8bit
9bit
10bit
11bit
12bit
*1 7bit: BR24T01-W
8bit: BR24T02-W
9bit: BR24T04-W
10bit: BR24T08-W
11bit: BR24T16-W
2
5
6
Vcc
SCL
GND
BR24T01-W
BR24T02-W
BR24T04-W
BR24T08-W
BR24T16-W
BR24T32-W
BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W
BR24T1M-W
1
3
4
7
8
WP
SDA
A2
A1
A0
12bit: BR24T32-W
13bit: BR24T64-W
14bit: BR24T128-W
15bit: BR24T256-W
16bit: BR24T512-W
17bit: BR24T1M-W
*2 A0= Don't use : BR24T04-W, BR24T1M-W
A0, A1=Don't use: BR24T08-W
A0, A1, A2=Don't use: BR24T16-W
Technical Note
5/21
BR24T□□□□Series
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© 2011 ROHM Co., Ltd. All rights reserved.
●Characteristic data (The following values are Typ. ones.)
0
0.5
1
1.5
2
2.5
3
3.5
0123456
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
0
0.5
1
1.5
2
2.5
0123456
SUPPLY VOLTAGE : Vcc(V)
STANBY CURRENT : I
SB
(uA)
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
0123456
SUPPLY VOLTAGE : Vcc(V)
START CONDITION
SET UP TIME : tSU:STA(us)
0.1
1
10
100
1000
10000
0123456
SUPPLY VOLTAGE : Vcc(V)
SCL FREQUENCY : fｓｃｌ（ｋH
Z
）
-200
-150
-100
-50
0
50
0123456
SUPPLY VOLTAGE : Vcc(V)
INPUT DATA HOLD TIME : t
HD: STA
(ns)
0
0.2
0.4
0.6
0.8
1
0123456
SUPPLY VOLTAGE : Vcc(V)
DATA CLK H TIME : t
HIGH
(us)
0
0.5
1
1.5
2
2.5
0123456
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
Fig.9 Current consumption at WRITE operation I
CC
1
(fscl=400kHz BR24T01/02/04/08/16/32/64-W) Fig.10 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T128/256-W)
Fig.14 Stanby operation I
SB
(
fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W
)
Fig.17 Data clock High Period t
HIGH
0
0.3
0.6
0.9
1.2
1.5
0123456
SUPPLY VOLTAGE : Vcc（V）
ＤＡＴＡ CLK L TIME : t
LOW
(us)
Fig.18 Data clock Low Period t
LOW
0
0.2
0.4
0.6
0.8
1
0123456
SUPPLY VOLTAGE : Vcc(V)
START CONDITION HOLD TIME : t
HD : STA
(us)
Fig.19 Start Condition Hold Time t
HD : STA
Fig.20 Start Condition Setup Time t
SU : STA
Fig.21 Input Data Hold Ti me t
HD : DAT
（HIGH） Fig.22 Input Data Hold Time ｔ
HD : DAT
(LOW） Fig.23 Input Data Setup Time ｔ
SU: DAT
(HIGH)
-200
-150
-100
-50
0
50
0123456
SUPPLY VOLTAGE : Vcc(V)
INPUT DATA HOLD TIME : t
HD :DAT
(ns)
-200
-100
0
100
200
300
0123456
SUPPLY VOLTAGE : Vcc(V)
INPUT DATA SET UP TIME : t
SU: DAT
(ns)
Fig.16 SCL frequency f
SCL
Fig.12 Current consumption at READ operation I
CC
2
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
Fig.11 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24T512/1M-W)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
Fig.13 Current consumption at READ operation I
CC
2
(fscl=400kHz BR24T512/1M-W)
Fig.15 Stanby operation I
SB
(fscl=400kHz BR24T512/1M-W)
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0
0.5
1
1.5
2
2.5
0123456
SUPPLY VOLTAGE : Vcc(V)
STANBY CURRENT : I
SB
(uA)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃ Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC SPEC
SPEC SPEC
SPEC
SPEC SPEC
SPEC SPEC
SPEC
The plan for
inserting data.
(BR24T512/1M-W)
The plan for
inserting data.
(BR24T512/1M-W)
The plan for
inserting data.
(BR24T512/1M-W)
Technical Note
6/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Characteristic data (The following values are Typ. ones.)
0
0.5
1
1.5
2
0123456
SUPPLY VOLTAGE : Vcc(V)
BUS OPEN TIME
BEFORE TRANSMISSION : tBUF(us)
0
1
2
3
4
5
6
0123456
SUPPLY VOLTAGE : Vcc(V)
INTERNAL WRITING
CYCLE TIME : tWR(ms)
-200
-100
0
100
200
300
0123456
SUPPLY VOLTAGE : Vcc(V)
INPUT DATA SET UP TIME : tSU : DAT(ns)
0.0
0.5
1.0
1.5
2.0
0123456
SUPPLY VOLTAGE : Vcc(V)
OUTPUT DATA DELAY TIME : tPD(us)
Fig.24 Input Data setup time t
SU : DAT
(LOW) Fig.25 'L' Data output delay time t
PD
0Fig.26 'H' Data output delay time ｔ
PD
1
Fig.28 BUS open ti me before transmission ｔ
BUF
Fig.29 Internal writing cycle time ｔ
WR
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
NOISE REDUCTION
EFECTIVE TIME : tl(SCL H) (us)
Fig.30 Noise reduction efection time t
l
（SCL H） Fig.31 Noise reduction efective time t
l
（SCL L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
NOISE REDUCTION
EFECTIVE TIME : tl(SCL L)(us)
Fig.32 Noise resuction efecctive time ｔ
ｌ
（SDA H）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLATGE : Vcc(V)
NOISE REDUCTION
EFECTIVE TIME : tl(SDA H)(us)
Fig.33 Noise reduction efective time t
l
（SDA L）
0
0.1
0.2
0.3
0.4
0.5
0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
NOISE REDUCTION
EFFECTIVE TIME : tl(SAD L)(us)
Fig.35 WP setup time t
SU : WP
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0123456
SUPPLY VOLTAGE : Vcc(V)
WP SET UP TIME : tSU : WP(us)
Fig.36 WP efective time t
HIGH : WP
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0123456
SUPPLYVOLTAGE : Vcc(V)
WP EFFECTIVE TIME : tHIGH : WP(us)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC SPEC
SPEC
SPEC
SPEC
SPEC SPEC SPEC
SPEC
0.0
0.5
1.0
1.5
2.0
0123456
SUPPLY VOLTAGE : Vcc(V)
OUTPUT DATA DELAY TIME : tPD(us)
SPEC
SPEC
-0.5
0.0
0.5
1.0
1.5
2.0
0123456
SUPPLY VOLTAGE : Vcc(V)
STOP CONDITION SETUP TIME : t
su
:STO(us)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0123456
SUPPLYVOLTAGE : Vcc(V)
WP DATA HOLD TIME : tHD : WP(us)
Fig.27 Stop condition setup time
ｔ
SU
:STO
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Fig.34 WP data hold time tHD:WP
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Technical Note
7/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●I2C BUS communication
○I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each b yte. I2C BUS carries out data transmission with plur al devices con nect ed
by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended b y SDA rising from 'LOW' to ' HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releas es the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs ackno wledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for reco gnizing a device type.
The device code of this IC is fixed to '1010' .
・Next slave addresses (A2 A1 A0 --- device addr ess) are for selecting devices, an d plural ones can be used o n a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE ) of slave address is used for designating write or read action,
and is as shown belo w.
Setting W/R to 0 ------- write (setting 0 to word address setting of random read)
Setting W/R to 1 ------- read
Type Slave a ddress Maximum number of
Connected buses
BR24T01-W,BR24T02-W 1 0 1 0 A2 A1 A0 R/W
―― 8
BR24T04-W 1 0 1 0 A2 A1 P0 R/W
―― 4
BR24T08-W 1 0 1 0 A2 P1 P0 R/W
―― 2
BR24T16-W 1 0 1 0 P2 P1 P0 R/W
―― 1
BR24T32-W,BR24T64-W,BR24T128-W,
BR24T256-W,BR24T512-W 1 0 1 0 A2 A1 A0 R/W
―― 8
BR24T1M-W 1 0 1 0 A2 A1 P0 R/W
―― 4
P0～P2 are page select bits.
89 89 89
S P
condition condition
ACK STOPACKDATA DATAADDRES
S
START R/W ACK
1-7
SDA
SCL 1-7 1-7
Fig.37 Data transfer timing
Technical Note
8/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Write Command
○Write cy cle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write
continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write
bytes is specified per device of each capacity. Up to 256 arbitrary bytes can be written.(In the case of BR24T1M-W)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n) DATA(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+15)
A
C
K
SLAVE
ADDRESS
10 0
1A0 A1 A2 WA
7 D0 D7 D0
注)
WA
0
A1 A2 WA
7 D7
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 WA
0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
Fig.38 Byte write cycle (BR24T01/02/04/08/16-W)
A1 A2 WA
14
1 1 0 0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS DATA
SLAVE
ADDRESS
A0 D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
13 WA
12 WA
11 WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
WA
15
*1 As for WA1 2, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
Fig.39 Byte write cycle (BR24T32/64/128/256/512/1M-W)
Fig.40 Page write cycle (BR24T01/02/04/08/16-W)
Fig.41 Page write cycle (BR24T32/64/128/256/512/1M-W)
*1 As for WA1 2, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+1 27)
As for BR24T1M-W becomes (n+255)
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
A
DDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n+31)
A
C
K
SLAVE
A
DDRESS
1
0 0 0
1
0
A
0
A
1
A
2 WA
14 D0
注 ) *1
DATA(n)
D0D7
A
C
K
2nd WORD
A
DDRESS(n)
WA
0
WA
13 WA
12 WA
11
*2
Note)
Fig.42 Difference of slave address of each type
As for WA7, BR 24 T0 1-W becomes Don't care.
*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)
*2
*1
WA
15
*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T04/08/16/1M-W A0 becomes P0.
10 0
1A0
A1
A2
*1 *2 *3
Technical Note
9/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8Byte (BR24T01-W, BR24T02-W)
Up to 16Byte (BR24T04-W, BR24T08-W, BR24T16-W)
Up to 32Byte (BR24T32-W, BR24T64-W)
Up to 64Byte (BR24T 128-W, BR24T256-W)
Up to 128Byte (BR24T512-W)
Up to 256Byte (BR24T1M-W )
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)
・As for page write cycle of BR24T01-W and BR24T 02-W, after the significant 4 bits (in the case of BR24T 01-W) of word
address, or the significant 5 bits (in the case of BR24T02-W) of word address are design ated arbitrarily, by continuing
data input of 2 bytes or more, the ad dress of insig nificant 3 bits is incremented internally, and data up to 8 bytes can be
written.
・As for page write command of BR24T04-W, BR24T08-W and BR24T16-W, after page select bit ’P0’(in the case of
BR24T04-W), after page select bit ’P0,P1’(in the case of BR24T08-W), after page select bit ’P0,P1,P2’(in the case of
BR24T16-W) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of
insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
・As for page write cycle of BR24T32-W and BR24T 64-W, after the significant 7 bits (in the case of BR24T 32-W) of word
address, or the significant 8 bits (in the case of BR24T64-W) of word address are design ated arbitrarily, by continuing
data input of 2 bytes or more, the address of insig nificant 5 bits is incremented internally, and data up to 32 bytes can
be written.
・As for page write cycle of BR24T128-W and BR24T 256-W, after the significant 8 bits (in the case of BR24T 128-W) of
word address, or the significant 9 bits (in the case of BR24T256-W) of word address are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64
bytes can be written.
・As for page write cycle of BR24T512-W after the significant 9 bits of word address is designated arbitrarily, by continuing
data input of 2 bytes or more, the ad dress of insignificant 7 bits is incremented internally, and data up to 128 byt es can
be written.
・As for page write cycle of BR24T 1M-W after page select bit ’P0’ and the significant 8 bit of word address are designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and
data up to 256 bytes can be written.
Technical Note
10/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
○Notes on page write cycle
List of numbers of page write
Number of Pages 8Byte 16Byte 32Byte 64Byte 128Byte 256Byte
Product number BR24T01-W
BR24T02-W BR24T04-W
BR24T08-W
BR24T16-W BR24T32-W
BR24T64-W BR24T128-W
BR24T256-W BR24T512-W BR24T1M-W
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24T256-W, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte b ulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)
○Internal address increment
Page write mode (in the case of BR24T16-W)
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･ which please note.
※0Eh･･･0E in hexadecimal, therefore,
00001110 becomes a binary number.
WA7 WA4 WA3 WA2 WA1 WA0
0 00000
0 00001
0 00010
0 01110
0 01111
0 00000
Increment
0Eh
Significant bit is fixed.
No digit up
Technical Note
11/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a
command to read data by designating address, and is used generally. Current read cycle is a command to read data of
internal address register without designating address, and is used when to verify just after write cycle. In both the read
cycles, sequential read cycle is available, and the next address data can be read in succession.
・In random read cycle, data of designated word address can be re ad.
・When the command just before curre nt read cycle is random read c ycle, current read cycle (each including s equential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL
signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Fig.43 Random read cycle (BR24T01/02/04/08/16-W)
Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)
*1 As for WA 1 2, BR 2 4T32-W become Don’t care.
As for WA13, BR24T32/64-W become Don’t care.
As for WA14, BR24T32/64/128-W become Don’t care.
As for WA15, BR24T32/64/128/256-W become Don’t care.
Fig.45 Current read cycle
Fig.46 Sequential read cycle (in the case of current rea d cycle)
*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T08/16/1M-W, A0 becomes P0.
Note)
*1 As for WA7,BR24T01-W become Don’t care.
Fig.47 Difference of slave address of each type
A2 A0
A1
A1
A2
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st WORD
ADDRESS
（）
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0
1
A0 D7 D0
2nd WORD
ADDRESS(n)
A
C
K
S
T
A
R
T SLAVE
ADDRESS
100
1
R
/
W
R
E
A
D
WA
0
Note)
*1
WA
15
WA
14
WA
13
WA
12
WA
11
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WORD
ADDRESS(n)
SDA
LINE
A
C
K
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 WA
7 A0 D0
SLAVE
ADDRESS
10 0 1A1 A2
S
T
A
R
T
D7
R
/
W
R
E
A
D
WA
0
Note)
*1
S
T
A
R
T
S
T
O
P
SDA
LINE
A
C
K
DATA(n)
A
C
K
SLAVE
ADDRESS
10 0 1 A0 A1 A2 D0 D7
R
/
W
R
E
A
D
Note)
R
E
A
D
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
DATA
(
n
)
SDA
LINE
A
C
K
A
C
K
DATA
(
n+x
)
A
C
K
SLAVE
ADDRESS
10 0
1A0
A1
A2
D0
D7 D0
D7
Note）
*1 As for WA12, BR2 4T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)
*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)
1
0
0
1A0
A1
A2
*1 *2 *3
Technical Note
12/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48-(a), Fig.48-(b), Fig.48-(c).) In
dummy clock input area, rel ease the SDA b us ('H' by pull up). In dummy clock are a, ACK output and read data '0' (both 'L'
level) may be output from EE PROM, therefore, if 'H' is input forcibl y, output may conflict and over curre nt may flow, leading
to instantaneous power failure of system power source or influence upon d evices.
●Acknowledge polling
During internal write executio n, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave addr ess) is sent, and if the first ACK signal s ends b ack 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, W/R = 0, when to carry out current read cycle after write, slave address W/R = 1 is sent,
and if ACK sig nal sends back 'L', then execute word address input and data output and so forth.
1 2 13 14
SCL
Dummy clock×14 Start×2
SCL
Fig.48-(a) The case of dummy clock +START+START+ command input
※Start command from START input.
2 1 8 9
Dummy clock×9 Start
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
Start
Normal command
Normal command
Normal command
Normal command
Start×9
SDA
SDA
SCL
SD
1 2 3 8 9 7
Fig.48-(c) START×9+ command input
Normal command
Normal command
SDA
Slave
address
Word
address
…
…
S
T
A
R
T
First write command
A
C
K
H
A
C
K
L
Slave
address
Slave
address
Slave
address Data
Write command
During internal write,
ACK = HIGH is sent back.
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
tWR
tWR
Second write command
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
A
R
T
S
T
O
P
S
T
O
P
A
C
K
H
A
C
K
H
A
C
K
L
A
C
K
L
Fig.49 Case to continuously writ e by acknowledge polling
Technical Note
13/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid ar ea, by setting WP=' H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. T herefore, execute software reset. And when command is cancelled by
start, stop condition, during random read c ycle, sequential read cycle, or current read cycle, inter nal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
・Rise of D0 taken clock
SCL
D0 ACK
Enlarged view
SCL
SDA ACK D0
・Rise of SDA
SDA
WP
WP cancel invalid area WP cancel valid area
Data is not written.
Fig.50 WP valid timing
Slave
address D7 D6 D5 D4 D3 D2 D1 D0 Data tWR
SDA D1
S
T
A
R
T
A
C
K
L
A
C
K
L
A
C
K
L
A
C
K
L
S
T
O
P
Word
address
Fig.51 Case of cancel by start, stop condition during slave address input
SCL
SDA 1 1 0 0
Start condition Stop condition
Enlarged view
WP cancel invalid area
Technical Note
14/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requir es pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
①SDA rise time to be determi ned by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential ○
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin 0.2Vcc.
VCC－ILRPU－0.2 VCC ≧ VIH
L
IHCC
PU IVV8.0
R
Ex.) VCC =3V IL=10µA VIH=0.7 VCC
from②
6
PU 1010 37.038.0
R
300 [kΩ]
○ Minimum value of RPU
The minimum value of RPU is determined by the following factors.
When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
OL
PU
OLCC I
RVV
OL
OLCC
PU IVV
R
②VOLMAX= should secure the input 'L' level (VIL) of microcontroller and EEP ROM
including recommended noise margin 0.1Vcc.
VOLMAX ≦ VIL－0.1 VCC
Ex.) VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from①3
PU 103 4.03
R
867[Ω]
And VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition ② is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive perform ance of output port of microcontroller.
Fig.52 I/O circuit diagram
Microcontroller
RPU A SDA terminal
IL IL
Bus line
capacity
CBUS
BR24TXX
Technical Note
15/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Cautions on microcontroller connection
○RS
In I2C BUS, it is recommended that SDA por t is of open drain in put/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs bet ween the pull up res istance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
○Maximum value of Rs
The maximum value of Rs is determin ed by the following relations.
①SDA rise time to be determi ned by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential ○
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
ILCCOL
SPU
OLCC VV1.0V
RR VV
PU
ILCC
OLCC
SR
VV1.1 VV
R
Ex)VCC=3V VIL=0.3VCC VOL=0.4V RPU=20kΩ
3
S1020
33.031.1 31.04.033.0
R
]k[67.1 Ω
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When ov er cur rent flo ws, noises in po wer source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
I
R
V
S
CC
I
V
RCC
S
EX) VCC=3V I=1mA
][300
1010 3
R3
S
Ω
RPU
Microcontroller
RS
EEPROM
Fig.53 I/O circuit diagram Fig.54 Input / output collision timing
A
CK
'L' output of EEPROM
'H' output of microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
SCL
SDA
Microcontroller EEPROM
'L'output
R
S
R
PU
'H' output
Over current I
Fig.56 I/O circuit diagram
Fig.55 I/O Circuit Diagram
RPU
Micro controller
RS
EEPROM
IOL
A
Bus line
capacity
CBUS
VOL
VCC
VIL
Technical Note
16/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)
○Input / output (SDA)
Fig.57 Input pin circuit diagram
Fig.58 Input / output pin circuit diagram
Technical Note
17/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SC L ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tOFF
tR
Vbot
0
VCC
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 c annot be observed. When SD A becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
b) In the case when the above condition 2 cannot be observed.
→After po wer source becomes stable, execute software reset(P12).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at lo w power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or belo w, i t
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor ( 0.1µF) bet ween IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
Recommended conditions of tR, tOFF,Vbot
tR tOFF Vbot
10ms or below 10ms or larger 0.3V or below
100msor below 10msor larger 0.2V or below
Fig.59 Rise waveform diagram
Fig.60 When SCL= 'H' and SDA= 'L' Fig.61 When SCL='L' and SDA='L'
tLOW
tSU:DAT
tDH
A
fter Vcc becomes stable
SCL
V
CC
SDA
tSU:DAT
A
fter Vcc becomes stable
Technical Note
18/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Notes for use
(1) Described numeric values and data are design representative values, and t he values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics an d fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as im pressed voltage and action temperature range a nd so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absol ute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it
that conditions exceedin g the absolute maximum ratings shoul d not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that
of GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and po wer source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a stron g electromagnetic field may cause malfu nctio n, therefore, evaluate design s ufficiently.
Technical Note
19/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
●Order part number
B R 2 4 T 1 2 8 F V T - W G E 2
Part No. BUS type
24：I2C
Operating
temperature/
Power source
Voltage
-40℃~+85℃
1.7V~5.5V
Capacity
01=1K 64=64K
02=2K 128=128K
04=4K 256=256K
08=8K 512=512K
16=16K 1M=1024K
32=32K
Package
Blank :DIP-T8
F :SOP8
FJ :SOP-J8
FV : SSOP-B8
FVT : TSSOP-B8
FVJ : TSSOP-B8J
FVM : MSOP8
NUX :VSON008X2030
Double
Cell
Halogen
Free
Packaging and forming specification
E2: Embossed tape and reel
(SOP8, SOP8-J8, SSOP-B8,
TSSOP-B8, TSSOP-B8J)
TR: Embossed tape and reel
(MSOP8, VSON008X2030)
None: T ube
(DIP-T8)
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
TubeContainer
Quantity
Direction of feed 2000pcs
Direction of products is fixed in a container tube
(Unit : mm)
DIP-T8
0°−15°
7.62
0.3±0.1
9.3±0.3
6.5±0.3
85
14
0.51Min.
3.4±0.3
3.2±0.2
2.54 0.5±0.1
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
(Unit : mm)
SOP8
0.9±0.15
0.3MIN
4
°
+
6
°
−
4
°
0.17 +0.1
-
0.05
0.595
6
43
8
2
5
1
7
5.0±0.2
6.2±0.3
4.4±0.2
(MAX 5.35 include BURR)
1.27
0.11
0.42±0.1
1.5±0.1
S
0.1 S
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
Direction of feed
Reel 1pin
(Unit : mm)
SOP-J8
4°+6°
−4°
0.2±0.1
0.45MIN
234
5678
1
4.9±0.2
0.545
3.9±0.2
6.0±0.3
(MAX 5.25 include BURR)
0.42±0.1
1.27
0.175
1.375±0.1
0.1 S
S
Technical Note
20/21
BR24T□□□□Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
Direction of feed
Reel ∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
3000pcs
E2
()
1pin
(Unit : mm)
TSSOP-B8
0.08 S
0.08
M
4 ± 4
234
8765
1
1.0±0.05
1PIN MARK
0.525
0.245+0.05
−0.04
0.65
0.145+0.05
−0.03
0.1±0.05
1.2MAX
3.0±0.1
4.4±0.1
6.4±0.2
0.5±0.15
1.0±0.2
(MAX 3.35 include BURR)
S
Direction of feed
Reel
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
2500pcs
E2
()
1pin
(Unit : mm)
TSSOP-B8J
0.08
M
0.08 S
S
4 ± 4
(MAX 3.35 include BURR)
578
1234
6
3.0±0.1
1PIN MARK
0.95±0.2
0.65
4.9±0.2
3.0±0.1
0.45±0.15
0.85±0.05
0.145
0.1±0.05
0.32
0.525
1.1MAX
+0.05
−0.03
+0.05
−0.04
Direction of feed
Reel
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
3000pcs
TR
()
1pin
(Unit : mm)
MSOP8
0.08 S
S
4.0±0.2
8
3
2.8±0.1
1
6
2.9±0.1
0.475
4
57
(MAX 3.25 include BURR)
2
1PIN MARK
0.9MAX
0.75±0.05
0.65
0.08±0.05
0.22 +0.05
−0.04
0.6±0.2
0.29±0.15
0.145 +0.05
−0.03
4°
+6°
−4°
Technical Note
21/21
BR24T□□□-W Series
www.rohm.com 2011.03 - Rev.A
© 2011 ROHM Co., Ltd. All rights reserved.
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
4000pcs
TR
()
Direction of feed
Reel 1pin
(Unit : mm)
VSON008X2030
5
1
8
4
1.4±0.1
0.25
1.5±0.1
0.5
0.3±0.1
0.25 +0.05
−0.04
C0.25
0.6MAX
(0.12)
0.02+0.03
−0.02 3.0±0.1
2.0±0.1
1PIN MARK
0.08 S
S
R1120
A
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
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Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
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shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
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The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
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