CY26404ZC - Cypress Semiconductor

PacketClock™

One-PLL General Purpose Clock Generator

CY26404

Cypress Semiconductor Corporation •3901 North First Street •San Jose, CA 95134 •408-943-2600

Document #: 38-07470 Rev. ** Revised December 9, 2002

Features Benefits

• Integrated phase-locked loop Internal PLL with up to 400-MHz internal operation

• Low-skew, low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs

• 3.3V operation with 2.5V output option Enables application compatibility

• 16-TSSOP Industry standard package saves on board space

Part Number Outputs Input Frequency Output Frequency Range

CY26404 6 20 MHz 2 x 50 MHz, 1 x 100 MHz

Output Pin Default Frequency Unit

CLK1 7 50 MHz

CLK2 8 50 MHz

CLK3 9 OFF

CLK4 12 OFF

CLK5 14 100 MHz

CLK6 15 OFF

Logic Block Diagram

XIN

XOUT

CLK1 50 MHz

OUTPUT

MULTIPLEXER

AND

DIVIDERS

PLL

OSC.

CLK3 off

VCO

VDDL AVSS

AVDD VSS

CLK2 50 MHz

VSSL VDD

16-pin TSSOP

CY26404

VSS

VSSL

SCL

CLK1

XIN XOUT

VDD

SDA

AVSS

CLK3

CLK2

CLK6

CLK5

AVDD

VDDL

CLK4

Pin Configurati on

SCL

SDA

SPI

Control

CLK4 off

CLK5 100 MHz

CLK6 o ff

CY26404

Document #: 38-07470 Rev. ** Page 2 of 11

Frequency Calculat ions and Register

Definitions Using the Serial Programming

Interface (SPI)

The CY26404 provides an industry-standard serial interface

for vol atile, in -system programming of uniq ue frequen cies an d

opti ons. Seri al prog rammi ng al lows for qui ck des ign ch anges

and pro duct enhanc ements, eliminates inventory of old de sign

parts, and simplifies manufacturing.

The SPI provides volatile programming, i.e., when the target

system is po wered dow n , the C Y26 404 revert s back to its de-

fault st ate. When the s ystem is pow ered back up, the S PI reg-

isters will need to be reconfigured again.

All programmable registers in the CY26404 are addressed

with eight bits and contain eight bits of data. The CY26404 is

a slave device with an address of 1101010 (6AH).

Tabl e 1 lists the SPI registers and their definitions. Specific

Reference Frequency

The REF can be a crystal or a driven frequency. For crystals,

the freq uency range must be between 8 MHz and 3 0 MHz. F or

a driven frequency, the frequency range must be between

1 MHz and 133 MHz.

Using a Crystal as the Reference Input

The input crystal oscillator of the CY26404 is an important

feature because of the flexibility it allows the user in selecting

a crystal as a REF source. The input oscillator has program-

mable gain, allowing for maximum compatibility with a

reference crystal, regardless of manufacturer , process, perfor-

mance and quali ty.

Programmable Crystal Input Oscillator Gain Settings

The Input crystal oscillator gain (XDRV) is controlled by two

bits in register 12H, and are set according to Table 2. The

parameters controlling the gain are the crystal frequency, the

internal crystal parasitic resistance (ESR, available from the

manufacturer), and the CapLoad setting during crystal

start-up.

Bits 3 and 4 of register 12H control the input crystal oscillator

gain setting. Bit 4 is the MSB of the setting, and bit 3 is the

LSB. The setting is programmed according to Table 2.

All other bits in the register are reserved and should be pro-

grammed low. See Table 3 for bit locations and values.

Using an External Clock as the Reference Input

The CY2 6404 c an al so ac cept an ext ernal c lock as re ferenc e,

with spe eds up to 133 M Hz. With an e xternal c lock , the XDR V

(register 12H) bits must be set according to Table 4.

Pin Description

Name Pin Number Description

XIN 1Reference Input

VDD 2Voltage Supply

AVDD 3Analog Voltage Supply

SDA 4Serial Data Input

AVSS 5Analog Ground

VSSL 6CLK1-CLK4 Ground

CLK 1 7Clock Output 1 = 50 MHz at VDDL Level

CLK 2 8Clock Output 2 = 50 MHz at VDDL Level

CLK 3 9Default is Off

SCL 10 Seri al Clock Inp ut

VDDL 11 CLK1-CLK4 Voltage Supply (2.5V or 3.3V)

CLK 4 12 Default is Off

VSS 13 Ground

CLK 5 14 Clock Output 5 = 100 MHz at VDD Level

CLK 6 15 Default is Off

XOUT[1] 16 Reference Output

Table 1. Summary Table – CY26404 Programmable Registers

RegisterDescription D7D6D5D4D3D2D1D0

09H CLKOE control 0 0 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1

0CH DIV1SRC mux and

DIV1N divider DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)

12H Input crystal oscillator

drive control 000XDRV(1)XDRV(0)000

13H Input load capacitor

control Cap-

Load(7) Cap-

Load(6) Cap-

Load(5) Cap-

Load(4) Cap-

Load(3) Cap-

Load(2) Cap-

Load(1) Cap-

Load(0)

40H Charge Pump and

PB counter 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)

42H PO counter , Q counter PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

CY26404

Document #: 38-07470 Rev. ** Page 3 of 11

44H Crosspoint switch

matrix control CLKSRC2

for CLK1 CLKSRC1

for CLK1 CLKSRC0

for CLK1 CLKSRC2

for CLK2 CLKSRC1

for CLK2 CLKSRC0

for CLK2 CLKSRC2

for CLK3 CLKSRC1

for CLK3

45H CLKSRC0

for CLK3 CLKSRC2

for CLK4 CLKSRC1

for CLK4 CLKSRC0

for CLK4 CLKSRC2

for CLK5 CLKSRC1

for CLK5 CLKSRC0

for CLK5 CLKSRC2

for CLK6

46H CLKSRC1

for CLK6 CLKSRC0

for CLK6 111111

47H DIV2SRC mux and

DIV2N divider DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)

Table 2. Programmable Crystal Input Oscillator Gain Settings

Calculated CapLoad Value 00H 20H 20H–30H 30H–40H

Crys tal ESR 30Ω60Ω30Ω60Ω30Ω60Ω

Crystal

Input

Frequency

8–15 MHz 000101100110

15–20 MHz 011001101010

20–25 MHz 011010101011

25–30 MHz 10 10 10 11 11 N/A

Table 3. Bit Locations and Values

AddressD7D6D5D4D3D2D1D0

12H 0 0 0 XDRV(1) XDRV(0) 0 0 0

Table 4. Programmable External Reference Input Oscillator Drive Settings

Reference Frequency 1–25 MHz 25–50 MHz 50–90 MH z 90–133 MHz

Drive Setting 00 01 10 11

Table 1. Summary Table – CY26404 Programmable Registers (continued)

RegisterDescription D7D6D5D4D3D2D1D0

CY26404

Document #: 38-07470 Rev. ** Page 4 of 11

Input Load Capacitors

Input load capacitors allow the user to set the load capacitance

of the CY26404 to match the load capacitance from a crystal.

The value of the load capacitors is determined by 8 bits in a

programmable register [13H]. Total load capacitance is deter-

mined by the formul a:

CapLoad = (CL – CBRD – CCHIP)/0.09375 pF

where:

•CL = specified load capacitance of your crystal.

•CBRD = the total board capacitance, due to external capac-

itors and board trace capacitance. In CyClocksRT™, this

value defaults to 2 pF.

•CCHIP = 6 pF.

•0.09375 pF = the st ep res olu tio n av ai lab le d ue t o th e 8-b it

In Cycloc ks RT the CY26404 is matc hed to the CY2 215 0, an d

only th e crys tal ca pacitance (CL) is spec ified . CCHIP is se t to 6

pF, and CBRD defaults to 2 pF. If your board capacitance is

higher or lower than 2 pF, the formula above can be used to

calcul ate a new CapLo ad va lue a nd progra mmed into regis ter

13H.

In CyC loc ksRT, en ter the cr ysta l capac itan ce (CL). The value

of CapLoad will be determined a utomatically a nd programmed

into the CY26404. Through the SDAT and SCLK pins, the

value can b e adj usted up or do wn if you r board cap ac itan ce i s

greater or less than 2 pF. For an external clock source,

CapLoad defaults to 0. See Table 5 for CapLoad bit locations

and values.

The input load capacitors are placed on the CY26404 die to

reduce external component cost. These capacitors are true

parallel-plate capacitors, designed to reduce the frequency

shift th at o ccurs when no n-li near load capacitance is affected

by load, bias, supply and temperature changes.

PLL Frequency, Q Counter [42H(6..0)]

The first counter is known as the Q counter. The Q counter

divides REF by its calculated value. Q is a 7-bit divider with a

maximum value of 127 and minimum value of 0. The primary

value of Q is determined by 7 bits in register 42H (6..0), but 2

is added to this register value to achieve the total Q, or Qtotal.

Qtotal is defined by the formula:

Qtotal = Q + 2

The min imum val ue of Qtotal is 2 . The ma ximum v alue o f Qtotal

is 129. Register 42H is defined in the table.

Stable operation of the CY26404 cannot be guaranteed if

REF/Qtotal falls below 250 kHz. Qtotal bit locations and values

are defined in Table 6.

PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7)

The next counter definition is the P (product) counter. The P

counter i s multipl ied with the (REF/Q total) value to achie ve the

VCO frequency. The product counter, defined as Ptotal, is

made up of two int ernal variable s, PB and PO. The formula for

calcul ati ng Ptotal is:

Ptotal = (2(PB + 4) + PO)

PB is a 10-bit variable, defined by registers 40H(1:0) and

41H(7:0). The 2 LSBs of register 40H are the two MSBs of

variable PB. Bits 4..2 of register 40H are used to de termine the

charge pum p settings (see Section 5). The 3 MSBs of reg ister

40H are preset and reserved and cannot be changed.

PO is a single-bit variable, defined in register 42H(7). This

allows for odd numbers in Ptotal.

The remain in g 7 bits of 42H are used to de fin e the Q cou nte r,

as shown in Table 6.

The minim um val ue of Ptotal is 8 . T he maxi mu m va lue of Ptotal

is 2055. To achieve the minimum value of Ptotal, PB and PO

should both be programmed to 0. To achieve the maximum

value of Ptotal, PB should be programmed to 1023, and PO

should be prog ram me d to 1.

Sta bl e op era t io n of th e C Y2 6 40 4 c a nn ot b e gu ar an t ee d i f the

value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below

100 MHz. Regis ters 40H, 41H and 42H a re defined in Table 7.

PLL Post Divider Options [OCH(7..0)], [47H(7..0)]

The output of the VCO is routed through two independent

muxes, then to two divider banks to determine the final clock

output frequency. The mux determines if the clock signal

feeding in to the divide r banks is the calculated VCO frequency

or REF. There are two select muxes (DIV1SRC and DIV2SRC)

and two divider banks (Divider Bank 1 and Divider Bank 2)

used to determine this clock signal. The clock signal passing

through DIV1SRC and DIV2SRC is referred to as DIV1CLK

and DIV2CLK, respectively.

The divider banks have 4 unique divider options available: /2,

/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-

dently programmed (DIV1N and DIV2N) for each of the 2

divider banks. The minimum value of DIVxN is 4. The

maxim um val ue of DIVxN is 127. A va lue of DIVxN be low 4 i s

not guaranteed to work properly.

DIV1SRC is a single bit variable, controlled by register OCH.

The remaining 7 bits of register OCH determine the value of

post divider DIV1N.

DIV2SRC is a single-bit variable, controlled by register 47H.

The remaining 7 bits of register 47H determine the value of

post divider DIV2N.

Charge Pump Settings [40H(2..0)]

The correc t pump sett ing is import ant for PLL st abilit y. Charge

pump se ttings ar e controlle d by bit s (4..2) of regis ter 40H, an d

are dependent on internal variable PB (see “PLL Frequency,

P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 9 summa-

rizes the proper charge pump settings, based on Ptotal.

See Table 10 for register 40H bit locations and values.

Table 5. Input Load Capacitor Register Bit Settings

AddressD7D6D5D4D3D2D1D0

13H CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)

CY26404

Document #: 38-07470 Rev. ** Page 5 of 11

Although using the above table will guarantee stability, it is

recommended to use the Print Preview function in

CyClocksRT to determine the correct charge pump settings for

optimal jitter performance.

PLL stability cannot be guaranteed for values below 16 and

above 1023. If values above 1023 are needed, use

CyClocksRT to determine the best charge pump setting.

Clock Output Settings: CLKSRC – Clock Output Cross-

point Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)]

CLKOE – Clock Output Enable Control [09H(5..0)]

Every clo ck out put can be de fine d to c om e from on e of s eve n

unique frequency sources. The CLKSRC(2..0) crosspoint

switch matrix defines which source is attached to each

indivi dual clock outp ut. CLKSRC(2..0) is set in Regist ers 44H,

45H, and 46H. The remainder of register 46H(5:0) must be

written with the va lues st ated in th e registe r tab le when wr iting

In addition, each clock output has individual CLKOE control,

set by register 09H(5..0).

When DIV1N is divisible by 4, then CLKSRC(0,1,0) is

guaranteed to be rising edge phase-aligned with

CLKSRC(0,0,1). When DIV1N is 6, then CLKSRC(0,1,1) is

guaranteed to be rising edge phase-aligned with

CLKSRC(0,0,1).

When DIV2N is divisible by 4, then CLKSRC(1,0,1) is

guaranteed to be rising edge phase-aligned with

CLKSRC(1,0,0). When DIV2N is divisible by 8, then

CLKSRC(1,1,0) is guara nteed to be rising edge p hase-aligned

with CLKSRC(1,0,0).

Each clock output has its own output enable, controlled by

CLKOE bit to 1. CLKOE settings are in Table 13.

The output swing of CLK1 through CLK4 is set by VDDL. The

output swing of CLK5 and CLK6 is set by VDD.

Table 6. Q Counter Register Def inition

Address D7 D6 D5 D4 D3 D2 D1 D0

42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)

42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

Table 7. P Counter Register Definition

Address D7 D6 D5 D4 D3 D2 D1 D0

40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0)

42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0)

Table 8. PLL Post Divi der Options

Address D7 D6 D5 D4 D3 D2 D1 D0

OCH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)

47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)

Table 9. Charge Pump Sett ings

Charge Pump Setting – Pump(2..0 ) Calcul ated Ptotal

000 16 – 44

001 45 – 479

010 480 – 639

011 640 – 799

100 800 – 1023

101, 110, 111 Do not use – device will be unstable

Table 10. Register 40H Change Pump Bit Settings

AddressD7D6D5D4D3D2D1D0

40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8)

CY26404

Document #: 38-07470 Rev. ** Page 6 of 11

Test, Reserved, and Blank Reg isters

Writing to any of the following registers will cause the part to

exhibit abnormal behavior, as follows.

[00H to 08H] – Reserved

[0AH to 0BH] – Reserved

[0DH to 11H] – Reserved

[14H to 3FH] – Reserved

[43H] – Reserved

[48H to FFH] – Reserved.

Programmable Interf ace Timing

The CY26404 utilizes a 2-wire serial-interface SDAT and

SCLK that operates up to 400 kbits/second in Read or Write

mode. The basic Write serial format is as follows.

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

data; ACK; 8-bit data in MA + 1 if desired; ACK; 8-bit data in

MA+2; AC K; etc. until STOP bit.Th e basic se rial format is illus-

trated in Figure 2.

Data Valid

Dat a is val id when the C lock is H IGH, and may onl y be trans i-

tioned when the clock is LOW, as illustrated in Figure 1.

Data Frame

Every new data frame is indicated by a start and stop

sequence, as illustrated in Figure 3.

Start Sequence – Start frame is indicated by SDAT going

LOW when SCLK is HIGH. Every time a Start signal is given,

the next 8-bit data must be the device address (7 bits) and a

R/W bit, followed by register add ress (8 bit s) and register da ta

(8 bits).

Stop Sequence – Stop frame is indicated by SDAT going

HIGH when SCLK is HIGH. A Stop frame frees the bus for

writing to another part on the same bus or writing to another

random register address.

Acknowle dge Pulse

During Write mode, the CY26404 will respond with an ACK

pulse after every 8 bits. This is accomplished by pulling the

SDAT line LOW during the N*9th clock cycle, as illu strat ed in

Figure 4. (N = the number of 8-bit segments transmitted.)

During Read mode, the ACK pulse after the data packet is sent

is generated by the master.

Table 11.

CLKSRC2 CLKSRC1 CLKSRC0 Definition and Notes

0 0 0 Reference inp ut.

0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are

4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8.

0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.

0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.

1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are

4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.

1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.

1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.

111Reserved – do not use.

Table 12.

AddressD7D6D5D4D3D2D1D0

44H CLKSRC2

for CLK1 CLKSRC1

for CLK1 CLKSRC0

for CLK1 CLKSRC2

for CLK2 CLKSRC1

for CLK2 CLKSRC0

for CLK2 CLKSRC2

for CLK3 CLKSRC1

for CLK3

45H CLKSRC0

for CLK3 CLKSRC2

for CLK4 CLKSRC1

for CLK4 CLKSRC0

for CLK4 CLKSRC2

for CLK5 CLKSRC1

for CLK5 CLKSRC0

for CLK5 CLKSRC2

for CLK6

46H CLKSRC1

for CLK6 CLKSRC0

for CLK6 111111

Table 13. CLKOE Bit Setting

Address D7 D6 D5 D4 D3 D2 D1 D0

09H 0 0 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1

CY26404

Document #: 38-07470 Rev. ** Page 7 of 11

Figure 1. Data Valid and Dat a Transition Periods

Figure 2. Data Frame Architecture

Figure 3. Start and Stop Frame

Figure 4. Frame Format (Device Address, R/W, Register Address, Register Data

SDAT

SCLK

Data valid Transition

to next bit

CLKLOW

CLKHIGH

VIH

VIL

tSU

tDH

SDAT Write

Start Signal

Device

Address

7-bit

R/W = 0

1-bit

8-bit

Address

Slave

1-bit

ACK Slave

1-bit

ACK

8-bit

Data

Stop Signal

Multiple

Contiguous

Registers

Slave

1-bit

ACK

8-bit

Data

(XXH) (XXH) (XXH+1)

Slave

1-bit

ACK

8-bit

Data

(XXH+2)

Slave

1-bit

ACK

8-bit

Data

(FFH)

Slave

1-bit

ACK

8-bit

Data

(00H)

Slave

1-bit

ACK Slave

1-bit

ACK

SDAT Read

Start Signal

Device

Address

7-bit

R/W = 0

1-bit

8-bit

Address

Slave

1-bit

ACK Slave

1-bit

ACK

7-Bit

Device

Stop Signal

Multiple

Contiguous

Registers

1-bit

R/W = 1

8-bit

Data

(XXH) Address(XXH)

Master

1-bit

ACK

8-bit

Data

(XXH+1)

Master

1-bit

ACK

8-bit

Data

(FFH)

Master

1-bit

ACK

8-bit

Data

(00H)

Master

1-bit

ACK Master

1-bit

ACK

SDAT

SCLK

START Transition

to next bit STOP

SDAT

SCLK

DA6 DA5DA0 R/W ACK RA7 RA6RA1 RA0 ACK STOP

START ACK D7 D6 D1 D0

+++

CY26404

Document #: 38-07470 Rev. ** Page 8 of 11

Absolute Maximum Conditions

Recommended Operating Conditions

DC Electrical Speci fications

Parameter Description Min. Max. Unit

fSCLK Frequency of SCLK 400 kHz

Start mode time from SDA LOW to SCL LOW 0.6 µs

CLKLOW SCLK LOW period 1.3 µs

CLKHIGH SCLK HIGH period 0.6 µs

tSU Data transition to SCLK HIGH 100 ns

tDH Data hold (SCLK LOW to data transition) 0 ns

Rise time of SCLK and SDAT 300 ns

Fall time of SCLK and SDAT 300 ns

Stop mode time from SCLK HIGH to SDAT HIGH 0.6 µs

Stop mode to Start mode 1.3 µs

Parameter Description Min. Max. Unit

VDD Supply Voltage –0.5 7.0 V

VDDL I/O Supply Voltage 7.0 V

TJJunction Temperature 125 °C

Digital Inputs AVSS – 0.3V AVDD + 0.3V V

Digital Outputs referred to VDD VSS – 0.3V VDD + 0.3V V

Digital Outputs referred to VDDL VSS – 0.3V VDDL +0.3V V

Electro-Static Discharge 2 kV

Parameter Description Min. Typ. Max. Unit

VDD Operating Voltage 3.135 3.3 3.465 V

VDDL Operating Voltage 2.375 2.5 3.465 V

TAA m bient Temperature 0 70 °C

CLOAD Max. Load Capacitance 15 pF

fREF Crystal or Driven Reference Frequency 20 MHz

Parameter[2] Name Description Min. Typ. Max. Unit

IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 mA

IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA

IOH Output High Current VOH = VDDL – 0.5, VDDL = 2.5V 8 16 mA

IOL Output Low Current VOL = 0.5, VDDL = 2.5V 8 16 mA

VIH Input High Voltage CMOS levels, 70% of VDD 0.7 VDD

VIL Input Low Voltage CMOS levels, 30% of VDD 0.3 VDD

CIN Input Cap a ci t an ce OE Pin 7 pF

IIZ Input Leakage Current OE Pin 5 µA

IVDD Supply Current AVDD/VDD Current 30 mA

IVDDL Supply Current VDDL Current (VDDL = 3.465V) 10 mA

IVDDL Supply Current VDDL Current (VDDL = 2.625V) 8 mA

Notes:

1. Float XOUT if XIN is externally driven.

2. Not 100% test ed.

CY26404

Document #: 38-07470 Rev. ** Page 9 of 11

AC Electrical Speci fications

Parameter[2] Name Description Min. Typ. Max. Unit

DC Duty Cycle is defined in Figure 1; t1/t2, 50% of

VDD 40 50 60 %

t3Risi ng Edge Slew Rate Output C loc k Rise Time, 20% – 80% of

VDD/VDDL = 3.3V 0.8 1.4 V/ns

t3Risi ng Edge Slew Rate Output C loc k Rise Time, 20% – 80% of

VDDL = 2.5V 0.6 1.2 V/ns

t4Falling Edge Slew

Rate Out put C lock Fall T im e, 80% – 20% of

VDD/VDDL = 3.3V 0.8 1.4 V/ns

t4Falling Edge Slew

Rate Out put C lock Fall T im e, 80% – 20% of

VDDL = 2.5V 0.6 1.2 V/ns

t5Skew Delay between related outputs at rising edge 200 ps

t9Clock Jitter Peak to Peak period jitter 150[3] ps

t10 PLL Lock Time 3ms

Note:

3. Applies only when device is in default mode. When programmed through the serial interface, the typical jitter is 250 ps.

0.1 µF

VDD

0.1 µF

AVDD

CLK out

CLOAD

GND

OUTPUTS

Test and Measurement Set-up

Figure 5. Duty Cycle Definition; DC = t2/t1

Figure 6. Rise and Fall Time Definitions

CLK 50% 50%

CLK

80%

20%

Ordering Information

Ordering Code Package Name Package Type Operating Range Operating Voltage

CY26404ZC Z16 16-Pin TSSOP Commercial 3.3V

CY26404ZCT Z16 16-Pin TSSOP - Tape & Reel Commercial 3.3V

CY26404

Document #: 38-07470 Rev. ** Page 10 of 11

of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

Package Drawing and Dimensions

PacketClock and CyClocksR t are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned

in this document may be the trademarks of their respective holders.

16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16

51-85091-**

CY26404

Document #: 38-07470 Rev. ** Page 11 of 11

Document History Page

Document Title: CY26404 PacketClock™ One-PLL General Purpose Clock Generator

Document Number: 38-07470

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 118470 12/10/02 CKN New Data Sheet