CY26404 PacketClockTM One-PLL General Purpose Clock Generator Features Benefits * Integrated phase-locked loop Internal PLL with up to 400-MHz internal operation * Low-skew, low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs * 3.3V operation with 2.5V output option Enables application compatibility * 16-TSSOP Industry standard package saves on board space Part Number CY26404 Outputs Input Frequency Output Frequency Range 6 20 MHz 2 x 50 MHz, 1 x 100 MHz Logic Block Diagram XIN VCO XOUT CLK2 50 MHz OUTPUT MULTIPLEXER AND DIVIDERS P PLL CLK3 off CLK4 off CLK5 100 MHz CLK6 off SCL SPI Control SDA VDDL CY26404 16-pin TSSOP CLK1 50 MHz Q OSC. Pin Configuration VSSL VDD AVDD AVSS 1 16 XOUT 2 15 AVDD 3 14 SDA 4 13 CLK6 CLK5 VSS AVSS 5 12 CLK4 VSSL 6 11 VDDL CLK1 7 10 CLK2 8 9 SCL CLK3 VSS Output Pin Default Frequency Unit CLK1 7 50 MHz CLK2 8 50 MHz CLK3 9 OFF CLK4 12 OFF CLK5 14 100 CLK6 15 OFF Cypress Semiconductor Corporation Document #: 38-07470 Rev. ** XIN VDD MHz * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised December 9, 2002 CY26404 Pin Description XIN 1 All programmable registers in the CY26404 are addressed with eight bits and contain eight bits of data. The CY26404 is Description a slave device with an address of 1101010 (6AH). Reference Table Input 1 lists the SPI registers and their definitions. Specific VDD 2 register definitions and their allowable values are listed below. Voltage Supply AVDD 3 Analog Voltage SupplyFrequency Reference SDA 4 AVSS 5 VSSL 6 CLK 1 7 CLK 2 8 CLK 3 9 SCL 10 VDDL 11 CLK 4 12 Serial DataThe Input REF can be a crystal or a driven frequency. For crystals, the Analog Groundfrequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between CLK1-CLK4 1 Ground MHz and 133 MHz. Clock Output 1 = 50 MHz at VDDL Level Using a Crystal as the Reference Input Clock Output 2 = 50 MHz at VDDL Level The input crystal oscillator of the CY26404 is an important Default is Off feature because of the flexibility it allows the user in selecting a Input crystal as a REF source. The input oscillator has programSerial Clock mable gain, allowing for maximum compatibility with a CLK1-CLK4 Voltage Supply or 3.3V) reference crystal, (2.5V regardless of manufacturer, process, performance and quality. Default is Off VSS 13 Ground CLK 5 14 CLK 6 15 XOUT[1] 16 Name Pin Number Frequency Calculations and Register Definitions Using the Serial Programming Interface (SPI) Programmable Crystal Input Oscillator Gain Settings Clock Output 5= 100 crystal MHz atoscillator VDD Level The Input gain (XDRV) is controlled by two bits in register 12H, and are set according to Table 2. The Default is Off parameters controlling the gain are the crystal frequency, the Reference internal Output crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 2. The CY26404 provides an industry-standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. All other bits in the register are reserved and should be programmed low. See Table 3 for bit locations and values. Using an External Clock as the Reference Input The CY26404 can also accept an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 4. The SPI provides volatile programming, i.e., when the target system is powered down, the CY26404 reverts back to its default state. When the system is powered back up, the SPI registers will need to be reconfigured again. Table 1. Summary Table - CY26404 Programmable Registers Register Description 09H CLKOE control 0CH DIV1SRC mux and DIV1N divider 12H Input crystal oscillator drive control 13H 40H 41H 42H D7 D6 D5 D4 D3 D2 D1 D0 0 0 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 0 0 0 XDRV(1) XDRV(0) 0 0 0 Input load capacitor control CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) Charge Pump and PB counter 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) PO counter, Q counter Document #: 38-07470 Rev. ** Page 2 of 11 CY26404 Table 1. Summary Table - CY26404 Programmable Registers (continued) Register 44H Description Crosspoint switch matrix control D7 D6 D5 D4 D3 D2 D1 D0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 for CLK1 for CLK1 for CLK1 for CLK2 for CLK2 for CLK2 for CLK3 for CLK3 45H CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for CLK3 for CLK4 for CLK4 for CLK4 for CLK5 for CLK5 for CLK5 for CLK6 46H CLKSRC1 CLKSRC0 for CLK6 for CLK6 47H DIV2SRC mux and DIV2N divider 1 1 1 1 1 1 DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Table 2. Programmable Crystal Input Oscillator Gain Settings Calculated CapLoad Value Crystal Input Frequency 00H 20H 20H-30H 30H-40H Crystal ESR 30 60 30 60 30 60 8-15 MHz 00 01 01 10 01 10 15-20 MHz 01 10 01 10 10 10 20-25 MHz 01 10 10 10 10 11 25-30 MHz 10 10 10 11 11 N/A Table 3. Bit Locations and Values Address D7 D6 D5 D4 D3 D2 D1 D0 12H 0 0 0 XDRV(1) XDRV(0) 0 0 0 Table 4. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting Document #: 38-07470 Rev. ** 1-25 MHz 25-50 MHz 50-90 MHz 90-133 MHz 00 01 10 11 Page 3 of 11 CY26404 made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Input Load Capacitors Input load capacitors allow the user to set the load capacitance of the CY26404 to match the load capacitance from a crystal. The value of the load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings (see Section 5). The 3 MSBs of register 40H are preset and reserved and cannot be changed. CapLoad = (CL - CBRD - CCHIP)/0.09375 pF where: * CL = specified load capacitance of your crystal. * CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRTTM, this value defaults to 2 pF. * CCHIP = 6 pF. * 0.09375 pF = the step resolution available due to the 8-bit register. In CyclocksRT the CY26404 is matched to the CY22150, and only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF, and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula above can be used to calculate a new CapLoad value and programmed into register 13H. PO is a single-bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining 7 bits of 42H are used to define the Q counter, as shown in Table 6. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY26404 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. Registers 40H, 41H and 42H are defined in Table 7. PLL Post Divider Options [OCH(7..0)], [47H(7..0)] In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad will be determined automatically and programmed into the CY26404. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 5 for CapLoad bit locations and values. The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The input load capacitors are placed on the CY26404 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes. The divider banks have 4 unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the 2 divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. PLL Frequency, Q Counter [42H(6..0)] The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7-bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: DIV1SRC is a single bit variable, controlled by register OCH. The remaining 7 bits of register OCH determine the value of post divider DIV1N. DIV2SRC is a single-bit variable, controlled by register 47H. The remaining 7 bits of register 47H determine the value of post divider DIV2N. Qtotal = Q + 2 The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. Register OCH and 47H are defined in Table 8. Stable operation of the CY26404 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 6. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see "PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]"). Table 9 summarizes the proper charge pump settings, based on Ptotal. PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7) The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is See Table 10 for register 40H bit locations and values. Table 5. Input Load Capacitor Register Bit Settings Address 13H D7 D6 D5 D4 D3 D2 D1 D0 CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) Document #: 38-07470 Rev. ** Page 4 of 11 CY26404 Table 6. Q Counter Register Definition Address D7 D6 D5 D4 D3 D2 D1 D0 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) 41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) Table 7. P Counter Register Definition Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) 41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) Table 8. PLL Post Divider Options Address D7 D6 D5 D4 D3 D2 D1 D0 OCH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Table 9. Charge Pump Settings Charge Pump Setting - Pump(2..0) Calculated Ptotal 000 16 - 44 001 45 - 479 010 480 - 639 011 640 - 799 100 800 - 1023 101, 110, 111 Do not use - device will be unstable Table 10. Register 40H Change Pump Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) Although using the above table will guarantee stability, it is recommended to use the Print Preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. Clock Output Settings: CLKSRC - Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] CLKOE - Clock Output Enable Control [09H(5..0)] Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6). Document #: 38-07470 Rev. ** In addition, each clock output has individual CLKOE control, set by register 09H(5..0). When DIV1N is divisible by guaranteed to be rising CLKSRC(0,0,1). When DIV1N guaranteed to be rising CLKSRC(0,0,1). 4, then CLKSRC(0,1,0) is edge phase-aligned with is 6, then CLKSRC(0,1,1) is edge phase-aligned with When DIV2N is divisible by 4, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by 8, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13. The output swing of CLK1 through CLK4 is set by VDDL. The output swing of CLK5 and CLK6 is set by VDD. Page 5 of 11 CY26404 Test, Reserved, and Blank Registers [0DH to 11H] - Reserved [14H to 3FH] - Reserved [43H] - Reserved [48H to FFH] - Reserved. Writing to any of the following registers will cause the part to exhibit abnormal behavior, as follows. [00H to 08H] - Reserved [0AH to 0BH] - Reserved Table 11. CLKSRC2 CLKSRC1 CLKSRC0 0 0 0 Reference input. Definition and Notes 0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. 0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. 0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. 1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. 1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. 1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. 1 1 1 Reserved - do not use. Table 12. Address D7 D6 D5 D4 D3 D2 D1 D0 44H CLKSRC2 for CLK1 CLKSRC1 for CLK1 CLKSRC0 for CLK1 CLKSRC2 for CLK2 CLKSRC1 for CLK2 CLKSRC0 for CLK2 CLKSRC2 for CLK3 CLKSRC1 for CLK3 45H CLKSRC0 for CLK3 CLKSRC2 for CLK4 CLKSRC1 for CLK4 CLKSRC0 for CLK4 CLKSRC2 for CLK5 CLKSRC1 for CLK5 CLKSRC0 for CLK5 CLKSRC2 for CLK6 46H CLKSRC1 for CLK6 CLKSRC0 for CLK6 1 1 1 1 1 1 Table 13. CLKOE Bit Setting Address D7 D6 D5 D4 D3 D2 D1 D0 09H 0 0 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 Programmable Interface Timing The CY26404 utilizes a 2-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in Read or Write mode. The basic Write serial format is as follows. Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit data; ACK; 8-bit data in MA + 1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until STOP bit.The basic serial format is illustrated in Figure 2. Data Valid Stop Sequence - Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY26404 will respond with an ACK pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 4. (N = the number of 8-bit segments transmitted.) During Read mode, the ACK pulse after the data packet is sent is generated by the master. Data is valid when the Clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 1. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3. Start Sequence - Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit, followed by register address (8 bits) and register data (8 bits). Document #: 38-07470 Rev. ** Page 6 of 11 CY26404 Data valid Transition to next bit SDAT tDH CLKHIGH tSU VIH SCLK CLKLOW VIL Figure 1. Data Valid and Data Transition Periods 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK ACK ACK R/W = 0 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) SDAT Write Multiple Contiguous Registers 1-bit Slave ACK 1-bit Slave ACK 8-bit Register Data (FFH) 1-bit Slave ACK 1-bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal 1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master ACK ACK ACK R/W = 1 R/W = 0 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1) SDAT Read Multiple Contiguous Registers 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (FFH) 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (00H) Stop Signal Start Signal Figure 2. Data Frame Architecture SDAT Transition to next bit START SCLK STOP Figure 3. Start and Stop Frame SDAT + START DA6 SCLK DA5DA0 + + R/W ACK RA7 RA6RA1 + + RA0 ACK D7 D6 D1 D0 ACK STOP + Figure 4. Frame Format (Device Address, R/W, Register Address, Register Data Document #: 38-07470 Rev. ** Page 7 of 11 CY26404 Parameter fSCLK Description Min. Frequency of SCLK Max. Unit 400 kHz Start mode time from SDA LOW to SCL LOW 0.6 s CLKLOW SCLK LOW period 1.3 s CLKHIGH SCLK HIGH period 0.6 s tSU Data transition to SCLK HIGH 100 ns tDH Data hold (SCLK LOW to data transition) 0 ns Rise time of SCLK and SDAT 300 ns Fall time of SCLK and SDAT 300 ns Stop mode time from SCLK HIGH to SDAT HIGH 0.6 Stop mode to Start mode 1.3 s s Absolute Maximum Conditions Parameter Description VDD Supply Voltage VDDL I/O Supply Voltage TJ Junction Temperature Min. Max. -0.5 Unit 7.0 V 7.0 V 125 C AVDD + 0.3V V Digital Inputs AVSS - 0.3V Digital Outputs referred to VDD VSS - 0.3V VDD + 0.3V V Digital Outputs referred to VDDL VSS - 0.3V VDDL +0.3V V Electro-Static Discharge 2 kV Recommended Operating Conditions Min. Typ. Max. Unit VDD Parameter Operating Voltage Description 3.135 3.3 3.465 V VDDL Operating Voltage 2.375 2.5 3.465 V TA Ambient Temperature 70 C CLOAD Max. Load Capacitance fREF Crystal or Driven Reference Frequency 0 15 pF 20 MHz DC Electrical Specifications Parameter[2] Min. Typ. IOH Output High Current Name VOH = VDD - 0.5, VDD/VDDL = 3.3V Description 12 24 IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA IOH Output High Current VOH = VDDL - 0.5, VDDL = 2.5V 8 16 mA 8 16 IOL Output Low Current VOL = 0.5, VDDL = 2.5V VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD CIN Input Capacitance OE Pin Max. Unit mA mA 0.7 VDD 0.3 VDD 7 pF mA A IIZ Input Leakage Current OE Pin IVDD Supply Current AVDD/VDD Current 5 30 IVDDL Supply Current VDDL Current (VDDL = 3.465V) 10 mA IVDDL Supply Current VDDL Current (VDDL = 2.625V) 8 mA Notes: 1. Float XOUT if XIN is externally driven. 2. Not 100% tested. Document #: 38-07470 Rev. ** Page 8 of 11 CY26404 AC Electrical Specifications Parameter[2] Name DC Description Min. Typ. Max. Unit Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 40 50 60 % t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDDL = 2.5V 0.6 1.2 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDDL = 2.5V 0.6 1.2 V/ns t5 Skew Delay between related outputs at rising edge t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time 200 ps 150[3] ps 3 ms Note: 3. Applies only when device is in default mode. When programmed through the serial interface, the typical jitter is 250 ps. Test and Measurement Set-up VDD CLK out 0.1 F CLOAD OUTPUTS AVDD 0.1 F GND t1 t2 CLK 50% 50% Figure 5. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 6. Rise and Fall Time Definitions Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26404ZC Z16 16-Pin TSSOP Commercial 3.3V CY26404ZCT Z16 16-Pin TSSOP - Tape & Reel Commercial 3.3V Document #: 38-07470 Rev. ** Page 9 of 11 CY26404 Package Drawing and Dimensions 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** PacketClock and CyClocksRt are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07470 Rev. ** Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26404 Document History Page Document Title: CY26404 PacketClockTM One-PLL General Purpose Clock Generator Document Number: 38-07470 REV. ECN NO. Issue Date Orig. of Change ** 118470 12/10/02 CKN Document #: 38-07470 Rev. ** Description of Change New Data Sheet Page 11 of 11