NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Based on DDR3-1066/1333 64Mx16 (1GB) / 128Mx8 (2GB) SDRAM A-Die Features *Performance: Speed Sort PC3-8500 PC3-10600 -BE -CG Unit DIMM CAS Latency 7 9 fck - Clock Freqency 533 667 tck - Clock Cycle 1.875 1.5 ns fDQ - DQ Burst Freqency 1066 1333 Mbps MHz * 204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 1GB: 128Mx64 Unbuffered DDR3 SO-DIMM based on 64Mx16 DDR3 SDRAM A-Die devices. * 2GB: 256Mx64 Unbuffered DDR3 SO-DIMM based on 128Mx8 DDR3 SDRAM A-Die devices. * Intended for 533MHz/667MHz applications * Inputs and outputs are SSTL-15 compatible * VDD = VDDQ = 1.5V 0.075V * SDRAMs have 8 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 6,7,8,9 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write * Two different termination values (Rtt_Nom & Rtt_WR) * 13/10/2 (row/column/rank) Addressing for 1GB * 14/10/2 (row/column/rank) Addressing for 2GB * Extended operating temperature rage * Auto Self-Refresh option * Serial Presence Detect * Gold contacts * 1GB: SDRAMs are in 96-ball BGA Package * 2GB: SDRAMs are in 78-ball BGA Package * RoHS compliance + Halogen Free Description NT1GC64BH8A1PS-BE and NT2GC64B8HA1NS-BE are unbuffered 204-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 (1GB) and 256Mx64 (2GB) high-speed memory array. Modules use eight 64Mx16 (1GB) 96-ball BGA packaged devices and sixteen 128Mx8 (2GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR3 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of 1066Mbps/1333Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A12 (1GB)/A0-A13 (2GB) and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.3 06/2009 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Ordering Information Part Number Speed Organization NT1GC64BH8A1PS-BE DDR3-1066 PC3-8500 533MHz (1.875ns @ CL = 7) NT1GC64BH8A1PS-CG DDR3-1333 PC3-10600 NT2GC64B8HA1NS-BE DDR3-1066 PC3-8500 533MHz (1.875ns @ CL = 7) NT2GC64B8HA1NS-CG DDR3-1333 PC3-10600 Power Leads 1.5V Gold Note 128Mx64 667MHz (1.5ns @ CL = 9) 256Mx64 667MHz (1.5ns @ CL = 9) Pin Description Pin Name Description Pin Name Description CK0, CK1 Clock Inputs, positive line DQ0-DQ63 , Clock Inputs, negative line DQS0-DQS7 Data strobes Clock Enable - Data strobes complement CKE0, CKE1 Data input/output Row Address Strobe Column Address Strobe Temperature event pin Write Enable Reset pin , Chip Selects VREFDQ , VREFCA A0-A9, A11, A13 DM0-DM7 Address Inputs VDDSPD Data Masks Input/Output Reference SPD and Temp sensor power A10/AP Address Input/Auto-Precharge A12/ Address Input/Burst Chop SA0, SA1 Vtt Serial Presence Detect Address Inputs Termination voltage BA0-BA2 SDRAM Bank Address Inputs VSS Ground ODT0, ODT1 Active termination control lines VDD Core and I/O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input/output Note: A13 is for 2GB modules only. REV 1.3 06/2009 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM DDR3 SDRAM Pin Assignment Pin Front Pin Back Pin Front Pin Back Pin Front Pin 1 VREFDQ 3 VSS 2 VSS 53 DQ19 4 DQ4 55 VSS 5 DQ0 6 DQ5 57 7 DQ1 9 VSS 8 VSS 10 11 DM0 12 13 VSS 15 DQ2 17 19 Back Pin Front Pin 54 VSS 56 DQ28 105 VDD 107 A10/AP 106 VDD 108 BA1 DQ24 58 DQ29 109 BA0 110 59 DQ25 60 61 VSS 62 VSS 111 VDD 113 DQS0 63 DM3 64 DQS3 115 14 VSS 65 VSS 16 DQ6 67 DQ26 66 VSS 117 VDD 68 DQ30 119 A13/NC DQ3 18 DQ7 69 VSS 20 VSS 71 DQ27 70 DQ31 121 VSS 72 VSS 123 VDD 21 DQ8 22 DQ12 73 CKE0 74 CKE1 125 23 DQ9 24 25 VSS 26 DQ13 75 VDD 76 VDD VSS 77 NC 78 NC 27 28 DM1 79 BA2 80 29 31 DQS1 30 81 VDD VSS 32 VSS 83 A12/ 33 DQ10 34 DQ14 85 A9 35 DQ11 36 DQ15 87 VDD 37 VSS 38 VSS 89 39 DQ16 40 DQ20 41 DQ17 42 DQ21 43 VSS 44 45 47 DQS2 49 51 155 VSS 156 VSS 157 DQ42 158 DQ46 159 DQ43 160 DQ47 112 VDD 161 VSS 162 VSS 114 163 DQ48 164 DQ52 116 ODT0 165 DQ49 166 DQ53 118 VDD 167 VSS 168 VSS 120 ODT1 169 170 DM6 122 NC 171 DQS6 172 VSS 124 VDD 173 VSS 174 DQ54 NC 126 VREFCA 175 DQ50 176 DQ55 127 VSS 128 VSS 177 DQ51 178 VSS 129 DQ32 130 DQ36 179 VSS 180 DQ60 NC 131 DQ33 132 DQ37 181 DQ56 182 DQ61 82 VDD 133 VSS 134 VSS 183 DQ57 184 VSS 84 A11 135 136 DM4 185 VSS 186 86 A7 137 DQS4 138 VSS 187 DM7 188 DQS7 88 VDD 139 VSS 140 DQ38 189 VSS 190 VSS A8 90 A6 141 DQ34 142 DQ39 191 DQ58 192 DQ62 91 A5 92 A4 143 DQ35 144 VSS 193 DQ59 194 DQ63 93 VDD 94 VDD 145 VSS 146 DQ44 195 VSS 196 VSS VSS 95 A3 96 A2 147 DQ40 148 DQ45 197 SA0 198 46 DM2 97 A1 98 A0 149 DQ41 150 VSS 199 VDDSPD 200 SDA 48 VSS 99 VDD 100 VDD 151 VSS 152 201 SA1 202 SCL VSS 50 DQ22 101 CK0 102 CK1 153 DM5 154 DQS5 Vtt 204 Vtt DQ18 52 DQ23 103 104 203 Back Note: A13 is for 2GB modules only. REV 1.3 06/2009 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 , Input Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE0, CKE1 Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. , Input Active Low Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue, Rank 0 is selected by ; Rank 1 is selected by , , Input Active Low When sampled at the positive rising edge of CK and falling edge of , signals , , define the operation to be executed by the SDRAM. ODT0, ODT1 Input Active High Asserts on-die termination for DQ, DM, DQS, and signals if enabled via the DDR3 SDRAM mode register. DM0 - DM7 Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window. signals are complements, and timing is relative to the cross point of respective DQS and . If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately. DQS0 - DQS7 - I/O Cross point BA0, BA1, BA2 Input - Selects which DDR3 SDRAM internal bank of four or eight is activated. Input - During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A0 - A9 A10/AP A11 A12/ A13 DQ0 - DQ63 Input - Data Input/Output pins. VDD, VDDSPD, VSS Supply - Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. VREFDQ, VREFCA Supply - Reference voltage for SSTL15 inputs SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL Input - This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA0 - SA2 Input - Address pins used to select the Serial Presence Detect and Temp sensor base address. Output - The pin is reserved for use to flag critical module temperature. Input - This signal resets the DDR3 SDRAM REV 1.3 06/2009 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM 240ohm +/-1% ZQ CK CKE ODT A[0:13]/BA[0:2] D1 LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] DQS6 DM6 DQ[48:55] DQS7 DM7 DQ[56:63] LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] 240ohm +/-1% ZQ D2 CK CKE ODT A[0:13]/BA[0:2] DQS4 DM4 DQ[32:39] DQS5 DM5 DQ[40:47] 240ohm +/-1% ZQ CK CKE ODT A[0:13]/BA[0:2] D3 Vtt 06/2009 CK1 CKE1 ODT1 D4 LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] 240ohm +/-1% ZQ SCL D5 SCL A0 A1 A2 SA0 SA1 LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 240ohm +/-1% ZQ D6 CK1 LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] SPD SDA WP Vtt SPD / TS D0-D7 D0-D7 D0-D7 D0-D7, SPD, Temp sensor D0-D3 D0-D3 D4-D7 D4-D7 Temp Sensor D0-D7 240ohm +/-1% ZQ Notes : D7 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and relationships are maintained as shown. Vtt Vtt VDD REV 1.3 240ohm +/-1% ZQ CK CKE ODT A[0:13]/BA[0:2] LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] D0 LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] CK CKE ODT A[0:13]/BA[0:2] DQS2 DM2 DQ[16:23] DQS3 DM3 DQ[24:31] 240ohm +/-1% ZQ CK CKE ODT A[0:13]/BA[0:2] LDQS L LDM DQ[0:7] UDQS UDM DQ[8:15] CK CKE ODT A[0:13]/BA[0:2] DQS0 DM0 DQ[0:7] DQS1 DM1 DQ[8:15] CK CKE ODT A[0:13]/BA[0:2] CK0 CKE0 ODT0 A[0:13]/BA[0:2] Functional Block Diagram [1GB - 2 Ranks, 64Mx16 DDR3 SDRAMs] VDD 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM D0 240ohm +/-1% DQS DM DQ[0:7] ZQ D2 SCL SA0 SA1 SCL A0 A1 A2 SPD D14 240ohm +/-1% DQS DM DQ[0:7] D8 ZQ D15 240ohm +/-1% 240ohm +/-1% DQS DM DQ[0:7] ZQ D10 ZQ D13 Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK1 SDA WP CKE0 CKE1 ODT0 ODT1 D12 DQS4 DM4 DQ[32:39] CK CKE ODT A[0:13]/BA[0:2] CK CKE ODT A[0:13]/BA[0:2] 240ohm +/-1% ZQ 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and relationships are maintained as shown. 06/2009 ZQ 240ohm +/-1% ZQ DQS DM DQ[0:7] 240ohm +/-1% ZQ D6 DQS6 DM6 DQ[48:55] CK CKE ODT A[0:13]/BA[0:2] CK0 CKE0 ODT0 D9 Notes : REV 1.3 240ohm +/-1% DQS DM DQ[0:7] CK CKE ODT A[0:13]/BA[0:2] DQS DM DQ[0:7] CK CKE ODT A[0:13]/BA[0:2] DQS2 DM2 DQ[16:23] 240ohm +/-1% ZQ CK CKE ODT A[0:13]/BA[0:2] DQS DM DQ[0:7] ZQ D4 DQS DM DQ[0:7] DQS DM DQ[0:7] 240ohm +/-1% ZQ D7 DQS7 DM7 DQ[56:63] CK CKE ODT A[0:13]/BA[0:2] 240ohm +/-1% DQS DM DQ[0:7] CK CKE ODT A[0:13]/BA[0:2] DQS0 DM0 DQ[0:7] ZQ Vtt DQS DM DQ[0:7] 240ohm +/-1% ZQ D5 DQS5 DM5 DQ[40:47] CK CKE ODT A[0:13]/BA[0:2] D1 D3 CK CKE ODT A[0:13]/BA[0:2] DQS DM DQ[0:7] ZQ 240ohm +/-1% DQS DM DQ[0:7] ZQ CK CKE ODT A[0:13]/BA[0:2] 240ohm +/-1% DQS DM DQ[0:7] CK CKE ODT A[0:13]/BA[0:2] DQS1 DM1 DQ[8:15] 240ohm +/-1% Vtt CK CKE ODT A[0:13]/BA[0:2] D11 Vtt CK CKE ODT A[0:13]/BA[0:2] DQS DM DQ[0:7] ZQ Cterm CK CKE ODT A[0:13]/BA[0:2] 240ohm +/-1% DQS DM DQ[0:7] CK CKE ODT A[0:13]/BA[0:2] DQS3 DM3 DQ[24:31] VDD VDD Cterm CK1 CKE1 ODT1 A[0:13]/BA[0:2] Functional Block Diagram [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] Vtt SPD / TS D0-D15 D0-D15 D0-D15 D0-D15, SPD, Temp sensor D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 Temp Sensor D0-D15 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Serial Presence Detect (Part 1 of 2) [1GB - 2 Ranks, 64Mx16 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Reserved 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width 9 Fine timebase dividend/divisor (in ps) 10 -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B SO-DIMM SO-DIMM 03 03 8 banks, 1Gb 8 banks, 1Gb 02 02 13 rows, 10 columns 13 rows, 10 columns 09 09 1.5 V 1.5 V 00 00 2 ranks, 16 bits 2 ranks, 16 bits 0A 0A Non ECC, 64bits Non ECC, 64bits 03 03 2.5ps 2.5ps 52 52 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 10ns 7.5ns 50 3C 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 22 Minimum Active-to-Precharge delay (tRASmin) 23 Minimum Active-to-Active/Refresh delay (tRCmin) 24 1,1 1,1 11 11 37.5ns 36ns 2C 20 50.625ns 49.125ns 95 89 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 01 29 Minimum four active window delay (tFAWmin) MSB 50ns 45ns 90 68 83 83 8D 8D 30 SDRAM device output drivers suported 31 SDRAM device thermal and refresh options 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, Extended Temperature Extended Temperature Range, Range, ASR, ASR, ODTS, ODTS, PASR, PASR, Non Thermal Sensor Support Non Thermal Sensor Support 00 00 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, 11 11 62 Raw Card ID reference Raw Card A Raw Card A 00 00 63 DRAM address mapping edge connector Undefined Undefined 00 00 64-116 Reserved Undefined Undefined -- -- 117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B 119-121 Module manufacturer Information 126-127 CRC REV 1.3 06/2009 Undefined Undefined -- -- Calculated Value Calculated Value 5309 2DD0 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Serial Presence Detect (Part 2 of 2) [1GB - 2 Ranks, 64Mx16 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B 148-149 DRAM device manufacturer ID 150-175 Manufacturer reserved Undefined Undefined -- -- 176-255 Customer reserved Undefined Undefined -- -- Note1: NT1GC64BH8A1PS-BE -> 4E543147433634424838413150532D424520 NT1GC64BH8A1PS-CG -> 4E543147433634424838413150532D434720 REV 1.3 06/2009 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Serial Presence Detect (Part 1 of 2) [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Reserved 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width 9 Fine timebase dividend/divisor (in ps) 10 -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, 92 92 Revision 1.0 Revision 1.0 10 10 DDR3 SDRAM DDR3 SDRAM 0B 0B SO-DIMM SO-DIMM 03 03 8 banks, 1Gb 8 banks, 1Gb 02 02 14 rows, 10 columns 14 rows, 10 columns 11 11 1.5 V 1.5 V 00 00 2 ranks, 8 bits 2 ranks, 8 bits 09 09 Non ECC, 64bits Non ECC, 64bits 03 03 2.5ps 2.5ps 52 52 Medium timebase dividend 1ns 1ns 01 01 11 Medium timebase divisor 8ns 8ns 08 08 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns 0F 0C 13 Reserved Undefined Undefined 00 00 14 CAS latencies supported 6,7,8 6,7,8,9 1C 3C 15 CAS latencies supported Undefined Undefined 00 00 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns 69 69 17 Minimum write recovery time (tWRmin) 15ns 15ns 78 78 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns 69 69 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns 3C 30 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns 69 69 21 Upper nibble for tRAS and tRC 22 Minimum Active-to-Precharge delay (tRASmin) 23 Minimum Active-to-Active/Refresh delay (tRCmin) 24 1,1 1,1 11 11 37.5ns 36ns 2C 20 50.625ns 49.125ns 95 89 Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) 70 70 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns 03 03 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns 3C 3C 27 Minimum internal Read-to-Precharge command delay (tRTPmin) 7.5ns 7.5ns 3C 3C 28 Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) 01 00 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns 2C F0 30 SDRAM device output drivers suported 83 83 31 SDRAM device thermal and refresh options 8D 8D 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, Extended Temperature Extended Temperature Range, Range, ASR, ASR, ODTS, ODTS, PASR, PASR, Non Thermal Sensor Support Non Thermal Sensor Support 00 00 Standard Monolithic Device Standard Monolithic Device 00 00 Undefined Undefined -- -- Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm 0F 0F 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, 11 11 62 Raw Card ID reference Raw Card F Raw Card F 05 05 63 DRAM address mapping edge connector Undefined Undefined 00 00 64-116 Reserved Undefined Undefined -- -- 117-118 Module manufacture ID Nanya Technology Nanya Technology 830B 830B 119-121 Module manufacturer Information 126-127 CRC REV 1.3 06/2009 Undefined Undefined -- -- Calculated Value Calculated Value 84E6 C64F 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Serial Presence Detect (Part 2 of 2) [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description -BE -CG -BE -CG 128-145 Module part number ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined 00 00 147 Module PCB revision Undefined Undefined 00 00 Nanya Technology Nanya Technology 830B 830B 148-149 DRAM device manufacturer ID 150-175 Manufacturer reserved Undefined Undefined -- -- 176-255 Customer reserved Undefined Undefined -- -- Note1: NT2GC64B8HA1NS-BE -> 4E54324743363442384841314E532D424520 NT2GC64B8HA1NS-CG -> 4E54324743363442384841314E532D434720 REV 1.3 06/2009 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Environmental Requirements Symbol Parameter TOPR Operating Temperature (ambient) TSTG Storage Temperature Rating Units 0 to 65 C -50 to 100 C Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Rating Units Note Voltage on VDD pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on VDDQ pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on I/O pins relative to Vss -0.4 V ~ 1.975 V V 1 -55 to +100 C 1, 2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater Operating temperature Conditions Symbol TOPER Parameter Rating Units Note Normal Operating Temperature Range 0 to 85 C 1, 2 Extended Temperature Range 85 to 95 C 1, 3 Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range. DC Electrical Characteristics and Operating Conditions Symbol VDD VDDQ Min Typ Max Units Notes Supply Voltage Parameter 1.425 1.5 1.575 V 1,2 Output Supply Voltage 1.425 1.5 1.575 V 1,2 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. REV 1.3 06/2009 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter DDR3-1066 (-BE) Min. DDR3-1333 (-CG) Max. Min. Max. Units Note 1 VIH.CA(DC) DC Input Logic High Vref + 0.100 VDD Vref + 0.100 VDD V VIL.CA(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.CA(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.175 Note 2 V 1, 2 VIL.CA(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.175 V 1, 2 VIH.CA(AC150) AC Input Logic High - - Vref + 0.15 Note 2 V 1, 2 VIL.CA(AC150) AC Input Logic Low - - Note 2 Vref - 0.15 V 1, 2 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefCA(DC) Reference Voltage for ADD, CMD Inputs Note: 1. For input only pins except RESET#. Vref = VrefCA(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter DDR3-1066 (-BE) Min. DDR3-1333 (-CG) Max. Min. Max. Units Note VIH.DQ(DC) DC Input Logic High Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.DQ(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.DQ(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.15 Note 2 V 1, 2, 5 VIL.DQ(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.15 V 1, 2, 5 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM Inputs Note: 1. For input only pins except RESET#. Vref = VrefDQ(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. 5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV (peak to peak). REV 1.3 06/2009 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [1GB - 2 Rank, 64Mx16 DDR3 SDRAMs] Symbol Parameter/Condition PC3-8500 PC3-10600 (-BE) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current 480 546 mA IDD1 Operating One Bank Active-Read-Precharge Current 546 634 mA IDD2P0 Precharge Power-Down Current Slow Exit 123 123 mA IDD2P1 Precharge Power-Down Current Fast Exit 264 290 mA IDD2Q Precharge Quiet Standby Current 484 528 mA IDD2N Precharge Standby Current 396 440 mA IDD3P Active Power-Down Current 290 308 mA IDD3N Active Standby Current 484 572 mA IDD4R Operating Burst Read Current 1074 1294 mA IDD4W Operating Burst Write Current 942 1074 mA IDD5B Burst Refresh Current 854 1052 mA IDD6 Self Refresh Current: Normal Temperature Range 106 106 mA IDD7 Operating Bank Interleave Read Current 1206 1426 mA PC3-8500 PC3-10600 (-BE) (-CG) Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] Symbol Unit IDD0 Operating One Bank Active-Precharge Current 783 871 mA IDD1 Operating One Bank Active-Read-Precharge Current 915 1003 mA IDD2P0 Precharge Power-Down Current Slow Exit 246 246 mA IDD2P1 Precharge Power-Down Current Fast Exit 528 581 mA IDD2Q Precharge Quiet Standby Current 968 1056 mA IDD2N Precharge Standby Current 792 880 mA IDD3P Active Power-Down Current 581 616 mA IDD3N Active Standby Current 968 1144 mA IDD4R Operating Burst Read Current 1531 1883 mA IDD4W Operating Burst Write Current 1311 1619 mA IDD5B Burst Refresh Current 1707 2103 mA 211 211 mA 2059 2411 mA IDD6 Self Refresh Current: Normal Temperature Range IDD7 Operating Bank Interleave Read Current REV 1.3 06/2009 Parameter/Condition 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Standard Speed Bins Speed Bin DDR3-1066 (-BE) DDR3-1333 (-CG) 7-7-7 9-9-9 Unit CL - tRCD - tRP Parameter Internal read Symbol Min Max Min Max tAA 13.125 20 13.5 20 ns tRCD 13.125 - 13.5 - ns tRP 13.125 - 13.5 - ns tRC 50.625 - 49.5 - ns tRAS 37.5 9*tREFI 36 9*tREFI ns command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL=5 tCK(AVG) Reserved Reserved CWL=6, 7 tCK(AVG) Reserved Reserved CWL=5 tCK(AVG) CWL=6 tCK(AVG) Reserved Reserved CWL=7 tCK(AVG) Reserved Reserved CWL=5 tCK(AVG) Reserved Reserved CWL=6 tCK(AVG) CWL=7 tCK(AVG) Reserved Reserved CWL=5 tCK(AVG) Reserved Reserved CWL=6 tCK(AVG) ns CL = 5 CL = 6 CL = 7 CL = 8 2.5 3.3 1.875 <2.5 1.875 <2.5 CWL=7 tCK(AVG) Reserved CWL=5, 6 tCK(AVG) Reserved CWL=7 tCK(AVG) Reserved CWL=5, 6 tCK(AVG) Reserved CWL=7 tCK(AVG) Reserved 2.5 3.3 Reserved 1.875 <2.5 1.5 <1.875 ns ns 1.5 <1.875 Reserved ns CL = 10 06/2009 ns Reserved CL = 9 REV 1.3 ns 1.5 <1.875 Supported CL settings 6, 7, 8 6, 8, 9 nCK Supported CWL Settings 5, 6 5, 6, 7 nCK 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module Symbol DDR3-1066 (-BE) min max Parameter Clock Timing tCK(DLL_OF tCK(avg) tCH(avg) tCL(avg) Minimum Clock Cycle Time (DLL off mode) Average Clock Period(Refer to "Standard Speed Average high pulse width Average low pulse width tCK(abs) Absolute Clock Period tCH(abs) tCL(abs) JIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) Absolute high pulse width Absolute low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Clcyle Period Jitter Cycle to Cycle Period Jitter Cumulative error accross 2 cycles Cumulative error accross 3 cycles Cumulative error accross 4cycles Cumulative error accross 5cycles Cumulative error accross 6 cycles Cumulative error accross 7 cycles Cumulative error accross 8 cycles Cumulative error accross 9 cycles Cumulative error accross 10 cycles Cumulative error accross 11 cycles Cumulative error accross 12 cycles tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles REV 1.3 06/2009 Unit 8 - 8 - ns 0.47 0.47 0.53 0.53 0.47 0.47 0.53 0.53 tCK(avg) tCK(avg) tCK(avg)min + tJIT(per)min tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)max tJIT(per)min tJIT(per)max 0.43 0.43 -90 -80 90 80 0.43 0.43 -80 -70 180 160 -132 -157 -175 -188 -200 -209 -217 -224 -231 -237 -242 80 70 160 140 -118 118 -140 140 -155 155 -168 168 -177 177 -186 186 -193 193 -200 200 -205 205 -210 210 -215 215 tERR(npr)min tERR(npr)max tERR(npr)min = tERR(npr)max = = (1+ = (1+ (1+ 0.68In(n)) * (1+ 0.68In(n)) * 0.68In(n)) * 0.68In(n)) * tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max Data Timing tDQSQ tQH tLZ(DQ) tHZ(DQ) DQS, DQS to DQ skew per group, per access DQ output hold time from DQS, DQS DQ low-impedence time from CK / DQ high-impedence time from CK / Data Setup time to DQS, DQS referenced to tDS(base) Vih(ac)/ Vil(ac) levels Data Hold time to DQS, DQS referenced to Vih(dc)/ tDH(base) Vil(dc) levels Data Strobe Timing tRPRE DQS, DQS differential READ Preamble tRPST DQS, DQS differential READ Postamble tQSH DQS, DQS differential output high time tQSL DQS, DQS differential output low time tWPRE DQS, DQS differential WRITE Preamble tWPST DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from tDQSCK rising CK, tLZ(DQS) DQS, DQS low-impedance time (Referenced from DQS, DQS high-impedance time (Referenced from tHZ(DQS) RL+BL/2) tDQSL DQS, DQS differential input low pulse width tDQSH DQS, DQS differential input high pulse width tDQSS DQS, DQS rising edge to CK, rising edge DQS, DQS falling edge setup time to CK, rising tDSS edge tDSH DQS, DQS falling edge hold time to CK, rising DDR3-1333 (-CG) min max 0.38 -600 - 132 157 175 188 200 209 217 224 231 237 242 150 300 300 0.38 -500 - 125 250 250 ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) ps ps 25 TBD ps 100 TBD ps 0.9 0.3 0.38 0.38 0.9 0.3 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 0.3 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) -300 300 -255 255 ps -600 300 -500 250 ps - 300 - 250 ps 0.4 0.4 -0.25 0.6 0.6 0.25 0.4 0.4 -0.25 0.6 0.6 0.25 tCK(avg) tCK(avg) tCK(avg) 0.2 - 0.2 - tCK(avg) 0.2 - 0.2 - tCK(avg) 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Symbol Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE tRTP Command delay Delay from start of internal write transaction to tWTR internal read command tWR WRITE recovery time tMRD Mode Register Set command cycle time DDR3-1066 (-BE) min max tMOD Mode Register Set command update delay tCCD CAS to CAS command delay 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 tDAL Auto Precharge write recovery + precharge time WR + roundup (tRP/tCK(avg)) tMPRR End of MPR Read burst to MSR for MPR (exit) ACTIVE to PRECHARGE command period Refer to tRAS "Standard Speed Bins" ACTIVE to ACTIVE command period (1k page size tRRD -x4/x8) ACTIVE to ACTIVE command period (2k page size tRRD -x16) tFAW Four activate window (1k page size - x4/x8) tFAW Four activate window (2k page size - x16) Command and Address setup time to CK, tIS(base) referenced Vih(ac) / Vil(ac) levels Command and Address hold time from CK, tIH(base) referenced Vih(ac) / Vil(ac) levels tIS(base) Commad and Address setup time to CK, AC150 referenced to Vih(ac) / Vil(ac) levels Calibration Timing tZQinit Power-up and RESET calibration time tZQoper Normal operation Full calibration time tZQCS normal operation Short calibration time Reset Timing tXPR Exit Reset from CKE HIGH to a valid command 1 max(4nCK, 7.5ns) max(4nCK, 10ns) 37.5 50 - DDR3-1333 (-CG) min max 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - - nCK - ns nCK - WR + roundup (tRP/tCK(avg)) nCK nCK nCK - - Unit max(4nCK, 6ns) max(4nCK, 7.5ns) 30 45 0 0 ns ns 125 65 ps 200 140 ps ps - - 65+125 512 256 64 - 512 256 64 - max(5nCK, tRFC(min) +10ns) - max(5nCK, tRFC(min) +10ns) - nCK nCK nCK Self RefreshTimings max(5nCK, tRFC(min) +10ns) tXSDLL Exit Self Refresh to Commands requiring a locked tDLLK(min) Minimum CKE low width for Self Refresh entry to tCKE(min)+1nC tCKESR exit timing K Valid Clock Requirement after Self Refresh Entry max(5nCK, tCKSRE (SRE) or Power Down Entry (PDE) 10ns) Valid Clock Requirement before Self Refresh max(5nCK, tCKSRX Exit(SRX) or Power-Down Exit (PDX) or Reset Exit 10ns) Power Down Timings Exit Power Down with DLL on to any valid max(3nCK, tXP command; Exit Precharge Power Down with DLL 7.5ns) frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to max(10nCK, tXPDLL commands requiring a locked DLL 24ns) max(3nCK, tCKE CKE minimm pulse width 5.625ns) tCPDED Command Pass disable delay 1 tPD Power Down Entry to Exit Timing tCKE(min) tACTPDEN Timing of ACT command to Power Down entry 1 tPRPDEN Timing of PRE or PREA command to Power Down 1 tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 tXS REV 1.3 06/2009 Exit Self Refresh to Commands not requiring a locked DLL - 9tREFI - max(5nCK, tRFC(min) +10ns) tDLLK(min) tCKE(min)+1n CK max(5nCK, 10ns) max(5nCK, 10ns) max(3nCK, 6ns) max(10nCK, 24ns) max(3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 + 1 - nCK - 9tREFI - nCK nCK nCK nCK 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Symbol Parameter DDR3-1066 (-BE) min max tWRPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 + (tWR/tCK(avg)) - tWRAPDEN Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 + WR + 1 - tWRPDEN Timing of WR command to Power Down entry (BC4MRS) WL + 2 + (tWR/tCK(avg)) - Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry WL + 2 + WR + 1 1 tMOD(min) tWRAPDEN tREFPDEN tMRSPDEN ODT Timings ODT high time without write command or with write command and BC4 tODTH8 ODT high time without write command oand BL8 Asynchronous RTT turn-on delay (Power-Down with tAONPD DLL frozen) Asynchronous RTT turn-off delay (Power Down with tAOFPD DLL frozen) tAON RTT turn-on RTT_NOM and RTT_WR turn-off time from tAOF ODTLoff reference tADC RTT dynamic change skew Write Leveling Timings First DQS/DQS rising edge after write leveling mode tWLMRD is programmed tWLDQSEN DQS/DQS delay after write leveling mode is Write leveling setup time from rising CK, CK tWLS crossing to rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS tWLH crossing to rising CK, CK crossing tWLO Write leveling output delay tWLOE Write levleing output error tRFC REF command to ACT or REF command time tREFI Average period refresh interval (0CtCASE85C) tREFI Average period refresh interval (85C<tCASE95C) tODTH4 REV 1.3 06/2009 4 - DDR3-1333 (-CG) min max WL + 4 + (tWR/tCK(avg) ) WL + 4 + WR +1 WL + 2 + (tWR/tCK(avg) ) WL + 2 + WR +1 1 tMOD(min) - - 4 6 - 1 9 Unit nCK nCK nCK nCK nCK - nCK 6 - nCK 1 9 ns ns 1 9 1 9 -300 300 -250 250 ps 0.3 0.7 0.3 0.7 tCK(avg) 0.3 0.7 0.3 0.7 tCK(avg) 40 - 40 - nCK 25 - 25 - nCK 245 - 195 - ps 245 - 195 - ps 0 0 9 2 0 0 9 2 ns ns ns us us 110 7.8 3.9 110 7.8 3.9 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Package Dimensions [1GB - 2 Ranks, 64Mx16 DDR3 SDRAMs] 67.60 +/- 0.15 (2.661 +/- 0.006) 63.60 (2.504) 6.0 (0.236) 1 30.0 +/- 0.15 (1.181 +/- 0.006) 3.8 max. (0.150 max.) 20.0 (0.787) 2.0 (0.079) 203 Detail A 21.0 (0.827) 1.0 +0.07/-0.1 Detail B 39.0 (1.535) 4.0 (0.157) 3.0 (0.118) 1.35 (0.053) 2.55 (0.100) 0.25 max. (0.010 max.) 2x 4.0 +/- 0.1 (0.157 +/- 0.004) 2x O1.80 (0.071) 0.45 +/- 0.03 (0.018 +/- 0.001) 1.0 (0.039) 0.6 (0.024) 1.5 (0.059) Detail A Detail B Units: Millimeters (Inches) Note: Device position and scale are only for reference. REV 1.3 06/2009 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Package Dimensions [2GB - 2 Ranks, 128Mx8 DDR3 SDRAMs] 67.60 +/- 0.15 (2.661 +/- 0.006) 63.60 (2.504) 6.0 (0.236) 1 30.0 +/- 0.15 (1.181 +/- 0.006) 3.8 max. (0.150 max.) 20.0 (0.787) 2.0 (0.079) 203 Detail A 21.0 (0.827) 1.0 +0.07/-0.1 Detail B 39.0 (1.535) 4.0 (0.157) 3.0 (0.118) 1.35 (0.053) 2.55 (0.100) 0.25 max. (0.010 max.) 2x 4.0 +/- 0.1 (0.157 +/- 0.004) 2x O1.80 (0.071) 0.45 +/- 0.03 (0.018 +/- 0.001) 1.0 (0.039) 0.6 (0.024) 1.5 (0.059) Detail A Detail B Units: Millimeters (Inches) Note: Device position and scale are only for reference. REV 1.3 06/2009 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH8A1PS / NT2GC64B8HA1NS 1GB: 128M x 64 / 2GB: 256M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SO-DIMM Revision Log Rev Date Modification 0.1 05/2008 Preliminary Release 1.0 07/2008 Official Release 1.1 09/2008 Revise SPD from Rev0.8 to Rev1.0 1.2 05/2009 Modify IDDx current 1GB & 2GB 1066/1333MHz 1.3 06/2009 IDD and SPD update Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c) 2008 REV 1.3 06/2009 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.