©2008 Fairchild Semiconductor International Rev. A3, October 2008
FQD7N20L / FQU7N20L
FQD7N20L / FQU7N20 L
200V LOGIC N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation modes. These devices are
well suited for high efficiency switching DC/DC conv ert ers,
switch mode power supplies, and motor control.
Features
5.5A, 200V, RDS(on) = 0.75 @VGS = 10 V
Low gate charge ( typical 6.8 nC)
Low Crss ( typical 8.5 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Low level gate drive requirement allowing direct
operation from logic drivers
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S
D
G
I-PAK
FQU Series
D-P AK
FQD Series GS
D
GS
D
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Thermal Char acteristics
Symbol Parameter FQD7N20L / FQU7N20L Units
VDSS Drain-Source Voltage 200 V
IDDrain Current - Continuous (TC = 25°C) 5.5 A
- Continuous (TC = 100°C) 3.48 A
IDM Drain Current - Pulsed (Note 1) 22 A
VGSS Gate-Source Voltage ± 20 V
EAS Single Pulsed Avalanche Energy (Note 2) 73 mJ
IAR Avalanche Current (Note 1) 5.5 A
EAR Repetitive Avalanche Energy (Note 1) 4.5 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns
PDPower Dissipation (TA = 25°C) * 2.5 W
Power Dissipation (TC = 25°C) 45 W
- Derate above 25°C 0.36 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8 from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 2.78 °C/W
RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W
* When mounted on the minimum pad size recommended (PCB Mount)
October 2008
QFET
®
RoHS Compliant
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
Rev. A3, October 2008
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 3.6mH, IAS = 5.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 6.5A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit ions Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA200 -- -- V
BVDSS
/ TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.17 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 200 V, VGS = 0 V -- -- 1 µA
VDS = 160 V, TC = 125°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µA1.0 -- 2.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 2.75 A
VGS = 5 V, I D = 2.75 A -- 0.59
0.62 0.75
0.78
gFS Forward Transconductance VDS = 30 V, ID = 2.75 A -- 5.6 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 390 500 pF
Coss Output Capacitance -- 55 70 pF
Crss Reverse Transfer Capacitance -- 8.5 11 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 100 V, ID = 6.5 A,
RG = 25
-- 12 35 ns
trTurn-On Rise Time -- 125 260 ns
td(off) Turn-Off D e l a y Time -- 20 50 ns
tfTurn -Off Fa ll Time -- 65 140 n s
QgTotal Gate Cha rge VDS = 160 V, ID = 6.5 A,
VGS = 5 V
-- 6.8 9.0 nC
Qgs Gate-Source Charge -- 1.6 -- nC
Qgd Gate-Drain Charge -- 3.4 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 5.5 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 22 A
VSD Drain-Source Diode Forward V oltage VGS = 0 V, I S = 5.5 A -- -- 1.5 V
trr Reverse Recovery Time VGS = 0 V, I S = 6.5 A,
dIF / dt = 100 A/µs
-- 110 -- ns
Qrr Reverse Recovery Charge -- 0.44 -- µC
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
10-1 100101
0
200
400
600
800 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Notes :
1. VGS = 0 V
2. f = 1 M Hz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
10-1
100
101
150 No tes :
1. VGS = 0V
2. 250μ
s Pu lse T es t
25
IDR, Reverse Drain Current [A]
VSD, So urc e-Drain vo ltag e [V]
0246810
10-1
100
101
150
25
-55
No tes :
1. VDS = 30V
2. 250μ
s Pu lse T es t
ID, Dr ain Current [A]
VGS, Gate-Source Voltage [V]
10-1 100101
10-1
100
101
VGS
To p : 10 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
B o tto m : 3. 0 V
Notes :
1. 250μ
s Pulse Test
2. TC = 25
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
03691215
0
2
4
6
8
10
12
VDS = 100V
VDS = 40V
VDS = 160V
Note : ID = 6.5 A
VGS, Gate-Source Voltage [V]
QG, Tota l Ga t e Cha rg e [nC]
03691215
0
1
2
3
4
N o te : TJ = 25
VGS = 5V
VGS = 10V
RDS(on) [],
Drain-Source On-R esistance
ID , Dr a in Cu r ren t [A]
Typical Characteristics
Figure 5. Capacitanc e C haracterist i cs Figure 6. Gate Charge C haracter is tics
Figure 3. On-Resist anc e Variation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Fo rward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Charact er i st ics
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
10-5 10-4 10-3 10-2 10-1 100101
10-1
100
Note s :
1 . ZθJC(t) = 2 .7 8 /W M a x .
2 . D u ty F a c to r, D = t1/t2
3 . TJM - T C = P DM * Z θJC(t)
s ingle pu lse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC
(t), T h erma l R e sp o ns e
t1, S q u a re W a ve P u ls e Du ra tio n [se c ]
25 50 75 100 125 150
0
1
2
3
4
5
6
ID, Drain Current [A]
TC, Case Temperature [
]
100101102
10-1
100
101
102
DC 10 ms
1 ms
100 µs
Operation in This Area
is Limited by R DS(on)
Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
No tes :
1. VGS = 10 V
2. ID = 3.25 A
RDS(ON) , (N o r maliz e d )
Drain-Source On-Resistance
TJ, Junc tion Tem p erature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1 . VGS = 0 V
2 . ID = 250 μ
A
BV DSS , (Norm alized)
Drain-Source Breakdow n V oltage
TJ, Junction Tem perature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figu re 7. Br ea kdown Voltage Variati o n
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Respons e Cur ve
t1
PDM
t2
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
Charge
VGS
5V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
VGS
5V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
5V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
5V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
Peak Diode Recover y dv/dt Test Circuit & Waveforms
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
6.60 ±0.20
2.30 ±0.10
0.50 ±0.10
5.34 ±0.30
0.70 ±0.20
0.60 ±0.20
0.80 ±0.20
9.50 ±0.30
6.10 ±0.20
2.70 ±0.20 9.50 ±0.30
6.10 ±0.20
2.70 ±0.20
MIN0.55
0.76 ±0.10 0.50 ±0.10
1.02 ±0.20
2.30 ±0.20
6.60 ±0.20
0.76 ±0.10
(5.34)
(1.50)
(2XR0.25)
(5.04)
0.89 ±0.10
(0.10) (3.05)
(1.00)
(0.90)
(0.70)
0.91 ±0.10
2.30TYP
[2.30±0.20]
Dimensions in Millimeters
Mechanical Dimensions
D - PAK
©2008 Fairchild Semiconductor International
FQD7N20L / FQU7N20L
Rev. A3, October 2008
Mechanical Dimensions
Dimensions in Millimeters
I - PAK
FQD7N20L / FQU7N20L
FQD7N20L / FQU7N20L Rev. A3www.fairchildsemi.com
Rev. I37
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Definition of Terms
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tm
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