LTC3315A
1
Rev. A
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual 5V, 2A Synchronous Step-Down
DC/DCs in 2mm × 2mm LQFN
The LT C
®
3315A features dual 2A monolithic synchro-
nous step-down converters operating from a 2.25V to
5.5V input supply in one package for space-constrained
applications with demanding performance requirements.
Using constant frequency, peak current mode control at
switching frequencies up to 3MHz with a minimum on-
time as low as 25ns, both bucks achieve high efficiency
and fast transient response in a very small application
footprint.
The LTC3315A operates in forced continuous or pulse
skip mode for low noise or in Burst Mode
®
operation for
high efficiency at light loads. The common buck switching
frequency is 2MHz and can be synchronized to an external
oscillator via the MODE/SYNC pin.
The LTC3315A can regulate outputs as low as 500mV.
Other features include precision enable thresholds, a
PGOOD signal, output overvoltage protection, thermal
shutdown, output short-circuit protection, and up to 100%
duty cycle operation for low dropout. The LTC3315A is
available in a compact 2mm × 2mm LQFN package.
Efficiency vs Load Current
Dual 2MHz 2A Buck Regulators
APPLICATIONS
n Dual Outputs Each with 2A Output Current
n High Efficiency: 19mΩ NMOS and 75mΩ PMOS
n Wide Bandwidth, Fast Transient Response
n Switching Frequency Synchronizable Up to 3MHz
n VIN Range: 2.25V to 5.5V
n VOUT Range: 0.5V to VIN
n VOUT Accuracy: ±1%
n Low Ripple Burst Mode
®
Operation
n Peak Current Mode Control
n Minimum On-Time: 25ns
n Safely Tolerates Inductor Saturation in Overload
n Shutdown Current: 1.2µA
n Precision 400mV Enable Thresholds
n Internal Soft-Start and Compensation
n Power Good Output
n Low Profile, Thermally Enhanced 12-Lead
2mm × 2mm × 0.74mm LQFN Package
n AEC-Q100 Qualified for Automotive Applications
n Servers, Telecom Supplies, Optical Networking
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies
n Industrial/Automotive/Communications
All registered trademarks and trademarks are the property of their respective owners.
880nH
33µF
140k
100k
6.8pF
10µF
1µH
261k
100k
10µF
22µF
4.7pF
V
IN
SW1
SW2
PGOOD
3315A TA01a
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
2.25V TO 5.5V
V
OUT1
1.2V, 2A
V
OUT2
1.8V, 2A
fSW = 2MHz
EFFICIENCY
POWER LOSS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
EFFICIENCY (%)
POWER LOSS (W)
3315A TA01b
L = 880nH, L DCR = 19mΩ
f
SW
= 2MHz
V
IN
= 3.3V, V
OUT
= 1.2V
Burst Mode OPERATION
LTC3315A
2
Rev. A
For more information www.analog.com
ORDER INFORMATION
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN ............................................................... –0.3V to 6V
EN1, EN2 .............. –0.3V to Lesser of (VIN + 0.3V) or 6V
FB1, FB2 ............... –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC ........ –0.3V to Lesser of (VIN + 0.3V) or 6V
PGOOD ......................................................... –0.3V to 6V
IPGOOD ......................................................................5mA
Operating Junction Temperature (Notes 2, 3):
LTC3315AE ........................................ –40°C to 125°C
LTC3315AI ......................................... –40°C to 125°C
LTC3315AJ ........................................ –40°C to 150°C
LTC3315AH ........................................ –40°C to 150°C
LTC3315AMP ..................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Maximum Reflow (Package Body) Temperature ... 260°C
(Note 1)
TOP VIEW
EN1
FB1
FB2
EN2
VIN
GND
GND
VIN
MODE/SYNC
SW1
PGOOD
SW2
10
9
8
7
1
2
3
4
LQFN PACKAGE
12-LEAD (2mm × 2mm × 0.74mm)
TJMAX = 150°C, θJA = 51°C/W, θJCBOTTOM = 8.6°C/W,
θJCTOP = 80°C/W, θJB = 12°C/W, ΨJT = 0.8°C/W,
θ
AND Ψ
VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
13
GND
12 11
5 6
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
Operating Supply Voltage (VIN)l2.25 5.5 V
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 3.3V unless otherwise specified.
TAPE AND REEL (MINI) TAPE AND REEL
PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)DEVICE FINISH CODE
LTC3315AEV#TRMPBF LTC3315AEV#TRPBF
LHFY e4
LQFN (Laminate
Package with QFN
Footprint)
MSL 3
–40°C to 125°C
LTC3315AIV#TRMPBF LTC3315AIV#TRPBF –40°C to 125°C
LTC3315AJV#TRMPBF LTC3315AJV#TRPBF –40°C to 150°C
LTC3315AHV#TRMPBF LTC3315AHV#TRPBF –40°C to 150°C
LTC3315AMPV#TRMPBF LTC3315AMPV#TRPBF –55°C to 150°C
AUTOMOTIVE PRODUCTS**
LTC3315AEV#WTRMPBF LTC3315AEV#WTRPBF
LHFY e4
LQFN (Laminate
Package with QFN
Footprint)
MSL 3
–40°C to 125°C
LTC3315AIV#WTRMPBF LTC3315AIV#WTRPBF –40°C to 125°C
LTC3315AJV#WTRMPBF LTC3315AJV#WTRPBF –40°C to 150°C
LTC3315AHV#WTRMPBF LTC3315AHV#WTRPBF –40°C to 150°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Device temperature grade is indicated by a label on the shipping container.
• TRM = 500 pieces.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
• Tape and reel specifications. Some packages are available in 500 unit
reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
LTC3315A
3
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising l2.05 2.15
150
2.25 V
mV
VIN Quiescent Current in Shutdown 1.2 2 µA
VIN Quiescent Current with One Buck Enabled Burst Mode, Buck in Regulation, Sleeping
All Modes, Not Sleeping (Note 4)
45
1.5
70
2.3
µA
mA
VIN Quiescent Current with Both Bucks Enabled Burst Mode, Bucks in Regulation, Sleeping
All Modes, Not Sleeping (Note 4)
70
2.8
110
4.2
µA
mA
Enable Threshold
Enable Threshold Hysteresis
VEN Rising l375 400
50
425 mV
mV
EN Pin Leakage VEN = 5.5V ±20 nA
Voltage Regulation, Buck 1 and Buck 2
Regulated Feedback Voltage (VFB)l495 500 505 mV
Feedback Voltage Line Regulation 2.25V ≤ VIN ≤ 5.5V 0.015 0.05 %/V
Feedback Pin Input Current VFB = 500mV ±20 nA
PMOS Current Limit (ILIM) Current out of SW, VOUT/VIN ≤ 0.2 2.9 3.2 3.5 A
NMOS Current Limit (IVALLEY) Current out of SW 2.4 2.7 3.0 A
NMOS Reverse Current Limit Current into SW, Forced Continuous 0.5 1 1.5 A
PMOS ON-Resistance 75 mΩ
NMOS ON-Resistance 19 mΩ
SW Leakage Current Shutdown, VIN = 5.5V ±200 nA
Minimum On Time VIN = 5.5V l25 45 ns
Maximum Duty Cycle l100 %
Overtemperature Shutdown (OT)
Overtemperature Shutdown Hysteresis
Temperature Rising (Note 5) 165
5
°C
°C
Power Good/Soft-Start
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT l
l
97
0.6
98
1.1
99
1.6
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT l
l
107
1
110
2.2
114
3.5
%
%
PGOOD Delay 120 µs
PGOOD Leakage Current VPGOOD = 5.5V 20 nA
PGOOD Pull-Down Resistance VPGOOD = 0.1V 10 20 Ω
Soft-Start Time (Note 6) l0.25 1 3 ms
Oscillator and MODE/SYNC
Internal Oscillator Frequency (fSW)l1.85 2 2.15 MHz
Synchronization Frequency Range l1 3 MHz
Minimum SYNC High or Low Pulse Width l40 ns
SYNC Level High on MODE/SYNC
SYNC Level Low on MODE/SYNC
l
l
1.2
0.4
V
V
MODE/SYNC No Clock Detect Time 10 µs
MODE/SYNC Pin Threshold For Programming Pulse Skipping Mode
For Programming Burst Mode
l
l
VIN – 0.1
0.1 V
V
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 3.3V unless otherwise specified.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3315A is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3315AE is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
LTC3315A
4
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
VFB vs Temperature PMOS RDS(ON) vs Temperature NMOS RDS(ON) vs Temperature
NMOS, PMOS Leakage vs
Temperature
Oscillator Frequency vs
Temperature Oscillator Frequency vs VIN
characterization, and correlation with statistical process controls. The
LTC3315AI is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC3315AJ and the LTC3315AH are guaranteed
over the –40°C to 150°C operating junction temperature range, and the
LTC3315AMP is guaranteed over the –55°C to 150°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent
with these specifications is determined by specific operating conditions
in conjunction with board layout, the rated package thermal impedance,
and other environmental factors. The junction temperature (TJ in °C) is
calculated from ambient temperature (TA in °C) and power dissipation (PD
in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance. See High
Temperature Considerations section for more details.
Note 3: The LTC3315A includes overtemperature protection which
protects the device during momentary overload conditions. Junction
temperatures will exceed 150°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Static current, switches not switching. Actual current will be
higher due to gate charge losses at the switching frequency.
Note 5: Overtemperature shutdown is not tested in production.
Note 6: The soft-start time is the time from the start of switching until the
FB pin reaches 475mV.
ELECTRICAL CHARACTERISTICS
TEMPERATURE (°C)
–50
–25
0
25
50
75
150
V
FB
(mV)
3315 G01
V
IN
= 2.25V
V
IN
= 3.3V
V
IN
= 5.5V
TEMPERATURE (°C)
0
25
50
75
0
25
50
75
R
DS(ON)
(mΩ)
3315ab G02
V
IN
= 2.25V
V
IN
= 3.3V
V
IN
= 5.5V
TEMPERATURE (°C)
0
25
50
75
0
5
10
15
20
25
30
35
40
45
50
R
DS(ON)
(mΩ)
3315ab G03
NMOS, V
IN
= 5.5V, SW = 5.5V
NMOS, V
IN
= 3.3V, SW = 3.3V
PMOS, V
IN
= 5.5V, SW = 0V
PMOS, V
IN
= 3.3V, SW = 0V
TEMPERATURE (°C)
–50
–25
0
25
50
75
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
LEAKAGE (µA)
3315ab G04
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
0
25
50
75
1.80
1.84
1.88
1.92
1.96
2.00
2.04
2.08
2.12
2.16
2.20
FREQUENCY (MHz)
3315aba G05
V
IN
(V)
2
2.5
3
3.5
4
4.5
5
5.5
1.80
1.84
1.88
1.92
1.96
2.00
2.04
2.08
2.12
2.16
2.20
FREQUENCY (MHz)
3315ab G06
LTC3315A
5
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
VIN Shutdown Quiescent Current
vs Temperature
VIN Quiescent Current vs
Temperature, All Modes, Not
Sleeping
VIN Quiescent Current vs
Temperature, Burst Mode,
Sleeping
Minimum On Time vs VIN
Minimum On Time vs
Temperature UVLO Threshold vs Temperature
EN Threshold vs Temperature Current Limit vs Temperature
Efficiency vs ILOAD Syncing,
Forced Continuous
V
IN
= 5.5V
V
IN
= 3.3V
TEMPERATURE (°C)
–50
–25
0
25
50
75
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
I
VIN
(µA)
3315ab G7
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
0
25
50
75
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
I
VIN
(mA)
3315ab G08
ONE BUCK ENABLED
BOTH BUCKS ENABLED
ONE BUCK ENABLED
BOTH BUCKS ENABLED
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
0
25
50
75
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
I
VIN
(µA)
3315ab G09
150°C
25°C
–50°C
V
IN
(V)
2
2.5
3
3.5
4
4.5
5
5.5
0
10
20
30
40
50
60
70
MINIMUM ON TIME (ns)
3315ab G10
V
IN
= 2.25V
V
IN
= 3.3V
V
IN
= 5.5V
TEMPERATURE (°C)
0
25
50
75
0
10
20
30
40
50
60
70
MINIMUM ON TIME (ns)
3315ab G11
UVLO RISING
UVLO FALLING
TEMPERATURE (°C)
0
25
50
75
1.8
1.9
2.0
2.1
2.2
2.3
2.4
V
IN
(V)
3315 G12
EN RISING
EN FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
V
EN
(mV)
3315ab G13
PMOS
NMOS
TEMPERATURE (°C)
0
25
50
75
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
CURRENT OUT OF SW PIN (A)
3315ab G14
V
OUT
= 1.2V
V
IN
= 3.3V
1MHz, L = 1.5µH, DCR = 33mΩ
2MHz, L = 880nH, DCR = 19mΩ
3MHz, L = 560nH, DCR = 16mΩ
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G15
LTC3315A
6
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 2.25V
PGOOD, OV vs Temperature
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 3.3V
VOUT Load Regulation
Efficiency vs ILOAD,
VOUT = 0.8V, VIN = 5.5V
VOUT Line Regulation
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 2.25V
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 3.3V
Efficiency vs ILOAD,
VOUT = 1.2V, VIN = 5.5V
OV RISING
OV FALLING
PGOOD RISING
PGOOD FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
96
98
100
102
104
106
108
110
112
PERCENTAGE OF THE REGULATED V
OUT
(%)
3315ab G16
V
OUT
= 1.2V
V
IN
= 5.5V
V
IN
= 5.0V
V
IN
= 3.3V
V
IN
= 2.25V
1m
10m
100m
1
2
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
3315ab G17
LOAD CURRENT (A)
V
OUT
= 1.2V
I
LOAD
= 0A
I
LOAD
= 2A
V
IN
(V)
2
2.5
3
3.5
4
4.5
5
5.5
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
3315ab G18
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3315ab G19
L DCR = 17mΩ
L = 680nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G20
L DCR = 17mΩ
L = 680nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
L DCR = 17mΩ
L = 680nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G21
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3315ab G22
L DCR = 19mΩ
L = 880nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G23
L DCR = 19mΩ
L = 880nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G24
L DCR = 19mΩ
L = 880nH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LTC3315A
7
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
Efficiency vs ILOAD,
VOUT = 3.3V, VIN = 4.2V
Efficiency vs ILOAD,
VOUT = 2.5V, VIN = 3.3V
Efficiency vs ILOAD,
VOUT = 3.3V, VIN = 5.5V
Efficiency vs ILOAD,
VOUT = 2.5V, VIN = 5.5V
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 2.25V
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 3.3V
Efficiency vs ILOAD,
VOUT = 1.8V, VIN = 5.5V
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3315ab G25
L DCR = 20mΩ
L = 1µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G26
L DCR = 20mΩ
L = 1µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G27
L DCR = 20mΩ
L = 1µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G28
L DCR = 23mΩ
L = 1.2µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G29
L DCR = 23mΩ
L = 1.2µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G30
L DCR = 23mΩ
L = 1.2µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LOAD CURRENT (A)
1m
10m
100m
1
2
0
10
20
30
40
50
60
70
80
90
EFFICIENCY (%)
3315ab G31
L DCR = 23mΩ
L = 1.2µH
f
SW
= 2MHz
BURST MODE
PULSE SKIP
FORCED CONTINUOUS
LTC3315A
8
Rev. A
For more information www.analog.com
Startup Transient, Pulse Skip
Mode
Transient Response, Pulse Skip
Mode
Startup Transient, FC Mode
Transient Response, FC Mode
Startup Transient, Burst Mode
Transient Response, Burst Mode
Operation
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.3V, unless otherwise noted.
10µs/DIV
I
LOAD
1A/DIV
V
OUT
50mV/DIV
I
L
1A/DIV
3315ab G32
LOAD STEP: 0.1A TO 1.5A, 5A/µs
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
10µs/DIV
I
LOAD
1A/DIV
V
OUT
50mV/DIV
I
L
1A/DIV
3315ab G33
LOAD STEP: 0.1A TO 1.5A, 5A/µs
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
LOAD STEP: 0.1A TO 1.5A, 5A/µs
10µs/DIV
I
LOAD
1A/DIV
V
OUT
50mV/DIV
I
L
1A/DIV
3315ab G34
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
I
L
500mA/DIV
PGOOD
5V/DIV
3315ab G35
R
LOAD
= 120Ω
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
R
LOAD
= 120Ω
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
I
L
500mA/DIV
PGOOD
5V/DIV
3315ab G36
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
R
LOAD
= 120Ω
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
I
L
500mA/DIV
PGOOD
5V/DIV
3315ab G37
REFER TO BUCK 1 IN TYPICAL APPLICATION:
DUAL 1.2V AND 0.8V 2MHz, 2A BUCK
REGULATORS, VIN = 3.3V
LTC3315A
9
Rev. A
For more information www.analog.com
PIN FUNCTIONS
EN1 (Pin 1): Enable Input for Buck Regulator 1. Active
high. The EN1 pin has a precision threshold and an
optional external resistor divider from VIN or another
supply programs when Buck Regulator 1 is enabled. If
the precision threshold is not required, drive EN1 to VIN
to enable. Do not float.
FB1 (Pin 2): Feedback Input for Buck Regulator 1.
Program the output voltage and close the control loop
by connecting this pin to the middle node of a resistor
divider between the output and ground. The LTC3315A
regulates FB1 to 500mV (typical). A phase lead capaci-
tor connected between VOUT1 and FB1 may be used to
optimize transient response.
FB2 (Pin 3): Feedback Input for Buck Regulator 2.
Program the output voltage and close the control loop
by connecting this pin to the middle node of a resistor
divider between the output and ground. The LTC3315A
regulates FB2 to 500mV (typical). A phase lead capaci-
tor connected between VOUT2 and FB2 may be used to
optimize transient response.
EN2 (Pin 4): Enable Input for Buck Regulator 2. Active
high. The EN2 pin has a precision threshold and an
optional external resistor divider from VIN or another
supply programs when Buck Regulator 2 is enabled. If
the precision threshold is not required, drive EN2 to VIN
to enable. Do not float.
PGOOD (Pin 5): Power Good Output. Open drain out-
put. When the regulated output voltage of either enabled
switching regulator falls below its PGOOD threshold or
rises above its overvoltage threshold, this pin is driven
low. When both buck regulators are disabled PGOOD is
driven low.
SW2 (Pin 6): Switch Node for Buck Regulator 2. Connect
an inductor to this pin with a short, wide trace.
VIN (Pin 7, Pin 10): Input Supply Pins. The VIN pins sup-
ply current to internal circuitry and to each buck’s PMOS
power switch. Connect both VIN pins together with a short,
wide trace and bypass to GND with low ESR capacitors
located as close as possible to the pins.
GND (Pin 8, Pin 9, Exposed Pad Pin 13): Ground.
Connect the exposed pad to a continuous ground plane
on the printed circuit board directly under the LTC3315A
for electrical contact and rated thermal performance.
Additionally, Pin 8 and Pin 9 should be shorted to the
exposed pad with a wide trace.
SW1 (Pin 11): Switch Node for Buck Regulator 1. Connect
an inductor to this pin with a short, wide trace.
MODE/SYNC (Pin 12): Mode Selection and External Clock
Synchronization Input. Ground this pin to enable pulse-
skipping mode. For higher efficiency at light loads, tie
this pin to VIN to enable Burst Mode. For fast transient
response and constant frequency operation over a wide
load range, float this pin to enable forced continuous
mode. Drive MODE/SYNC with an external clock to syn-
chronize both buck converters to the applied frequency.
When syncing, the operating mode is forced continuous.
The slope compensation is automatically adapted to the
external clock frequency. In the absence of an external
clock both buck converters will switch at the default
switching frequency.
LTC3315A
10
Rev. A
For more information www.analog.com
BLOCK DIAGRAM
BUCK1
GND: PINS 8, 9, 13 (EXPOSED PAD)
EN1
1
V
IN
SW1
7
11
2
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BUCK
CONTROL
V
IN
0.5V
VC2
SW2
10
6
3
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BUCK
CONTROL
0.4V
BUCK2
ENBUCK1
ENBUCK2
EN2
4
0.4V
PGOOD
3315ab BD
5
OSCILLATOR
0.49V
0.55V
0.49V
0.55V
MODE/SYNC
12
+
–
+
–
+
–
+
–
+
–
+
–
ENBUCK1
ENBUCK2
+
–
0.5V
+
–
GM
VC1
GM
OVER
TEMPERATURE
DETECT
OT
OT
INTERNAL
REFERENCE
0.5V
0.49V
0.55V
0.4V
MODE
DETECTION
FC
BURST
PULSE SKIP
0°
180°
LTC3315A
11
Rev. A
For more information www.analog.com
OPERATION
Buck Switching Regulators
The LTC3315A is a 5V dual 2A monolithic, constant fre-
quency, peak current mode step-down DC/DC converter.
The synchronous buck switching regulators are internally
compensated and require only external feedback resistors
to set the output voltage.
An internal oscillator, which can be externally synchro-
nized, turns on the internal PMOS power switch at the
beginning of each clock cycle. Current in the inductor
ramps up until the PMOS current comparator trips and
turns off the PMOS. The peak inductor current, IPEAK, at
which the PMOS turns off is controlled by an internal VC
voltage which the error amplifier regulates by compar-
ing the voltage on the feedback (FB) pin with an internal
500mV reference. An increase in the load current causes
a reduction in the feedback voltage relative to the refer-
ence, causing the error amplifier to raise the VC voltage
(and I
PEAK
)
until the average inductor current matches the
new load current. When the PMOS turns off, the NMOS
turns on and ramps down the inductor current for the
remainder of the clock cycle or, if in pulse skipping mode
or Burst Mode, until the inductor current falls to zero. If
an overload condition results in excessive current flowing
through the NMOS, the next clock cycle will be skipped
until the current returns to a safe level.
Each buck switching regulator has its own SW, FB, and
EN pins. The buck input supplies are internally connected,
but each V
IN
pin should have its own input bypass capaci-
tor (see Applications Information). The enable pins have
precision 400mV thresholds which may be used to pro-
vide event-based power-up sequencing by connecting
the enable pin to the output of another buck through a
resistor divider. If the EN pin of a buck is low, that buck is
in shutdown and in a low quiescent current state. If both
EN pins are low, both bucks are in shutdown, the SW
pins are high impedance, and the quiescent current of the
LTC3315A is 1µA (typical). If either EN pin is above the
enable threshold of 400mV its respective buck is enabled.
Both buck regulators have forward and reverse inductor
current limiting, soft-start to limit inrush current during
start-up, and short-circuit protection. When both bucks
are disabled and either buck is subsequently enabled,
there is a 400µs (typical) delay while internal circuitry
powers up followed by a 100µs (typical) no start time
before switching commences and the soft-start ramp
begins. If a second buck is then enabled, it will also have
a 100µs (typical) no start time. If the second buck is
enabled within 400µs of the first buck, it will wait until
the expiry of the 400µs to begin its no start time.
The buck switching regulators are switched 180° out of
phase with respect to each other. The phase determines
the fixed edge of the switching sequence, which is when
the PMOS turns on. The PMOS off (NMOS on) phase is
subject to the regulated duty cycle of each buck.
Mode Selection
The buck switching regulators operate in three different
modes set by the MODE/SYNC pin: pulse skipping mode
(when the MODE/SYNC pin is set low), forced continuous
PWM mode (when the MODE/SYNC pin is floating), and
Burst Mode (when the MODE/SYNC pin is set high). The
MODE/SYNC pin sets the operating mode for both buck
switching regulators.
In pulse skipping mode, the oscillator operates continu-
ously and positive SW transitions are aligned to the clock.
Negative inductor current is disallowed and during light
loads switch pulses are skipped to regulate the output.
In forced continuous mode, the oscillator runs continu-
ously, no pulses are skipped, and switching occurs in
every cycle. To maintain regulation, the inductor current
is allowed to reverse under light load conditions. This
mode allows the buck to run at a fixed frequency with
minimal output ripple. In forced continuous mode if the
inductor current reaches –1A (typical, 1A into the SW pin)
the NMOS will turn off for the remainder of the cycle to
limit the current.
In Burst Mode operation, at light loads, the output capaci-
tor is charged to a voltage slightly higher than its regu-
lation point. The regulator then goes into a sleep state,
during which time the output capacitor provides the load
current. In sleep most of the regulator’s circuitry is pow-
ered down, helping to conserve input power. When the
output voltage drops below its programmed value, the cir-
cuitry is powered back on and another burst cycle begins.
LTC3315A
12
Rev. A
For more information www.analog.com
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate in constant
frequency PWM mode.
Synchronizing the Oscillator to an External Clock
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values
and improves transient response. Operation at lower
frequencies improves efficiency by reducing switching
losses but requires larger inductance and/or capaci-
tance values to maintain low output voltage ripple. The
LTC3315A operates at a default frequency of 2MHz.
The LTC3315A’s internal oscillator is synchronized
through an internal PLL circuit to an external frequency by
applying a square wave clock signal to the MODE/SYNC
pin. During synchronization, the Buck 1 PMOS turn-on is
locked to the rising edge of the external frequency source.
Buck2 will be 180° out of phase with respect to Buck1.
While syncing, the buck switching regulators operate in
forced continuous mode. The synchronization frequency
range is 1MHz to 3MHz.
After detecting an external clock on the SYNC pin, the
internal PLL starts up at the default frequency. The inter-
nal PLL then gradually adjusts its operating frequency to
match the frequency and phase of the SYNC signal.
When the external clock is removed the LTC3315A will
detect the absence of the external clock within approxi-
mately 10µs. During this time it will continue to provide
clock cycles. Once the external clock removal has been
detected, the oscillator will gradually adjust its operating
frequency back to the default.
Power Failure Reporting Via PGOOD Pin
Power failure faults are reported via the PGOOD pin.
Both buck switching regulators have an internal power
good (PGOOD) signal and if a buck is enabled its internal
PGOOD signal must be high for the PGOOD pin to be high.
OPERATION
When the regulated output voltage of an enabled buck
rises above 98% of its programmed value, the PGOOD
signal transitions high. If the regulated output voltage
subsequently falls below 97% of its programmed value,
the PGOOD signal is pulled low. If either enabled buck’s
internal PGOOD signal stays low for greater than 120μs,
then the PGOOD pin is pulled low, indicating to a micro-
processor that a power fault has occurred. The 120μs
filter time prevents the pin from being pulled low during a
transient event. In addition, whenever PGOOD transitions
high there will be a 120μs assertion delay.
The LTC3315A also reports overvoltage conditions at
the PGOOD pin. If either enabled buck regulator’s out-
put voltage rises above 110% of its programmed value,
the PGOOD pin is pulled low after 120μs. Similarly, if all
enabled outputs that are overvoltage subsequently fall
below 107.8% of their programmed value, the PGOOD
pin transitions high again after 120μs.
An error condition that pulls the PGOOD pin low is not
latched. When the error condition goes away, the PGOOD
pin is released and is pulled high if no other error condi-
tion exists. PGOOD is also pulled low in the following
scenarios: if neither buck switching regulator is enabled,
if VIN is below the UVLO threshold, or if the LTC3315A is
over temperature (see below).
Output Overvoltage Protection
During an output overvoltage event, when the FB pin
voltage is greater than 110% of its regulated value, the
LTC3315A PMOS will be turned off immediately.
An output overvoltage event should not happen under
normal operating conditions.
Overtemperature Protection
To prevent thermal damage, the LTC3315A incorporates
an overtemperature (OT) function. When the LTC3315A
die temperature reaches 165°C (typical, not tested) all
enabled buck switching regulators are shut down and
remain in shutdown until the die temperature falls to
160°C (typical, not tested).
LTC3315A
13
Rev. A
For more information www.analog.com
OPERATION
APPLICATIONS INFORMATION
Output Voltage Soft-Start
Soft starting the output prevents current surge on the input
supply and/or output voltage overshoot. During soft-start,
the output voltage will proportionally track an internal
voltage ramp. An active pull-down circuit discharges that
internal voltage in the case of fault conditions. The ramp
will restart when the fault is cleared. Fault conditions that
initiate the soft-start ramp are the VIN voltage falling too
low or thermal shutdown.
Recovery from an output short-circuit (see below) may
involve another soft-start cycle if the FB voltage falls more
than 120mV (typical) below regulation. During such a
recovery, the FB voltage will quickly charge up to 120mV
(typical) and then follow the soft-start ramp until regula-
tion is reached.
Dropout Operation
As the input supply voltage approaches the output volt-
age, the duty cycle increases toward 100%. Further reduc-
tion of the supply voltage forces the PMOS to remain on
for more than one cycle, eventually reaching 100% duty
cycle. The output voltage will then be determined by the
input voltage minus the DC voltage drop across the inter-
nal PMOS and the inductor.
Low Supply Operation
The LTC3315A is designed to operate down to an input
supply voltage of 2.25V. An important thermal design
consideration is that the RDS(ON) of the power switches
increases at low input. Consider the worst case LTC3315A
power dissipation and die junction temperature at the low-
est input voltage.
Output Short-Circuit Protection and Recovery
The peak inductor current level at which the current com-
parator shuts off the PMOS is controlled by the error
amplifier. When the output current increases, the error
amplifier raises the internal VC voltage until the average
inductor current matches the load current. The LTC3315A
clamps the maximum internal V
C
voltage, thereby limiting
the peak inductor current.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during the downslope because
the voltage across the inductor is low. To keep the induc-
tor current in control a secondary limit is imposed on
the valley of the inductor current. If the inductor cur-
rent measured through the NMOS remains greater than
IVALLEY at the end of the cycle, the PMOS will be held
off. Subsequent switching cycles will be skipped until the
inductor current falls below IVALLEY.
Buck Switching Regulator Output Voltage and
Feedback Network
The output voltage of the buck switching regulators is
programmed by a resistor divider connected from the
switching regulator’s output to ground and is given by:
VOUT =VFB 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟(1)
as shown in Figure1 where VFB = 500mV. Typical val-
ues for R1 range from 40kΩ to 1MΩ. 1% resistors are
recommended to maintain output voltage accuracy. The
buck regulator transient response may improve with
an optional phase lead capacitor C
FF
that helps cancel
the pole created by the feedback resistors and the input
capacitance of the FB pin. Experimentation with capaci-
tor values between 2pF and 22pF may improve transient
response. The values used in the typical application cir-
cuits are a good starting point.
Figure1. Feedback Components
C
OUT
CFF
R2
VOUT
FB
3315ab F01
BUCK
SWITCHING
REGULATOR (OPTIONAL)
+
R1
LTC3315A
14
Rev. A
For more information www.analog.com
Operating Frequency Selection and Trade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response, and input
voltage range. The LTC3315A can operate at frequencies
between 1MHz and 3MHz.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
The minimum on-time of the buck regulator imposes a
minimum operating duty cycle. The highest switching
frequency (fSW(MAX)) for a given application can be cal-
culated as follows:
fSW(MAX) =
V
OUT
tON(MIN) • VIN(MAX)
(2
)
where VIN(MAX) is the maximum input voltage, VOUT is the
output voltage and tON(MIN) is the minimum top switch
on-time. This equation shows that a slower switching
frequency might be necessary to accommodate a high
VIN/VOUT ratio.
The LTC3315A is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the PMOS, the inductor DCR, and the load
current.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR, and
core loss.
Select the inductor value based on the following equations:
L≥VOUT
0.6A • fSW
• 1−VOUT
VIN(MAX)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟for VOUT
VIN(MAX)
≤0.5 (3
)
L≥VIN(MAX)
2.4A • fSW
for VOUT
VIN(MAX)
>0.5 (4)
where fSW is the switching frequency and VIN(MAX) is the
maximum applied input voltage.
To avoid overheating of the inductor, choose an inductor
with an RMS current rating that is greater than the maxi-
mum expected output load of the application. Overload and
short-circuit conditions need to be taken into consideration.
In addition ensure that the saturation current rating (typi-
cally labeled ISAT) is either higher than 3.5A, the maximum
current limit of the LTC3315A, or higher than the maximum
expected load plus half the inductor ripple:
ISAT >ILOAD(MAX) +1
2
ΔIL(5
)
where ILOAD(MAX) is the maximum output load current
for the application and ΔIL is the inductor ripple current
calculated as:
ΔIL=VOUT
L • fSW
• 1−VOUT
VIN
⎛
⎝
⎜
⎞
⎠
⎟(6)
To keep the efficiency high, choose an inductor with
the lowest series resistance (DCR) and a core material
intended for high frequency applications. Table1 shows
recommended inductors from several manufacturers.
Input Capacitors
Bypass the input of the LTC3315A with at least two ceramic
capacitors, one near each VIN pin for best performance.
Connect the ground of each capacitor to a wide PCB trace
on the top layer of the PCB that connects pins 8 and 9
with the exposed pad. These capacitors should be 0603
or 0805 in size. Smaller 0201 capacitors can also be
placed as close as possible to the LTC3315A directly on
the traces leading from VIN (Pin 7) and GND (Pin 8) and
on the traces leading from VIN (Pin 10) and GND (Pin 9)
to reduce input noise with minimal (if at all) increase in
application footprint. See the layout section for more
detail. X7R or X5R capacitors are recommended for best
performance across temperature and input voltage varia-
tions (see Table2). Note that larger input capacitance is
required when a lower switching frequency is used. If
the input power source has high impedance, or if there
APPLICATIONS INFORMATION
LTC3315A
15
Rev. A
For more information www.analog.com
is significant inductance due to long wires or cables, ad-
ditional bulk capacitance may be necessary. This can be
provided with an electrolytic capacitor
. A ceramic input
capacitor combined with trace or cable inductance forms
a high quality (underdamped) tank circuit. If the LTC3315A
circuit is plugged in to a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
voltage rating. This situation is easily avoided (see Linear
Technology Application Note 88).
Table2. Ceramic Capacitor Manufacturers
MANUFACTURER URL
AVX www.avxcorp.com
Murata www.murata.com
TDK www.tdk.com
Taiyo Yuden www.t-yuden.com
Samsung www.samsungsem.com
Wurth Elektronik www.we-online.com
Output Capacitor, Output Ripple, and Loop Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LTC3315A at the SW pin to produce the DC output. In
this role it determines the output ripple; thus, low imped-
ance at the switching frequency is important. The second
function is to store energy in order to satisfy transient
loads and to stabilize the LTC3315A’s control loop.
The LTC3315A is internally compensated and designed to
operate at a high bandwidth for fast transient response
capability. The selection of COUT affects the bandwidth of
the system, but the transient response is also affected by
APPLICATIONS INFORMATION
VOUT, VIN, fSW and other factors. A good place to start is
with an output capacitance value of approximately:
COUT =80µF •MHz
fSW
500mV
VOUT
(7
)
where COUT is the recommended output capacitor value
and fSW is the switching frequency. A lower value of output
capacitor saves space and cost, but transient performance
will suffer and loop stability must be verified. Ceramic ca-
pacitors have very low equivalent series resistance (ESR)
and provide the best output ripple and transient perfor-
mance. Use X5R or X7R ceramic capacitors. (see Table2).
Even better output ripple and transient performance can
be achieved by using low-ESL reverse geometry or three
terminal ceramic capacitors.
During a load step, the output capacitor must instantaneously
supply the current to support the load until the feedback
loop increases the switch current enough to support the
load. The time required for the feedback loop to respond
is dependent on the compensation components and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does the
output drop linearly. Although affected by VOUT, VIN, fSW,
tON(MIN), the equivalent series inductance (ESL) of the output
capacitor, and other factors, the output droop, VDROOP, is
usually about 3 times the linear drop of the first cycle:
VDROOP =
3 •
Δ
I
OUT
COUT • fSW
(8)
where ΔIOUT is the load step.
Table1. Recommended Inductors
MANUFACTURER FAMILY L (nH) MAX IDC (A) MAX DCR (mΩ) SIZE IN mm (L × W × H)
Murata DFE18SAN_G0 240 - 470 3.6 - 4.9 30 - 54 1.6 × 0.8 × 1.0
Murata DFE252010F 330 - 680 3.5 - 4.8 21 - 37 2.5 × 2.0 × 1.0
Vishay IHLP-1212BZ-11 220 - 1500 4.0 - 7.5 11.4 - 32 3.0 × 3.0 × 2.0
Vishay IHHP-0806AB-01 220 - 470 3.6 - 5.0 16 - 35 2.0 × 1.6 × 1.2
Wurth Elektronik WE-MAPI 330 - 1500 3.7 - 5.5 17 - 39 3.0 × 3.0 × 2.0
Wurth Elektronik WE-PMCI 250 - 470 3.6 - 4 12.5 - 31 3.2 × 2.5 × 1.2
Coilcraft XEL3515 72 - 560 3.2 - 23.7 6.5 - 16 3.5 × 3.2 × 1.5
LTC3315A
16
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Transient performance and control loop stability can
be improved with a higher COUT and/or the addition of
a feedforward capacitor, CFF, placed between VOUT and
FB. Capacitor CFF provides phase lead compensation by
creating a high frequency zero which improves the phase
margin and the high-frequency response. The values used
in the typical application circuits are a good starting point.
LTpowerCAD
®
is a useful tool to help optimize CFF and
COUT for the desired transient performance.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to experimentally verify
transient performance and control loop stability, and to
optimize CFF and COUT.
When using the load transient response method to stabilize
the control loop, apply an output current pulse going from
20% to 100% of full load current having a very fast rise
time. This will produce a transient on the output voltage.
Monitor VOUT for overshoot or ringing that might indicate
a stability problem (see Application Note 149).
Using the Precision Enable Threshold
The LTC3315A has precision threshold enable pins for
each buck regulator to enable or disable each buck. When
both are forced low, the device enters into a low current
shutdown mode.
The rising threshold of both EN comparators is 400mV,
with 50mV of hysteresis. The EN pins can be tied to VIN
if the shutdown feature is not used. Adding a resistor
divider from VIN to an EN pin to ground programs the
LTC3315A to regulate that output only when VIN is above
a desired voltage.
Typically, this threshold, VIN(EN), is used in situations
where the input supply is current limited, or has a rela-
tively high source resistance. A switching regulator draws
near constant power from its input source, so source cur-
rent increases as source voltage drops. This looks like
a negative resistance load to the source and can cause
the source to current limit or latch low under low source
voltage conditions. The VIN(EN) threshold prevents the
regulator from operating at source voltages where prob-
lems may occur. Referring to Figure2, this threshold can
Figure2. EN Divider
R4
VIN
EN
3315ab F02
BUCK
SWITCHING
REGULATOR R3
be adjusted by setting the values of R3 and R4 such that
they satisfy the following equation:
VIN(EN) =400mV • 1+R4
R3
⎛
⎝
⎜⎞
⎠
⎟(9)
The buck regulator will remain off until VIN is above
VIN(EN). The buck regulator will remain enabled until VIN
falls to 0.875 • VIN(EN) and EN is 350mV.
Alternatively a resistor divider from the output of one buck
to the EN pin of the second buck to ground provides event
based power-up sequencing as the first buck reaching
regulation enables the second buck. Replace V
IN(EN)
in
Equation 9 with the desired output voltage of the first buck
(e.g. 90% of the regulated value) at which the second
buck is enabled.
PCB Considerations
The LTC3315A is a high performance IC designed for high
efficiency and fast transient response. For optimal results
carefully consider the layout of the PCB board and follow
the below list to ensure proper operation. See Figure3 for
a recommended PCB layout.
1. Connect the exposed pad of the package (Pin 13)
directly to a large, unbroken ground plane under the
application circuit on the layer closest to the sur-
face layer to minimize thermal and electrical imped-
ance. Additionally, short the exposed pad to ground
pins 8 and 9 on the top layer. See the Analog Devices
Application Note, Application Notes for Thermally
Enhanced Leaded Plastic Packages for the proper size
and layout of the thermal vias and solder stencils.
2. Both of the input supply pins should have local decou-
pling capacitors with their grounded pins connecting
on the top layer to the ground plane around pin 8,
LTC3315A
17
Rev. A
For more information www.analog.com
GND
3315ab F03
GROUND
PLANE ON
LAYER 2
R1, R3 KELVIN
TO GND ON
LAYER 4 TO VIAS
ON EXPOSED
PAD, PIN 13
R4
R3
R1
R2
4
1
VOUT2
CFF2
CFF1
VOUT1
L2
L1
COUT2
7
COUT1
10
CIN2
CIN1
VIN
7
13
APPLICATIONS INFORMATION
Figure3. Recommended LTC3315A PCB Layout
pin 9, and the exposed pad. These capacitors provide
the AC current to the internal power MOSFETs and
their drivers. Large, switched currents flow in these
capacitors and it is important to minimize inductance
from these capacitors by choosing a small case size
such as 0603 and placing them close to the VIN pins
of theLTC3315A. To further minimize inductance and
input noise, smaller 0201 capacitors can be placed
as close as possible to the LTC3315A directly on the
traces leading from V
IN
(Pin7) and GND (Pin8) and on
the traces leading from VIN (Pin 10) and GND (Pin9)
minimal (if at all) increase in application footprint.
3. The switching power traces connecting SW1 and SW2
to their respective inductors should be minimized to
reduce radiated EMI and parasitic coupling. Due to
the large voltage swing on the switching nodes, high
input impedance sensitive nodes, such as the feedback
nodes, should be kept far away or shielded from the
switching nodes or poor performance couldresult.
4. The GND side of the switching regulator output capaci-
tors connects directly to the thermal ground plane
of the IC. Minimize the trace length from the output
capacitor to the inductor(s)/pin(s).
High Temperature Considerations
A thermal representation of the LTC3315A thermally
enhanced LQFN package is shown in Figure4 with the
silicon die and thermal metrics identified. The current
source represents power loss PD on the die; node voltages
represent temperatures; electrical impedances represent
conductive thermal impedances θ
JCBOTTOM
, θ
JCTOP
, θ
VIA
,
θCB, and convective thermal impedances θCA and θBA. The
junction temperature, TJ, is calculated from the ambient
temperature, TA, as:
TJ = TA + PD • θJA (11)
where, neglecting the θJCTOP + θCA path:
θJA ≈θJCB +
θ
CB
+θ
BA
2
⎛
⎝⎞
⎠!
θ
CB
+θ
BA
2
+θVIA
⎛
⎝⎞
⎠
(12)
where θJCB=θJCBOTTOM = 10°C/W. The value of
θJA=51°C/W reported in the Pin Configuration section
corresponds to JEDEC standard 2S2P test PCB, which
does not have good thermal vias, i.e., θ
VIA
is relatively
high. Assuming, somewhat arbitrarily but not unreason-
ably, that θVIA ~ (θCB + θBA)/2, and back calculating it is
seen that (θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board.
LTC3315A
18
Rev. A
For more information www.analog.com
Figure4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink
APPLICATIONS INFORMATION
θJCBOTTOM
θJCTOP
θCA
θCB
θCB
θCB
θCB θVIA
θBA
θBA
θBA
θBA
PCB
LQFN
TJ
TA
TA
TA
TA
PD
PCB
T
A
3315ab F04
DIE PACKAGE
SUBSTRATE
The importance of thermal vias becomes clear observing
that if the test PCB had low-thermal-resistance vias, the
θJA would have been reduced by up to 10°C/W, which is
an improvement of up to 20%. Similarly, having more
ground planes that are larger, uninterrupted and higher-
copper-weight improves θ
CB
+ θ
BA
, which has a dominant
effect on θJA, given the low value of θJCBOTTOM of the
package. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LTC3315A
is estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
LTC3315A
19
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
Dual 1.5V and 1.8V 2MHz, 2A Buck Regulators, VIN = 2.5V
470nH
22µF
200k
100k
3.3pF
10µF
470nH
261k
100k
10µF
22µF
3.3pF
1M
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
2.5V
VOUT2
V
OUT1
1.5V, 2A
V
OUT2
1.8V, 2A
fSW = 2MHz
1µF
0201
1µF
0201
3315A TA02
LTC3315A
20
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
Dual 1.2V and 0.8V 2MHz, 2A Buck Regulators, VIN = 3.3V
Dual 3.3V and 2.5V 2MHz, 2A Buck Regulators, VIN = 5V
680nH
33µF
140k
100k
6.8pF
10µF
560nH
60.4k
100k
10µF
33µF
10pF
1M
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
3.3V
VOUT1
V
OUT1
1.2V, 2A
V
OUT2
0.8V, 2A
fSW = 2MHz
3315A TA03
1.2µH
22µF
562k
100k
2.7pF
10µF
1.2µH
402k
100k
10µF
22µF
3.3pF
1M
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
5V
VIN
V
OUT1
3.3V, 2A
V
OUT2
2.5V, 2A
fSW = 2MHz
1µF
0201
1µF
0201
3315A TA04
LTC3315A
21
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
Dual 1.2V and 0.8V 3MHz, 2A Buck Regulators, VIN = 3.3V
Dual 1.2V and 0.8V 1MHz, 2A Buck Regulators, VIN = 3.3V
470nH
22µF
140k
100k
4.7pF
4.7µF
330nH
60.4k
100k
4.7µF
22µF
6.8pF
1M
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
3.3V
VIN
V
OUT1
1.2V, 2A
V
OUT2
0.8V, 2A
fSW = 3MHz
3315A TA06
3MHz
1.2µH
47µF
140k
100k
6.8pF
22µF
1.0µH
60.4k
100k
22µF
68µF
20pF
1M
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
3.3V
VIN
V
OUT1
1.2V, 2A
V
OUT2
0.8V, 2A
fSW = 1MHz
3315A TA05
1MHz
LTC3315A
22
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
LQFN Package
12-Lead (2mm × 2mm × 0.74mm)
(Reference LTC DWG # 05-08-1530 Rev B)
DETAIL B
A
PACKAGE TOP VIEW
5
PIN 1
CORNER
Y
X
aaa Z2×
12b
PACKAGE BOTTOM VIEW
4
6
SEE NOTES
E
D
b
e
e
b
E1
D1
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
H2
H1
L
DETAIL A
DETAIL C
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
0.7500
0.2500
0.2500
0.7500
0.2500
0.2500
DETAIL A
PIN 1 NOTCH
0.14 × 45°
11 12
6 5
1
4
10
7
aaa Z
2×
MX YZccc
MX YZccc
MX YZeee
MZfff
PACKAGE
OUTLINE
0.25 ±0.05
0.70 ±0.05
2.50 ±0.05
2.50 ±0.05
LQFN 12 0618 REV B
0.250
0.70
0.70
ddd Z
12×
Z
A1
DETAIL C
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
MIN
0.65
0.01
0.30
0.22
NOM
0.74
0.02
0.40
0.25
2.00
2.00
0.70
0.70
0.50
0.24 REF
0.50 REF
MAX
0.83
0.03
0.50
0.28
0.10
0.10
0.10
0.10
0.15
0.08
NOTES
DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. PRIMARY DATUM -Z- IS SEATING PLANE
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
5
4
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
6 THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
e
e/2
SUBSTRATE THK
MOLD CAP HT
LTC3315A
23
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 11/19 Added AEC-Q100 Qualified
Added #W Flow Part Numbers
1
2
LTC3315A
24
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2019
www.analog.com
11/19
RELATED PARTS
TYPICAL APPLICATION
Dual Buck Regulators with Supply Sequencing
880nH
33µF
140k
100k
6.8pF
10µF
1.0µH
261k
100k
10µF
22µF
4.7pF
1M
169k
100k
0.1µF
V
IN
SW1
SW2
PGOOD
EN2
MODE/SYNC
GND
EN1
V
IN
LTC3315A
VIN
2.25V TO 5.5V
VOUT1
V
OUT1
1.2V, 2A
V
OUT2
1.8V, 2A
fSW = 2MHz
3315A TA07
1µF
0201
1µF
0201
PART NUMBER DESCRIPTION COMMENTS
LTC3309A 6A, Low Voltage, Synchronous Step-Down
DC/DC in 2mm × 2mm LQFN
Monolithic Synchronous Step-Down DC/DC Capable of Supplying 6A at Switching
Frequencies Up to 3MHz. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output
Voltage Range with ±1% Accuracy. PGOOD Indication, RT Programming, SYNC Input.
2mm × 2mm LQFN
LTC3310S 10A, Low Voltage, Synchronous Step-Down
Silent Switcher
®
in 3mm × 3mm LQFN
Monolithic Synchronous Step-Down DC/DC Capable of Supplying 10A at Switching
Frequencies Up to 5MHz. Silent Switcher Architecture for Ultralow EMI Emissions.
2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with ±1%
Accuracy. PGOOD Indication, RT Programming, SYNC Input. Configurable for
Paralleling Power Stages. 3mm × 3mm LQFN
LTC3370/
LTC3371
4-Channel 8A Configurable 1A Buck DC/DCs Four Synchronous Buck Regulators with 8 × 1A Power Stages. Can Connect Up to Four
Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single
Inductor. 8 Output Configurations Possible. Precision PGOOD Indication. LTC3371
Has a Watchdog Timer. LTC3370: 32-Lead 5mm × 5mm QFN. LTC3371: 38-Lead
5mm × 7mm QFN and TSSOP
LTC3374/
LTC3374A
8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in
Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output
Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. 38-Lead
5mm × 7mm QFN and TSSOP
LTC3375 8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in
Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output
Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. I2C
Programming with a Watchdog Timer and Pushbutton. 48-Lead 7mm × 7mm QFN
LT8614 42V, 4A Synchronous Step-Down Silent
Switcher
®
with 2.5μA Quiescent Current
Synchronous Micropower Step-Down DC/DC Converter with Silent Switcher
Architecture. Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT. Up to 94% Efficiency
at 2MHz, 12VIN to 5VOUT. VIN: 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5μA, ISD <1μA,
18-Lead 3mm × 4mm QFN