Data Sheet
V1.2 2009-12
Microcontrollers
16/32-Bit
Architecture
XC2232N, XC2234N,
XC2236N, XC2238N
16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance
XC2000 Family / Value Line
Edition 2009-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein , any typical values stated herein and/or any
information regard ing the application of t he device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limit ation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements , compone nts may contain dangerous substances. For information on the types in
question, please cont act the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to ca use the failure
of that life-suppo rt device or system or to affect the safety or effectiveness of t hat device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human lif e. If they fa il, it is reasona ble to assume that th e healt h of the user or other per so ns may
be endangered.
Data Sheet
V1.2 2009-12
Microcontrollers
16/32-Bit
Architecture
XC2232N, XC2234N,
XC2236N, XC2238N
16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance
XC2000 Family / Value Line
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Data Sheet 4 V1.2, 2009-12
9
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
XC223xN Data Sheet
Revision History: V1.2 2009-12
Previous Versions:
V1.1, 2009-07
V1.0, 2009-03 Preliminary
Page Subjects (major changes since last revision)
10 Special device types XC2232N-24FxL and XC2232N-40FxL added.
Configuration of special device types adjusted to match with order book.
We Listen to Your Comments
Is there any info rmation in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve th e quality of this document.
Please send your proposal (includin g a reference to this document) to:
mcdocu.comments@infineon.com
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Table of Contents
Data Sheet 5 V1.2, 2009-12
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Basic Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Special Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4 Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7 Capture/Compare Unit (CC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8 Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.9 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.10 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.11 A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.12 Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . 50
3.13 MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.14 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.15 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.16 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.17 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.19 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.1.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Voltage Range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.1 DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3.2 DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 68
4.3.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.4 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table of Contents
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Table of Contents
Data Sheet 6 V1.2, 2009-12
4.7 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.7.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.7.2 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.7.2.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.7.2.2 Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.2.3 Selecting and Changing the Operating Frequency . . . . . . . . . . . . . . 89
4.7.3 External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.7.4 Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.7.5 Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.7.6 Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.2 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 7 V1.2, 2009-12
16/32-Bit Single-Chip Microcontrol ler
with 32-Bit Performance
XC223xN (XC2000 Family)
1 Summary of Features
For a quick overview and easy reference, the features of the XC223xN are summarized
here.
• High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for cod e and data
– 1,024 Bytes on-chip special function registe r area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
• Interrupt system with 16 priority levels providing 96 interrupt nodes
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
• Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
• Clock generation from internal or external clock sources,
using on-ch i p PL L or p rescaler
• Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
• On-chip memory modules
– 8 Kbytes on-chip stand-by RAM (SBRAM)
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– Up to 16 Kbytes on-chip data SRAM (DSRAM)
– Up to 16 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 320 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 8 V1.2, 2009-12
• On-Chip Peripheral Modules
– Two synchronizable A/D Converters with up to 9 channels, 10-bi t resolution,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– 16-channel general purpose capture/compare unit (CC2)
– Two capture/compare units for flexible PWM signal generation (CCU6x)
– Multi-functional general purpose timer unit with 5 timers
– Up to 6 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 256 message objects
(Full CAN/Basic CAN) on 6 CAN node
– On-chip system timer and on-chip real time clock
• Single power supply from 3.0 V to 5.5 V
• Power reduction and wake-up modes with flexible power management
• Programmable watchdog timer and oscillator watchdog
• Up to 40 general purpose I/O lines
• On-chip bootstrap loaders
• Supported by a full range of development tools including C compilers, macro-
assembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
• On-chip debug support via Device Access Port (DAP) or JTAG interface
• 64-pin Green LQFP package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering co de identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the temperature range:
– SAF-…: -40°C to 85°C
– SAK-…: -40°C to 125°C
• the package and the type of delivery.
For ordering codes for the XC223xN please contact your sales representative or local
distributor.
This document describes se veral derivatives of the XC223xN group:
Basic Device Types are readily available and
Special Device Types are only available on request.
As this document refers to all of these derivatives, some descriptions may not apply to a
specific product, in particular to the special device types.
For simplicity the term XC223xN is used for all derivative s throug hout this document.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 9 V1.2, 2009-12
1.1 Basic Device Types
Basic device types are available and can be ordered through Infineon’s direct and/or
distribution channels. The devices are available for the SAK temperature range only.
Table 1 Synopsis of XC223xN Basic Devic e Typ es
Derivative1)
1) The 80 MHz type is marked ...80L. The 40 MHz type is marked ...40L.
Flash
Memory2)
2) Specific information about the on-chip Flash memory in Table 3.
PSRAM
DSRAM3)
3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM.
Capt./Comp.
Modules4)
4) Due to bonding limitations in the XC223xN devices only a subset of the CCU61 features can be used. The
module has the T12 and T13 timer inputs and no outputs connected. Therefore only CCU61 timers can be
triggered from external. This can typically be used for periodic triggering of ADCs.
ADC5)
Chan.
5) Specific information about the ava ilable channels in Table 5.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
Interfaces5)
XC2236N-24F40L 192 Kbytes 8 Kbytes
8 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
4 Serial Chan.
XC2236N-40F80L 320 Kbytes 16 Kbytes
16 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
4 Serial Chan.
XC2238N-40F80L 320 Kbytes 16 Kbytes
16 Kbytes CC2
CCU60/1 7 + 2 6 CAN Node,
6 Serial Chan.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 10 V1.2, 2009-12
1.2 Special Device Types
Special device types are only available for high-volume applications on request. The
devices are available for the SAK an d SAF temperature ranges.
Table 2 Synopsis of XC223xN Special Device Types
Derivative1)
1) x is a placeholder for available speed grade in MHz. Can be 20, 40, 66 or 80.
Flash
Memory2)
2) Specific information about the on-chip Flash memory in Table 3.
PSRAM
DSRAM3)
3) All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM.
Capt./Comp.
Modules4)
4) Due to bonding limitations in the XC223xN devices only a subset of the CCU61 features can be used. The
module has the T12 and T13 timer inputs and no outputs connected. Therefore only CCU61 timers can be
triggered from external. This can typically be used for periodic triggering of ADCs.
ADC5)
Chan.
5) Specific information about the ava ilable channels in Table 5.
Analog input channels are listed for each Analog/Digital Converter module separately (ADC0 + ADC1).
Interfaces5)
XC2232N-40FxL 320 Kbytes 16 Kbytes
16 Kbytes CC2
CCU60/1 7 + 2 3 CAN Nodes,
6 Serial Chan.
XC2232N-24FxL 192 Kbytes 8 Kbytes
8 Kbytes CC2
CCU60/1 7 + 2 3 CAN Nodes,
6 Serial Chan.
XC2232N-8FxL 64 Kbytes 4 Kbytes
4 Kbytes CC2
CCU60/1 7 + 2 3 CAN Nodes,
6 Serial Chan.
XC2234N-40FxL 320 Kbytes 16 Kbytes
16 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
2 Serial Chan.
XC2234N-24FxL 192 Kbytes 8 Kbytes
8 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
2 Serial Chan.
XC2234N-16FxL 128 Kbytes 4 Kbytes
4 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
2 Serial Chan.
XC2236N-40FxL 320 Kbytes 16 Kbytes
16 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
4 Serial Chan.
XC2236N-24FxL 192 Kbytes 8 Kbytes
8 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
4 Serial Chan.
XC2236N-16FxL 128 Kbytes 4 Kbytes
4 Kbytes CC2
CCU60/1 7 + 2 1 CAN Node,
4 Serial Chan.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 11 V1.2, 2009-12
1.3 Definition of Feature Variants
The XC223xN types are offered with several Flash memory sizes. Table 3 and Table 4
describe the location of the avai lable Flash memory.
The XC223xN types are offered with different interface options. Table 5 lists the
available channels for each option.
Table 3 Continuous Flash Memory Ranges
Total Flash Size 1st Range1)
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for int ernal use (C0’F000H to C0’FFFFH).
2nd Range 3rd Range
320 Kbytes C0’0000H …
C0’EFFFH
C1’0000H …
C4’FFFFH
n.a.
192 Kbytes C0’0000H …
C0’EFFFH
C1’0000H …
C1’FFFFH
C4’0000H …
C4’FFFFH
128 Kbytes C0’0000H …
C0’EFFFH
C4’0000H …
C4’FFFFH
n.a.
64 Kbytes C0’0000H …
C0’EFFFH
n.a. n.a.
Table 4 Flash Memory Mod ul e Allocation (in Kbytes)
Total Flash Size Flash 01)
1) The uppermost 4-Kbyte sector of the fi rst Flash segmen t is reserved for internal use (C0’F000 H to C0’FFFFH).
Flash 1
320 256 64
192 128 64
128 64 64
64 64 -
Table 5 Interface Channel Association
Total Number Available Channels / Message Objects
7 ADC0 channels CH0, CH2, CH4, CH8, CH10, CH13, CH15
2 ADC1 channels CH0, CH4
1 CAN node CAN0
64 message objects
2 CAN nodes CAN0, CAN1
64 message objects
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Summary of Features
Data Sheet 12 V1.2, 2009-12
The XC223xN types are offered with several SRAM memory sizes. Figure 1 shows the
allocation rules for PSRAM and DSRAM. Note that the rules differ:
• PSRAM allocation starts from the lower address
• DSRAM allocation starts from the higher address
For example 8 Kbytes of PSRAM will be allocated at E0’0000h-E0’1 FFFh and 8 Kbytes
of DSRAM will be at 00’C000h-00’DFFFh.
Figure 1 SRAM Allocation
3 CAN nodes CAN0, CAN1, CAN2
64 message objects
6 CAN nodes CAN0, CAN1, CAN2, CAN3, CAN4, CAN5
256 message objects
2 serial channels U0C0, U0C1
4 serial channels U0C0, U0C1, U1C0, U1C1
6 serial channels U0C0, U0C1, U1C0, U1C1, U2C0, U2C1
Table 5 Interface Channel Association (cont’d)
Total Number Available Channels / Message Objects
MC_XC_SRAM_ALLOCATION
Available
PSRAM
Reserved for
PSRAM
E0'0000h
(E8'0000h)
Available
DSRAM
Reserved for
DSRAM
E7'FFFFh
(EF'FFFFh)
00'8000h
00'DFFFh
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 13 V1.2, 2009-12
2 General Device Information
The XC223xN series (16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance) is a part of the Infineon XC2000 Family of full-feature single-
chip CMOS microcontrollers. These devices extend the functionality and performance of
the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They
combine high CPU performance (up to 80 million instructions per second) with extended
peripheral functionality and enhanced IO capabilities. Optimized peripherals can be
adapted flexibly to meet the application requirements. These derivatives utilize clock
generation via PLL and internal or external clock sources. On-chip memory modules
include program Flash, program RAM, and data RAM.
Figure 2 XC223xN Lo gic Symbol
MC_XY_LOGSYMB64
Po rt 2
11 bit
Po rt 6
2 bit
Po rt 7
1 bit
V
AGND
(1)
V
AREF
(1)
V
DDP
(9)
V
SS
(4)
V
DDI
(4)
XTAL1
XTAL2
ESR0
Port 10
16 bit
Port 15
2 bit
Port 5
7 bit
via Port Pins
DAP/JTAG
2 / 4 bit
TRST Debug
2 bit
TESTM
PORST
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 14 V1.2, 2009-12
2.1 Pin Configuration and Definit ion
The pins of the XC223xN are described in detail in Table 6, which includes all alternate
functions. For further explanat ions please refer to the footnotes at the end of the table.
The following figure summarizes all pins, showing their locations on the four sides of the
package.
Figure 3 XC223xN Pin Configuration (top view)
MC_XY_PIN64
V
DDPA
16
P15.0
15
14
13
P6.1
12
P6.0
11
V
DDIM
10
9
8
7
6
5
TRST 4
TESTM 3
V
DDPB
2
V
SS
1
P7.0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
V
DDPB
ESR0
PORST
XTAL1
XTAL2
P10.15
P10.14
V
DDI1
P10.13
P10.12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
SS
V
DDPB
P5.8
P5.10
P5.13
P5.15
V
DDI1
P2.0
P2.1
P2.2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10.2
V
DDI1
P2.10
P10.3
P10.4
P10.5
P10.6
P10.7
V
DDPB
LQFP64
P15.4
P5.4
V
AREF
V
AGND
P5.0
P5.2
V
DDPB
V
SS
V
DDPB
P10.0
P10.1
P2.9
P2.7
P2.8
P10.11
P10.10
P10.9
P10.8
V
DDPB
V
SS
V
DDPB
P2.3
P2.4
P2.5
P2.6
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 15 V1.2, 2009-12
Key to Pin Definitions
•Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
•Type: Indicates the pad type and its power supply domain (A, B, M, 1).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DP: Double pad - can be used as standard or high speed pad
– In: Input only pad
– PS: Power supply pad
Table 6 Pin Definitions and Functions
Pin Symbol Ctrl. Type Function
3 TESTM IIn/BTestmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pull-up de vice will hold this pin high
when nothing is driving it.
4TRST IIn/BTest-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC223xN’s debug
system. In this case, pin TRST must be driven low
once to reset the debug system.
An internal pull-down device will hold this pin low
when nothing is driving it.
5 P7.0 O0 / I St/B Bit 0 of Port 7, General Purpose Input/Output
T3OUT O1 St/B GPT12E Timer T3 Toggle Latch Output
T6OUT O2 St/B GPT12E Timer T6 Toggle Latch Output
TDO_A OH /
IH St/B JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 0 or 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
ESR2_1 I St/B ESR2 Trigger Input 1
RxDC4B I St/B CAN Node 4 Receive Data Input
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 16 V1.2, 2009-12
7 P6.0 O0 / I DA/A Bit 0 of Port 6, General Purpose Input/Output
EMUX0 O1 DA/A External Analog MUX Control Output 0 (ADC0)
TxDC2 O2 DA/A CAN Node 2 Transmit Data Output
BRKOUT O3 DA/A OCDS Break Sig nal Output
ADCx_
REQGTyG IDA/AExternal Request Gate Input for ADC0/1
U1C1_DX0E I DA/A USIC1 Channel 1 Shift Data Input
8 P6.1 O0 / I DA/A Bit 1 of Port 6, General Purpose Input/Output
EMUX1 O1 DA/A External Analog MUX Control Output 1 (ADC0)
T3OUT O2 DA/A GPT12E Timer T3 Toggle Latc h Ou tpu t
U1C1_DOUT O3 DA/A USIC1 Channel 1 Shift Data Output
ADCx_
REQTRyE IDA/AExternal Request Trigger Input for ADC0/1
RxDC2E I DA/A CAN Node 2 Receive Data Input
ESR1_6 I DA/A ESR1 Trigger Input 6
10 P15.0 I In/A Bit 0 of Port 15, General Purpose Input
ADC1_CH0 I In/A An alog Input Channel 0 for ADC1
11 P15.4 I In/A Bit 4 of Port 15, General Purpose Input
ADC1_CH4 I In/A An alog Input Channel 4 for ADC1
T6INA I In/A GPT12E Timer T6 Count/Ga te In pu t
12 VAREF - PS/A Reference Voltage for A/D Converters ADC0/1
13 VAGND - PS/A Reference Ground for A/D Converters ADC0/1
14 P5.0 I In/A Bit 0 of Port 5, General Purpose Input
ADC0_CH0 I In/A An alog Input Channel 0 for ADC0
15 P5.2 I In/A Bit 2 of Port 5, General Purpose Input
ADC0_CH2 I In/A An alog Input Channel 2 for ADC0
TDI_A I In/A JTAG Test Da ta Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 17 V1.2, 2009-12
19 P5.4 I In/A Bit 4 of Port 5, General Purpose Input
ADC0_CH4 I In/A An alog Input Channel 4 for ADC0
T3EUDA I In/A GPT12E Timer T3 Exte rnal Up/Down Cont rol
Input
TMS_A I In/A JTAG Test Mode Selection Input
20 P5.8 I In/A Bit 8 of Port 5, General Purpose Input
ADC0_CH8 I In/A An alog Input Channel 8 for ADC0
ADC1_CH8 I In/A An alog Input Channel 8 for ADC1
CCU6x_
T12HRC IIn/AExternal Run Control Input for T12 of CCU60/1
CCU6x_
T13HRC IIn/AExternal Run Control Input for T13 of CCU60/1
U2C0_DX0F I In/A USIC2 Channel 0 Shift Data Input
21 P5.10 I In/A Bit 10 of Port 5, General Purpose Inp ut
ADC0_CH10 I In/A Analog Input Channel 10 for ADC0
ADC1_CH10 I In/A Analog Input Channel 10 for ADC1
BRKIN_A IIn/AOCDS Break Signal Input
U2C1_DX0F I In/A USIC2 Channel 1 Shift Data Input
CCU61_
T13HRA IIn/AExternal Run Control Input for T13 of CCU61
22 P5.13 I In/A Bit 13 of Port 5, General Purpose Inp ut
ADC0_CH13 I In/A Analog Input Channel 13 for ADC0
23 P5.15 I In/A Bit 15 of Port 5, General Purpose Inp ut
ADC0_CH15 I In/A Analog Input Channel 15 for ADC0
RxDC2F I In/A CAN Node 2 Receive Data Input
25 P2.0 O0 / I St/B Bit 0 of Port 2, General Purpose Input/Output
TxDC5 O1 St/B CAN Node 5 Transmit Data Output
RxDC0C I St/B CAN Node 0 Receive Data Input
T5INB I St/B GPT12E Timer T5 Count/G a te In pu t
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 18 V1.2, 2009-12
26 P2.1 O0 / I St/B Bit 1 of Port 2, General Purpose Input/Output
TxDC0 O1 St/B CAN Node 0 Transmit Data Output
RxDC5C I St/B CAN Node 5 Receive Data Input
T5EUDB I St/B G PT12E Timer T5 External Up/Down Control
Input
ESR1_5 I St/B ESR1 Trigger Input 5
27 P2.2 O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output
TxDC1 O1 St/B CAN Node 1 Transmit Data Output
ESR2_5 I St/B ESR2 Trigger Input 5
28 P2.3 O0 / I St/B Bit 3 of Port 2, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
CC2_CC16 O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out.
ESR2_0 I St/B ESR2 Trigger Input 0
U0C0_DX0E I St/B USIC0 Channel 0 Shift Data Input
U0C1_DX0D I St/B USIC0 Channel 1 Shift Data Input
RxDC0A I St/B CAN Node 0 Receive Data Input
TxDC2 O2 St/B CAN Node 2 Transmit Data Output
29 P2.4 O0 / I St/B Bit 4 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
TxDC0 O2 St/B CAN Node 0 Transmit Data Output
CC2_CC17 O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out.
ESR1_0 I St/B ESR1 Trigger Input 0
U0C0_DX0F I St/B USIC0 Channel 0 Shift Data Input
RxDC1A I St/B CAN Node 1 Receive Data Input
30 P2.5 O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output
U0C0_
SCLKOUT O1 St/B USIC0 Channel 0 Shift Clock Output
TxDC0 O2 St/B CAN Node 0 Transmit Data Output
CC2_CC18 O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out.
U0C0_DX1D I St/B USIC0 Channel 0 Shift Clock Input
ESR1_10 I St/B ESR1 Trigger Input 10
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 19 V1.2, 2009-12
31 P2.6 O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output
U0C0_
SELO0 O1 St/B USIC0 Channel 0 Se lect/Control 0 Output
U0C1_
SELO1 O2 St/B USIC0 Channel 1 Se lect/Control 1 Output
CC2_CC19 O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out.
U0C0_DX2D I St/B USIC0 Channel 0 Shift Control Input
RxDC0D I St/B CAN Node 0 Receive Data Input
ESR2_6 I St/B ESR2 Trigger Input 6
35 P2.7 O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output
U0C1_
SELO0 O1 St/B USIC0 Channel 1 Se lect/Control 0 Output
U0C0_
SELO1 O2 St/B USIC0 Channel 0 Se lect/Control 1 Output
CC2_CC20 O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out.
U0C1_DX2C I St/B USIC0 Channel 1 Shift Control Input
RxDC1C I St/B CAN Node 1 Receive Data Input
ESR2_7 I St/B ESR2 Trigger Input 7
36 P2.8 O0 / I DP/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_
SCLKOUT O1 DP/B USIC0 Chan nel 1 Shift Clock Output
EXTCLK O2 DP/B Programmable Clock Signal Output
CC2_CC21 O3 / I DP/B CAPCOM2 CC21IO Capture Inp./ Compare Out.
U0C1_DX1D I DP/B USIC0 Channel 1 Shift Clock Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 20 V1.2, 2009-12
37 P2.9 O0 / I St/B Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
TxDC1 O2 St/B CAN Node 1 Transmit Data Output
CC2_CC22 O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out.
CLKIN1 I St/B Clock Signal Input 1
TCK_A IH St/B DAP0/JTAG Clock Input
If JTAG pos. A is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
If DAP pos. 0 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
38 P10.0 O0 / I St/B Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
CCU60_
CC60 O2 St/B CCU60 Ch annel 0 Output
CCU60_
CC60INA ISt/BCCU60 Channel 0 Input
ESR1_2 I St/B ESR1 Trigger Input 2
U0C0_DX0A I St/B USIC0 Channel 0 Shift Data Input
U0C1_DX0A I St/B USIC0 Channel 1 Shift Data Input
39 P10.1 O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
CCU60_
CC61 O2 St/B CCU60 Ch annel 1 Output
CCU60_
CC61INA ISt/BCCU60 Channel 1 Input
U0C0_DX1A I St/B USIC0 Channel 0 Shift Clock Input
U0C0_DX0B I St/B USIC0 Channel 0 Shift Data Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 21 V1.2, 2009-12
40 P10.2 O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output
U0C0_
SCLKOUT O1 St/B USIC0 Channel 0 Shift Clock Output
CCU60_
CC62 O2 St/B CCU60 Ch annel 2 Output
CCU60_
CC62INA ISt/BCCU60 Channel 2 Input
U0C0_DX1B I St/B USIC0 Channel 0 Shift Clock Input
42 P2.10 O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
U0C0_
SELO3 O2 St/B USIC0 Channel 0 Se lect/Control 3 Output
CC2_CC23 O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out.
U0C1_DX0E I St/B USIC0 Channel 1 Shift Data Input
CAPINA I St/B GPT12E Register CAPREL Capture Input
43 P10.3 O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output
CCU60_
COUT60 O2 St/B CCU60 Ch annel 0 Output
U0C0_DX2A I St/B USIC0 Channel 0 Shift Control Input
U0C1_DX2A I St/B USIC0 Channel 1 Shift Control Input
44 P10.4 O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output
U0C0_
SELO3 O1 St/B USIC0 Channel 0 Se lect/Control 3 Output
CCU60_
COUT61 O2 St/B CCU60 Ch annel 1 Output
U0C0_DX2B I St/B USIC0 Channel 0 Shift Control Input
U0C1_DX2B I St/B USIC0 Channel 1 Shift Control Input
ESR1_9 I St/B ESR1 Trigger Input 9
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 22 V1.2, 2009-12
45 P10.5 O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output
U0C1_
SCLKOUT O1 St/B USIC0 Channel 1 Shift Clock Output
CCU60_
COUT62 O2 St/B CCU60 Ch annel 2 Output
U2C0_DOUT O3 St/B USIC2 Channel 0 Shift Data Output
U0C1_DX1B I St/B USIC0 Channel 1 Shift Clock Input
46 P10.6 O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
TxDC4 O2 St/B CAN Node 4 Transmit Data Output
U1C0_
SELO0 O3 St/B USIC1 Channel 0 Se lect/Control 0 Output
U0C0_DX0C I St/B USIC0 Channel 0 Shift Data Input
U1C0_DX2D I St/B USIC1 Channel 0 Shift Control Input
CCU60_
CTRAPA ISt/BCCU60 Emergency Trap Input
47 P10.7 O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
CCU60_
COUT63 O2 St/B CCU60 Ch annel 3 Output
U0C1_DX0B I St/B USIC0 Channel 1 Shift Data Input
CCU60_
CCPOS0A ISt/BCCU60 Position Input 0
RxDC4C I St/B CAN Node 4 Receive Data Input
T4INB I St/B GPT12E Timer T4 Count/G a te In pu t
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 23 V1.2, 2009-12
51 P10.8 O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output
U0C0_
MCLKOUT O1 St/B USIC0 Channel 0 Ma ster Clock Output
U0C1_
SELO0 O2 St/B USIC0 Channel 1 Se lect/Control 0 Output
U2C1_DOUT O3 St/B USIC2 Channel 1 Shift Data Output
CCU60_
CCPOS1A ISt/BCCU60 Position Input 1
U0C0_DX1C I St/B USIC0 Channel 0 Shift Clock Input
BRKIN_B ISt/BOCDS Break Signal Input
T3EUDB I St/B G PT12E Timer T3 External Up/Down Control
Input
52 P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output
U0C0_
SELO4 O1 St/B USIC0 Channel 0 Se lect/Control 4 Output
U0C1_
MCLKOUT O2 St/B USIC0 Channel 1 Ma ster Clock Output
CCU60_
CCPOS2A ISt/BCCU60 Position Input 2
TCK_B IH St/B DAP0/JTAG Clock Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
If DAP pos. 1 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
T3INB I St/B GPT12E Timer T3 Count/G a te In pu t
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 24 V1.2, 2009-12
53 P10.10 O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output
U0C0_
SELO0 O1 St/B USIC0 Channel 0 Se lect/Control 0 Output
CCU60_
COUT63 O2 St/B CCU60 Ch annel 3 Output
U0C0_DX2C I St/B USIC0 Channel 0 Shift Control Input
U0C1_DX1A I St/B USIC0 Channel 1 Shift Clock Input
TDI_B IH St/B JTAG Test Data Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
54 P10.11 O0 / I St/B Bit 11 of Port 10, General Purpose Input/Output
U1C0_
SCLKOUT O1 St/B USIC1 Channel 0 Shift Clock Output
BRKOUT O2 St/B OCDS Break Signal Output
U1C0_DX1D I St/B USIC1 Channel 0 Shift Clock Input
RxDC2B I St/B CAN Node 2 Receive Data Input
TMS_B IH St/B JTAG Test Mode Selection Input
If JTAG pos. B is selected during start-up, an
internal pull-up device will hold this pin high when
nothing is driving it.
55 P10.12 O0 / I St/B Bit 12 of Port 10, General Purpose Input/Output
U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output
TxDC2 O2 St/B CAN Node 2 Transmit Data Output
TDO_B OH /
IH St/B JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 1 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
U1C0_DX0C I St/B USIC1 Channel 0 Shift Data Input
U1C0_DX1E I St/B USIC1 Channel 0 Shift Clock Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 25 V1.2, 2009-12
56 P10.13 O0 / I St/B Bit 13 of Port 10, General Purpose Input/Output
U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output
TxDC3 O2 St/B CAN Node 3 Transmit Data Output
U1C0_
SELO3 O3 St/B USIC1 Channel 0 Se lect/Control 3 Output
U1C0_DX0D I St/B USIC1 Channel 0 Shift Data Input
58 P10.14 O0 / I St/B Bit 14 of Port 10, General Purpose Input/Output
U1C0_
SELO1 O1 St/B USIC1 Channel 0 Se lect/Control 1 Output
U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output
ESR2_2 I St/B ESR2 Trigger Input 2
U0C1_DX0C I St/B USIC0 Channel 1 Shift Data Input
RxDC3C I St/B CAN Node 3 Receive Data Input
59 P10.15 O0 / I St/B Bit 15 of Port 10, General Purpose Input/Output
U1C0_
SELO2 O1 St/B USIC1 Channel 0 Se lect/Control 2 Output
U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output
U1C0_DOUT O3 St/B USIC1 Channel 0 Shift Data Output
U0C1_DX1C I St/B USIC0 Channel 1 Shift Clock Input
60 XTAL2 O Sp/M Crystal Oscillator Amplifier Output
61 XTAL1 I Sp/M Crystal Oscillator Amplifier In pu t
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM.
ESR2_9 I St/B ESR2 Trigger Input 9
62 PORST IIn/BPower On Reset Input
A low level at this pin resets the XC223xN
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum durati on for a safe recognition
should be 120 ns.
An internal pull-up de vice will hold this pin high
when nothing is driving it.
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 26 V1.2, 2009-12
63 ESR0 O 0 / I St/B External Service Request 0
After power-up, ESR0 operates as open-drain
bidirectional reset with a weak pull-up.
U1C0_DX0E I St/B USIC1 Channel 0 Shift Data Input
U1C0_DX2B I St/B USIC1 Channel 0 Shift Control Input
6VDDIM - PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Data
Sheet for details.
24,
41,
57
VDDI1 - PS/1 Digital Core Supply Voltage for Domain 1
Decouple with a ceramic capacitor, see Data
Sheet for details.
All VDDI1 pins must be connected to each other.
9VDDPA - PS/A Digital Pad Supply Voltage for Domain A
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The A/D_Converters and ports P5, P6 and
P15 are fed from supply voltage VDDPA.
2,
16,
18,
32,
34,
48,
50,
64
VDDPB - PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regu lators and all po rts
except P5, P6 and P15 are fed from supply
voltage VDDPB.
1,
17,
33,
49
VSS - PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected
internally to VSS. To improve the EMC
behavior, it is recommended to connect th e
exposed pad to the board ground.
For thermal aspects, please refer to the
Data Sheet. Board layout examples are
given in an application note.
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
General Device Information
Data Sheet 27 V1.2, 2009-12
2.2 Identification Registers
The identification registers describe the current version of the XC223xN and of its
modules.
Table 7 XC223xN Identification Registers
Short Name Value Address Notes
SCU_IDMANUF 1802H00’F07EH
SCU_IDCHIP 3002H00’F07CH
SCU_IDMEM 304FH00’F07AH
SCU_IDPROG 1313H00’F078H
JTAG_ID 0018’B083H---
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 28 V1.2, 2009-12
3 Functional Description
The architecture of the XC223xN combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 4). This bus structure enhances overall system performance by
enabling the concurrent op eration of several subsystems of the XC223xN.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC223xN.
Figure 4 Block Diagram
DPRAM
CPU
PMU
DMU
ADC0
Module
8-/10-
Bit
RTC
MCHK
Interrupt & PEC
EBC
LXBus Control
External Bus
Control
DSRAM
System Functions
Clock, Reset, Power
Control, StandBy RAM
OCDS
Debug Support
Interrupt Bus
Peripheral Data Bus
Analog and Digital General Purpose IO (GPIO) Ports
MC_N-SERIES_BLOCKDIAGRAM
GPT
5
Timers
CC2
Module
16
Chan.
LXBus
WDT
Multi
CAN
CCU6x
Modules
3+1
Chan.
each
USICx
Modules
2
Chan.
each
PSRAM
Flash Memory
IMB
MAC Unit
MPU
ADC1
Module
8-/10-
Bit
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 29 V1.2, 2009-12
3.1 Memory Subsystem and Organization
The memory space o f the XC223xN is con figured in the von Ne umann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8 XC223xN Memory Map 1)
Address Area Start Loc. End Loc. Area Size2) Notes
IMB register space FF’FF00HFF’FFFFH256 Bytes
Reserved F0’0000HFF’FEFFH< 1 Mbyte Minus IMB registers
Reserved for EPSRAM E8’4000HEF’FFFFH496 Kbytes Mirrors EPSRAM
Emulated PSRAM E8’0000HE8’3FFFHup to
16 Kbytes With F lash timing
Reserved for PSRAM E0’4000HE7’FFFFH496 Kbytes Mirrors PSRAM
PSRAM E0’0000HE0’3FFFHup to
16 Kbytes Program SRAM
Reserved for Flash C5’0000HDF’FFFFH1,728 Kbytes
Flash 1 C4’0000HC4’FFFFH64 Kbytes
Flash 0 C0’0000HC3’FFFFH256 Kbytes3) Minus res. seg.
External memory area 40’0000HBF’FFFFH8 Mbytes
External IO area4) 21’0000H3F’FFFFH1,984 Kbytes
Reserved 20’BC00H20’FFFFH17 Kbytes
USIC0–2 alternate regs. 20’B000H20’BBFFH3 Kbytes Accessed via EBC
MultiCAN alternate regs. 20’8000H20’AFFFH12 Kbytes Accessed via EBC
Reserved 20’5800H20’7FFFH10 Kbytes
USIC0–2 registers 20’4000H20’57FFH6 Kbytes Accessed via EBC
Reserved 20’6800H20’7FFFH6 Kbytes
MultiCAN registers 20’0000H20’3FFFH16 Kbytes Accessed via EBC
External memory area 01’0000H1F’FFFFH1984 Kbytes
SFR area 00’FE00H00’FFFFH0.5 Kbytes
Dualport RAM (DPRAM) 00’F600H00’FDFFH2 Kbytes
Reserved for DPRAM 00’F200H00’F5FFH1 Kbytes
ESFR area 00’F000H00’F1FFH0.5 Kbytes
XSFR area 00’E000H00’EFFFH4 Kbytes
Data SRAM (DSRAM) 00’A000H00’DFFFH16 Kbytes
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 30 V1.2, 2009-12
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Po rti ons of the o n-chip D PRAM an d th e
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These inclu de peripheral s on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Up to 16 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write- protected.
Note: The actual size of the PSRAM depends on the quoted device type.
Reserved for DSRAM 00’8000H00’9FFFH8 Kbytes
External memory area 00’0000H00’7FFFH32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicat ed, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for int ernal use (C0’F000H to C0’FFFFH).
4) Several pipeline optimizations are not active with in the ext ernal IO area. This is necessary to control external
peripherals properly.
Table 8 XC223xN Memory Map (cont’d)1)
Address Area Start Loc. End Loc. Area Size2) Notes
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 31 V1.2, 2009-12
Up to 16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user
data. The DSRAM is accessed via a separate interface and is optimized for data access.
Note: The actual size of the DSRAM depends on the quoted device type.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for genera l purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
8 Kbytes of on-chip Stand-By SRAM (SBRAM) provide storage for system-relevant
user data that must be preserved while the major part of the device is powered down.
The SBRAM is accessed via a specific interface and is powered in domain M.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family. In order to ensure
upward compatibility they should either not be accessed or written with zeros.
In order to meet the requirements of designs where more memory is required than is
available on chip, up to 12 Mbytes (approximately, see Table 8) of external RAM and/or
ROM can be connected to the microcontroller. The External Bus Interface also provides
access to external peripherals.
The on-chip Flash memory stores code, constant data, and control data. The
320 Kbytes of on-chip Flash memory consist of 1 module of 64 Kbytes (preferably for
data storage) and 1 module of 256 Kbytes. Each module is organized in 4-Kbyte sectors.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Note: The actual size of the Flash memory depends on the chosen device type.
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The co mplete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with pr otected and efficien t writing algorithms for pr ogramming and erasing .
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.6.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 32 V1.2, 2009-12
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bi t e rro r and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application agai nst such soft errors.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 33 V1.2, 2009-12
3.2 Central Processing Unit (CPU)
The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instru ction-
fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and
accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply-and-divide uni t, a bit-mask generator, and a barrel
shifter.
Figure 5 CPU Block Diagram
DPRAM
CPU
IPIP
RF
R0
R1
GPRs
R14
R15
R0
R1
GPRs
R14
R15
IFU
Injection/
Exception
Handler
ADU
MAC
mca04917_x.vsd
CPUCON1
CPUCON2
CSP IP
Return
Stack
FIFO
Branch
Unit
Prefetch
Unit VECSEG
TFR
+/-
IDX0
IDX1
QX0
QX1
QR0
QR1 DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
MRW
MCW
MSW
MAL
+/-
MAH
Multiply
Unit
ALU
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDC
PSW
MDH
ZEROS
MDL
ONES
R0
R1
GPRs
R14
R15
CP
WB
Buffer
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
R0
R1
GPRs
R14
R15
PMU
DMU
DSRAM
EBC
Peripherals
PSRAM
Flash/ROM
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 34 V1.2, 2009-12
With this hardware most XC223xN instru ctions are executed in a single machine cycle
of 12.5 ns @ 80-MHz CPU clock. For example, shift and rotate instructions are always
processed during one machine cycle, no matter how many bits are shifted. Also,
multiplication and most MAC instructions execute in one cycle. All multiple-cycle
instructions have been optimized so that they can be executed very fast; for example, a
32-/16-bit division i s started within 4 cycles while the remaining cycles are executed in
the background. Another pipel ine optimization, the branch target prediction, eliminates
the execution time of branch instructions if the prediction was correct.
The CPU has a register conte xt consisting of up to three register b anks with 16 word-
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware im plementation can be be st utilize d by the
programmer with the highly efficient XC223xN instruction set. This includes the following
instruction classes:
• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate ad dressing modes are provided to
specify the required operands.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 35 V1.2, 2009-12
3.3 Memory Protection Unit (MPU)
The XC223xN’s Memory Protection Unit (MPU) protects user-specified memory areas
from unauthorized read, write, or instruction fe tch accesses. The MPU can protect the
whole address space including the peripheral area. This completes established
mechanisms such as the register security mechanism or stack overrun/underrun
detection.
Four Protection Levels support flexible system programming where operating system,
low level drivers, and applications run on separate levels. Each protection level permits
different access restrictions for instructions and/or data.
Every access is checked (if the MPU is enabled) and an access violating the permission
rules will be marked as invalid and leads to a protection trap.
A set of protection registers for each protection level sp ecifies the address ranges and
the access permissions. Applications requiring more than 4 protection levels can
dynamically re-pro gra m th e pr otection register s.
3.4 Memory Checker Module (MCHK)
The XC223xN’s Memory Checker Module calculates a checksum (fractional polynomial
division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on
a 32-bit linear feedback shift register and may, therefore, also be used to generate
pseudo-random numbers.
The Memory Checker Module is a 16-bit parallel input signature compression circuitry
which enables error detection within a block of data stored in memory, registers, or
communicated e.g. via serial communication lines. It reduces the probability of error
masking due to repeated error patterns by calculating the signature of blocks of data.
The polynomial used for operation is configurable, so most of the commonly used
polynomials may be used. Also, the block size for generating a CRC result is
configurable via a local counter. An interrupt may be generated if testing the current data
block reveals an error.
An autonomous CRC compare circuitry is included to enable redundant error detection,
e.g. to enable higher safety integrity levels.
The Memory Checker Module provides enhanced fault detection (beyond parity or ECC)
for data and instructions in volatile and non volatile memories. This is especially
important for the safety and reliability of embedded systems.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 36 V1.2, 2009-12
3.5 Interrupt System
The architecture of the XC223xN supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroll er. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Using a standard interrupt service the current program execution is suspended and a
branch to the interrupt vector table is perfo rmed. Wi th th e PEC just one cycle is ‘stolen ’
from the current CPU activity to perform t he PEC service. A PEC service implies a single
byte or word data transfer between any two memory locations with an additional
increment of either the PEC source pointer, the destination pointer, or both. An individual
PEC transfer counter is implicitly decremented for each PEC service except when
performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source-related vector location. PEC services
are particularly well suited to supporting the transmission or reception of blocks of data.
The XC223xN has eight PEC channels, each with fast interrupt-driven data transfer
capabilities.
With a minimum i nterrupt response time of 7/111) CPU clocks, the XC223xN can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 96 physical nodes with separate control register
containing an interrupt reque st flag, an interrupt enable flag and a n interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger l ogic (ETL) a routing matrix and 4 output ga ting units
(OGU). The ETL features rising ed ge, falling edg e, or both ed ges event detectio n. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XC223xN provides efficient mechanisms to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate system reaction similar to a standard interrupt service (branching
1) Depending if the jump cache is used or not.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 37 V1.2, 2009-12
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in th e trap flag register (TFR ). Unl ess anoth er hig her-prior ity trap se rvice
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6 On-Chip Debug Support (OCDS)
The On-Chip Debug Supp ort system built into the XC22 3xN provides a broad range of
debug and emulation features. User software running on the XC223xN can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. T his
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addi tion the OCDS system can be controlled b y the
CPU, e.g. by a monitor program. An injection interface a llows the execution of OCDS-
generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XC2000 Family emulation device. With
this device the DAP can operate on clock rates of up to 20 MHz.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 38 V1.2, 2009-12
3.7 Capture/Compare Unit (CC2)
The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of one system clock cycle (eight cycles in
staggered mode). The CAPCOM unit is typically used to handle high-speed I/O tasks
such as pulse and waveform generation, pulse width modulation (PWM), digital to
analog (D/A) conversion, software timing, or time recording with respect to external
events.
Two 16-bit timers with reload registers provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs allow event scheduling for the capture/compare registers relative to external
events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer and
programmed for capture or compare function.
All registers have each one port pin associated with it which serves as an input pin for
triggering the capture function, or as an output pin to indicate the occurrence of a
compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Table 9 Compare Modes
Compare Modes Function
Mode 0 Interrupt-only compare mode;
Several compare interrupts per timer period are possib le
Mode 1 Pin toggles on each compare match;
Several compare events per timer period are possible
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 39 V1.2, 2009-12
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an exte rnal event at the port pin asso ciated with this re gister. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a ne gative external sign al transition
at the pin can be selected as the triggering event.
The contents of all registers selected for one of the five compare modes are continuously
compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the compare mode selected.
Mode 2 Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode Generates single edges or pulses;
Can be used with any compare mode
Table 9 Compare Modes (cont’d)
Compare Modes Function
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 40 V1.2, 2009-12
Figure 6 CAPCOM Unit Block Diagram
Sixteen
16-bit
Capture/
Compare
Registers
Mode
Control
(Capture
or
Compare)
T7
Input
Control
T8
Input
Control
MC_CAPCOM2_BLOCKDIAG
CC16IRQ
CC31IRQ
CC17IRQ
T7IRQ
T8IRQ
CC16IO
CC17IO
T7IN
T6OUF
f
CC
T6OUF
f
CC
Reload Reg.
T7REL
Timer T7
Timer T8
Reload Reg.
T8REL
CC31IO
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 41 V1.2, 2009-12
3.8 Capture/Compare Units CCU6x
The XC223xN types feature the CCU60, CCU61 unit(s).
CCU6 is a high-reso lution capture and compare unit with app lication-specific modes. It
provides inputs to start the timers synchronously, an important feature in devices with
several CCU6 modules.
The module provides two independent timers (T12, T13), that can be used for PWM
generation, especially for AC motor control. Additionally, special control modes for block
commutation and multi-phase machines are sup ported.
Timer 12 Features
• Three capture/compare channels, where each channel can be used either as a
capture or as a compare channel.
• Supports generation of a three-phase PW M (six outputs, indivi dual signa ls for high-
side and low-side switches)
• 16-bit resolution, maximum count frequency = pe ripheral clock
• Dead-time control for each channel to avoid short circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-align ed PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode
• Automatic start on a HW event (T12HR, for synchronization purposes)
Timer 13 Features
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = pe ripheral clock
• Can be synchronized to T12
• Interrupt generation at period match and compare match
• Single-shot mode supported
• Automatic start on a HW event (T13HR, for synchronization purposes)
Additional Features
• Block commutation for brushless DC drives implemented
• Position detection via Hall sensor patte rn
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC drives
• Output levels can be selected and adapted to the power stage
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 42 V1.2, 2009-12
Figure 7 CCU6 Block Diagram
Timer T12 can work in capture and/or compare mode for its three channels. The modes
can also be combined . Timer T13 can work in compare mode only. Th e multi-channel
control unit generates output patte rns that can be modulated by timer T12 and/or timer
T13. The modulation sources can be selected and combined for signal modulation.
mc_ccu6_blockdiagram.vsd
C hannel 0
C hannel 1
C hannel 2
T12 Dead-
time
Control
Input / Output Control
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
CTRAP
C hannel 3T13
CCPOS0
1
1
1
2221
start
compare
capt ur e
3
Multi-
channel
Control
Trap
Control
compare
compare
compare
compare
1
trap input
CCPOS1
CCPOS2
out put select
out put select
3
Hall inp ut
CCU6 Module Kernel
fSYS
Interrupts
TxHR
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 43 V1.2, 2009-12
3.9 General Purpose Timer (GPT12E) Unit
The GPT12E unit is a very flexible multif unctional timer/counter structu re which ca n be
used for many different timing tasks such as event timing and counting, pulse width and
duty cycle measurements, pulse generatio n, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers organized in two separate modules,
GPT1 and GPT2. Each timer in each module may either operate independently in a
number of different modes or be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental
Interface Mode. In Timer Mode, the input clock for a timer is derived from the system
clock and divided by a programmable p rescale r. Counter Mo de allo ws timer clocki ng in
reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is control led by the ‘gate’ level on an e xternal input pin. Fo r these
purposes each timer has one associated port pin (TxIN) which serves as a gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The counting direction (up/down) for each timer can be programmed by software or
altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position
tracking.
In Incremental Interface Mode the GPT1 timers can be directly connected to the
incremental position sensor signals A and B through their respective inputs TxIN and
TxEUD. Direction and counting signals are internally derived from these two input
signals, so that the contents of the respective timer Tx corresponds to the sensor
position. The third position sensor signal T OP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to the basic operating modes, T2 and T4 may be configured as reload or
capture register for timer T3. A timer used as capture or reload register is stopped. Th e
contents of timer T3 is captured into T2 or T 4 in response to a sign al at the associated
input pin (TxIN). Timer T3 is re loaded with th e contents of T2 or T4, trigge red either by
an external signal or a selectab le state transition of its toggle latch T3OTL. When both
T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be con tinuously generated
without software intervention.
Note: Signals T2IN, T2EUD, T4EUD, and T6EUD are not connected to pins.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 44 V1.2, 2009-12
Figure 8 Block Diagram of GPT1
MC_GPT_BLOCK1
Aux. Timer T2
2
n
:1
T2
Mode
Control
Capture
U/D
Basic Clock
f
GPT
T3CON.BPS1
T3OTL T3OUT
Toggle
Latch
T2IN
T2EUD Reload
Core Timer T3
T3
Mode
Control
T3IN
T3EUD U/D
Interrupt
Request
(T3IRQ)
T4
Mode
Control
U/D
Aux. Timer T4
T4EUD
T4IN Reload
Capture
Interrupt
Request
(T4IRQ)
Interrupt
Request
(T2IRQ)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 45 V1.2, 2009-12
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
counting direction (up/dow n) for each timer can be programmed by software or altered
dynamically with an extern al signal on a port pin (TxEUD). Conc atenation of the timers
is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2
timers and to initiate a reload from the CAPREL register.
The CAPREL register can capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared
after the capture procedure. This allows the XC223xN to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of
GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 46 V1.2, 2009-12
Figure 9 Block Diagram of GPT2
MC_GPT_BLOCK2
GPT2 Timer T5
2
n
:1
T5
Mode
Control
GPT2 CAPREL
T3IN/
T3EUD
CAPREL
Mode
Control
T6
Mode
Control
Reload
Clear
U/D
Capture
Clear
U/D
T5IN
CAPIN
Interrupt
Request
(T5IRQ)
Interrupt
Request
(T6IRQ)
Interrupt
Request
(CRIRQ)
Basic Clock
f
GPT
T6CON.BPS2
T6IN
GPT2 Timer T6 T6OTL T6OUT
T6OUF
Toggle
FF
T6EUD
T5EUD
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 47 V1.2, 2009-12
3.10 Real Time Clock
The Real Time Clock (RTC) module of the XC223xN can be clocked with a clock signal
selected from internal sources or external sources (pins).
The RTC basically consists of a chain of divider blocks:
• Selectable 32:1 and 8:1 dividers (on - off)
• The reloadable 16-bit timer T14
• The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
Figure 10 RTC Block Diagram
Note: The registers associated with the RTC are only affected by a power reset.
CNT-Register
REL-Register
10 Bits6 Bits6 Bits10 Bi tsT14
MCB05568B
T14-Register
Interrupt Sub Node RTCINT
MUX
32
PRE
RUN
CNT
INT3
CNT
INT2
CNT
INT1
CNT
INT0
f
CNT
f
RTC
T14REL 10 Bits6 Bi ts6 Bi ts10 Bi ts
:
MUX
8:
REFCLK
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 48 V1.2, 2009-12
The RTC module can be used fo r different purposes:
• System clock to determine the current time and date
• Cyclic time-based interrupt, to provide a system time tick independent of CPU
frequency and other resources
• 48-bit timer for long-term measurements
• Alarm interrupt at a defined time
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 49 V1.2, 2009-12
3.11 A/D Converters
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with
7 + 2 multiplexed input channels and a sample and hold circuit have been integrated on-
chip. 2 inputs ca n be converted by both A/D converters. Conversions use the successive
approximation method. The sampl e time (to charge the capacitors) and the conversion
time are programmable so that they can be adjusted to the external circuit. The A/D
converters can also operate in 8-bi t conversion mode, further reducin g the conversion
time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequence s provid e a high deg ree of programmabi lity to meet
the application requirements. Both modules can be synchronized to allow parallel
sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically. For applications that require fewer analog input
channels, the remaini ng channel inputs can be used as digital input port pins.
The A/D converters of the XC223xN support two types of request sources which can be
triggered by several intern al and external events.
• Parallel requests are acti vated at the same time and then exe cuted in a predefined
sequence.
• Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features reduce the number of required CPU access operations allowing
the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed.
Result data can be reduce d by limit checking or accumulation of results.
The Peripheral Event Controlle r (PEC) can be used to control the A/D con verters or to
automatically store conversion results to a table in memory for later evalua tion, without
requiring the overhead of entering and exiting interrupt routines for ea ch data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages. This
can be selected for each pin separately with the Port x Digital Input Disable registers.
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Broken wire detection for each channel and a multiplexer test mode provide information
to verify the proper operation of the analog signal sources (e.g. a sensor system).
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 50 V1.2, 2009-12
3.12 Universal Serial Interface Channel Modules (USIC)
The XC223xN features the USIC modules USIC0, USIC1, USIC2. Each module provides
two serial communication channels.
The Universal Serial Interface Ch annel (USI C) module is based on a g eneric data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during run time.
Figure 11 General Structure of a USIC Module
The regular structure of the USIC module brings the following advantag es:
• Higher flexibility through configuration with same look-and-feel for data management
• Reduced complexity for low-level dr ivers serving different protocols
• Wide range of protocols with improved performances (baud rate, buffer handling)
USIC_basic.vsd
Bus Inter face
DBU
0
DBU
1
Control 0
Control 1
DSU
0
DSU
1
PPP_A
PPP_B
PPP_C
PPP_D
PPP_A
PPP_B
PPP_C
PPP_D
Pin Routing Shell
Buffer & Sh ift Structure Proto col Prepro cessors Pin sBus
fsys Fractional
Dividers Ba u d rate
Generators
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 51 V1.2, 2009-12
Target Protocols
Each USIC channel can rece ive and transmit data frames with a selectable data wo rd
width from 1 to 16 bits in each of the following protocols:
•UART (asynchronous serial channel)
– module capability: maximum baud rate = fSYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
•LIN Support (Local Interconnect Network)
– module capability: maximum baud rate = fSYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
•SSC/SPI/QSPI (synchronous serial channel with or without data buffer)
– module capability: maximum baud rate = fSYS / 2, limited by loop delay
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
•IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
•IIS (Inter-IC Sound Bus)
– module capability: maximum baud rate = fSYS / 2
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum achievable baud rate can be
limited. Please note that there may be additional delays, such as internal or
external propagation delays and driver delays (e.g. for collision detection in UART
mode, for IIC, etc.).
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 52 V1.2, 2009-12
3.13 MultiCAN Module
The MultiCAN module contains independently operating CAN nodes with Full-CAN
functionality which are able to exchange Data and Remote Frames using a gateway
function. Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
All CAN nodes share a common set of message objects. Each message object can be
individually allo cated to one of th e CAN nodes. Besid es serving as a storage container
for incoming and outgoing frames, message objects can be combined to build gateways
between the CAN nodes or to set up a FIFO buffer.
Note: The number of CAN nodes and message objects depends on the selected device
type.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to its own message object list and it transmits only messages
belonging to this message object list. A powerful, command-driven list controller
performs all message object list operations.
Figure 12 Block Diagram of MultiCAN Module
mc_multican_block.vsd
M ultiCA N M odule K ernel
Interrupt
Control
fCAN
Port
Control
CAN Co ntrol
Message
Object
Buffer
CAN
Node 0
Linked
List
Control
Clock
Control
Address
Decoder
CAN
Node n
TXDCn
RXDCn
TXDC0
RXDC0
...
...
...
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 53 V1.2, 2009-12
MultiCAN Features
• CAN functionality conforming to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
• Independent CAN nodes
• Set of independent message objects (shared by the CAN nodes)
• Dedicated control registers for each CAN node
• Data transfer rate up to 1 Mbit/s, individually programmable for each node
• Flexible and powerful me ssage transfer control and error handling capabiliti es
• Full-CAN functionality for message objects:
– Can be assigned to one of the CAN nodes
– Configurable as transmit or receive objects, or as message buffer FIFO
– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering
– Remote Monitoring Mode, and frame counter for monitoring
• Automatic Gateway Mode support
• 16 individually programmable interrupt nodes
• Analyzer mode for CAN bus monitoring
3.14 System Timer
The System Timer consists of a progra mmable prescaler and two concatenated timers
(10 bits and 6 bits). Both timers can generate in terrupt requests. Th e clock source can
be selected and the timers can also run during power reduction modes.
Therefore, the System Timer enables the software to maintain the current time for
scheduling functions or for the implem entation of a clock.
3.15 Watchdog Timer
The Watchdog Timer is one of the fail-safe mechanisms which have been implemented
to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is a lways enabled after an application reset of the chip. It can be
disabled and enabled at any time by executing the instructions DISWDT and ENWDT
respectively. The software has to service the Watchdog Timer before it overflows. If this
is not the case because of a hardware or software failure, the Watchdog Timer
overflows, generating a prewarning interrupt and then a reset request.
The Watchdog Time r is a 16-bit timer clocked with the system clock divided by 16,384
or 256. The Watchdog Timer register is set to a prespecified reload value (stored in
WDTREL) in order to allo w further variation of the moni tored time interval. Each time it
is serviced by the application software, the Watchdog Timer is reloaded and the
prescaler is cleared.
Time intervals between 3.2 μs and 13.4 s can be monitored (@ 80 MHz).
The default Watchdog Timer interval afte r power-up is 6.5 ms (@ 10 MHz).
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 54 V1.2, 2009-12
3.16 Clock Generation
The Clock Generati on Unit can ge nerate the system clock signal fSYS for the XC223xN
from a number of external or internal clock sou rce s:
• External clock signals with pad voltage or core volta ge levels
• External crystal or resonator using the on-chip oscillator
• On-chip clock source for operation without crystal/resonator
• Wake-up clock (ultra-low-power) to further reduce power consumpti on
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.7.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on on e of two selectable pins.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 55 V1.2, 2009-12
3.17 Parallel Ports
The XC223xN provides u p to 40 I/O lines wh ich are org anized into 4 input/outp ut ports
and 2 input ports. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given appli cation. For thi s reason, certain functions app ear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10 Summary of the XC223x N’s Ports
Port Width I/O Connected Modules
P2 11 I/O CAN, CC2, GPT12E, USIC, DAP/JTAG
P5 7 I Analog Inputs, CCU6, DAP/JTAG, GPT12E, CAN
P6 2 I/O ADC, CAN, GPT12E
P7 1 I/O CAN, GPT12E, SCU, DAP/JTAG, USIC
P10 16 I/O CCU6, USIC, DAP/JTAG, CAN
P15 2 I Analog Inputs, GPT12E
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 56 V1.2, 2009-12
3.18 Power Management
The XC223xN provides the means to control the power it consumes either at a given time
or averaged over a certain duration.
Three mechanisms can be used (and partly in parallel):
•Supply Voltage Management permits the temporary reduction of the supply voltage
of major parts of the logic or even its complete disconnection. This drastically reduces
the power consumed because it eliminates leakage current, particularly at high
temperature.
Several power reduction modes provide the best balance of power reduction and
wake-up time.
•Clock Generation Management controls the frequency of internal and external
clock signals. Clock signals for currently inactive parts of logic are disabled
automatically. The user can drastically reduce the consumed power by reducing th e
XC223xN system clock frequency.
External circuits can be controlled using the programmable frequency output
EXTCLK.
•Peripheral Manageme nt permits temporary disabling of perip heral modules. Each
peripheral can be disabled and enabled separately. The CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally with signals
generated by the external system, or internally by the on-chip wake-up timer. This
supports intermittent operation of the XC223xN by generating cyclic wake-up signals.
Full performance is available to quickly react to action requests while the intermittent
sleep phases greatly reduce the average system powe r consumption.
Note: When selecting the supply voltage and the clock sour ce and generation meth od,
the required parameters must be carefully written to the respective bit fields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the inte nded operation of power supply system and cloc k system.
Please refer to the Programmer’s Guide.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 57 V1.2, 2009-12
3.19 Instruction Set Summary
Table 11 lists the instructions of the XC223xN.
The addressing mode s that can be used with a specific in struction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11 Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise exclusive OR, (word/byte operands) 2 / 4
BCLR/BSET Clear/Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bi t 4
BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR 2
SHL/SHR Shift left/right direct word GPR 2
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 58 V1.2, 2009-12
ROL/ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS/Z Move byte operand to word op. with sign/zero extension 2 / 4
JMPA/I/R Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
JB(C) Jump relative if direct bit is set (an d clear bit) 4
JNB(S) Jump relative if direct bit is not set (and set bit) 4
CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine 4
TRAP Call interrupt service routine vi a immediate trap number 2
PUSH/POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and upda te
register with word operand 4
RET(P) Return from intra-segment subroutine
(and pop direct word register from system stack) 2
RETS Return from inter-segment subroutine 2
RETI Return from interrupt service subroutine 2
SBRK Software Break 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Unused instruction1) 4
SRVWDT Service Watchdog Timer 4
DISWDT/ENWDT Disable/Enable Watchdog Timer 4
EINIT End-of-Initialization Regi ster Lock 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
Table 11 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Des cription
Data Sheet 59 V1.2, 2009-12
NOP Null operation 2
CoMUL/CoMAC Multiply (and accumul ate) 4
CoADD/CoSUB Add/Subtract 4
Co(A)SHR (Arithmetic) Shift right 4
CoSHL Shift left 4
CoLOAD/STORE Load accumulator/Store MAC register 4
CoCMP Compare 4
CoMAX/MIN Maximum/Minimum 4
CoABS/CoRND Absolute value/Round accumu lator 4
CoMOV Data move 4
CoNEG/NOP Negate accumulator/Null operation 4
1) The Enter Power Down Mode instruction is not used in the XC223xN, due to the enhanced power control
scheme. PWRDN will be correctly decoded, but will trigger no action.
Table 11 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 60 V1.2, 2009-12
4 Electrical Parameters
The operating range for the XC223xN is defined by its electrical parameters. For proper
operation the specified limits must be respected when integrating the device in its target
environment.
4.1 General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Note: Stresses above the values listed under “Absolute Maxi mum Ratings” may cause
permanent damage to the device. This is a stress rating only. Functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for an extended time may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximu m ratings.
Table 12 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Output current on a pin
when high value is driven IOH SR -30 −−mA
Output current on a pin
when low value is driven IOL SR −−30 mA
Overload current IOV SR -10 −10 mA 1)
1) Overload condition occu rs if the input voltage VIN is out of the absolute maximum rating range. In this case the
current must be limited to the listed values by desi gn measures.
Absolute sum of overload
currents Σ|IOV|
SR −−100 mA 1)
Junction Te mp erature TJ SR -40 −150 °C
Storage Temperature TST SR -65 −150 °C
Digital core supply voltage VDDI SR -0.5 −1.65 V
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR -0.5 −6.0 V
Voltage on any pin with
respect to ground (Vss) VIN SR -0.5 −VDDP +
0.5 VVIN≤VDDP(max)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 61 V1.2, 2009-12
4.1.1 Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC223xN. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Note: Typical parameter values refer to room temperature and nominal su pply voltage,
minimum/maximum parameter values also include conditions of
minimum/maximum temperature and minimum/maximum supply voltage.
Additional details are described where applicable.
Table 13 Operating Conditions
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Voltage Regulator Buffer
Capacitanc e fo r DMP_M CEVRM
SR 1.0 −4.7 μF
1)
Voltage Regulator Buffer
Capacitanc e fo r DMP_1 CEVR1
SR 0.47 −2.2 μF
2)1)
External Load
Capacitance CL SR −203) −pF pin out
driver= default
4)
System frequency fSYS SR −−80 MHz 5)
Overload current for
analog inputs6) IOVA SR -2 −5 mA not subject to
production test
Overload current for digital
inputs6) IOVD SR -5 −5 mA not subject to
production test
Overload current coupling
factor for analog inputs7) KOVA
CC −2.5 x
10-4 1.5 x
10-3 -IOV< 0 mA; not
subject to
production test
−1.0 x
10-6 1.0 x
10-4 -IOV> 0 mA; not
subject to
production test
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 62 V1.2, 2009-12
Overload current coupling
factor for digital I/O pins KOVD
CC −1.0 x
10-2 3.0 x
10-2 -IOV< 0 mA; not
subject to
production test
−1.0 x
10-4 5.0 x
10-3 -IOV> 0 mA; not
subject to
production test
Absolute sum of overload
currents Σ|IOV|
SR −−50 mA not su bj e ct t o
production test
Digital core supply voltage VDDI SR 1.4 −1.6 V
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0 −5.5 V
Digital ground voltage VSS SR −0−V
1) To ensure the stability of t he voltage r egulators th e EVRs must be b uffered with cer amic capacitors. Separa te
buffer capacitors with the reco mended values shall be connected as close as possible to each VDDI pin to keep
the resistance of the board tracks below 2 Ohm. Connect all VDDI1 pins together. The minimum capacitance
value is required for proper operation under all conditions (e.g. temperature). Higher values slightly increase
the startup time.
2) Use one Capacitor for each pin.
3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties
section.
4) The timing is valid for pin drivers operating in default curren t mode (se lected af ter reset) . Reducing the o utput
current may lead to increased delays or reduced driving capability (CL).
5) The operating frequency range may be reduced for specific device types. This is indicated in the device
designation (...FxxL). 80 MHz devices are marked ...F80L.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application. Overload conditions must not
occur on pin XTAL1 (powered by VDDI).
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pins lea kage current (IOZ). The amount of error current depends on the overload
current and is defined by the overlo ad coupl ing facto r KOV. The polarity of the in jected erro r curren t is inverse
compared to the pola rity of the overl oad current that pr oduces it.The t otal current through a pin is | ITOT| = |IOZ|
+ (|IOV| KOV). The additional error current may distort the input voltage on analog inputs.
Table 13 Operating Conditions (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 63 V1.2, 2009-12
4.2 Voltage Range definit ions
The XC223xN timing depends on the supply voltage. If such a dependency exists the
timing values are given for 2 voltage areas commonly used. The voltage areas are
defined in the following tables.
4.2.1 Parameter Interpretation
The parameters listed in the follo wing include both the characteristics of the XC22 3xN
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
CC (Controller Characteristics):
The logic of the XC223xN provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XC223xN.
Table 14 Upper Voltage Range Definition
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 4.5 5.0 5.5 V
Table 15 Lower Volt age Range Definition
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0 3.3 4.5 V
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 64 V1.2, 2009-12
4.3 DC Parameters
These parameters are static or average values th at may be exceeded during switching
transitions (e.g. output current).
The XC223xN can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parame ters are specified separately for the uppe r and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XC223xN are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specifi ed in Section 4.7.4.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 65 V1.2, 2009-12
Pullup/Pulldown Device Behavior
Most pins of the XC223xN feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified curre nt values indicate how to load the respective pin dependin g on the
intended signal level. Figure 13 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
Figure 13 Pullup/Pulldown Current Definition
MC_XC2X_PULL
VDDP
VSS
Pullup
Pulldown
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 66 V1.2, 2009-12
4.3.1 DC Parameters for Upper Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 16 is valid under the following conditions: VDDP≤5.5 V; VDDP≥4.5 V;
VDDPtyp. 5.0 V
Table 16 DC Characteristics for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Pin capacitance (digital
inputs/outputs). To be
doubled for double bond
pins.1)
CIO CC −−10 pF not subject to
production test
Input Hysteresis2) HYS CC 0.11 x
VDDP
−−VRS=0Ohm
Absolute input leakage
current on pins of analog
ports3)
|IOZ1|
CC −10 200 nA VIN<VDDP ;
VIN>VSS
Absolute input leakage
current for all other pins.
To be doubled for double
bond pins.3)1)4)
|IOZ2|
CC −0.2 5 μATJ≤110 °C;
VIN>VSS ;
VIN<VDDP
−0.2 15 μATJ≤150 °C;
VIN>VSS ;
VIN<VDDP
Pull Level Force Current5) |IPLF| SR 250 −−μA
6)
Pull Level Keep Current7) |IPLK|
SR −−30 μA
6)
Input high voltage (all
except XTAL1) VIH SR 0.7 x
VDDP
−VDDP +
0.3 V
Input low voltage
(all except XTAL1) VIL SR -0.3 −0.3 x
VDDP
V
Output High voltage8) VOH CC VDDP -
1.0 −−VIOH≥IOHmax
VDDP -
0.4 −−VIOH≥IOHnom 9)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 67 V1.2, 2009-12
Output Low Voltage8) VOL CC −−1.0 V IOL≤IOLmax
−−0.4 V IOL≤IOLnom 9)
1) Because each double bond pin is conne ct ed to two pads (st anda rd pa d and high -speed pad) , i t has twice t he
normal value. For a list of affected pins refer to the pin definitions table in chapter 2.
2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
3) If the input voltage exceeds the respecti ve supply vo ltage due to ground bouncing ( VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional erro r current (IINJ) will flow if an overload curre nt flows through an adjacent pin.
Please refer to the defini tion of the overload coupling factor KOV.
4) The given values are worst -case val ues. In production test , this l eakage current i s only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
5) Drive the indicated minimum current t hrough this pin to change the default pin leve l driven by the enable d pull
device: VPIN <= VIL for a pullup; VPIN >= VIH for a pul ldown.
6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN >= VIH for a pullup; VPIN <= VIL for a pulldown.
8) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
9) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Table 16 DC Characteristics for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 68 V1.2, 2009-12
4.3.2 DC Param e te rs fo r L ow er Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 17 is valid under the following conditions: VDDP≥3.0 V; VDDPtyp. 3.3 V;
VDDP≤4.5 V
Table 17 DC Characteristics for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Pin capacitance (digital
inputs/outputs). To be
doubled for double bond
pins.1)
CIO CC −−10 pF not subject to
production test
Input Hysteresis2) HYS CC 0.07 x
VDDP
−−VRS=0Ohm
Absolute input leakage
current on pins of analog
ports3)
|IOZ1|
CC −10 200 nA VIN<VDDP ;
VIN>VSS
Absolute input leakage
current for all other pins.
To be doubled for double
bond pins.3)1)4)
|IOZ2|
CC −0.2 2.5 μATJ≤110 °C;
VIN>VSS ;
VIN<VDDP
−0.2 8 μATJ≤150 °C;
VIN>VSS ;
VIN<VDDP
Pull Level Force Current5) |IPLF| SR 150 −− 6)
Pull Level Keep Current7) |IPLK|
SR −−10 μA
6)
Input high voltage (all
except XTAL1) VIH SR 0.7 x
VDDP
−VDDP +
0.3 V
Input low voltage
(all except XTAL1) VIL SR -0.3 −0.3 x
VDDP
V
Output High voltage8) VOH CC VDDP -
1.0 −−VIOH≥IOHmax
VDDP -
0.4 −−VIOH≥IOHnom 9)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 69 V1.2, 2009-12
Output Low Voltage8) VOL CC −−1.0 V IOL≤IOLmax
−−0.4 V IOL≤IOLnom 9)
1) Because each double bond pin is conne ct ed to two pads (st anda rd pa d and high -speed pad) , i t has twice t he
normal value. For a list of affected pins refer to the pin definitions table in chapter 2.
2) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
3) If the input voltage exceeds the respecti ve supply vo ltage due to ground bouncing ( VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional erro r current (IINJ) will flow if an overload curre nt flows through an adjacent pin.
Please refer to the defini tion of the overload coupling factor KOV.
4) The given values are worst -case val ues. In production test , this l eakage current i s only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
5) Drive the indicated minimum current t hrough this pin to change the default pin leve l driven by the enable d pull
device: VPIN <= VIL for a pullup; VPIN >= VIH for a pul ldown.
6) These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in
general purpose IO pins.
7) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level: VPIN >= VIH for a pullup; VPIN <= VIL for a pulldown.
8) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
9) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Table 17 DC Characteristics for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 70 V1.2, 2009-12
4.3.3 Power Consumption
The power consumed by the XC223xN depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
• The switching current IS depends on the device ac tivity
• The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS and leakage current ILK must be added:
IDDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be con sidered.
The given power consumption parameters and their values refer to specific operating
conditions:
•Active mode:
Regular operation, i.e. periphe rals are active, code executio n out of Flash.
•Stopover mode:
Crystal oscillator and PLL stopped, Flash switched off, clock in domain DMP_1
stopped.
•Standby mode:
Voltage domain DMP_1 switched o ff completely, power supply co ntrol switched off.
DMP_M domain is supplied by ultra low power electronic voltage regulator
(ULPEVR). The alternate regulator EVR_M is switched off.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDI are charged with the
maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 71 V1.2, 2009-12
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XC223xN’s subsystem.
Besides the power consumed by the device logic the power supply pins also provide the
current that flows through the pin outp ut drive r s.
A small current is consumed because the drivers’ input stages are switched.
The IO power domains can be supplied separately. Power domain A (VDDPA) supplies the
A/D converters and Port 6. Power domain B (VDDPB) supplies the on-chip EVVRs and all
other ports.
Table 18 Switching Power Consumption
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Power supply current
(active) with all peripherals
active and EVVRs on
ISACT
CC −6 + 0.6
x fSYS1)
1) fSYS in MHz
8 + 1.0
x fSYS1) mA power_mode=
active ;
voltage_range=
both 2)3)4)
2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current
consumed by the pin output drivers. A small current is consumed because the drivers input stages are
switched. In Fast Startup Mode (with the Flash module s deactivat ed), the typical curre nt is reduce d to 3 + 0.6
x fSYS.
3) Please consider the additio nal conditions described in section "Active Mode Power Supply Current".
4) The pad supply voltage has only a minor influence on this parameter.
Power supply current in
standby mode ISSB CC −45 125 μA power_mode=
standby ;
voltage_range=
lower 5)
5) These values are valid if the voltage validation circuits for VDDPB (SWD) and VDDIM (PVC_M) are off. Leaving
SWD and PVC_M active adds another 90 μA.
−70 220 μA power_mode=
standby ;
voltage_range=
upper 5)
Power supply current in
stopover mode, EVVRs on ISSO CC −0.7 2.0 mA power_mode=
stopover ;
voltage_range=
both 4)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 72 V1.2, 2009-12
During operation domain A draws a maximum current of 1.5 mA for each active A/D
converter module from VDDPA.
In Fast Startup Mode (with the Flash modules deactivated), the typical current is reduced
to 3 + 0.6×fSYS mA.
Figure 14 Supply Current in Acti ve Mod e as a Function of Frequen cy
Note: Operating Conditions apply.
MC_XC2XN_IS
fSYS [MHz]
IS [mA]
10
20
40
20 40 80
60
50
60
70
90
100
ISACTtyp
ISACTmax
30
80
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 73 V1.2, 2009-12
Note: A fraction of the leakage curre nt flows through domain DMP_A (pin VDDPA). This
current can be calculated as 7,000
×
e-
α
, with
α
= 5000 / (273 + 1.3
×
TJ).
For TJ = 150°C, this results in a current of 160
μ
A.
The leakage power consumption can be calculated according to the following formulas:
ILK0 = 530,000 + e-α with α = 3000 / (273 + B×TJ)
ILK1 = 500,000 + e-α with α = 5000 / (273 + B×TJ)
Parameter B must be replaced by
• 1.0 for typical values
• 1.3 for maximum values
Table 19 Leakage Power Consumptio n
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Leakage supply current
(DMP_1 off)1)
1) The supply current caused by leakage depends mainly on the junction temperature and the supply voltage.
The temperature difference between the junction temperature TJ and the ambient temperature TA must be
taken into account. As this fr actio n of the suppl y current does n ot dep end on device a ctivit y, i t must b e added
to other power consumption values.
ILK0 CC −20 35 μATJ=25°C
2)
2) All inputs (including pins configur ed as input s) are set at 0 V to 0 .1 V or at VDDP - 0.1 V to VDDP and all output s
(including pins configured as outputs) are disconne cted.
−115 330 μATJ=85°C
2)
−270 880 μATJ=125°C
2)
−420 1,450 μATJ=150°C
2)
Leakage supply current
(DMP_1 powered)1) ILK1 CC −0.03 0.04 mA TJ=25°C
2)
−0.5 1.2 mA TJ=85°C
2)
−1.9 5.5 mA TJ=125°C
2)
−3.9 12.2 mA TJ=150°C
2)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 74 V1.2, 2009-12
Figure 15 Leakage Supply Current as a Func tion of Temperature
MC_XC2XN_ILK150
TJ [°C]
ILK [mA]
2
6
10
0 50 150
100-50
4
8
12
ILK0max
ILK0typ
ILK1max
ILK1typ
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 75 V1.2, 2009-12
4.4 Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance .
Note: Operating Conditions apply.
Table 20 ADC Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Switched capacitance at
an analog input CAINSW
CC −−4 pF not subject to
production test
1)
Total capacitance at an
analog input CAINT
CC −−10 pF not subject to
production test
1)
Switched capacitance at
the reference input CAREFSW
CC −−7 pF not subject to
production test
1)
Total capacitance at the
reference input CAREFT
CC −−15 pF not subject to
production test
1)
Differential Non-Linearity
Error |EADNL|
CC −0.8 1 LSB
Gain Error |EAGAIN|
CC −0.4 0.8 LSB
Integral Non-Linearity |EAINL|
CC −0.8 1.2 LSB
Offset Error |EAOFF|
CC −0.5 0.8 LSB
Analog clock frequency fADCI SR 0.5 −16.5 MHz voltage_range=
lower
0.5 −20 MHz voltage_range=
upper
Input resistance of the
selected analog channel RAIN CC −−2kOh
mnot subject to
production test
1)
Input resistance of the
reference input RAREF
CC −−2kOh
mnot subject to
production test
1)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 76 V1.2, 2009-12
Broken wire detection
delay against VAGND2) tBWG CC −−503)
Broken wire detection
delay against VAREF4) tBWR CC −−505)
Conversion time for 8-bit
result2) tc8 CC (11+S
TC) x
tADCI +
2 x
tSYS
−−
Conversion time for 10-bit
result6) tc10 CC (13+S
TC) x
tADCI +
2 x
tSYS
−−
Total Unadjusted Error |TUE|
CC −12LSB
7)
Wakeup time from analog
powerdown, fast mode4) tWAF CC −−4μs
Wakeup time from analog
powerdown, slow mode4) tWAS CC −−15 μs
Analog reference ground VAGND
SR VSS -
0.05 −1.5 V
Analog input voltage
range VAIN SR VAGND −VAREF V
8)
Analog reference voltage VAREF
SR VAGND
+ 1.0 −VDDPA
+ 0.05 V
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation. At room temperature and nominal
supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kOhm,
CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kOhm.
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 μs. Result below 10% (66H)
Table 20 ADC Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 77 V1.2, 2009-12
Figure 16 Equivalent Circuitry for Analog Inputs
4) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 μs. This function is influenced by leakage current, in particular at high
temperature. Resul t above 80% (332H)
6) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming. The 12-bit conversion time value contains 2 basic clocks f or post
calibration.
7) TUE is tested at VAREF = VDDPA = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage r ange. The specified TUE i s valid only if the ab solute sum of input overlo ad currents on an alog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
8) VAIN may exceed VAGND or VAREF up to the a bsolute maximum rat ings. However, the conversion r esult in the se
cases will be X000H or X3FFH, respectively.
A/D Converter
MCS05570
R
Source
V
AIN
C
Ext
C
AINT
C
AINS
-
R
AIN, On
C
AINS
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 78 V1.2, 2009-12
Sample time and conversion time of the XC223xN’s A/D converters are programmable.
The timing abo ve can be calculated using Table 21.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Converter Timing Example A:
Converter Timing Example B:
Table 21 A/D Con verter Computation Table
GLOBCTR.5-0
(DIVA) A/D Converter
Analog Clock fADCI
INPCRx.7-0
(STC) Sample Time1)
tS
1) The selected sample time is doubled if broken wire detection is active (due to the presa m pling phase).
000000BfSYS 00HtADCI × 2
000001BfSYS / 2 01HtADCI × 3
000010BfSYS / 3 02HtADCI × 4
:fSYS / (DIVA+1) : tADCI × (STC+2)
111110BfSYS / 63 FEHtADCI × 256
111111BfSYS / 64 FFHtADCI × 257
Assumptions: fSYS = 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
Analog clock fADCI = fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
Sample time tS= tADCI × 2 = 100 ns
Conversion 10-bit:
tC10 = 13 × tADCI + 2 × tSYS = 13 × 50 ns + 2 × 12.5 ns = 0.675 μs
Conversion 8-bit:tC8 = 11 × tADCI + 2 × tSYS = 11 × 50 ns + 2 × 12.5 ns = 0.575 μs
Assumptions: fSYS = 40 MHz (i.e. tSYS = 25 ns), DIVA = 02H, STC = 03H
Analog clock fADCI = fSYS / 3 = 13.3 MHz, i.e. tADCI = 75 ns
Sample time tS= tADCI × 5 = 375 ns
Conversion 10-bit:
tC10 = 16 × tADCI + 2 × tSYS = 16 × 75 ns + 2 × 25 ns = 1.25 μs
Conversion 8-bit:tC8 = 14 × tADCI + 2 × tSYS = 14 × 75 ns + 2 × 25 ns = 1.10 μs
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 79 V1.2, 2009-12
4.5 System Parameters
The following parameters specify several aspects which are important when integrating
the XC223xN into an application system.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 22 Various System Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Short-term deviation of
internal clock source
frequency1)
1) The short-term frequency deviation refers to a timeframe of 20 ms and is measured relative to the current
frequency at the beginning of the respective timeframe
ΔfINT CC -1 −1%
Internal clock source
frequency fINT CC 4.8 5.0 5.2 MHz
Wakeup clock source
frequency2)
2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to
production test - verified by design/characterization
fWU CC 400 500 600 kHz FREQSEL= 00
210 270 330 kHz FREQSEL= 01
140 180 220 kHz FREQSEL= 10
110 140 170 kHz FREQSEL= 11
Startup time from standby
mode with code execution
from Flash
tSSB CC 2.6 3.8 4.1 ms fWU= 140 kHz
1.6 2.1 2.5 ms fWU= 500 kHz
Startup time from stopover
mode with code execution
from PSRAM
tSSO CC 1 1 /
fWU3)
3) fWU in MHz
11 /
fWU3) 11 /
fWU3) μs
Core voltage (PVC)
supervision level VPVC CC VLV -
0.03 VLV VLV +
0.074)
4) This value includes a hysteresis of approximately 50 mV for rising voltage.
V
5)
Supply watchdog (SWD)
supervision level VSWD
CC VLV -
0.106) VLV VLV +
0.15 V voltage_range=
lower 5)
VLV -
0.15 VLV VLV +
0.15 V voltage_range=
upper 5)
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 80 V1.2, 2009-12
Conditions for tSSB Timing Measurement
The time required for the transition from Standby to Base mode is called tSSB. It is
measured under the following conditions:
Precondition: The Standby mode has been entere d using th e procedure de fined i n the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from FLASH
after startup.
Conditions for tSSO Timing Measurement
The time required for the transition from Stopover to Stopover Waked-Up mode is
called tSSO. It is measured under the following conditions:
Precondition: The Stopover mode has been entered using the procedure defined in the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from PSRAM
after startup.
5) VLV = selected SWD voltage level
6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 81 V1.2, 2009-12
Table 23 Coding of bit fields LEVxV in Register SWDCON 0
Code Default Voltage Level Notes1)
1) The indicated default levels are selected automatically after a power reset.
0000B2.9 V
0001B3.0 V LEV1V: reset request
0010B3.1 V
0011B3.2 V
0100B3.3 V
0101B3.4 V
0110B3.6 V
0111B4.0 V
1000B4.2 V
1001B4.5 V LEV2V: no request
1010B4.6 V
1011B4.7 V
1100B4.8 V
1101B4.9 V
1110B5.0 V
1111B5.5 V
Table 24 Coding of bit fields LEVxV in Registers PVCyCO N z
Code Default Voltage Level Notes1)
1) The indicated default levels are selected automatically after a power reset.
000B0.95 V
001B1.05 V
010B1.15 V
011B1.25 V
100B1.35 V LEV1V: reset request
101B1.45 V LEV2V: interrupt request
110B1.55 V
111B1.65 V
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 82 V1.2, 2009-12
4.6 Flash Memory Parameters
The XC223xN is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XC223xN’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 25 Flash Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Parallel Flash module
program/erase limit
depending on Flash read
activity
NPP SR −−21) NFL_RD≤1
−−12) NFL_RD>1
Flash erase endurance for
security pages NSEC SR 10 −−cycle
stRET≤20 years
Flash wait states3) NWSFLAS
H SR 1−− fSYS≤8MHz
2−− fSYS≤13 MHz
3−− fSYS≤17 MHz
4−− fSYS>17MHz
Erase time per
sector/page tER CC −74) 8.0 ms
Programming time per
page tPR CC −34) 3.5 ms
Data retention time tRET CC 20 −−year
sNEr≤1,000 cycl
es
Drain disturb limit NDD SR 32 −−cycle
s
Maximum number of
erase cycles before
unacceptable
performance degradation
occurs
NEr SR 15,000
5) −−cycle
stRET≤5years
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 83 V1.2, 2009-12
Access to the XC223xN Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
1) The unused Flash module(s) can be erased/programmed while code is executed and/or data is read from only
one Flash module or from PSRAM. The Flash module that delivers code/data can, of course, not be
erased/programmed.
2) Flash module 1 can be erased/programmed while code is executed and /or data is re ad f rom Flash modul e 0.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Programming and erase times d epend on th e inter nal Fla sh clock source. The cont rol stat e machi ne n eeds a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
5) A maximum of 64 Flash sectors can be cycled 15,000 times. For all other sectors the limit is 1,000 cycles.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 84 V1.2, 2009-12
4.7 AC Parameters
These parameters descri be the dynamic behavior of the XC 223xN.
4.7.1 Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
Figure 17 Input Output Waveforms
Figure 18 Floating Waveforms
MCD05556C
0.3 VDDP
Input Signal
(driven b y te s te r)
Output Signal
(measured)
H o ld time
Output delay Output delay
H o ld tim e
Output timings refer to the rising edge of CLKO UT.
Input timings are calculated from the time, when the input signal reaches
VIH or VIL, resp ec tiv e ly .
0.2 VDDP
0.8 VDDP
0.7 VDDP
MCA05565
Timing
Reference
Points
V
Load
+ 0.1 V
V
Load
- 0. 1 V
V
OH
- 0.1 V
V
OL
+ 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 m V
change from the loaded V
OH
/V
OL
level occurs (I
OH
/I
OL
= 20 mA).
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 85 V1.2, 2009-12
4.7.2 Definition of Internal Timing
The internal operation of the XC223xN is controlled by the internal system clock fSYS.
Because the system clock signal fSYS can be generated from a nu mber of internal and
external sources using different mech anisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XC223xN.
Figure 19 Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 19 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
MC_XC2X_CLOCKGEN
Phase Locked Loop Operation (1:N)
f
IN
Di rect Clock Dri ve (1:1)
Prescaler Op eratio n ( N :1)
f
SYS
f
IN
f
SYS
f
IN
f
SYS
TCS
TCS
TCS
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 86 V1.2, 2009-12
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
fSYS = fIN.
The frequency of fSYS is the same as the freq uency of fIN. In this case the hi gh and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source throu gh the output prescaler K1 (= K1DIV+1):
fSYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the freque ncy of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
fSYS = fOSC / 1024.
4.7.2.1 Phase Locked Loop (PLL)
When PLL operation is sele cted (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDI1.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 87 V1.2, 2009-12
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the give n circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 20).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 ×T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
fSYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 88 V1.2, 2009-12
Figure 20 Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL=20pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
VDDPB pin 64 and VSS pin 1) is limited to a peak-to-pe ak voltage of VPP = 50 mV.
This can be achieved by appropriate blocking of the supply voltage as close as
possible to the supply pins and using PCB supply and ground planes.
PLL frequency band selection
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output freq uencies:
MC_XC2X_JITTER
Cycles
T
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
D
T
20 40 60 80 100
ns fSYS = 66 MH z
1
fVCO = 132 M Hz
fVCO = 66 MHz
±9 fSYS = 33 M Hz
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 89 V1.2, 2009-12
4.7.2.2 Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
fSYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consump tion.
4.7.2.3 Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bit fields, to avoid unintended
intermediate states.
Many applications change the frequen cy of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching curren ts, which influ ences the power supply.
To ensure proper o peration of the on-chip EVRs while the y generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
Table 26 System PLL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VCO output frequency fVCO CC 48 −112 MHz VCOSEL= 00b
;
VCOmode=con
trolled
−−38 MHz VCOSEL= 00b
;
VCOmode=fre
e running
96 −160 MHz VCOSEL= 01b
;
VCOmode=con
trolled
−−76 MHz VCOSEL= 01b
;
VCOmode=fre
e running
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 90 V1.2, 2009-12
To avoid the indicated p roblems, recommen ded sequences are pro vided which en sure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 91 V1.2, 2009-12
4.7.3 External Clock Input Parameters
These parameters specify the external clock generation for the XC223xN. The clock can
be generated in two ways:
• By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
• By supplyi ng an external clock signal. This clock signal can be suppl ied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1
…
t4) are only valid for an external clock
input signa l .
Note: Operating Conditions apply.
Table 27 External Clock Input Characteristics
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Oscillator frequency fOSC SR 4 −40 MHz Input= Clock
Signal
4−16 MHz Input= Crystal
or Resonator
XTAL1 input current
absolute value |IIL| CC −−20 μA
Input clock high time t1 SR 6 −−ns
Input clock low time t2 SR 6 −−ns
Input clock rise time t3 SR −88ns
Input clock fall time t4 SR −88ns
Input voltage amplitude on
XTAL1 VAX1 SR 0.3 x
VDDI
−−V
1)
1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1.
Input voltage range limits
for signal on XTAL1 VIX1 SR -1.7 +
VDDI
−1.7 V 2)
2) Overload conditions must not occur on pin XTAL1.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 92 V1.2, 2009-12
Figure 21 External Clock Drive XTAL1
Note: For crystal/resonator operation, it is strongly recommended to measure the
oscillation allowance (negative resistance) in the final target system (layout) to
determine th e op ti mu m parameters for oscillator operation.
Please refer to the limits specified by the crystal/resonator supplier.
MC_EXTCLOCK
t
1
t
2
t
OSC
= 1/f
OSC
t
3
t
4
V
OFF
V
AX1
0.1 V
AX1
0.9 V
AX1
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 93 V1.2, 2009-12
4.7.4 Pad Properties
The output pad drivers of the XC223xN can op erate in several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing th e driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. th e rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
VDDP. Therefore the following tables list the pad parameters for the upper voltage range
and the lower voltage range, respectively.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 28 is valid under the following conditions: VDDP≤5.5 V; VDDP≥4.5 V;
VDDPtyp. 5.0 V
Table 28 Standard Pad Par ameters for Upper Voltage Rang e
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Maximum output driver
current (absolute value)1) IOmax
CC −−4.0 mA Driver_Strength
=Medium
−−10 mA Driver_Strength
=Strong
−−0.5 mA Driver_Strength
=Weak
Nominal output driver
current (absolute value) IOnom
CC −−1.0 mA Driver_Strength
=Medium
−−2.5 mA Driver_Strength
=Strong
−−0.1 mA Driver_Strength
=Weak
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 94 V1.2, 2009-12
Rise and Fall times (10% -
90%) tRF CC −−23 +
0.6 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Medium
−−11.6 +
0.22 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Medium
−−4.2 +
0.14 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Sharp
−−20.6 +
0.22 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Slow
−−212 +
1.9 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Weak
1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16
neighboring output pins, the total outpu t current in each direct ion (ΣIOL and Σ-IOH) must remain below 50 mA.
Table 28 Standard Pad Par ameters for Upper Voltage Rang e (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 95 V1.2, 2009-12
Table 29 Standard Pad Parameters for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Maximum output driver
current (absolute value)1) IOmax
CC −−2.5 mA Driver_Strength
=Medium
−−10 mA Driver_Strength
=Strong
−−0.5 mA Driver_Strength
=Weak
Nominal output driver
current (absolute value) IOnom
CC −−1.0 mA Driver_Strength
=Medium
−−2.5 mA Driver_Strength
=Strong
−−0.1 mA Driver_Strength
=Weak
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 96 V1.2, 2009-12
Rise and Fall times (10% -
90%) tRF CC −−37 +
0.65 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Medium
−−24 +
0.3 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Medium
−−6.2 +
0.24 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Sharp
−−34 +
0.3 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Slow
−−500 +
2.5 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Weak
1) An output current above |IOXnom| may be drawn from up to three pins at the same time. For any group of 16
neighboring output pins, the total outpu t current in each direct ion (ΣIOL and Σ-IOH) must remain below 50 mA.
Table 29 Standard Pad Parameters for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 97 V1.2, 2009-12
4.7.5 Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 30 is valid under the following conditions: CL=20pF; SSC=master;
voltage_range= upper
Table 31 is valid under the following conditions: CL=20pF; SSC=master;
voltage_range= lower
Table 30 USIC SSC Master Mode Timing for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tSYS -
81)
1) tSYS = 1 / fSYS
−−ns
Slave select output SELO
inactive afte r la st
SCLKOUT receive edge
t2 CC tSYS -
61) −−ns
Data output DOUT valid
time t3 CC -6 −9ns
Receive data input setup
time to SCLKOUT receive
edge
t4 SR 31 −−ns
Data input DX0 hold time
from SCLKOUT re cei ve
edge
t5 SR -4 −−ns
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 98 V1.2, 2009-12
Table 32 is valid under the following conditions: CL=20pF; SSC= slave ;
voltage_range= upper
Table 31 USIC SSC Master Mode Timing for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tSYS -
101)
1) tSYS = 1 / fSYS
−−ns
Slave select output SELO
inactive afte r la st
SCLKOUT receive edge
t2 CC tSYS -
91) −−ns
Data output DOUT valid
time t3 CC -7 −11 ns
Receive data input setup
time to SCLKOUT receive
edge
t4 SR 40 −−ns
Data input DX0 hold time
from SCLKOUT re cei ve
edge
t5 SR -5 −−ns
Table 32 USIC SSC Slave Mode Timing for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Select input DX2 setup to
first clock input DX1
transmit edg e 1)
t10 SR 7 −−ns
Select input DX2 hold after
last clock input DX1
receive edg e1)
t11 SR 7 −−ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR 7 −−ns
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 99 V1.2, 2009-12
Table 33 is valid under the following conditions: CL=20pF; SSC= slave ;
voltage_range= lower
Data input DX0 hold time
from clock input DX1
receive edg e1)
t13 SR 5 −−ns
Data output DOUT valid
time t14 CC 7 −33 ns
1) These input timings are valid f or asynchronous input signal ha ndling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 33 USIC SSC Slave Mode Timing for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Select input DX2 setup to
first clock input DX1
transmit edg e 1)
1) These input timings are valid f or asynchronous input signal ha ndling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
t10 SR 7 −−ns
Select input DX2 hold after
last clock input DX1
receive edg e1)
t11 SR 7 −−ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR 7 −−ns
Data input DX0 hold time
from clock input DX1
receive edg e1)
t13 SR 5 −−ns
Data output DOUT valid
time t14 CC 8 −41 ns
Table 32 USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 100 V1.2, 2009-12
Figure 22 USIC - SSC Master/Slave Mod e Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock Output
SCLKOUT
Data Output
DOUT
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0
Select Output
SELOx
Active
Master Mod e Timing
Slave Mode Timing
t
11
t
10
Clock Input
DX1
Data Output
DOUT
t
14
t
14
Data
valid
Data Input
DX0
Select Input
DX2
Active
t
13
t
12
T ransmit Edge: with this clock edge, transmit data is shifted to tra nsmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Receive
Edge Last Receive
Edge
InactiveInactive
T ransmit
Edge
InactiveInactive
First Transmit
Edge Receive
Edge Transmit
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLKCFG = 00
B
. Also valid for for SCLKCFG = 01
B
with inverted SCLKOUT signal.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 101 V1.2, 2009-12
4.7.6 Debug Interface Timing
The debugger can communicate with the XC223xN either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 34 is valid un der the following conditions: CL= 20 pF; voltage_range= upper
Table 35 is valid un der the following conditions: CL= 20 pF; voltage_range= lower
Table 34 DAP Interface Timi ng for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAP0 clock period t11 SR 25 −−ns
DAP0 high time t12 SR 8 −−ns
DAP0 low time t13 SR 8 −−ns
DAP0 clock rise time t14 SR −−4ns
DAP0 clock fall time t15 SR −−4ns
DAP1 setup to DAP0
rising edge t16 SR 6 −−ns
DAP1 hold after DAP0
rising edge t17 SR 6 −−
DAP1 valid per DAP0
clock period1)
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t19 CC 17 20 −
Table 35 DAP Interface Ti ming for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAP0 clock period t11 SR 25 −−ns
DAP0 high time t12 SR 8 −−ns
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 102 V1.2, 2009-12
Figure 23 Test Clock Timing (DAP0)
Figure 24 DAP Timing Host to Device
DAP0 low time t13 SR 8 −−ns
DAP0 clock rise time t14 SR −−4ns
DAP0 clock fall time t15 SR −−4ns
DAP1 setup to DAP0
rising edge t16 SR 6 −−ns
DAP1 hold after DAP0
rising edge t17 SR 6 −−
DAP1 valid per DAP0
clock period1) t19 CC 12 17 −
1) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Table 35 DAP Interface Ti ming for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
MC_DAP0
0.9
V
DDP
0.5
V
DDP
t
11
t
12
t
13
0.1
V
DDP
t
15
t
14
t16 t17
DAP0
DAP1
MC_DAP1_RX
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 103 V1.2, 2009-12
Figure 25 DAP Timing Device to Host
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: The se parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid un der the following conditions: CL= 20 pF; voltage_range= upper
Table 36 Interface Timing for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1 SR 50 −−ns 1)
TCK high time t2 SR 16 −−ns
TCK low time t3 SR 16 −−ns
TCK clock rise time t4 SR −−8ns
TCK clock fall time t5 SR −−8ns
TDI/TMS setup to TCK
rising edge t6 SR 6 −−ns
TDI/TMS hold after TCK
rising edge t7 SR 6 −−ns
TDO valid from TCK falling
edge (propagation delay)2) t8 CC −25 29 ns
TDO high impedance to
valid output from TCK
falling edge3)2)
t9 CC −25 29 ns
DAP1
MC_DAP1_TX
t
11
t
19
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 104 V1.2, 2009-12
Table 37 is valid un der the following conditions: CL= 20 pF; voltage_range= lower
TDO valid output to high
impedance from TCK
falling edge2)
t10 CC −25 29 ns
TDO hold after TCK falling
edge2) t18 CC 5 −−ns
1) Under typical conditions, the interf ace can operate at transfer rates up to 20 MHz.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Table 37 Interface Ti ming for Lower Vol tage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1 SR 50 −−ns
TCK high time t2 SR 16 −−ns
TCK low time t3 SR 16 −−ns
TCK clock rise time t4 SR −−8ns
TCK clock fall time t5 SR −−8ns
TDI/TMS setup to TCK
rising edge t6 SR 6 −−ns
TDI/TMS hold after TCK
rising edge t7 SR 6 −−ns
TDO valid from TCK falling
edge (propagation delay)1) t8 CC −32 36 ns
TDO high impedance to
valid output from TCK
falling edge2)1)
t9 CC −32 36 ns
TDO valid output to high
impedance from TCK
falling edge1)
t10 CC −32 36 ns
TDO hold after TCK falling
edge1) t18 CC 5 −−ns
Table 36 Interface Timing for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet 105 V1.2, 2009-12
Figure 26 Test Clock Timing (TCK)
Figure 27 JTAG Timing
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
MC_JTAG_TCK
0.9 V
DDP
0.5 V
DDP
t
1
t
2
t
3
0.1 V
DDP
t
5
t
4
t
6
t
7
t
6
t
7
t
9
t
8
t
10
TCK
TMS
TDI
TDO
MC_JTAG
t
18
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Package and Reliability
Data Sheet 106 V1.2, 2009-12
5 Package and Reliability
The XC2000 Family devices use the package type PG-LQFP (Plastic Green - Low
Profile Quad Flat Package). The following specifications must be regarded to ensure
proper integration of the XC223xN in its target environment.
5.1 Packaging
These parameters specify the packaging rather than the silicon.
Note: To improve the EMC behavior, it is recommended to connect th e exposed pad to
the board ground, independent of the thermal require ments.
Board layout examples are given in an applica tion note.
Package Compatibility Considerations
The XC223xN is a member of the XC2000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
Table 38 Package Parameters (PG-LQFP-64-6)
Parameter Symbol Limit Values Unit Notes
Min. Max.
Exposed Pad Dimension Ex × Ey – 5.6 × 5.6 mm –
Power Dissipation PDISS –0.8W–
Thermal resistance
Junction-Ambient RΘJA – 31 K/W No thermal via1)
1) Device mounted on a 2-layer JE DEC board ( according t o JESD 51-3) or a 4-laye r board wi thout thermal vias;
exposed pad not soldered.
29 K/W 4-layer, no pad2)
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not
soldered.
18 K/W 4-layer, pad3)
3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered
to the board.
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Package and Reliability
Data Sheet 107 V1.2, 2009-12
Package Outlines
Figure 28 PG-LQFP-64-6 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
D
12
H
0.2 A-B D4x
A-B0.2 64x
D
B
12
1
64 64
1
Index Marking Index Marking
0.5
7.5
+0.07
0.2 -0.03
PG-LQFP-64-6, -8, -12-PO V13
0.08 MA-B D
C
COPLANARITYSEATING
PLANE
C
0.08
±0.05
0.1
STAND OFF
±0.05
1.4
1.6 MAX.
±0.15
0.6
H
A
-0.06
+0.05
0.15
0˚...7˚
64x
64x
C
10
0.5 x 45˚
1)
10 1)
1) Does not include plastic or metal protrusion of 0.25 max. per side
Bottom View
Exposed Diepad
Ox
Oy
Ex
Ey
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Package and Reliability
Data Sheet 108 V1.2, 2009-12
5.2 Thermal Considerations
When operating the XC223xN in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting the rma l
damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
