AS1115-BQFT - AMS AG - Product.Network

AS1115

64 LEDs, I²C Interfaced LED Driver with Keyscan

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 1 - 24

Datasheet

1 General Description

The AS1115 is a compact LED driver for 64 single LEDs

or 8 digits of 7-segments. The devices can be pro-

grammed via an I²C compatible 2-wire interface.

Every segment can be individually addressed and

updated separately. Only one external resistor (RSET) is

required to set the current. LED brightness can be con-

trolled by a na l og or di g i tal means.

The devices include an integrated BCD code-B/HEX

decoder, multiplex scan circuitry, segment and display

drivers, and a 64-bit memory. Internal memory stores

the shift register settings, eliminating the need for contin-

uous device reprogramming.

All outputs of the AS1115 can be configured for key

readback. Key-switch status is obtained by polling for up

to 64 keys while 16 keys can be us ed to tri g ge r an inte r-

rupt.

Additionally the AS1115 offers a diagnostic mode for

easy and fast production testing.

The AS1115 features a low shutdown current of typically

200nA, and an operational current of typicall y 350µA.

The number of digits can be programmed, the devices

can be reset by software, and an external clock is also

supported.

The device is available in a QSOP-24 and the

TQFN(4x4)-24 package.

Figure 1. AS1115 - Typical Application Diagram

2 Key Features

! 3.4MHz I²C-Compatible Interface

! Individual LED Segment Co ntrol

! Readback for 16 Keys plus Interrupt

! Open and Shorted LED Erro r Dete cti o n

- Global or Individual Error Detection

! Hexadecimal- or BCD-Code for 7-Segment Displays

! 200nA Low-Power Shutdown Current (typ; data

retained)

! Digital and Analog Brightness Control

! Display Blanked o n Powe r-U p

! Drive Common-Cathode LED Displays

! Supply Voltage Range: 2.7 to 5.5V

! Software Reset

! Optional External Clock

! Package:

- QSOP-24

- TQFN(4x4)-24

3 Applications

The AS1115 is ideal for seven-segment or dot matrix

user interface displays of set-top boxes, VCRs, DVD-

players, washing machines, micro wave ovens, refriger-

ators and other white good or personal electronic appli-

cations.

AS1115

DIG0 to

DIG7

SEGA-DP

KEY0-7

SDA

SCL

IRQ

VDD

ISET

SDA

IRQ

GND

SCL

2.7 to 5.5V

9.53kΩ

µP

KEYA

KEYB

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 2 - 24

AS1115

Datasheet - Pin o u t

4 Pinout

Pin Assignments

Figure 2. Pin Assignments (Top View)

Pin Descriptions

Table 1. Pin Descripti ons

Pin Name QSOP-24 TQFN(4x4)-24 Description

SDA 122Serial-Data I/O. Open drain digital I/O I²C data pin.

DIG0:DIG7 2-5, 7-10 1, 2, 4, 5, 6, 7,

23, 24

Digit Drive Lines. Eight digit drive lines that sink current from the display

common cathode. Keyscan detection optio nal, but must be polled by the

µProzessor.

GND 63Ground.

KEYA 11 8 Keyscan Input. Keyscan lines for key readback. Can be used for self-

adressing.

KEYB 12 9 Keyscan Input. Keyscan lines for key readback.

ISET 13 10 Set Segment Current. Connect to VDD or a reference voltage through

RSET to set the peak segment current (see Selecting RSET Resistor

Value and Using External Drivers on page 19).

SCL 14 11 Serial-Clock Input. 3.4MHz maximum rate.

IRQ 24 21 Interupt Request Output. Open drain pin.

SEGA:SEGG

, SEGDP 15-18,

20-23 12-15, 17-20 Seven Segment and Decimal Point Drive Lines. 8 seven-segment

drives and decimal point drive that source current to the display.

VDD 19 16 Positive Supply Voltage. Connect to +2.7 to +5.5V supply.

-Exposed Pad Exposed Pad. This pin also functions as a heat sink. Solder it to a large

pad or to the circuit-board ground plane to maximize power dissipation.

IRQ

SEGD

SEGDP

SEG E

SEGC

VDD

SEGG

SEGB

SEGF

SEGA

SCL

ISET

SDA

DIG0

DIG1

DIG2

DIG3

GND

DIG4

DIG5

DIG6

DIG7

KEYA

KEYB

AS1115

SEG E

KEYA

SEGB

DIG2 1

GND 3AS1115

DIG5 5

ISET

SEGA

VDD16

SEGC

SEGG

SEGF

DIG3 2

DIG4 4

DIG6 6

SCL

KEYB

DIG7

DIG0

IRQ

SEGDP

SEGD

SDA

DIG1

Exposed

Pad

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 3 - 24

AS1115

Datasheet - Ab so lu te Ma xi mu m R at in gs

5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in Sectio n 6 Electrical

Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

Table 2. Absolute Maximum Ratings

Parameter Min Max Units Notes

Input Voltage Range VDD to GND -0.3 7 V

All other pins to GND -0.3 7 or

VDD + 0.3 V

Current DIG0:DIG7 Sink Curren t 500 mA

SEGA:SEGG, SEGDP 100 mA

Humidity 5 85 % Non-condensing

Electrostatic Discharge Digital outputs 1000 V Norm: MIL 833 E method 3015

All other pin s 1000 V

Latch-Up Immunity ±100 mA EIA/JESD78

Thermal Resistance ΘJA 88 ºC/W on PCB, QSOP-24 package

30.5 ºC/W on PCB, TQFN(4x4)-24 package

Ambient Temperature -40 +85 ºC

Storage Temperature -55 150 ºC

Package Body Temperature +260 ºC

The reflow peak soldering

temperature (body temperature)

specified is in accordance with IPC/

JEDEC J-STD-020D “Moisture/

Reflow Sensitivity Classification for

Non-Hermetic Solid State Surface

Mount Devices”.

The lead finish for Pb-free leaded

packag es is matt e tin (1 00 % Sn).

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 4 - 24

AS1115

Datasheet - Ele c t r i c a l C h a r a c t e r i s t i c s

6 Electrical Characteristics

VDD = 2.7V to 5.5V, RSET = 9.53kΩ, TAMB = -40 to +85°C,

typ. values @

TAMB

= +25ºC,

VDD = 5.0V

(unless otherwise

specified).

Table 3. Electrical Characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD Operating Supply V o ltage 2.7 5.5 V

IDDSD Shutdown Supply Current All digital inputs at VDD or

GND, TAMB = +25ºC 0.2 2 µA

single digit, TAMB = +85ºC 4 µA

IDD Operating Supply Current RSET = open circuit. 0.35 0.6 mA

All segments and decimal

point on; ISEG = -40mA. 335

fOSC Display Scan Rate 8 digits scanned 0.48 0.96 kHz

IDIGIT Digit Drive Sink Current VOUT = 0.65V 320 mA

ISEG Segment Drive Source Current VDD = 5.0V, VOUT = (VDD -1V) -35 -41 -47 mA

ΔISEG Segment Drive Current Matching 3 %

ISEG Segment Drive Source Current Average Current 47 mA

Table 4. Logic Inputs/Outputs Characteristics

Symbol Parameter Conditions Min Typ Max Unit

IIH, IIL Input Current SDA, SCL VIN = 0V or VDD -1 1 µA

VIH Logic High Input Voltage SDA, SCL 0.7xVDD V

VIL Logic Low Input Voltage SDA, SCL 0.3xVDD V

VOL(SDA) SDA Output Low Voltage ISINK = 3mA 0.4 V

VKEYopen Keyscan Open Input Voltage 0.8xVDD V

VKEYshort Keyscan Short Input Voltage 0.7x VDD V

VOL(IRQ) Interrupt Output Low Voltage ISINK = 3mA 0.4 V

ΔVIHysteresis Voltage DIN, CLK, LD/CS 1 V

CBCapacitive Load for each Bus Line 400 pF

Open Detection Level Threshold 0.7x

VDD 0.75x

VDD 0.8x

VDD V

Short Detection Level Threshold 0.05x

VDD 0.1x

VDD 0.15x

VDD V

Table 5. Timing Characteristics (CB = 100pF (max) on each Bus Line)

Symbol Parameter Conditions Min Typ Max Unit

fSCL SCL Frequency 0.1 3.4 MHz

tBUF Bus Free Time Between STOP and

START Conditions 1.3 µs

tHOLDSTART Hold Time for Repeated

START Condition 160 ns

tLOW SCL Low Period 160 ns

tHIGH SCL High Period 60 ns

tSETUPSTART Setup Time for Repeated

START Condition 160 ns

tSETUPDATA Data Setup Time 10 ns

tHOLDDATA Data Hold Time 70 ns

tRISE(SCL) SCL Rise Time 10 40 ns

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 5 - 24

AS1115

Datasheet - Ele c t r i c a l C h a r a c t e r i s t i c s

Notes:

1. The Min / Max values of the Timing Characteristics are guaranteed by design.

2. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC

(Statistical Quality Control) methods.

Figure 3. Timing Diagram

tRISE(SCL1) SCL Rise Time after Repeated START

Condition and After an ACK Bit 10 80 ns

tFALL(SCL) SCL Fall Time 10 40 ns

tRISE(SDA) SDA Rise Time 10 80 ns

tFALL(SDA) SDA Fall Time 10 80 ns

tSETUPSTOP STOP Condition Setup Time 160 ns

tSPIKESUP Pulse Width of Spike Suppressed 50 ns

Key Readback

Debounce Time 20 ms

Table 5. Timing Characteristics (CB = 100pF (max) on each Bus Line)

Symbol Parameter Conditions Min Typ Max Unit

Repeated

START

SDI

SCL

STARTSTOP

tBUF

tLOW

tHOLDSTART

tHOLDDATA

tHIGH

tSETUPDATA

tHOLDSTART tSPIKESUP

tSETUPSTOP

tSETUPSTART

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 6 - 24

AS1115

Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

7 Typical Operating Characteristics

RSET = 9.53kΩ, VRset = VDD;

Figure 4. Display Scan Rate vs. Supply Voltage; Figure 5. Display Scan Rate vs. Temperature;

680

700

720

740

760

780

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

Vdd (V)

f osc (Hz) .

Tamb=-40°C

Tamb=+25°C

Tamb=+85°C 680

700

720

740

760

780

800

-40 -15 10 35 60 85

Tamb (°C)

f osc (Hz) .

Vdd=2.7V

Vdd=4V

Vdd=5V

Vdd=5.5V

Figure 6. Segment Current vs. Temperature; Figure 7. Segment Current vs. RSET;

-40 -15 10 35 60 85

Tamb (°C)

Iseg (mA) .

Vseg = 1.7V; Vdd = 2.7V

Vseg = 1.7V; Vdd = 5V

Vseg = 3V; Vdd = 5V

Vseg = 4V; Vdd = 5V 0

0 102030405060708090

Rset ( k Ohm)

Iseg (mA) .

Vseg = 4V; Vdd = 5V

Vseg = 3V; Vdd = 5V

Vseg = 2V; Vdd = 5V

Vseg = 1.7V; Vdd = 2.7V

Figure 8. Segment Current vs. Supply Voltage; Figure 9. Segment Current vs. VDD; VRset = 2.8V

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

Vdd (V)

Iseg (mA) .

Vseg = 1.7V

Vseg = 3V

Vseg = 4V

2.7 3 3.3 3.6 3.9 4.2

Vdd (V)

Iseg (mA) .

Vseg = 1.7V

Vseg = 2V

Vseg = 2.3V

Vseg = 3.1V

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 7 - 24

AS1115

Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

Figure 10. VDIGIT vs. IDIGIT Figure 11. In put High Level vs. Supply Voltage

0.1

0.2

0.3

0.4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35

Idig (A )

Vdig (V) .

Vdd = 2.7V

Vdd = 3.3V

Vdd = 4V

Vdd = 5V

Vdd = 5.5V 0

0.5

1.5

2.5

3.5

2.73.13.53.94.34.75.15.5

Vdd (V)

Vih (V) .

Figure 12. ISEG vs. VSEG; VDD = 5V Fi g ure 13. ISEG vs. VSEG; VDD = 4V

2 2.5 3 3.5 4 4.5 5

Vseg (V)

Iseg (mA) .

Rext = 10k

Rext = 13k

Rext = 18k

Rext = 30k

Rext = 56k

11.522.533.54

Vseg (V)

Iseg (mA) .

Rext = 8k2

Rext = 10k

Rext = 13k

Rext = 18k

Rext = 30k

Figure 14. ISEG vs. VSEG; VDD = 3.3V Figure 15. ISEG vs. VSEG; VDD = 2.7V

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2

Vseg (V)

Iseg (mA) .

Rext = 6k8

Rext = 8k2

Rext = 10k

Rext = 13k

Rext = 18k

1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

Vseg (V)

Iseg (mA) .

Rext = 4k

Rext = 5 k 6

Rext = 6k8

Rext = 10k

Rext = 13k

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 8 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

8 Detailed Description

Block Diagram

Figure 16. AS1115 - Block Diagram (QSOP-24 Package)

Figure 17. ESD Structure

AS1115

Registers

Digital Control

Logic

Oszillator

Open/Short

Detection

I²C

Interface

–

VDD

Scan - Registers

Control - Registers

Data - Registers

(PWM, Debounce,....)

RSET

ISET

15-18, 20-23

SEGA-G,

SEGDP

2-5, 7-10

DIG0 to DIG7

GND

VDD

11, 12

KEYA, KEYB

VDD

SDA

SCL

IRQ

VDD valid for the pins:

- IRQ

- SCL

- SDA

- ISET

- SEGA-G, SEGDP

- KEYA, KEYB

VDD

valid for the pins:

- DIG0 to DIG7

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 9 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

I²C Interface

The AS1115 supports the I²C serial bus and data transmi ssion protocol in high-speed mode at 3.4MHz. The AS1115

operates as a slave on the I²C bus. The bus must be controlled by a master device that generates the seria l clock

(SCL), controls the bus access, and generates the ST AR T and STOP conditions. Connections to the bus are made via

the open-drain I/O pi ns SC L and SDA.

Figure 18. I²C Interface Initialisation

Figure 19. Bus Protocol

The bus protocol (as shown in Figure 19) is defined as:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH will be interpreted as control signals.

The bus conditions are defi ned as:

-Bus Not Busy. Data and clock lines remain HIGH.

-St art Dat a T ransfer. A change in the state of the data line, from HIGH to LOW , while the clock is HIGH, defines a

START condition.

-Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

-Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions is not li mited and is determined by the master device.

The information is transferred byte-wise and each receiver acknowledges wit h a ninth-bit.

Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.

-Acknowledge: Each receiving device, when addressed, is oblig ed to generate an acknowledge after the recep-

tion of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge

bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pu lse in such a way

that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and

hold times must be taken into account. A master must signal an end of data to the slave by not generating an

1981 98

0000 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8

Default values at power up: A1 = A0 = 0

SDI

SCL

Slave Address R/W

Direction Bit

START

1 2 6 7 8 9 1 23-88 9

ACK

MSB

Repeat if More Bytes Transferred STOP or

Repeated

START

ACK from

Receiver

ACK from

Receiver

ACK

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 10 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

acknowledge bit on the last byte t hat has been clocked out of the slave. In this case, the slave must leave the

data line HIGH to enable the master to gene rate the STOP condition.

-Figure 19 on page 9 details how data transfer is accomplished on the I²C bus. Depending upon the state of the R/

W bit, two types of data transfer are possible:

-Master T ransmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by

a number of data bytes. The slave returns an acknowled ge bit after the slave address and each received byte.

-Slave T ransmitter to Master Receiver . The first byte, the slave address, is transmitted by the master . The slave

then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master . The

master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received

byte, a not-acknowledge is returned. The master device gen erates all of the serial clock pulses and the START

and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a

repeated START condition is also the beginning of the next serial transfer, the bus will not be released.

The AS1115 can operate in the following slave modes:

-Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an

acknowledge bit is transmitted. ST AR T and ST OP conditions are recognized as the beginning and end of a serial

transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.

-Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver

mode. However, in this mode the direction bit will indicat e that the transfer direction is reversed. Serial data is

transmitted on SDA by the AS1 115 while the serial clock is input on SCL. START and STOP conditions are recog-

nized as the beginning and end of a serial transfer.

I²C Device Self Addressing

If this feature is used, 2 of the 16 key readback nodes can be left open or shorted for self-addressing. This is done with

KEYA together with SEGG and SEGF. This two nodes cannot be used for key-readback in this case. After startup all

devices have the predefined adress 0000000. A single command for self-addressing will update all connected AS1 115.

This command has to be don e after startup or everytime the AS1115 gets disconnect ed from the supply. The I² C

address definition must be done with fixed connection, since I²C detection is excluded from debounce time of key reg-

isters.

I²C Device Address Byte

The address byte (see Figure 20) is the first byt e received following the START condition from the master device.

Figure 20. I²C Device Address Byte

- The default slave address is fa ctory-set to 0000000.

- The two LSB bits of the address byte are the device select bits, A0 to A1, which can be set by the self-adress

command after startup. A maximum of four devices with the same pre-set code can therefore be connected on

the same bus at one time.

- The last bit of the address byte (R/W) define the operation to be performe d. When set to a 1 a read operation is

selected; wh en set to a 0 a write operati on is selected.

Following the ST AR T condition, the AS1 115 monitors the I²C bus, checking the device type identifier being transmitted.

Upon receiving the address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

0000000R/W

MSB654321LSB

00000A1 A0 R/W

MSB654321LSB

predefined address:

updated address:

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 11 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Command Byte

The AS1115 operation, (see Table 6) is determined by a command byte (see Figure 21 on page 11).

Figure 21. Command Byte

Figure 22. Command and Single Data Byte Received

Figure 23. Setting the Pointer to a Address Register to select a Data Register for a Read Operation

Figure 24. Reading nBytes from AS1115

D15 D14 D13 D12 D11 D10 D09 D08

MSB654321LSB

From Master to Slave

From Slave to Master

AAPAS Command Byte Data ByteSlave Address

D14 D13 D12 D11 D10 D9 D8D15 D6 D5 D4 D3 D2 D1 D0D7

Acknowledge

from AS1115

0 00 Acknowledge

from AS1115

Acknowledge

from AS1115

R/W

AS1115 Registers

Autoincrement

Memory Word

Address

1 Byte

From Master to Slave

From Slave to Master

APAS Command Byte

Slave Address

D14 D13 D12 D11 D10 D9 D8D15

00 Acknowledge

from AS1115

Acknowledge

from AS1115

R/W

AS1115 Registers

From Master to Slave

From Slave to Master

A/APAS First Data Byte Second Data ByteSlave Address

D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0D7

Not Acknowledge

from Master

0 10 Acknowledge

from Master

Acknowledge

from AS1115

R/W

AS1115 Registers

Autoincrement

Memory Word

Address

n Bytes

Autoincrement

to next address

Stop reading

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 12 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Initial Power-Up

On initial power-up, the AS1115 regist ers are reset to their default values, the di splay is blanked, and the device goes

into shutdown mode. At this time, all registers should be programmed for normal operation.

Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control

Shutdown Mode

The AS1115 devices feature a shutdown mode, where th ey consume only 200nA (typ ) current. Shutdown mode is

entered via a write to the Shutdown Register (see Table 7). During shutdown mo de the Digit-Registers maintain their

data.

Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display

(repeatedly enteri ng and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should

be at GND or VDD (CMOS logic level).

When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown

Note: When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shut-

down mode. If the AS1115 is used with an external clock, Shutdown Register bit D7 should be set to 1 when

writing to th e Sh utdown Register.

Digit- and Control-Registers

The AS1 115 devices contain 8 Digit-Registers,1 1 control-registers and 10 diagnostic-registers, which are listed in Table

6. All registers are selected using a 8-bit address word, and communication is done via the I²C interface.

! Digit Registers – These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly

without rewriting the whole reg ister contents.

! Control Registers – These registe r s consist of decode mode, display intensity, number of scanned digits, shut-

down, display test and feat ures selection registers.

Table 6. Register Addre s s Map

Type

D15:D13 D12 D11 D10 D9 D8 D7:D0

Digit Register

Digit 0 000 0 0 0 0 1

(see Table 9 on page 14,

Table 10 on p age 14 and

Table 11 on page 15)

N/A

Digit 1 000 0 0 0 1 0 N/A

Digit 2 000 0 0 0 1 1 N/A

Digit 3 000 0 0 1 0 0 N/A

Digit 4 000 0 0 1 0 1 N/A

Digit 5 000 0 0 1 1 0 N/A

Digit 6 000 0 0 1 1 1 N/A

Digit 7 000 0 1 0 0 0 N/A

Control Register

Decode-Mode 000 0 1 0 0 1 (see Ta ble 8 on page 13)13

Global Intensity 000 0 1 0 1 0 (see Table 17 on page 17)17

Scan Limit 000 0 1 0 1 1 (see Tabl e 19 on page 17)17

Shutdown 000 0 1 1 0 0 (see Table 7 on page 13)12

Self-Adressing 001 0 1 1 0 1 N/A

Feature 000 0 1 1 1 0 (see Table 20 on page 18)18

Display Test Mode 000 0 1 1 1 1 (see Table 14 on page 16)13

DIG0:DIG1 Intensit y 000 1 0 0 0 0 (see Table 18 on page 17)

DIG2:DIG3 Intensit y 000 1 0 0 0 1 (see Table 18 on page 17)

DIG4:DIG5 Intensit y 000 1 0 0 1 0 (see Table 18 on page 17)

DIG6:DIG7 Intensit y 000 1 0 0 1 1 (see Table 18 on page 17)

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 13 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

The Shutdown Register controls AS1115 shutdown mode.

Decode Enable Register (0x09)

The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code – characters 0:9, E, H, L,

P, and -, or HEX code – characters 0:9 and A:F) is selected by bit D2 (page 18) of the Feature Register. The Decode

Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Regis-

ter corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so

on). Table 9 lists some examples of the possible settings for the Decode Enable Reg ister bits.

Note: A logic high enables de coding and a logic low bypasses the decoder altog ether.

When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,

disregarding bits D6:D4. Bit D7 sets the decimal poi nt (SEG DP) independent of the decoder and is positive logic (bit

D7 = 1 turns the decimal point on). Table 9 lists the code-B font; Table 10 lists the HEX font.

When no-decode mode is selected, data bits D7:D0 of the Digit-R egisters correspond to the segment lines of the

AS1115. Table 11 show s the 1:1 pairing of each data bit to the appropriate segment line.

Keyscan/Diagnostic Register

Diagnostic Digit 0 000 1 0 1 0 0 N/A

Diagnostic Digit 1 000 1 0 1 0 1 N/A

Diagnostic Digit 2 000 1 0 1 1 0 N/A

Diagnostic Digit 3 000 1 0 1 1 1 N/A

Diagnostic Digit 4 000 1 1 0 0 0 N/A

Diagnostic Digit 5 000 1 1 0 0 1 N/A

Diagnostic Digit 6 000 1 1 0 1 0 N/A

Diagnostic Digit 7 000 1 1 0 1 1 N/A

KEYA 000 1 1 1 0 0

KEYB 000 1 1 1 0 1

Table 7. Shutdown Register Forma t (Address (HEX) = 0x0C))

Mode HEX Code Regist er Data

D7 D6 D5 D4 D3 D2 D1 D0

Shutdown Mode,

Reset Feature Register to Default Settings 0x00 0XXXXXX0

Shutdown Mode, Feature Register Unchanged 0x80 1XXXXXX0

Normal Operation,

Reset Feature Register to Default Settings 0x01 0XXXXXX1

Normal Operation, Feature Registe r Unchanged 0x81 1 XXXXXX1

Table 8. Decode Enable Register Format Examples

Decode Mode HEX Code Register Data

D7 D6 D5 D4 D3 D2 D1 D0

No decode for digits 7:0 0x00 0000000 0

Code-B/HEX decode for digit 0. No decode for digits 7:1 0x01 00000001

Code-B/HEX decode for digit 0:2. No decode for digits 7:3 0x07 00000111

Code-B/HEX decode for digits 0:5. No decode for digits 7:6 0x3F 00111111

Code-B/HEX decode for digits 0,2,5.

No decode for digi ts 1, 3, 4, 6, 7 0x25 00100101

Table 6. Register Addre s s Map

Type

D15:D13 D12 D11 D10 D9 D8 D7:D0

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 14 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Figure 25. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking

Table 9. Code-B F ont

Char-

acter Register Data Char-

acter Register Data

D7 D6:D4 D3 D2 D1 D0 D7 D6: D4 D3 D2 D1 D0 D7 D6:D4 D3 D2 D1 D0

X 0000 X 0110 X 1100

X 0001 X 0111 X 1101

X 0010 X 1000 X 1110

X 0011 X 1001 X 1111

X 0100 X 1010 1* XXXXX

X 0101 X 1011

* The decimal point can be enabled with every character by setting bit D7 = 1.

Table 10. HEX Font

Char-

acter Register Data Char-

acter Register Data

D7 D6:D4 D3 D2 D1 D0 D7 D6: D4 D3 D2 D1 D0 D7 D6:D4 D3 D2 D1 D0

X 0000 X 0110 X 1100

X 0001 X 0111 X 1101

X 0010 X 1000 X 1110

X 0011 X 1001 X 1111

X 0100 X 1010 1* XXXXX

X 0101 X 1011

* The decimal point can be enabled with every character by setting bit D7 = 1.

EDC

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 15 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

I²C Self Addressing

If this feature is used, 2 of the 16 key readback nodes can be left open or shorted for self-addressing. This is done with

KEYA together with SEGG (A0) and SEGF (A1). This two nodes cannot be use d for key-readback in this case. After

startup all devices have the predefined adress 0000000. A single command for selfaddressing will update all con-

nected AS1115. This command has to be done after startup or everytime the AS1115 gets disconnected from the sup-

ply. The I²C address definition must be done with fixed connection, since I²C detection is excluded from debounce time

of key registers.

Note: A short writes a logical “0” whereas an open writes a logical “1” as address bit.

Keyscan Register

These two registers contain the result of the keysca n input of the 16 keys. To ensure proper results the data in these

registers are updated only if the logic data scanned is stable for 20ms (debounce time). A change of the data stored

within these two registers is indicated by a logic low on the IRQ pin. The IRQ is high-impedance if a read operation on

the key scan registers is started.

Note: If I²C self addressing is used segment G&F of KEYA is used for the two LSB of the I²C address. In this case

these two nodes cannot be us ed as a key. Additionally the debounce time is disabled for these two bits.

The data within the keyscan register is updated continuously during every cycle (1/10 of refresh rate). There-

fore, to get a valid readback of keys it is recommended to read out the keyscan registers immediately after the

IRQ is triggered. A short writes a logical “0” whereas an open writes a logical “1” as keyscan register bit.

Note: If the blink_en bit (bit D4 in the Feature Register 0x0E) is set to ‘1’, t he keyscan is not returning a valid value.

Table 11. No-Decode Mode Data Bits and Corresponding Segment Lines

D7 D6 D5 D4 D3 D2 D1 D0

Corresponding Segment Line DP A B C D E F G

Table 12. Self Addressing Register (Address (HEX) = 0x2D))

D7 D6 D5 D4 D3 D2 D1 D0

Factory-set IC address XXXXXXX0

User-set IC address X X XXXXX1

Table 13. LED Diagnostic Register Address

Key D7 D6 D5 D4 D3 D2 D1 D0

0x1C KEYA DP A B C D E F G

0x1D KEYB

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 16 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Display-Test Mode

The AS1115 can detect open or shorted LEDs. Readout of either open LEDs or short LEDs is possible, as well as a OR

relation of open and short.

Note: All settings of the digit- and control-registers are maintained.

LED Diagnostic Registers

These eight registers contain the result of the LED open/short test for the individual LED of each digit.

Note: If one or more short occures in the LED array, detection of individual LED fault cou ld become ambiguous.

Intensity Control Register (0x0A)

The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog

means using RSET (see Sel ecting RSET Resistor Value and Using External Drivers on page 19). The intensity can be

controlled globally for all digits, or for each digit individually . The global intensity command will write intensity data to all

four individual brightn ess regist ers, while the individual intesity command will only write to the associated individual

intensity register.

Table 14. Testmode Register Summary

D7 D6 D5 D4 D3 D2 D1 D0

X RSET_short RSET_open LED_global LED_test LED_open LED_short DISP_test

Table 15. Testmode Register Bit Description (Address (HEX) = 0x0F))

Addr: 0x0F Address

Bit Bit Name Default Access D7:D0

D0 DISP_test 0 W Optical display test. (Testmode for external visual test.)

0: Normal operation; 1: Run display test (All digits are tested

independently from scan limit & shutdown register.)

D1 LED_short 0 W Starts a test for shorted LEDs. (Can be set together with D2)

0: Normal operation; 1: Activat e testmode

D2 LED_open 0 W Starts a test for open LEDs. (Can be set together with D1)

0: Normal operation; 1: Activat e testmode

D3 LED_test 0 R Indicates an ongoing open/short LED test

0: No ongoing LED test; 1: LED test in progress

D4 LED_global 0 R Indicates that the last open/short LED test has detected an error

0: No error detected; 1: Error detected

D5 RSET_open 0 R Checks if external resistor RSET is open

0: RSET correct; 1: RSET is open

D6 RSET_short 0 R Checks if external resist or R SET is shorted

0: RSET correct; 1: RSET is shorted

D7 0 - Not used

Table 16. LED Diagnostic Register Address

HEX

Address

Segment Register

HEX

Address

Segment

Digit D7 D6 D5 D4 D3 D2 D1 D0 Digit D7 D6 D5 D4 D3 D2 D1 D0

0x14 DIG0

DP A B C D E F G

0x18 DIG4

DP A B C D E F G

0x15 DIG1 0x19 DIG5

0x16 DIG2 0x1A DIG6

0x17 DIG3 0x1B DIG7

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 17 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the

Intensity Control Register. The modulator scales the average segment -current in 16 steps from a maximum of 15/16

down to 1/16 of the peak current set by RSET.

Scan-Limit Register (0x0B)

The Scan-Limit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the

update frequency is typically 700Hz. If the number of digits displayed is reduced, the up date frequency is increased.

The frequency can be calculated using 10 x fOSC/(N+2), where N is the number of digits.

Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros).

Table 17. Intensity Register Format

Duty Cycle HEX Code Register Dat a Duty Cycle HEX Code Register Data

MSB D2 D1 LSB MSB D2 D1 LSB

1/16 (min on) 0xX0 0 0 0 0 9/16 0xX8 1 0 0 0

2/16 0xX1 0 0 0 1 10/16 0xX9 1 0 0 1

3/16 0xX2 0010 11/16 0xXA 1010

4/16 0xX3 0 0 1 1 12/16 0xXB 1 0 1 1

5/16 0xX4 0 1 0 0 13/16 0xXC 1 1 0 0

6/16 0xX5 0 1 0 1 14/16 0xXD 1 1 0 1

7/16 0xX6 0 1 1 0 15/16 0xXE 1 1 1 0

8/16 0xX7 0 1 1 1 15/16 (max on) 0xXF 1 1 1 1

Table 18. Intensity Register Address

Type D7:D4 D3:D0

0x0A Global X Global Intensity

0x10 Digit Digit 1 Intensity Digit 0 Intensity

0x11 Digit Digit 3 Intensity Digit 2 Intensity

0x12 Digit Digit 5 Intensity Digit 4 Intensity

0x13 Digit Digit 7 Intensity Digit 6 Intensity

Table 19. Scan-Limit Register Format (Address (H EX) = 0x0B))

Scan Limit HEX

Code Register Data Scan Limit HEX

Code Register Data

D7:D3 D2 D1 D0 D7:D3 D2 D1 D0

Display digit 0 only 0xX0 X 0 0 0 Display digits 0:4 0xX4 X 1 0 0

Display digits 0:1 0xX1 X 0 0 1 Display digits 0:5 0xX5 X 1 0 1

Display digits 0:2 0xX2 X 0 1 0 Display digits 0:6 0xX6 X 1 1 0

Display digits 0:3 0xX3 X 0 1 1 Display digits 0:7 0xX7 X 1 1 1

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 18 - 24

AS1115

Datasheet - D et a i l e d De s c r i p t i o n

Feature Register (0x0E)

The Feature Register is used for enabling various features including switching the device into external clock mode,

applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, setting the blinking rate,

and resetting th e blink timing.

Note: At power-up the Feature Reg ister is initialized to 0.

Table 20. Feature Registe r Summary

D7 D6 D5 D4 D3 D2 D1 D0

blink_

start sync blink_

freq_sel blink_en NU decode_sel reg_res clk_en

Table 21. Feature Register Bit Descriptions (Address (HEX) = 0xXE)

Addr: 0xXE Feature Register

Enables and disables various device fe atures.

Bit Bit Name Default Access Bit Description

D0 clk_en 0R/W

External clock active.

0 = Internal oscillator is used for system clock.

1 = Pin CLK of the serial interface operates as system clock input.

D1 reg_res 0R/W

Resets all control registers except the Feature Register.

0 = Reset Disabled. Normal operation.

1 = All control registers are reset to default state (except the Feature

Note: The Digit Registers maintain their data.

D2 decode_sel 0R/W

Selects display decoding for the selected digits (Table 8 on page 13).

0 = Enable Code-B decoding (see Table 9 on page 14).

1 = Enable HEX decoding (see Table 10 on page 14).

D3 NU Not used

D4 blink_en 0R/W

Enables blinking.

0 = Disable blinking. 1 = Enable blinking.

D5 blink_freq_sel 0R/W

Sets blink with low frequency (with the internal oscillato r enabled):

0 = Blink period typically is 1 second (0.5s on, 0. 5s off).

1 = Blink period is 2 seconds (1s on, 1s off).

D6 sync 0R/W

Synchronizes blinking on the rising edge of pin LD/CS. The multiplex

and blink timing counter is cleared on the rising edge of pin LD/CS. By

setting this bit in mult iple devices, the blink timin g can be synchronized

across all the devices.

D7 blink_start 0R/W

S t art Blinking with display enabled phase. When bit D4 (blink_en) is set,

bit D7 determines how blinking starts.

0 = Blinking starts with the display turned off.

1 = Blinking starts with the display turned on.

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 19 - 24

AS1115

Datasheet - Ty p i c a l A p p l i c a t i o n

9 Typical Application

Selecting RSET Resistor Value and Using External Drivers

Brightness of the display segments is controlled via RSET. The current that flo ws into ISET defines the current that flows

through the LEDs.

Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operat-

ing voltages, and LED voltage drop (VLED) are given in Table 22 & Table 23. The maximum current the AS1115 can

drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary

that the devices drive high currents.

Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 16).

Calculating Power Dissipation

The upper limit for power dissipation (PD) for the AS1115 is determined from the following equation:

PD = (VDD x 5mA) + (VDD - VLED)(DUTY x ISEG x N) (EQ 1)

Where:

VDD is the supply voltage.

DUTY is the duty cycle set by intensity register (page 17).

N is the number of segments driven (worst case is 8)

VLED is the LED forward voltage

ISEG = segment current set by RSET

Dissipation Example :

ISEG = 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V (EQ 2)

PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W (EQ 3)

Thus, for a TQFN(4x4)-24 package ΘJA = +30.5°C/W, the maximum allowed TAMB is given by:

TJ,MAX = TAMB + PD x

JA = 150°C = TAMB + 0.865W x 30.5°C/W (EQ 4)

In this example the maximum ambient temperatu re must stay below 123.61°C.

Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V

ISEG (mA) VLED VLED VLED

1.5V 2.0V 1.5V 2.0V 2.5V 1.5V 2.0V 2.5V 3.0V

VDD = 2.7V

5kΩ4.4kΩ

VDD = 3.3V

6.7kΩ6.4kΩ5.7kΩ

VDD = 3.6V

7.5kΩ7.2kΩ6.6kΩ5.5kΩ

30 6.9kΩ5.9kΩ9.1kΩ8.8kΩ8.1kΩ10.18kΩ9.8kΩ9.2kΩ7.5kΩ

20 10.7kΩ9.6kΩ13.9kΩ13.3kΩ12.6kΩ15.6kΩ15kΩ14.3kΩ13kΩ

10 22.2kΩ20.7kΩ28.8kΩ27.7kΩ26kΩ31.9kΩ31kΩ29.5kΩ27.3kΩ

Table 23. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V & 5.0V

ISEG

(mA) VLED VLED

1.5V 2.0V 2.5V 3.0V 3.5V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V

VDD = 4.0V

8.6kΩ8.3kΩ7.9kΩ7.6kΩ5.2kΩ

VDD = 5.0V

11.35kΩ11.12kΩ10.84kΩ10.49kΩ10.2kΩ9.9kΩ

30 11.6kΩ11.2kΩ10.8kΩ9.9kΩ7.8kΩ15.4kΩ15.1kΩ14.7kΩ14.4kΩ13.6kΩ13.1kΩ

20 17.7kΩ17.3kΩ16.6kΩ15.6kΩ13.6kΩ23.6kΩ23.1kΩ22.6kΩ22kΩ21.1kΩ20.2kΩ

10 36.89kΩ35.7kΩ34.5kΩ32.5kΩ29.1kΩ48.9kΩ47.8kΩ46.9kΩ45.4kΩ43.8kΩ42kΩ

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 20 - 24

AS1115

Datasheet - Ty p i c a l A p p l i c a t i o n

8x8 Dot Matrix Mode

The application example in Figure 26 shows the AS1115 in the 8x8 LED dot matrix mode.

The LED columns have common cathodes an d are connected to the DIG0:7 outputs. The rows are connected to the

segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed

in Table 6 on page 12.

The Decode Enable Register (see page 13) must be set to ‘00000000’ as described in Table 8 on page 13. Single

LEDs in a column can be addressed as described in Table 11 on page 15, where bit D0 corresponds to segment G and

bit D7 corresponds to segment DP.

Figure 26. Application Example as LED Dot Matrix Driver

Keyscan

The key readback of the AS1115 can be used eit her for push buttons as well as switches. If only a single key is

pressed (shorted) at a time no add itional diodes are required. If a detection of multiple simultaneous keystrokes is

required diodes wi thin the keypath, as shown in Figure 27, are required. Pressing multiple keys without the diodes

would result in ambiguous resu lts. Since KEYA and KEYB have independent inputs only keys on the same path are

affected.

Figure 27. Keyscan Configuration

Note: If the blink_en bit (bit D4 in the Feature Register 0x0E) is set to ‘1’, t he keyscan is not returning a valid value.

Supply Bypassing and Wiring

In order to achieve optimal performance the AS1 115 should be placed very close to the LED display to minimize effects

of electromagnetic interference and wiring inductance.

Furthermore, it is recommended to connect a 10µF and a 0.1µF ceramic capacitor between pins VDD and GND to

avoid power supply ripple (see Figure 26).

Diode Arrangement

DIG0 to

DIG7

SEG A to G

SEP DP

AS1115

SDA

SCL

IRQ

VDD

ISET

SDA

IRQ

GND

SCL

2.7 to 5V 9.53kΩ

µP

KEYA

KEYB

SEGA SEGB SEGC SEGD SEG E SEGF SEGG SEGDP

IRQ Diodes are optional and only required if multiple keystrokes must be

detected simultaneously.

If I²C Self-Adressing is used these two keys cannot be used for read-

back and must be either hard wired opened or shorted.

A short writes a logical “0” whereas an open writes a logical “1” as

address bit.

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 21 - 24

AS1115

Datasheet - Pa ck ag e D ra wi ng s a nd Marking s

10 Package Drawings and Markings

The AS1115 is available in the QSOP-24 package.

Figure 28. QSOP-24 Package

Symbol Min Max

A 1.35 1.75

A1 0.10 0.25

A2 1.37 1.57

b 0.20 0.30

C 0.19 0.25

D 8.55 8.74

E 5.79 6.20

E1 3.81 3.99

e 0.635 BSC

h 0.22 0.49

L 0.40 1.27

θ0º 8º

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 22 - 24

AS1115

Datasheet - Pa ck ag e D ra wi ng s a nd Marking s

Figure 29. TQFN(4x4)-24 Package

Notes:Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.

1. All dimensions are in millimeters; angles in degrees.

2. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm f r om terminal tip.

Dimension L1 represents terminal full back from package edge up to 0.1mm is acceptable.

3. Coplanarity applies to the exposed heat slug as well as the termin al.

4. Radius on terminal is optional.

2419 20 21 22 23

789101112

Symbol Min Typ Max

A 0.50 0.55 0.60

A1 0.00 0.05

A3 0.152REF

b 0.18 0.23 0.28

D 4.00BSC

E 4.00BSC

D2 2.70 2.80 2.90

E2 2.70 2.80 2.90

Symbol Min Typ Max

e 0.50BSC

L 0.30 0.35 0.40

L1 0.00 0.10

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 23 - 24

AS1115

Datasheet - O r d e r i n g I n f o m a t i o n

11 Ordering Infomation

The devices are available as t he standard products shown in Tabl e 24.

Note: All products are RoHS compliant and Pb-free.

Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect

For further info rmation and requests, please contact us mailto:sales@austriamicrosystems.com

or find your local distribu tor at http://www.austriamicrosystems.com/distributor

Table 24. Ordering Information

Ordering Code Marking Description Delivery Form Package

AS1115-BSST AS1115 64 LEDs, I²C Interfaced LED Driver

with Keyscan Tape and Reel QSOP-24

AS1115-BQFT ASSD Tape and Reel TQFN(4x4)-24

www.austriamicrosystems.com/LED-Driver-ICs/AS1115 Revision 1.07 24 - 24

AS1115

Datasheet

Copyrights

translated, stored, or used without the prior written conse nt of the copyright owner.

All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing

in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding

the information set forth herein or regarding the freedom of the describ ed devices from patent infringement.

austriamicrosyst ems AG reserves the right to change spec ifications and prices at any time and without notice.

Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for

current information. This product is intended for use in normal commercial applicat ions. Applications requiring

extended temperature range, unusual environmental requirements, or high reliability applications, such as military,

medical life-support or life-sustaining equipment are specifically not recommended without additional processing by

austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show

deviations from the standard production flow, such as t est flow or test location.

The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,

austriamicrosystems AG shall not be liable to reci pient or any third party for any damages, including but not limited to

personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or

consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-

nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of

austriamicrosystems AG rendering of technical or other services.

Cont act Information

Headquarters

austriamicrosystems AG

Tobelbaderstrasse 30

A-8141 Unterpremstaetten, Austria

Tel: +43 (0) 3136 500 0

Fax: +43 (0) 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:

http://www.austriamicrosystems.com/contact