1www.pericom.com 01/04/13
Product Features
LVDS compatible outputs
Supply voltage of 3.3V ±10%
25MHz input frequency
HCSL outputs, 0.7V Current mode dierential pair
Jitter 60ps cycle-to-cycle (typ)
Spread of ±0.25%, -0.5%, -0.75%, and no spread
Industrial temperature range
Packaging: (Pb-free and Green)
16-pin, 173 mils wide TSSOP
PI6C557-03
PCI Express Clock
Description
e PI6C557-03 is a spread spectrum clock generator
supporting PCI Express and Ethernet requirements. e device
is used for PC or embedded systems to substantially reduce
Electromagnetic Interference (EMI).
e PI6C557-03 provides two dierential (HCSL) spread spectrum
outputs. e PI6C557-03 is congured to select spread and clock
selection. Using Pericom's patented Phase-Locked Loop (PLL)
techniques, the device takes a 25MHz crystal input and produces
two pairs of dierential outputs (HCSL) at 25MHz, 100MHz,
125MHz and 200MHz clock frequencies. It also provides spread
selection of ±0.25%, -0.5%, -0.75%, and no spread.
Block Diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDX
CLK0
CLK0
GNDA
VDDA
CLK1
CLK1
IREF
S0
S1
SS0
X1/CLK
X2
OE
GNDX
SS1
Pin Conguration
Phase Lock Loop
Crystal
Driver
VDD
GND
X1/CLK
X2
25 MHz
crystal or clock
Control
Logic
SS1:SS02
S1:S0
2
CLK0
CLK0
RR
CLK1
CLK1
2
2
OE
Pulling
Capacitors
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PI6C557-03
PCI Express Clock
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Pin Description
Pin # Pin Name I/O Type Description
1S0 Input Select pin 0 (Internal pull-up resistor). See Table 1.
2 S1 Input Select pin 1 (Internal pull-up resistor). See Table 1.
3 SS0 Input Spread Select pin 0 (Internal pull-up resistor). See Table 2.
4 X1/CLK Input Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
5 X2 Output Crystal connection. Leave unconnected for clock input.
6OE Input Output enable. Internal pull-up resistor.
7 GNDX Power Crystal ground pin.
8 SS1 Input Spread Select pin 1 (Internal pull-up resistor). See Table 2.
9 IREF Output Precision resistor attached to this pin is connected to the internal current reference.
10 CLK1 Output HCSL compliment clock output
11 CLK1 Output HCSL clock output
12 VDDA Power Connect to a +3.3V source.
13 GNDA Power Output and analog circuit ground.
14 CLK0 Output HCSL compliment clock output
15 CLK0 Output HCSL clock output
16 VDDX Power Connect to a +3.3V source.
Table 1: Output Select Table
S1 S0 CLK(MHz)
0 0 25
0 1 100
1 0 125
1 1 200
Table 2: Spread Selection Table
SS1 SS0 Spread
0 0 Center ±0.25
0 1 Down -0.5
1 0 Down -0.75
1 1 No Spread
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PI6C557-03
PCI Express Clock
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Application Information
Decoupling Capacitors
Decoupling capacitors of 0.01μF should be connected between
each VDD pin and the ground plane and placed as close to the
VDD pin as possible.
Crystal
Use a 25MHz fundamental mode parallel resonant crystal with
less than 300PPM of error across temperature.
Crystal Capacitors
CL = Crystals's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
For example, for a crystal with 16pF load caps, the external ef-
fective crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance is 50Ω,
then RR = 475Ω providing an IREF of 2.32 mA. e output
current (IOH) is 6*IREF.
Output Termination
e PCI Express dierential clock outputs of the PI6C557-03
are open source drivers and require an external series resistor
and a resistor to ground. ese resistor values and their allow-
able locations are shown in detail in the PCI Express Layout
Guidelines section.
e PI6C557-03 can be congured for LVDS compatible voltage
levels. See the LVDS Compatible Layout Guidelines section.
R
R
=475
6*IREF
=2.3mA IREF
See Output Termination
Sections
Output Structures
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PI6C557-03
PCI Express Clock
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PCI Express Layout Guidelines
Common Recommendations for Dierential Routing Dimension or Value Unit
L1 length, route as non-coupled 50Ω trace. 0.5 max inch
L2 length, route as non-coupled 50Ω trace. 0.2 max inch
L3 length, route as non-coupled 50Ω trace. 0.2 max inch
R
S
33
R
T
49.9
Dierential Routing on a Single PCB Dimension or Value Unit
L4 length, route as coupled microstrip 100Ω dierential trace. 2 min to 16 max inch
L4 length, route as coupled stripline 100Ω dierential trace. 1.8 min to 14.4 max inch
Dierential Routing to a PCI Express connector Dimension or Value Unit
L4 length, route as coupled microstrip 100Ω dierential trace. 0.25 min to 14 max inch
L4 length, route as coupled stripline 100Ω dierential trace. 0.225 min to 12.6 max inch
R
S
R
S
R
T R
T
PCI-Express
Load or
Connector
L1 L2
L3’
L4
L1’ L2’
L3
L4’
PI6C557-03
Output
Clock
0.175 V
0.52 V
0.175 V
0.52 V
t
OR t
OF
500 ps 500 ps
700 mV
0
PCI Express Device Routing
Typical PCI Express (HCSL) Waveform
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PI6C557-03
PCI Express Clock
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Application Information
LVDS Recommendations for Dierential Routing Dimension or Value Unit
L1 length, route as non-coupled 50Ω trace. 0.5 max inch
L2 length, route as non-coupled 50Ω trace. 0.2 max inch
R
P
100
R
Q
100
R
T
150
L3 length, route as 100Ω dierential trace.
L3 length, route as 100Ω dierential trace.
LVDS Device Routing
Typical LVDS Waveform
L1
L2’
L3
L1’
L2
L3’
R
Q R
P
LVDS
Device
Load
PI6C557-03
Clock
Output
R
T
R
T
1150 mV
1250 mV
t
OR t
OF
500 ps 500 ps
1325 mV
1000 mV
1150 mV
1250 mV
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PI6C557-03
PCI Express Clock
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Supply Voltage to Ground Potential ...........................................................5.5V
All Inputs and Outputs ..................................................... -0.5V to VDD+0.5V
Ambient Operating Temperature .................................................-40 to +85°C
Storage Temperature .....................................................................-65 to +150°C
Junction Temperature .............................................................................. 150°C
Soldering Temperature ............................................................................. 260°C
Electrical Specications
Maximum Ratings
Recommended Operation Conditions
Parameter Min. Typ. Max. Unit
Ambient Operating Temperature -40 +85 °C
Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V
DC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C)
Symbol Parameter Conditions Min. Typ. Max. Unit
VDD Supply Voltage 3.0 3.3 3.60 V
V
IH
Input High Voltage(1) S0, S1, OE, CLK, SS0, SS1 2.0 VDD +0.3 V
V
IL
Input Low Voltage(1) S0, S1, OE, CLK, SS0, SS1 GND -0.3 0.8 V
IIL Input Leakage Current 0 < Vin < VDD
With input pull-up
and pull-downs -20 20
µA
Without input pull-up
and pull-downs -5 5
I
DD
Operating Supply
Current
R
L
= 50Ω, C
L
= 2pF 65 mA
I
DDOE
OE = LOW 35 mA
CIN Input Capacitance Input pin capacitance 7 pF
COUT Output Capacitance Output pin capacitance 6 pF
L
PIN
Pin Inductance 5 nH
R
OUT
Output Resistance CLK Outputs 3.0
Notes:
1. Single edge is monotonic when transitioning through region.
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. is is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specication is not implied. Ex-
posure to absolute maximum rating conditions for extended
periods may aect reliability.
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PI6C557-03
PCI Express Clock
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AC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85oC)
Symbol Parameter Conditions Min. Typ. Max. Unit
F
IN
Input Frequency 25 MHz
VOUT Output Frequency 25 200 MHz
VOH Output High Voltage (1,2) @VDD = 3.3V 660 700 850 mV
V
OL
Output Low Voltage(1,2) -150 0 mV
V
CPA
Crossing Point Voltage(1,2) Absolute 250 350 550 mV
VCN Crossing Point Voltage(1,2,4) Variation over all edges 140 mV
JCC Jitter, Cycle-to-Cycle(1,3) 60 100 ps
MF
Modulation Frequency Spread Spectrum 30 31.5 33 kHz
tOR Rise Time(1,2) From 0.175V to 0.525V 175 332 700 ps
tOF Fall Time(1,2) From 0.525V to 0.175V 175 344 700 ps
T
R
/∆T Rise/Fall Time Variation(1,2) 125 ps
T
SKEW
Skew between outputs VDD/2 50 ps
TDU TY-
CYCLE
Duty Cycle(1,3) 45 55 %
T
OE
Output Enable Time(5) All outputs 0.1 μs
TOT Output Disable Time(5) All outputs 0.1 μs
tSTABLE From power-up to VDD=3.3V 1.6 3.0 ms
t
SPREAD
Setting period aer spread change 3.0 ms
Ferror Synthesizer Error PLL locked, xtal load is matched and
SSC o 0ppm
Notes:
1. RL = 50Ω with CL = 2 pF and RR = 475Ω
2. Single-ended waveform
3. Dierential waveform
4. Measured at the crossing point
5. CLK pins are tri-stated when OE is LOW
ermal Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
θJA ermal Resistance Junction to Ambient Still air 90 °C/W
θ
JC
ermal Resistance Junction to Case 24 °C/W
Recomended Crystal Specication
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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PI6C557-03
PCI Express Clock
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Ordering Information(1-3)
Ordering Code Package Code PackageType
PI6C557-03LE L Pb-free & Green, 16-Pin TSSOP
Note:
1. ermal characteristics and package top marking information can be found at http://www.pericom.com/packaging/
2. E = lead-free and green packaging
3. Adding an X sux = tape/reel
Pericom Semiconductor Corporation 1-800-435-2336 | All Trademarks Property of Respective Owners
Packaging Mechanical: 16-contact TSSOP (L)
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
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