LTC3309A
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
5V, 6A Synchronous Step-Down
Silent Switcher in 2mm x 2mm LQFN
The LTC
®
3309A is a very small, high efficiency, low noise,
monolithic synchronous 6A step-down DC/DC converter
operating from a 2.25V to 5.5V input supply. Using con-
stant frequency, peak current mode control at switching
frequencies up to 3MHz and minimum on-time as low as
22ns, this regulator achieves fast transient response with
small external components. Silent Switcher architecture
minimizes EMI emissions.
The LTC3309A operates in forced continuous or pulse
skip mode for low noise, or the low-ripple Burst Mode
operation for high efficiency at light loads, ideal for bat-
tery-powered systems. The IC regulates output voltages
as low as 500mV. Other features include output over-
voltage protection, short-circuit protection, thermal shut-
down, clock synchronization, and up to 100% duty cycle
operation for low dropout. The device is available in a low
profile 12-lead 2mm × 2mm ×0.74mm LQFN package
with exposed pad for low thermal resistance.
High Efficiency, 2MHz, 1.2V 6A Step-Down Converter
Efficiency and Power Loss
in Burst Mode Operation
APPLICATIONS
n High Efficiency: 8mΩ NMOS, 31mΩ PMOS
n Programmable Frequency to 3MHz
n Tiny Inductor and Capacitors
n Peak Current Mode Control
n 22ns Minimum On-Time
n Wide Bandwidth, Fast Transient Response
n Silent Switcher™ Architecture
n Ultralow EMI Emissions
n Low Ripple Burst Mode
®
Operation with IQ of 40µA
n Safely Tolerates Inductor Saturation in Overload
n VIN Range: 2.25V to 5.5V
n VOUT Range: 0.5V to VIN
n VOUT Accuracy: ±1% Over Temperature Range
n Precision 400mV Enable Threshold
n Shutdown Current: 1µA
n Power Good, Internal Compensation and Soft Start
n Thermally Enhanced 2mm × 2mm LQFN Package
n AEC-Q100 Qualified for Automotive Applications
n Optical Networking, Servers, Telecom
n Automotive, Industrial, Communications
n Distributed DC Power Systems (POL)
n FPGA, ASIC, µP Core Supplies
All registered trademarks and trademarks are the property of their respective owners.
1µF
0201
3309A TA01a
EN SW
SW
VIN VIN
PGND
140k10pF
10µF
10µF
220nH
100k
10nF
33µF
x2
V
OUT
1.2V
6A
V
IN
= 2.25V TO 5.5V
VIN
FB
AGND
PGOOD
LTC3309A
1µF
0201
MODE/SYNC
RT
f
OSC
= 2MHz
V
IN
= 3.3V
V
OUT
= 1.2V
f
SW
= 2 MHz
EFFICIENCY
COILCRAFT XEL3515–221
LOAD CURRENT (A)
0.001
0.01
0.1
1
6
0
10
20
30
40
50
60
70
80
90
100
0.0001
0.001
0.01
0.1
1
10
EFFICIENCY (%)
POWER LOSS (W)
3309A TA01b
LTC3309A
2
Rev. A
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN .............................................................. –0.3V to 6V
EN ........................ –0.3V to Lesser of (VIN + 0.3V) or 6V
FB ........................ –0.3V to Lesser of (VIN + 0.3V) or 6V
MODE/SYNC ........ –0.3V to Lesser of (VIN + 0.3V) or 6V
RT ........................ –0.3V to Lesser of (VIN + 0.3V) or 6V
AGND to PGND ....................................... –0.3V to +0.3V
PGOOD ......................................................... –0.3V to 6V
IPGOOD ......................................................................5mA
Operating Junction Temperature Range (Note 2):
LTC3309AE ....................................... –40˚C to +125°C
LTC3309AI .........................................–40˚C to +125˚C
LTC3309AJ ........................................–40˚C to +150˚C
LTC3309AH .......................................–40˚C to +150˚C
LTC3309AMP .....................................–55˚C to +150˚C
Storage Temperature Range .................–65˚C to +150°C
Maximum Reflow (Package Body) Temperature ...260°C
(Note 1)
TOP VIEW
AGND
EN
VIN
PGND
RT
MODE/SYNC
VIN
PGND
FB
PGOOD
SW
SW
10
9
8
7
1
2
3
4
LQFN PACKAGE
12-LEAD (2mm × 2mm × 0.74mm)
TJMAX = 150°C, θJA = 51°C/W, θJB = 12°C/W,
θJCBOTTOM = 8.6°C/W, θJCTOP = 73°C/W, ΨJT = 0.6°C/W
θ
AND Ψ
VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PCB,
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
13
PGND
12 11
5 6
ORDER INFORMATION
TAPE AND REEL TAPE AND REEL MINI PART MARKING* PACKAGE TYPE TEMPERATURE RANGE
LTC3309AEV#TRPBF LTC3309AEV#TRMPBF LHFP
LQFN
(Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3309AIV#TRPBF LTC3309AIV#TRMPBF LHFP –40°C to 125°C
LTC3309AJV#TRPBF LTC3309AJV#TRMPBF LHFP –40°C to 150°C
LTC3309AHV#TRPBF LTC3309AHV#TRMPBF LHFP –40°C to 150°C
LTC3309AMPV#TRPBF LTC3309AMPV#TRMPBF LHFP –55°C to 150°C
AUTOMOTIVE PRODUCTS**
LTC3309AEV#WTRPBF LTC3309AEV#WTRMPBF LHFP
LQFN
(Laminate Package with QFN Footprint)
–40°C to 125°C
LTC3309AIV#WTRPBF LTC3309AIV#WTRMPBF LHFP –40°C to 125°C
LTC3309AJV#WTRPBF LTC3309AJV#WTRMPBF LHFP –40°C to 150°C
LTC3309AHV#WTRPBF LTC3309AHV#WTRMPBF LHFP –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
LTC3309A
3
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
Operating Supply Voltage (VIN)l2.25 5.5 V
VIN Undervoltage Lockout
VIN Undervoltage Lockout Hysteresis
VIN Rising l2.0 2.1
150
2.2 V
mV
VIN Quiescent Current in Shutdown VEN = 0.1V 1 2 µA
VIN Quiescent Current (Note 3) Burst Mode Operation, Sleeping
All Modes, Not Sleeping
40
1.2
60
2
µA
mA
Enable Threshold
Enable Threshold Hysteresis
VEN Rising l0.375 0.4
50
0.425 V
mV
EN Pin Leakage VEN =0.5V ±20 nA
Voltage Regulation
Regulated Feedback Voltage (VFB)l0.495 0.5 0.505 V
Feedback Voltage Line Regulation VIN = 2.25V to 5.5V 0.015 0.05 %/V
FB Pin Input Current VFB = 0.5V ±20 nA
Minimum On Time (tON,min) VIN = 5.5V l22 42 ns
Maximum Duty Cycle l100 %
Top Switch ON-Resistance 31 mΩ
Bottom Switch ON-Resistance 8 mΩ
Top Switch Current Limit (IPEAKMAX) VOUT/VIN ≤ 0.2 9.1 9.6 10.1 A
Bottom Switch Current Limit (IVALLEYMAX) 7.8 A
Bottom Switch Reverse Current Limit (IREVMAX) Forced Continuous Mode –1.5 –3.0 –4.5 A
SW Leakage Current VEN = 0.1V ±100 nA
Power Good and Soft-Start
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated VOUT l
l
97
0.7
98
1.2
99
1.7
%
%
Overvoltage Rising Threshold
Overvoltage Hysteresis
As a Percentage of the Regulated VOUT l
l
107
1
110
2.2
114
3.5
%
%
PGOOD Delay 120 µs
PGOOD Pull Down Resistance VPGOOD = 0.1V 10 20 Ω
PGOOD Leakage Current VPGOOD = 5.5V 20 nA
Soft-Start Duration VOUT rising from 0V to PGOOD Threshold l0.25 1 3 ms
Oscillator and MODE/SYNC
Default Oscillator Frequency l1.9 2 2.1 MHz
Oscillator Frequency with RT = 34.8kΩ l1.9 2 2.1 MHz
Frequency Range RT Programming and Synchronization l1 3 MHz
Minimum SYNC High or Low Pulse Width l40 ns
SYNC Pulse Voltage Levels Level High
Level Low
l
l
1.2
0.4
V
V
MODE/SYNC No Clock Detect Time 10 µs
MODE/SYNC Pin Threshold For Programming Pulse Skip Mode
For Programming Forced Continuous Mode
For Programming Burst Mode Operation
l
l
l
1.0
VIN – 0.1
Float
0.1
VIN – 1.0
V
V
V
The l denotes the specifications which apply over the specified operating
junction temperature range (Note 2), otherwise specifications are at TA = 25°C; VIN=3.3V, VEN=VIN, MODE/SYNC=Float, unless
otherwise noted.
LTC3309A
4
Rev. A
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3309A is tested under pulsed load conditions such
that TJ≈TA. The LTC3309AE is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LTC3309AI is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3309AJ and LTC3309AH are guaranteed
over the –40°C to 150°C operating junction temperature range. The
LTC3309AMP is guaranteed over the –55°C to 150°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures above
125°C. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance,
and other environmental factors. The junction temperature (TJ in °C) is
calculated from ambient temperature (TA in °C) and power dissipation (PD
in Watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance. See High Temperature Considerations section for more
details.
The LTC3309A includes overtemperature protection that protects the
device during momentary overload conditions. Junction temperatures will
exceed 150°C when overtemperature protection is engaged. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 3: Supply current specification does not include switching currents.
Actual supply currents will be higher.
ELECTRICAL CHARACTERISTICS
LTC3309A
5
Rev. A
For more information www.analog.com
Default Switching Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=3.3V, TA = 25°C, unless otherwise noted.
Switch On Resistance Switch On Resistance
Switching Frequency
Default Switching Frequency
RT Switching Frequency
Feedback Voltage Minimum On-Time Minimum On-Time
TEMPERATURE (C)
–50
–25
0
25
50
75
100
125
150
495
496
497
498
499
500
501
502
503
504
505
FEEDBACK VOLTAGE (mV)
3309A G01
150°C
25°C
–50°C
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
0
10
20
30
40
50
60
MINIMUM ON–TIME (ns)
3309A G02
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
MINIMUM ON–TIME (ns)
3309A G03
PMOS
NMOS
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
4
8
12
16
20
24
28
32
36
40
44
R
DS(ON)
(mΩ)
3309A G04
V
IN
= 3.3V
PMOS
NMOS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
5
10
15
20
25
30
35
40
R
DS(ON)
(mΩ)
3309A G05
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
1.80
1.84
1.88
1.92
1.96
2.00
2.04
2.08
2.12
2.16
2.20
DEFAULT FREQUENCY (MHz)
3309A G06
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.80
1.84
1.88
1.92
1.96
2.00
2.04
2.08
2.12
2.16
2.20
DEFAULT FREQUENCY (MHz)
3309A G07
R
T
(kΩ)
20
25
30
35
40
45
50
55
60
65
70
75
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
FREQUENCY (MHz)
3309A G08
R
T
= 34.8 kΩ
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.80
1.84
1.88
1.92
1.96
2.00
2.04
2.08
2.12
2.16
2.20
FREQUENCY (MHz)
3309A G09
LTC3309A
6
Rev. A
For more information www.analog.com
VIN UVLO Threshold
VIN Shutdown Current
VIN Quiescent Current, Burst
Mode Operation, Sleeping
VIN Quiescent Current All Modes,
Not Sleeping
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=3.3V, TA = 25°C, unless otherwise noted.
Switch Current Limits
EN Threshold
PMOS Current Limit
Switch Leakage
PMOS Current Limit
V
OUT
/V
IN
= 0.2
PMOS I
PEAKMAX
NMOS I
VALLEYMAX
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
3309A G10
SWITCH CURRENT (A)
V
OUT
/V
IN
= 0.2
INPUT VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
3309A G11
150°C
25°C
–60°C
PMOS CURRENT (A)
V
IN
= 5V
V
IN
= 2.5V
V
IN
= 3.3V
DUTY CYCLE (%)
0
10
20
30
40
50
60
70
80
90
100
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
PMOS CURRENT (A)
3309A G12
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
V
IN
CURRENT (µA)
3309A G13
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
30
35
40
45
50
55
60
65
70
V
IN
CURRENT (µA)
3309A G14
V
IN
= 5.5V
V
IN
= 3.3V
V
IN
= 2.25V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.00
1.05
1.10
1.15
1.20
1.25
1.30
V
IN
CURRENT (mA)
3309A G15
V
IN
= 5.5V
PMOS
NMOS
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
SWITCH LEAKAGE CURRENT (µA)
3309A G16
EN RISING
EN FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
340
350
360
370
380
390
400
410
EN THRESHOLD (mV)
EN Threshold
3309A G17
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.8
1.9
2.0
2.1
2.2
2.3
2.4
V
IN
UVLO (V)
V
IN
UVLO Threshold
3309A G18
LTC3309A
7
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=3.3V, TA = 25°C, unless otherwise noted.
UV, OV PGOOD Thresholds
Efficiency, VIN=2.5V
Burst Mode Operation
Efficiency vs fSW,
3.3VINto1.2VOUT, ILOAD=3A
Efficiency, VIN=3.3V
Burst Mode Operation
Efficiency vs VIN, VOUT=1.2V,
fSW=2MHz, BurstMode
Operation
Efficiency, VIN=5.0V
Burst Mode Operation
Efficiency vs Load, 3.3Vto1.2V,
fSW=2MHz
VOUT Load Regulation in
VOUT=1.2V Application
VOUT Line Regulation in
VOUT=1.2V Application
UV, V
OUT
RISING
UV, V
OUT
FALLING
OV, V
OUT
RISING
OV, V
OUT
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
96
98
100
102
104
106
108
110
112
PERCENTAGE OF THE REGULATED V
OUT
(%)
UV, OV PGOOD Thresholds
3309A G19
V
IN
= 2.5V
V
IN
= 3.3V
V
IN
= 5V
I
LOAD
(A)
0
1
2
3
4
5
6
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
In V
OUT
= 1.2V Application
V
OUT
Load Regulation
3309A G20
I
LOAD
= 0A
I
LOAD
= 1A
I
LOAD
= 3A
I
LOAD
= 6A
INPUT VOLTAGE (V)
2.5
3
3.5
4
4.5
5
5.5
1.188
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
1.212
V
OUT
(V)
In V
OUT
= 1.2V Application
V
OUT
Line Regulation
3309A G21
f
SW
= 2MHz, COILCRAFT XEL3515–221
V
OUT
= 0.5V
V
OUT
= 0.75V
V
OUT
= 1.0V
V
OUT
= 1.2V
V
OUT
= 1.8V
I
LOAD
(A)
0.001
0.01
0.1
1
6
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
3309A G22
V
OUT
= 0.5V
V
OUT
= 0.75V
V
OUT
= 1.0V
V
OUT
= 1.2V
V
OUT
= 1.8V
I
LOAD
(A)
0.001
0.01
0.1
1
6
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
3309A G23
f
SW
= 2MHz, COILCRAFT XEL3515–221
f
SW
= 2MHz, COILCRAFT XEL3515–221
V
OUT
= 1.0V
V
OUT
= 1.2V
V
OUT
= 1.8V
V
OUT
= 2.5V
V
OUT
= 3.3V
I
LOAD
(A)
0.001
0.01
0.1
1
6
50
55
60
65
70
75
80
85
90
95
100
EFFICIENCY (%)
3309A G24
COILCRAFT XEL3515 SERIES
L = 150nH
L = 220nH
L = 350nH
SWITCHING FREQUENCY (MHz)
1
1.4
1.8
2.2
2.6
3.0
87
88
89
90
91
92
EFFICIENCY (%)
3309A G25
COILCRAFT XEL3515–221
6A (CONTINUOUS)
0.1A (BURSTING)
V
IN
(V)
2
2.5
3
3.5
4
4.5
5
5.5
80
82
84
86
88
90
92
EFFICIENCY (%)
3309A G26
BURST
PULSE SKIP
FC
f
SW
= 2MHz, COILCRAFT XEL3515–221
I
LOAD
(A)
0.001
0.01
0.1
1
6
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3309A G27
LTC3309A
8
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=3.3V, TA = 25°C, unless otherwise noted.
Switching Waveforms,
Forced Continuous Mode
Switching Waveforms,
Pulse Skip Mode
Switching Waveforms,
Burst Mode Operation
Start-Up Waveforms
Burst Mode Operation
Start-Up Waveforms
Pulse Skip Mode
Start-Up Waveforms
Forced Continuous Mode
Load Transient Response,
Forced Continuous Mode
Load Transient Response,
Pulse Skip Mode
Load Transient Response,
Burst Mode Operation
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
PGOOD
5V/DIV
I
L
1A/DIV
3309A G28
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
PGOOD
5V/DIV
I
L
500mA/DIV
3309A G29
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
RLOAD = 120Ω
200µs/DIV
EN
2V/DIV
V
OUT
500mV/DIV
PGOOD
5V/DIV
I
L
500mA/DIV
3309A G30
200ns/DIV
SW
2V/DIV
V
OUT
10mV/DIV
I
L
1A/DIV
3309A G31
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
ILOAD = 1A
4µs/DIV
SW
2V/DIV
V
OUT
10mV/DIV
I
L
200mA/DIV
3309A G32
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
ILOAD = 10mA
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
ILOAD = 100mA
800ns/DIV
SW
2V/DIV
V
OUT
10mV/DIV
I
L
500mA/DIV
3309A G33
V
OUT
50mV/DIV
I
L
2A/DIV
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 66µF, L = 220nH
LOAD STEP: 0.1A TO 4.5A IN 1µs
10µs/DIV
3309A G34
ILOAD
2.5A/DIV
10µs/DIV
V
OUT
50mV/DIV
I
L
2A/DIV
3309A G35
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 66µF, L = 220nH
LOAD STEP: 0.1A TO 4.5A IN 1µs
ILOAD
2.5A/DIV
10µs/DIV
3309A G36
V
OUT
50mV/DIV
I
L
2A/DIV
3.3VIN to 1.2VOUT, 2MHz TYPICAL APPLICATION
COUT = 66µF, L = 220nH
LOAD STEP: 0.1A TO 4.5A IN 1µs
ILOAD
2.5A/DIV
LTC3309A
9
Rev. A
For more information www.analog.com
PIN FUNCTIONS
AGND (Pin 1): The AGND pin is the output voltage remote
ground sense. Connect the AGND pin directly to the nega-
tive terminal of the output capacitor at the load. The AGND
pin is also the ground reference for the internal analog cir-
cuitry. Place a small analog bypass 0201 or 0402 ceramic
capacitor as close as possible to the VIN (Pin 3) and AGND
pins. Connect RT and FB returns to AGND as well.
EN (Pin 2): The EN pin has a precision IC enable thresh-
old with hysteresis. An external resistor divider, from
VIN or from another supply, can be used to program the
threshold below which the LTC3309A will shut down. If
the precision threshold is not required, tie EN directly
to VIN. When the EN pin is low the LTC3309A enters a
low current shutdown mode where all internal circuitry
is disabled. Do not float this pin.
VIN (Pins 3, 8): The VIN pins supply current to internal
circuitry and topside power switch. Connect both VIN pins
together with short wide traces and bypass to PGND and
AGND with low ESR capacitors located as close as pos-
sible to the pins.
PGND (Pins 4, 7, Exposed Pad Pin 13): The PGND pins
are the return path of the internal bottom side power
switch. Connect the negative terminal of the input capaci-
tors as close to the PGND pins as possible. For low para-
sitic inductance and good thermal performance, connect
Pin 4 and Pin 7 to a large continuous ground plane on
the printed circuit board directly under the LTC3309A.
The PGND exposed pad is the main electrical and thermal
highway and should be connected to large PCB ground
plane(s) with many vias.
SW (Pins 5, 6): The SW pins are the switching outputs of
the internal power switches. Connect these pins together
and to the inductor with a short, wide trace.
MODE/SYNC (Pin 9): The MODE/SYNC pin is a mode
selection and external clock synchronization input. Ground
this pin to enable Pulse Skip mode at light loads. For
higher efficiency at light loads, tie this pin to V
IN
to enable
the low-ripple Burst Mode operation. For faster transient
response, lower noise and full frequency operation over
a wide load range, float this pin to enable forced continu-
ous mode. Drive MODE/SYNC with an external clock to
synchronize the switcher to the applied frequency. While
synchronizing, the part operates in the forced continuous
mode. The slope compensation is automatically adapted
to the external clock frequency. In the absence of an
external clock the switching frequency is determined by
theRTpin.
RT (Pin 10): The RT pin sets the switching frequency with
an external resistor to AGND. If this pin is tied to VIN, the
buck will switch at the default oscillator frequency. If the
external clock is driving the MODE/SYNC pin, the RT pin
is ignored.
PGOOD (Pin 11): The PGOOD pin is the open drain output
of an internal power good comparator. When the regulated
output voltage falls below the PGOOD threshold or rises
above the overvoltage threshold, this pin is pulled low.
When VIN is above VIN UVLO and the part is in shutdown,
this pin is also pulled low.
FB (Pin 12): Program the output voltage and close the
control loop by connecting this pin to the middle node
of a resistor divider between the VOUT and AGND. The
LTC3309A regulates FB to 500mV (typical). A phase lead
capacitor connected between FB and VOUT may be used
to optimize transient response.
LTC3309A
10
Rev. A
For more information www.analog.com
BLOCK DIAGRAM
+
–
0.4V
FAULT
FAULT
+
–
0.55V
+
–
0.49V
SS
ISS
3309A BD
VIN
V
IN
SW
PGND
FB
PGOOD
L
COUT
V
OUT
CIN
VIN
CSS
CFF
RA
RB
SWITCH LOGIC
AND
ANTI-SHOOT
THROUGH
QS
R
MODE/SYNC
RT
BURST
DETECT
+
–
OSCILLATOR
INTERNAL
REFERENCE
SLOPE
COMP
EN
R1
R2
(OPT)
AGND
RT
0.55V
0.5V
0.49V
MODE
DETECT
BURST
FORCED CONTINUOUS
PULSE SKIP
RC
CC
CPAR
GM0.5V
VC
3, 8
5, 6
4, 7, AND
13 (EXPOSED PAD)
12
11
9
10
2
1
LTC3309A
11
Rev. A
For more information www.analog.com
OPERATION
Voltage Regulation
The LTC3309A is a 5V, 6A monolithic, constant frequency,
peak current mode control, step-down DC/DC converter.
The synchronous buck switching regulators are internally
compensated and require only external feedback resistors
to set the output voltage. An internal oscillator, with the
frequency set using a resistor on the RT pin or synchro-
nized to an external clock, turns on the internal top power
switch at the beginning of each clock cycle. Current in the
inductor ramps up until the top switch current comparator
trips and turns off the top power switch. The peak induc-
tor current at which the top switch turns off is controlled
by an internal VC voltage. The error amplifier regulates VC
by comparing the voltage on the FB pin with an internal
500mV reference. An increase in the load current causes a
reduction in the feedback voltage relative to the reference,
causing the error amplifier to raise the VC voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on and ramps down the inductor cur-
rent for the remainder of the clock cycle or, if in pulse skip
or Burst mode, until the inductor current falls to zero. If
an overload condition results in excessive current flowing
through the bottom switch, the next clock cycle will be
skipped until switch current returns to a safe level.
The enable pin has a precision 400mV threshold to pro-
vide event-based power-up sequencing by connecting the
EN pin to the output of another buck through a resistor
divider. If the EN pin is low, the device is shut down and
in a low quiescent current state. When the EN pin is above
its threshold, the switching regulator will be enabled.
The LTC3309A has forward and reverse inductor current
limiting, short-circuit protection, output over-voltage pro-
tection, and soft-start to limit inrush current during start-
up or recovery from a short-circuit.
Mode Selection
The LTC3309A operates in three different modes set by
the MODE/SYNC pin: pulse skip mode (when the MODE/
SYNC pin is set low), forced continuous mode (when the
MODE/SYNC pin is floating) and Burst Mode operation
(when the MODE/SYNC pin is set high).
In pulse skip mode, the oscillator operates continuously
and positive SW transitions are aligned to the clock.
Negative inductor current is disallowed and, during light
loads, switch pulses are skipped to regulate the output
voltage.
In forced continuous mode, the oscillator operates con-
tinuously. The top switch turns on every cycle and regu-
lation is maintained by allowing the inductor current to
reverse at light load. This mode allows the buck to run
at a fixed frequency with minimal output ripple. In forced
continuous mode, if the inductor current reaches ILIMR
(into the SW pin), the bottom switch will turn off for the
remainder of the cycle to limit the current.
In Burst Mode operation at light loads, the output capaci-
tor is charged to a voltage slightly higher than its regu-
lation point. The regulator then goes into a sleep state,
during which time the output capacitor provides the
load current. In sleep, most of the regulator’s circuitry is
powered down, helping conserve input power. When the
output voltage drops below its programmed value, the
circuitry is powered on and another burst cycle begins.
The sleep time decreases as load current increases. In
Burst Mode operation, the regulator will burst at light
loads whereas at higher loads it will operate in constant
frequency PWM mode.
LTC3309A
12
Rev. A
For more information www.analog.com
OPERATION
Synchronizing the Oscillator to an External Clock
The LTC3309A’s internal oscillator can be synchronized
through an internal PLL circuit to an external frequency
by applying a square wave clock signal to the MODE/
SYNC pin.
During synchronization, the top power switch turn-on is
locked to the rising edge of the external frequency source.
While synchronizing, the switcher operates in forced con-
tinuous mode. The slope compensation is automatically
adapted to the external clock frequency. The synchroniza-
tion frequency range is 1MHz to 3MHz.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the signal on the MODE/SYNC pin. When the external
clock is removed, the LTC3309A will detect the absence
of the external clock within approximately 10μs. During
this time, the PLL will continue to provide clock cycles.
Once the external clock removal has been detected, the
oscillator will gradually adjust its operating frequency to
the one programmed by the RT pin.
Output Power Good
When the LTC3309A’s output voltage is within the
–2%/+10% window of the nominal regulation voltage the
output is considered good and the open-drain PGOOD pin
goes high impedance and is typically pulled high with an
external resistor. Otherwise, the internal pull-down device
will pull the PGOOD pin low. The PGOOD pin is also pulled
low during the following fault conditions: EN pin is low,
VIN is too low or thermal shutdown. To filter noise and
short duration output voltage transients, the lower thresh-
old has a hysteresis of 1.2%, the upper threshold has a
hysteresis of 2%, and both have a built-in time delay to
report PGOOD, typically 120µs.
Output Overvoltage Protection
During an output overvoltage event, when the FB pin volt-
age is greater than 110% of nominal, the LTC3309A top
power switch will be turned off. If the output remains out
of regulation for more than 120µs, the PGOOD pin will
be pulled low.
An output overvoltage event should not happen under
normal operating conditions.
Overtemperature Protection
To prevent thermal damage to the LTC3309A and its sur-
rounding components, the device incorporates an over-
temperature (OT) function. When the die temperature
reaches 165°C (typical, not tested) the switcher is shut
down and remains in shutdown until the die temperature
falls to 160°C (typical, not tested).
Output Voltage Soft-Start
Soft starting the output prevents current surge on the
input supply and/or output voltage overshoot. During the
soft-start, the output voltage will proportionally track the
internal node voltage ramp. An active pull-down circuit
discharges that internal node in the case of fault condi-
tions. The ramp will restart when the fault is cleared. Fault
conditions that initiate the soft-start ramp are the EN pin
transitioning low, VIN voltage falling too low, or thermal
shutdown.
Dropout Operation
As the input supply voltage approaches the output volt-
age, the duty cycle increases toward 100%. Further reduc-
tion of the supply voltage forces the main switch to remain
on for more than one cycle, eventually reaching 100%
duty cycle. The output voltage will then be determined by
the input voltage minus the DC voltage drop across the
internal P-channel MOSFET and the inductor.
LTC3309A
13
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Low Supply Operation
The LTC3309A is designed to operate down to an input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the RDS(ON) of the inter-
nal power switches increases. Calculate the worst case
LTC3309A power dissipation and die junction temperature
at the lowest input voltages.
Output Short-Circuit Protection and Recovery
The peak inductor current level, at which the current com-
parator shuts off the top power switch, is controlled by the
internal VC voltage. When the output current increases,
the error amplifier raises VC until the average inductor
current matches the load current. The LTC3309A clamps
the maximum V
C
voltage, thereby limiting the peak induc-
tor current.
When the output is shorted to ground, the inductor cur-
rent decays very slowly when the bottom power switch
is on because the voltage across the inductor is low. To
keep the inductor current in control, a secondary limit is
imposed on the valley of the inductor current. If the induc-
tor current measured through the bottom power switch
remains greater than IVALLEYMAX at the end of the cycle,
the top power switch will be held off. Subsequent switch-
ing cycles will be skipped until the inductor current falls
below IVALLEYMAX.
Recovery from an output short circuit may involve a soft-
start cycle if V
FB
falls more than approximately 100mV
below regulation. During such a recovery, VFB will quickly
charge up by that ~100mV and then follow the soft-start
ramp until regulation is reached.
Refer to the Block Diagram for reference.
Output Voltage and Feedback Network
The output voltage is programmed by a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
RA=RB
VOUT
500mV – 1
⎛
⎝
⎜⎞
⎠
⎟
(1)
as shown in Figure1:
Figure1.
COUT
CFF
RA
VOUT
FB
3309A F01
BUCK
SWITCHING
REGULATOR (OPTIONAL)
+
RB
Feedback Resistor Network
Reference designators refer to the Block Diagram. Typical
values for RB range from 40kΩ to 400kΩ. 0.1% resistors
are recommended to maintain output voltage accuracy.
The buck regulator transient response may improve with
an optional phase lead capacitor C
FF
that helps cancel
the pole created by the feedback resistors and the input
capacitance of the FB pin. Experimentation with capaci-
tor values between 2pF and 22pF may improve transient
response. The values used in the typical application cir-
cuits are a good starting point.
Operating Frequency Selection and T
rade-Offs
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response and input
voltage range.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
LTC3309A
14
Rev. A
For more information www.analog.com
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
The minimum on-time of the buck regulator imposes a
minimum operating duty cycle. The highest switching
frequency (fSW(MAX)) for a given application can be cal-
culated as follows:
fSW MAX
( )
=
VOUT
tON MIN
( )
• VIN MAX
( )
(2)
where VIN(MAX) is the maximum input voltage, VOUT
is the output voltage and tON(MIN) is the minimum top
switch on-time. This equation shows that a slower
switching frequency is necessary to accommodate a high
VIN(MAX)/VOUT ratio.
The LTC3309A is capable of a maximum duty cycle of
100%, therefore, the VIN-to-VOUT dropout is limited by
the RDS(ON) of the top switch, the inductor DCR and the
load current.
Setting the Switching Frequency
The LTC3309A uses a constant frequency peak current
mode control architecture. There are three methods to
set the switching frequency.
The first method, connecting the RT pin to VIN, sets the
switching frequency to the internal default with a nominal
value of 2MHz.
The second method is with a resistor (RT) tied from the
RT pin to ground. The frequency can be programmed
from 1MHz to 3MHz. Table1 and the Equation 3 show
the necessary R
T
value for a desired switching frequency:
RT=
73.4
f
sw
– 1.9
(3)
where RT is in kΩ and fSW is the desired switching fre-
quency in MHz, ranging from 1MHz to 3MHz.
APPLICATIONS INFORMATION
Table1. RT Value vs Switching Frequency
fSW (MHz) RT (kΩ)
1.0 71.5
1.2 59.0
1.4 49.9
1.6 43.2
1.8 38.3
2.0 34.8
2.2 30.9
2.4 28.7
2.6 26.1
2.8 24.3
3.0 22.6
The third method to set the switching frequency is by syn-
chronizing the internal PLL circuit to an external square
wave clock applied to the MODE/SYNC pin. The synchro-
nization frequency range is 1MHz to 3MHz. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.2V. High and low pulse widths should
both be at least 40ns.
Inductor Selection and Maximum Output Current
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR and
core loss.
Select the inductor value based on the following equation:
L≥VOUT
1.8A • fSW
• 1−VOUT
V
IN MAX
( )
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟ for VOUT
V
IN MAX
( )
≤0.5
(4)
L≥0.25 • VIN MAX
( )
1.8A • f
SW
for VOUT
V
IN MAX
( )
>0.5
(5)
where fSW is the switching frequency, VIN(MAX) is the
maximum input voltage.
To avoid overheating of the inductor choose an induc-
tor with an RMS current rating that is greater than the
maximum expected output load of the application.
Overload and short-circuit conditions need to be taken
into consideration.
LTC3309A
15
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
In addition, ensure that the saturation current rating
(typically labeled ISAT) of the inductor is higher than the
maximum expected load current plus half the inductor
ripplecurrent:
ISAT >ILOAD MAX
( )
+
1
2
ΔIL
(6)
where I
LOAD(MAX)
is the maximum output load current for
a given application and ΔIL is the inductor ripple current
calculated as:
ΔIL=VOUT
L • f
SW
• 1– VOUT
V
IN
⎛
⎝
⎜
⎞
⎠
⎟
(7)
A more conservative choice would be to use an inductor
with an I
SAT
rating higher than the maximum current limit
of the LTC3309A.
To keep the efficiency high, choose an inductor with
the lowest series resistance (DCR). The core material
should be intended for high frequency applications.
Table 2 shows recommended inductors from several
manufacturers.
Table2. Recommended Inductors with Typical Specifications
Inductance (nH) ITEMP (A)* ISAT (A) DCR (mΩ) W×L×H (mm) Manufacturer Manufacturer's Part Number
220-560 9.3-5.1 9.3-6.7 9.5-18.7 3.0×3.0×1.2 Vishay IHLP-1212AB-11
330 5.2 6.8 16 2.7×2.2×1.0 Sumida 252010CDMCCDS-R33MC
330, 470 6.0, 4.9 8.5, 6.7 14, 23 2.5×2.0×1.2 Murata DFE252012F
330 5.6 7.6 16 2.5×2.0×1.0 Murata DFE252010F-R33M
330 6.4 7.5 14 2.5×2.0×1.2 Cyntec HMLQ25201B-R33MSR-87
330 5.5 7.3 16 2.5×2.0×1.0 Cyntec HMLQ25201T-R33MSR
330 5.5 8.3 14 3.0×3.0×2.0 Wurth Elektronik 744383360033
250 5.5 12 10 3.2×2.5×1.5 Wurth Elektronik 74479290125
240 6 9.5 18 2.5×2.0×1.0 NIC NPIM20LP
240 6.5 7.5 15 2.0×1.6×1.0 NIC NPIM26LP
240 5.2 6.5 19 2.2×1.8×1.0 Sumida 201610CDMCCDS-R24MC
240 6 7.8 13 2.0×1.6×1.2 Murata DFE201612E-R24M
240 5.5 7 16 2.0×1.6×1.0 Murata DFE201610E-R24M
220 5.9 7.0 9.4 2.5×2.0×1.0 Cyntec HMLB25201T- R22MSR-01
220 7.4 7.1 8.4 2.5×2.0×1.2 Vishay IHHP1008ABERR22M01
220 8.0 7.0 13(max) 2.5×2.0×1.2 XFRMS XFHCLY3LT-R22M
72-560 23.6-8.1 16.0-6.5 2.85-21.5 3.2×3.5×1.5 Coilcraft XEL3515
110 6.3 11 8 2.0×1.2×1.0 Murata DFE201210S-R11M
100 7.7 12.8 9 2.5×2.0×1.2 Cyntec VCTA25201B-R10MSG-87
100 11.5 12.9 7.35 3.3×3.3×1.0 Vishay IHLP1212AZEER10M5A
100 6 11 6 2.5×2.0×2.0 XFRMS XF2520A-R10M
*Strongly depends on the PCB thermal properties
second function is to store energy in order to satisfy tran-
sient loads and stabilize the LTC3309A’s control loop.
The LTC3309A is internally compensated and has been
designed to operate at a high bandwidth for fast tran-
sient response capability. The selection of C
OUT
affects
the bandwidth of the system, but the transient response
is also affected by V
OUT
, V
IN
, f
SW
and other factors. A
good place to start is with the output capacitance value
of approximately:
COUT =20 • IMAX
fSW
0.5
VOUT
(8)
where COUT is the recommended output capacitor value
in µF, fSW is the switching frequency in MHz, IMAX=6A
is the rated output current in Amps, and VOUT is in Volts.
A lower value output capacitor saves space and cost but
transient performance will suffer and loop stability must
be verified.
Ceramic capacitors have very low equivalent series
resistance (ESR) and provide the best output ripple and
transient performance. Use X5R or X7R ceramic capaci-
tors (see Table3). Even better output ripple and transient
performance can be achieved by using low-ESL reverse
geometry or three-terminal ceramic capacitors.
During a load step, the output capacitor must instanta-
neously supply the current to support the load until the
feedback loop increases the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo-
nents and the output capacitor size. Typically, 3 to 4 cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. Although affected by
VOUT, VIN, fSW, tON(MIN), the equivalent series inductance
(ESL) of the output capacitor, and other factors, the output
droop, VDROOP, is usually about 3 times the linear drop
of the first cycle:
VDROOP =3 • ΔIOUT
C
OUT
• f
SW
(9)
where ΔIOUT is the load step.
Input Capacitors
Bypass the input of the LTC3309A with at least two
ceramic capacitors close to the part, one on each side
from VIN to PGND, for best performance. These capaci-
tors should be 0603 or 0805 in size. Smaller, optional
0201 capacitors can also be placed as close as possible
to the LTC3309A directly on the traces leading from VIN
(Pin3) and PGND (Pin4) and on the traces leading from
VIN (Pin8) and PGND (Pin7) for better performance with
minimal (if at all) increase in application footprint. See the
layout section for more detail. X7R or X5R capacitors are
recommended for best performance across temperature
and input voltage variations (see Table3). Note that larger
input capacitance is required when a lower switching fre-
quency is used. If the input power source has high imped-
ance, or there is significant inductance due to long wires
or cables, additional bulk capacitance may be necessary.
This can be provided with an electrolytic capacitor.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LTC3309A circuit is plugged into a live sup-
ply, the input voltage can ring to twice its nominal value,
possibly exceeding the LTC3309A’s voltage rating. This
situation is easily avoided (see Application Note AN88).
Table3. Ceramic Capacitor Manufacturers
VENDOR URL
AVX www.avxcorp.com
Murata www.murata.com
TDK www.tdk.com
Taiyo Yuden www.t-yuden.com
Samsung www.samsungsem.com
Wurth Elektronik www.we-online.com
Output Capacitor, Output Ripple and Transient
Response
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LTC3309A at the SW pin to produce the DC output.
In this role, it determines the output ripple; thus, low
impedance at the switching frequency is important. The
LTC3309A
16
Rev. A
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APPLICATIONS INFORMATION
LTC3309A
17
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Transient performance and control loop stability can be
improved with a higher COUT and/or the addition of a
feedforward capacitor CFF placed between VOUT and FB.
Capacitor CFF provides phase lead compensation by cre-
ating a high frequency zero which improves the phase
margin and the high-frequency response. The values used
in the typical application circuits are a good starting point.
LTpowerCAD
®
is a useful tool to help optimize CFF and
COUT for a desired transient performance.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to experimentally verify
transient performance and control loop stability, and to
optimize CFF and COUT.
When using the load transient response method to sta-
bilize the control loop apply an output current pulse of
20% to 100% of full load current having a very fast rise
time. This will produce a transient on the output voltage.
Monitor VOUT for overshoot or ringing that might indicate
a stability problem (see Application NoteAN149).
Output Voltage Sensing
The LTC3309A’s AGND pin is the ground reference for the
internal analog circuitry, including the bandgap voltage
reference. To achieve good load regulation connect the
AGND pin to the negative terminal of the output capacitor
(COUT) at the load. Any drop in the high current power
ground return path will be compensated. The AGND
node carries very little current and, therefore, can be a
minimal size trace. Place a small analog bypass 0201
or 0402 ceramic capacitor as close as possible to the
LTC3309A directly on the traces leading from VIN (Pin3)
and AGND pin. All of the signal components, such as the
FB resistor dividers and the RT resistor, should be refer-
enced to the AGND node. See the example PCB Layout
for moreinformation.
Enable Threshold Programming
The LTC3309A has a precision threshold enable pin to
enable or disable the switching. When forced low, the
device enters a low current shutdown mode.
The rising threshold of the EN comparator is 400mV,
with 50mV of hysteresis. The EN pin can be tied to VIN
if the shutdown feature is not used. Adding a resistor
divider from VIN to EN programs the LTC3309A to regu-
late the output only when VIN is above a desired voltage
(see Figure2). Typically, this threshold, VIN(EN), is used
in situations where the input supply is current limited, or
has a relatively high source resistance. A switching regu-
lator draws near constant power from its input source,
so source current increases as source voltage drops. This
looks like a negative resistance load to the source and can
cause the source to current limit or latch low under low
source voltage conditions. The V
IN(EN)
threshold prevents
the regulator from operating at source voltages where
problems may occur. This threshold can be adjusted by
setting the values R1 and R2 such that they satisfy the
followingequation:
VIN EN
( )
=R1
R2 +1
⎛
⎝
⎜⎞
⎠
⎟• 400mV
(10)
as shown in Figure2:
Figure2.
R1
VIN
EN
3309A F02
BUCK
SWITCHING
REGULATOR R2
EN Divider
The LTC3309A will remain off until VIN is above VIN(EN).
The buck regulator will remain enabled until VIN falls to
0.875•VIN(EN) and EN is 350mV.
Alternatively, a resistor divider from an output of an
upstream regulator to the EN pin of the LTC3309A pro-
vides event-based power-up sequencing, enabling the
LTC3309A when the output of the upstream regulator
reaches a predetermined level (e.g. 90% of the regu-
lated output). Replace VIN(EN) in Equation10 with that
predeterminedlevel.
LTC3309A
18
Rev. A
For more information www.analog.com
Low EMI PCB Layout
The LTC3309A is specifically designed to minimize
EMI/EMC emissions and also to maximize efficiency
and improve transient response when switching at
highfrequencies.
See Figure3 for a recommended PCB layout.
For optimal performance the LTC3309A requires that
both input supply VIN pins (Pins 3, 8) each have a local
decoupling capacitor with their ground terminals soldered
directly to the ground plane on the top layer near PGND
pins (Pins 4, 7). These capacitors provide the AC current
to the internal power MOSFETs and their drivers. Large,
switched currents flow in the VIN and PGND pins and the
input capacitors. The loops formed by the input capacitors
should be as small as possible by placing the capacitors
adjacent to the VIN and PGND pins. Capacitors with small
case size such as 0603 are optimal due to lowest parasitic
Figure3a. Recommended PCB Layout for the LTC3309A
Small Solution Size
inductance. Even smaller 0201 capacitors can additionally
be placed right next to the respective VIN and PGND pins
for better performance with minimal (if at all) increase in
application footprint. In addition, place a local, unbroken
ground plane under the application circuit on the layer
closest to the surface layer.
Decoupling AGND is also very important. Place a small
analog bypass, 0201 or 0402 capacitor as close as pos-
sible to the LTC3309A directly on the traces leading from
VIN (Pin 3) and AGND (Pin 1).
Place the inductor on the same side of the circuit board.
The trace connecting SW pins (Pins5,6) to the inductor
should be as short as possible to reduce radiated EMI and
parasitic coupling.
Keep the FB and RT nodes small and far away or shielded
from the noisy SW node.
APPLICATIONS INFORMATION
3309A F03b
PGND
AGND
COUT3 COUT1
COUT4 COUT2
VOUT
L
CIN1
RB
RA
CFF
CIN2
CIN4
CIN3
PGND
VIN
VIN
GROUND PLANE ON LAYER 2
RT
CBYP
1
7
4
10
13
3309A F03a
PGND
AGND
VOUT
VOUT
COUT1
COUT2
L
CIN1
RB
RA
CFF
CIN2
CIN4
CIN3
PGND
VIN
VIN
GROUND PLANE ON LAYER 2
RT
CBYP
1
7
4
10
13
Figure 3b. Recommended PCB Layout for the LTC3309A with
capacitors COUT1 and COUT2 rotated by 90°, which reduces
high-frequency output ripple. Optional 0201 capacitors COUT3
and COUT4 further improve the high-frequency output ripple
LTC3309A
19
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
High Temperature Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LTC3309A. Connect the exposed
pad on the bottom of the package (Pin 13) to a large,
unbroken ground plane under the application circuit on
the layer closest to the surface layer. Place many vias to
minimize thermal and electrical impedance. Solder the
PGND pins (Pins 4, 7) directly to a ground plane on the
top layer. Connect the top layer ground plane to ground
plane(s) on lower levels with many thermal vias. These
layers will spread heat dissipated by the LTC3309A.
Figure4 is a simplified thermal representation of a ther-
mally enhanced LQFN package with exposed pad, with
the silicon die and thermal metrics identified. The current
source represents power loss PD on the die; node voltages
represent temperatures; electrical impedances represent
conductive thermal impedances θ
JCBOTTOM
, θ
JCTOP
, θ
VIA
,
θCB, and convective thermal impedances θBA and θCA. The
junction temperature, TJ, is calculated from the ambient
temperature, TA, as:
TJ = TA + PD • θJA (11)
where, neglecting the θJCTOP + θCA path:
θJA≈θJCBOTTOM +
θ
CB
+θ
BA
2
⎛
⎝
⎜⎞
⎠
⎟!
θ
CB
+θ
BA
2
+θVIA
⎛
⎝
⎜⎞
⎠
⎟
(12)
where θJCBOTTOM = 8.6°C/W. The value of θJA =
51°C/W reported in the Pin Configuration section cor-
responds to JEDEC standard 2S2P test PCB, which
does not have good thermal vias, i.e., θ
VIA
is relatively
high. Assuming, somewhat arbitrarily but not unrea-
sonably, that θVIA~(θCB+θBA)/2, we back calculate
(θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board. The
importance of thermal vias becomes clear once we
observe that if the test PCB had low-thermal-resistance
vias, the θJA would have been reduced by up to 10°C/W,
which is an improvement of up to 20%. Similarly, having
more ground planes that are larger, uninterrupted and
higher-copper-weight improves θ
CB
+ θ
BA
, which has a
dominant effect on θJA, given the low value of θJCBOTTOM
of the package. See the Application Note, “Application
Notes for Thermally Enhanced Leaded Plastic Packages”,
for the proper size and layout of the thermal vias and sol-
der stencils. The maximum load current should be derated
as the ambient temperature approaches the maximum
junction rating. Power dissipation within the LTC3309A
is estimated by calculating the total power loss from an
efficiency measurement and subtracting the inductor loss.
Figure4.
θJCBOTTOM
θJCTOP
θCA
θCB
θCB
θCB
θCB θVIA
θBA
θBA
θBA
θBA
PCB
LQFN
TJ
TA
TA
TA
TA
PD
PCB
TA
TCTOP
3309A F04
DIE PACKAGE
SUBSTRATE
Multi-Layer PCB with Thermal Vias Acts as a Heat Sink
LTC3309A
20
Rev. A
For more information www.analog.com
VIN UVLO 3.0V, 1MHz, 1.8V, 6A, Pulse Skip Mode
Small Solution Size, 3MHz, 1.2V, 6A, Forced Continuous Mode
3309A TA02
EN SW
SW
VIN VIN
PGND
71.5k
261k15pF
10µF
10µF
470nH
100k
68µF
x2
VOUT
1.8V
6A
VIN = 3.0V TO 5.5V
VFB
1.3M
200k
1M
VIN
AGND
PGOOD
LTC3309A
10nF
VIN
1µF
0201
MODE/SYNC
RT
fOSC = 1MHz
1µF
0201
3309A TA03
EN SW
SW
VIN VIN
PGND
22.6k
140k10pF
10µF
10µF
150nH
100k
22µF
x2
VOUT
1.2V
6A
VIN = 2.25V TO 5.5V
VFB
1µF
0201
1µF
0201
1M
VIN
AGND
PGOOD
LTC3309A
10nF
VIN
MODE/SYNC
RT
FLOAT
fOSC = 3MHz
TYPICAL APPLICATIONS
LTC3309A
21
Rev. A
For more information www.analog.com
VIN UVLO 3.0V, 2.5V, 6A, Syncing to 1MHz
3309A TA04
EN SW
SW
VIN VIN
PGND
VIN
402k6.8pF
10µF
10µF
680nH
100k
47µF
x2
VOUT
2.5V
6A
VIN = 3.0V TO 5.5V
VFB
1.3M
200k
511k
VOUT
AGND
PGOOD
LTC3309A
10nF
VIN
1µF
0201
1µF
0201
MODE/SYNC
RT
fSYNC = 1MHz
TYPICAL APPLICATIONS
High Efficiency, 2MHz, 6A, 5V to 3.3V
3309A TA05
SW
SW
EN
PGND
511k
10µF
VOUT
AGND
PGOOD
LTC3309A
562k6.8pF
10µF
330nH
100k
VOUT
3.3V
6A
VIN = 5V
FB 22µF
x2
10nF
VIN
VIN VIN
0.1µF
0201
1µF
0201
MODE/SYNC
RT
fOSC = 2MHz
LTC3309A
22
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
High Efficiency, 2MHz, 6A, 5V to 2.5V
High Efficiency, 2MHz, 6A, 3.3V to 1.8V
3309A TA06
SW
SW
VIN VIN
402k6.8pF
10µF
330nH
100k
VOUT
2.5V
6A
VIN = 5V
FB
EN
PGND
511k
10µF
VOUT
AGND
PGOOD
LTC3309A 22µF
x2
10nF
VIN
1µF
0201
1µF
0201
MODE/SYNC
RT
fOSC = 2MHz
3309A TA07
EN SW
SW
VIN VIN
PGND
511k
261k15pF
10µF
10µF
220nH
100k
33µF
x2
VOUT
1.8V
6A
VOUT
VIN = 3.3V
FB
AGND
PGOOD
LTC3309A
10nF
VIN
1µF
0201
1µF
0201
MODE/SYNC
RT
fOSC = 2MHz
LTC3309A
23
Rev. A
For more information www.analog.com
High Efficiency, 2MHz, 6A, 3.3V to 1.0V
High Efficiency, 2MHz, 6A, 2.5V to 0.75V
3309A TA08
LTC3309A
EN SW
SW
VIN VIN
200k10pF
10µF
10µF
180nH
200k
33µF
x2
VOUT
1.0V
6A
VIN = 3.3V
FB
511k
VOUT
AGND
PGOOD
10nF
VIN
PGND
1µF
0201
1µF
0201
MODE/SYNC
RT
fOSC = 2MHz
SW
SW
VIN
VIN
100k10pF
10µF
10nF
10µF
150nH
200k
47µF
x2
VOUT
0.75V
6A
FB
3309A TA09
EN
VIN = 2.5V
511k
VOUT
AGND
PGOOD
VIN
LTC3309A
PGND
1µF
0201
1µF
0201
MODE/SYNC
RT
fOSC = 2MHz
TYPICAL APPLICATIONS
LTC3309A
24
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
LQFN Package
12-Lead (2mm × 2mm × 0.74mm)
(Reference LTC DWG # 05-08-1530 Rev B)
DETAIL B
A
PACKAGE TOP VIEW
5
PIN 1
CORNER
Y
X
aaa Z2×
12b
PACKAGE BOTTOM VIEW
4
6
SEE NOTES
E
D
b
e
e
b
E1
D1
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
H2
H1
L
DETAIL A
DETAIL C
SUGGESTED PCB LAYOUT
TOP VIEW
0.0000
0.0000
0.7500
0.2500
0.2500
0.7500
0.2500
0.2500
DETAIL A
PIN 1 NOTCH
0.14 × 45°
11 12
6 5
1
4
10
7
aaa Z
2×
MX YZccc
MX YZccc
MX YZeee
MZfff
PACKAGE
OUTLINE
0.25 ±0.05
0.70 ±0.05
2.50 ±0.05
2.50 ±0.05
LQFN 12 0618 REV B
0.250
0.70
0.70
ddd Z
12×
Z
A1
DETAIL C
SYMBOL
A
A1
L
b
D
E
D1
E1
e
H1
H2
aaa
bbb
ccc
ddd
eee
fff
MIN
0.65
0.01
0.30
0.22
NOM
0.74
0.02
0.40
0.25
2.00
2.00
0.70
0.70
0.50
0.24 REF
0.50 REF
MAX
0.83
0.03
0.50
0.28
0.10
0.10
0.10
0.10
0.15
0.08
NOTES
DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. PRIMARY DATUM -Z- IS SEATING PLANE
METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN
SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES
5
4
DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER
MAY BE EITHER A MOLD OR MARKED FEATURE
6
THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII
e
e/2
SUBSTRATE THK
MOLD CAP HT
LTC3309A
25
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 11/19 Add AEC-Q100 Qualified
Add J-grade and #W parts
Modify Top + Bottom Switch Current Limit descriptors
Note 2: Add J-grade
Capacitor changes in various app circuits
1
2
3
4
18-26
LTC3309A
26
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2019
www.analog.com
11/19
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High Efficiency, 2MHz, 0.5V, 6A
3309A TA08
EN
SW
SW
VIN VIN
PGND
10µF
10nF
10µF
110nH
68µF
x2
1M
(OPT)
VOUT
0.5V
6A
VIN = 2.25V TO 5.5V
AGND
FB
RT
LTC3309A
511k
VOUT
PGOOD
VIN
1µF
0201
1µF
0201
MODE/SYNC
fOSC = 2MHz