LIS3LV02DL-TR - STMicroelectronics

PRELIMINARY DATA

This is a preliminary information on a product now in development or undergoing evaluation. Details are subject to change without notice.

February 2006 Rev 1 1/36

LIS3LV02DL

MEMS INERTIAL SENSOR

3-Axis - ±2g/±6g Digital Output Low Voltage Linear Accelerometer

Features

■2.16V to 3.6V single supply operation

■1.8V compatible IOs

■I2C/SPI digital output interfaces

■Programmable 12 or 16 bit data representation

■Interrupt activated by motion

■Programmable interrupt threshold

■Embedded self test

■High shock survivability

■ECOPACK® compliant (see Section 8)

Description

The LIS3LV02DL is a three axes digital output

linear accelerometer that includes a sensing

element and an IC interface able to take the

information from the sensing element and to

provide the measured acceleration signals to the

external world through an I2C/SPI serial interface.

The sensing element, capable of detecting the

acceleration, is manufactured using a dedicated

process developed by ST to produce inertial

sensors and actuators in silicon.

The IC interface instead is manufactured using a

CMOS process that allows high level of integration

to design a dedicated circuit which is factory

trimmed to better match the sensing element

characteristics.

The LIS3LV02DL has a user selectable full scale

of ±2g, ±6g and it is capable of measuring

acceleration over a bandwidth of 640 Hz for all

axes. The device bandwidth may be selected

accordingly to the application requirements. A

self-test capability allows the user to check the

functioning of the system

The device may be configured to generate an

inertial wake-up/free-fall interrupt signal when a

programmable acceleration threshold is crossed

at least in one of the three axes.

The LIS3LV02DL is available in plastic SMD

package and it is specified over a temperature

range extending from -40°C to +85°C.

The LIS3LV02DL belongs to a family of products

suitable for a variety of applications:

■Free-Fall detection

■Motion activated functions in portable terminals

■Antitheft systems and Inertial navigation

■Gaming and Virtual Reality input devices

■Vibration Monitoring and Compensation

LGA-16

Order codes

Part number Op. Temp. range, °CPackage Packing

LIS3LV02DL -40 to +85 LGA-16 Tray

LIS3LV02DL-TR -40 to +85 LGA-16 Tape and Reel

www.st.com

Contents LIS3LV02DL

2/36

Contents

1 Block Diagram & Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 LGA-16 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Mechanical and Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Mechanical characteristics1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Electrical characteristics1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4.3 Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 IC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 SPI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.1 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2.2 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.3 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

LIS3LV02DL Contents

3/36

7.2 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4 OFFSET_Z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 GAIN_X (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 GAIN_Y (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.7 GAIN_Z (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.8 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.9 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.10 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.11 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.12 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.13 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.14 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.15 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.16 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.17 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.19 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.20 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.21 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.22 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.23 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.24 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.25 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.26 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.27 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.28 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.29 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.30 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.31 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Block Diagram & Pin Description LIS3LV02DL

4/36

1 Block Diagram & Pin Description

1.1 Block diagram

Figure 1. Block Diagram

1.2 LGA-16 Pin description

Figure 2. Pin Connection

Σ∆

CHARGE

AMPLIFIER

MUX

Y+

Z+

Y-

Z-

Regs

X+

X-

MUX

Reconstruction

Filter

Σ∆

Array

SPI

SCL/SPC

SDA/SDO/SDI

SDO

CONTROL LOGIC

INTERRUPT GEN.

RDY/INT

Reconstruction

Filter

Reconstruction

Filter

CLOCK

TRIMMING

CIRCUITS

REFERENCESELF TEST

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

LIS3LV02DL

(TOP VIEW)

914

SCL/SPC

VDD_IO

SDO

RDY/INT

GND

RES

VDD

RES

VDD

GND

RES

SDA/SDI/SDO

LIS3LV02DL Block Diagram & Pin Description

5/36

Table 1. Pin description

Pin# Name Function

1 RDY/INT Data ready/inertial wake-up interrupt

2 SDO SPI Serial Data Output

SDA/

SDI/

SDO

I2C Serial Data (SDA)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

4 Vdd_IO Power supply for I/O pads

5 SCL/SPC I2C Serial Clock (SCL)

SPI Serial Port Clock (SPC)

6CS

SPI enable

I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

7 NC Internally not connected

8CK

Optional External clock, if not used either leave unconnected or

connect to GND

9 GND 0V supply

10 Reserved Either leave unconnected or connect to Vdd_IO

11 Vdd Power supply

12 Reserved Connect to Vdd

13 Vdd Power supply

14 GND 0V supply

15 Reserved Either leave unconnected or connect to GND

16 GND 0V supply

Mechanical and Electrical specifications LIS3LV02DL

6/36

2 Mechanical and Electrical specifications

2.1 Mechanical characteristics1

Table 2. Mechanical Characteristics

(All the parameters are specified @ Vdd=3.3V, T=25°C unless otherwise noted)

Symbol Parameter Test conditions Min. Typ.2Max. Unit

FS Measurement range3FS bit set to 0 ±1.7 ±2.0 g

FS bit set to 1 ±5.3 ±6.0 g

Dres Device Resolution Full-scale = 2g

BW=40Hz 1.0 mg

So Sensitivity

Full-scale = 2g, 12 bit

representation 920 1024 1126 LSb/g

Full-scale = 6g, 12 bit

representation 306 340 374 LSb/g

TCS0 Sensitivity Change Vs

Temperature

Full-scale = 2g, 12 bit

representation 0.025 %/

°C

Off Zero-g Level Offset

Accuracy4,5

Full-scale = 2g

X, Y axis -70 70 mg

Full-scale = 2g

Z axis -90 90 mg

Full-scale = 6g

X, Y axis -90 90 mg

Full-scale = 6g

Z axis -100 100 mg

LTOff Zero-g Level Offset Long

Term Accuracy6

Full-scale = 2g

X, Y axis TBD %FS

Full-scale = 2g

Z axis TBD %FS

Full-scale = 6g

X, Y axis TBD %FS

Full-scale = 6g

Z axis TBD %FS

TCOff Zero-g Level Change Vs

Temperature Max Delta from 25°C 0.2 mg/

°C

LIS3LV02DL Mechanical and Electrical specifications

7/36

Note: 1 The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V

2 Typical specifications are not guaranteed

3 Verified by wafer level test and measurement of initial offset and sensitivity

4 Zero-g level offset value after MSL3 preconditioning

5 Offset can be eliminated by enabling the built-in high pass filter (HPF)

6 Results of accelerated reliability tests

7 Self Test output changes with the power supply. Self test “output change” is defined as

OUTPUT[LSb](Self-test bit on ctrl_reg1=1)-OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=1g/1024 at

12bit representation, 2g Full-Scale

8 Output data reach 99% of final value after 5/ODR when enabling Self-Test mode due to device

filtering

9 ODR is output data rate. Refer to table 3 for specifications

NL Non Linearity

Best fit straight line

X, Y axis

Full-scale = 2g

BW=40Hz

±2%FS

Best fit straight line

Z axis

Full-scale = 2g

BW=40Hz

±3 %FS

CrAx Cross Axis -3.5 3.5 %

Vst Self test Output Change7,8

Full-scale=2g

X axis 250 550 900 LSb

Full-scale=2g

Y axis 250 550 900 LSb

Full-scale=2g

Z axis -100 -350 -600 LSb

Full-scale=6g

X axis 80 180 300 LSb

Full-scale=6g

Y axis 80 180 300 LSb

Full-scale=6g

Z axis -30 -120 -200 LSb

BW System Bandwidth9ODRx/4 Hz

To p Operating Temperature

Range -40 +85 °C

Wh Product Weight 72 mgram

Table 2. Mechanical Characteristics (continued)

(All the parameters are specified @ Vdd=3.3V, T=25°C unless otherwise noted)

Symbol Parameter Test conditions Min. Typ.2Max. Unit

Mechanical and Electrical specifications LIS3LV02DL

8/36

2.2 Electrical characteristics1

Note: 1 The product is factory calibrated at 2.5V. The device can be used from 2.16V to 3.6V

2 Typical specifications are not guaranteed

3 Digital filter cut-off frequency

4 Time to obtain valid data after exiting Power-Down mode

Table 3. Electrical Characteristics

(All the parameters are specified @ Vdd=2.5V, T=25°C unless otherwise noted)

Symbol Parameter Test conditions Min. Typ.2Max. Unit

Vdd Supply voltage 2.16 2.5 3.6 V

Vdd_IO I/O pads Supply voltage 1.71 Vdd V

Idd Supply current T = 25°C, Vdd=3.3V 0.65 0.80 mA

VIH Digital High level Input

voltage

0.8*Vdd

_IO V

VIL Digital Low level Input

voltage

0.2*Vdd

_IO V

VOH High level Output Voltage 0.9*Vdd

_IO V

VOL Low level Output Voltage 0.1*Vdd

_IO V

IddPdn Current consumption in

Power-down mode T = 25°C 1 10 µA

ODR1 Output Data Rate1 Dec factor = 512 40 Hz

ODR2 Output Data Rate 2 Dec factor = 128 160 Hz

ODR3 Output Data Rate 3 Dec factor = 32 640 Hz

ODR4 Output Data Rate 4 Dec factor = 8 2560 Hz

BW System Bandwidth3ODRx/4 Hz

To n Turn-on time45/ODRx s

Fmax SPI frequency Vdd_IO<2.4V 4 MHz

Vdd_IO>2.4V 8 MHz

To p Operating Temperature

Range -40 +85 °C

LIS3LV02DL Mechanical and Electrical specifications

9/36

2.3 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 4. Absolute maximum ratings

Note: 1 Supply voltage on any pin should never exceed 6.0V.

Symbol Ratings Maximum Value Unit

Vdd Supply voltage -0.3 to 6 V

Vdd_IO I/O pins Supply voltage -0.3 to Vdd +0.1 V

Vin Input voltage on any control pin

(CS, SCL/SPC, SDA/SDI/SDO, CK) -0.3 to Vdd_IO +0.3 V

APOW Acceleration (Any axis, Powered, Vdd=2.5V) 3000g for 0.5 ms

10000g for 0.1 ms

AUNP Acceleration (Any axis, Unpowered) 3000g for 0.5 ms

10000g for 0.1 ms

TOP Operating Temperature Range -40 to +85 °C

TSTG Storage Temperature Range -40 to +125 °C

ESD Electrostatic discharge protection

4.0 (HBM) kV

200 (MM) V

1.5 (CDM) kV

This is a Mechanical Shock sensitive device, improper handling can cause

permanent damages to the part

This is an ESD sensitive device, improper handling can cause permanent damages

to the part

Mechanical and Electrical specifications LIS3LV02DL

10/36

2.4 Terminology

2.4.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g

acceleration to it. As the sensor can measure DC accelerations this can be done easily by

pointing the axis of interest towards the center of the earth, noting the output value, rotating the

sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, ±1g

acceleration is applied to the sensor. Subtracting the larger output value from the smaller one

and divide the result by 2 leads to the actual sensitivity of the sensor. This value changes very

little over temperature and also very little over time. The Sensitivity Tolerance describes the

range of Sensitivities of a large population of sensor.

2.4.2 Zero-g level

Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal output

signal if there is no acceleration present. A sensor in a steady state on a horizontal surface will

measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The output is ideally

in the middle of the dynamic range of the sensor (content of OUT registers 00h, 00h with 16 bit

representation, data expressed as 2’s complement number). A deviation from ideal value in this

case is called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS

sensor and therefore the offset can slightly change after mounting the sensor onto a printed

circuit board or exposing it to extensive mechanical stress. Offset changes little over

temperature, see “Zero-g level change vs. temperature”. The Zero-g level of an individual

sensor is stable over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of

a population of sensors.

2.4.3 Self Test

Self Test allows to test the mechanical and electric part of the sensor, allowing the seismic

mass to be moved by means of an electrostatic test-force. The Self Test function is off when the

self-test bit of ctrl_reg1 (control register 1) is programmed to ‘0‘. When the self-test bit of

ctrl_reg1 is programmed to ‘1‘ an actuation force is applied to the sensor, simulating a definite

input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which

is related to the selected full scale and depending on the Supply Voltage through the device

sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of

the signals produced by the acceleration acting on the sensor and by the electrostatic test-

force. If the output signals change within the amplitude specified inside table 2 than the sensor

is working properly and the parameters of the interface chip are within the defined specification.

LIS3LV02DL Functionality

11/36

3 Functionality

The LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer

packaged in a LGA package. The complete device includes a sensing element and an IC

interface able to take the information from the sensing element and to provide a signal to the

external world through an I2C/SPI serial interface.

3.1 Sensing element

A proprietary process is used to create a surface micro-machined accelerometer. The

technology allows to carry out suspended silicon structures which are attached to the substrate

in a few points called anchors and are free to move in the direction of the sensed acceleration.

To be compatible with the traditional packaging techniques a cap is placed on top of the

sensing element to avoid blocking the moving parts during the moulding phase of the plastic

encapsulation.

When an acceleration is applied to the sensor the proof mass displaces from its nominal

position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using

charge integration in response to a voltage pulse applied to the sense capacitor.

At steady state the nominal value of the capacitors are few pF and when an acceleration is

applied the maximum variation of the capacitive load is up to 100fF.

3.2 IC Interface

The complete measurement chain is composed by a low-noise capacitive amplifier which

converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three

Σ∆ analog-to-digital converters, one for each axis, that translate the produced signal into a

digital bitstream.

The Σ∆ converters are coupled with dedicated reconstruction filters which remove the high

frequency components of the quantization noise and provide low rate and high resolution digital

words.

The charge amplifier and the Σ∆ converters are operated respectively at 61.5 kHz and 20.5

kHz.

The data rate at the output of the reconstruction depends on the user selected Decimation

Factor (DF) and spans from 40 Hz to 2560 Hz.

The acceleration data may be accessed through an I2C/SPI interface thus making the device

particularly suitable for direct interfacing with a microcontroller.

The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of

measured acceleration data is available thus simplifying data synchronization in digital system

employing the device itself.

The LIS3LV02DL may also be configured to generate an inertial Wake-Up, Direction Detection

and Free-Fall interrupt signal accordingly to a programmed acceleration event along the

enabled axes.

Functionality LIS3LV02DL

12/36

3.3 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).

The trimming values are stored inside the device by a non volatile structure. Any time the

device is turned on, the trimming parameters are downloaded into the registers to be employed

during the normal operation. This allows the user to employ the device without further

calibration.

LIS3LV02DL Application Hints

13/36

4 Application Hints

Figure 3. LIS3LV02DL Electrical Connection

The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO

line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near

as possible to the pin 13 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper behavior

of the IC (refer to Fig. 3). It is possible to remove Vdd mantaining Vdd_IO without blocking the

communication busses.

The functionality of the device and the measured acceleration data is selectable and accessible

through the I2C/SPI interface.When using the I2C, CS must be tied high while SDO must be left

floating. Refer to dedicated application note for further information on device usage.

4.1 Soldering Information

The LGA-16 package is lead free and green package qualified for soldering heat resistance

according to JEDEC J-STD-020C. Pin #1 indicator are physically connected to GND. Soldering

recommendations are available upon request.

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

Vdd_IO

SCL/SPC

SDA/SDI/SDO

SDO

RDY/INT

10uF

Vdd

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

100nF

GND

LIS3LV02DL

(TOP VIEW)

914

Digital Interfaces LIS3LV02DL

14/36

5 Digital Interfaces

The registers embedded inside the LIS3LV02DL may be accessed through both the I2C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire

interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS

line must be tied high (i.e connected to Vdd_IO).

Table 5. Serial interface pin description

5.1 I2C Serial Interface

The LIS3LV02DL I2C is a bus slave. The I2C is employed to write the data into the registers

whose content can also be read back.

The relevant I2C terminology is given in the table below

Table 6. Serial interface pin description

There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial

DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from

the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded

inside the LIS3LV02DL. When the bus is free both the lines are high.

The I2C interface is compliant with Fast Mode (400 kHz) I2C standards as well as the Normal

Mode.

PIN Name PIN Description

CS SPI enable

I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

SCL/SPC I2C Serial Clock (SCL)

SPI Serial Port Clock (SPC)

SDA/SDI/SDO

I2C Serial Data (SDA)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

SDO SPI Serial Data Output (SDO)

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master The device which initiates a transfer, generates clock signals and terminates a

transfer

Slave The device addressed by the master

LIS3LV02DL Digital Interfaces

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5.1.1 I2C Operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this

has been transmitted by the Master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and the

eighth bit tells whether the Master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits after a

start condition with its address. If they match, the device considers itself addressed by the

Master. The Slave ADdress (SAD) associated to the LIS3LV02DL is 0011101b.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during

the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable

low during the HIGH period of the acknowledge clock pulse. A receiver which has been

addressed is obliged to generate an acknowledge after each byte of data has been received.

The I2C embedded inside the LIS3LV02DL behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave

acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb

represent the actual register address while the MSB enables address auto increment. If the

MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow

multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’

(Write) the Master will transmit to the slave with direction unchanged.

Transfer when Master is writing one byte to slave

Transfer when Master is writing multiple bytes to slave:

Transfer when Master is receiving (reading) one byte of data from slave:

Transfer when Master is receiving (reading) multiple bytes of data from slave

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of

bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb)

first. If a receiver can’t receive another complete byte of data until it has performed some other

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Master ST SAD + W SUB SR SAD + R MAK

Slave SAK SAK SAK DATA

Master MAK NMAK SP

S l a ve DATA DATA

Digital Interfaces LIS3LV02DL

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function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data

transfer only continues when the receiver is ready for another byte and releases the data line. If

a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it

is performing some real time function) the data line must be left HIGH by the slave. The Master

can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is

HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation

of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of first register to read.

In the presented communication format MAK is Master Acknowledge and NMAK is No Master

Acknowledge.

5.2 SPI Bus Interface

The LIS3LV02DL SPI is a bus slave. The SPI allows to write and read the registers of the

device.

The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

Figure 4. Read & write protocol

CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the

transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by

the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are

respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of

SPC and should be captured at the rising edge of SPC.

Both the Read Register and Write Register commands are completed in 16 clock pulses or in

multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling

edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of

CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising

edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from

the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.

When 1, the address will be auto incremented in multiple read/write commands.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

SPC

SDI

SDO

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

LIS3LV02DL Digital Interfaces

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bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb

first).

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is

0 the address used to read/write data remains the same for every block. When MS bit is 1 the

address used to read/write data is incremented at every block.

The function and the behavior of SDI and SDO remain unchanged.

5.2.1 SPI Read

Figure 5. SPI Read protocol

The SPI Read command is performed with 16 clock pulses. Multiple byte read command is

performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 6. Multiple bytes SPI Read Protocol (2 bytes example)

SPC

SDI

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

SPC

SDI

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

Digital Interfaces LIS3LV02DL

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5.2.2 SPI Write

Figure 7. SPI Write protocol

The SPI Write command is performed with 16 clock pulses. Multiple byte write command is

performed adding blocks of 8 clock pulses at the previous one.

bit 0: WRITE bit. The value is 0.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb

first).

bit 16-... : data DI(...-8). Further data in multiple byte writing.

Figure 8. Multiple bytes SPI Write Protocol (2 bytes example)

5.2.3 SPI Read in 3-wires mode

3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in

CTRL_REG2.

Figure 9. SPI Read protocol in 3-wires mode

SPC

SDI

RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

AD5 AD4 AD3 AD2 AD1 AD0MS

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

SPC

SDI/O

RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

LIS3LV02DL Digital Interfaces

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The SPI Read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

Multiple read command is also available in 3-wires mode.

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6 Register mapping

The table given below provides a listing of the 8 bit registers embedded in the device and the

related address.

Table 7. Registers address map

Reg. Name Type

Default Comment

Binary Hex

rw 0000000 - 0001110 00 - 0E Reserved

WHO_AM_I r 0001111 0F 00111010 Dummy register

rw 0010000 - 0010101 10-15 Reserved

OFFSET_X rw 0010110 16 Calibration Loaded at boot

OFFSET_Y rw 0010111 17 Calibration Loaded at boot

OFFSET_Z rw 0011000 18 Calibration Loaded at boot

GAIN_X rw 0011001 19 Calibration Loaded at boot

GAIN_Y rw 0011010 1A Calibration Loaded at boot

GAIN_Z rw 0011011 1B Calibration Loaded at boot

0011100 -0011111 1C-1F Reserved

CTRL_REG1 rw 0100000 20 00000111

CTRL_REG2 rw 0100001 21 00000000

CTRL_REG3 rw 0100010 22 00001000

HP_FILTER RESET r 0100011 23 dummy Dummy register

0100100-0100110 24-26 Not Used

STATUS_REG rw 0100111 27 00000000

OUTX_L r 0101000 28 output

OUTX_H r 0101001 29 output

OUTY_L r 0101010 2A output

OUTY_H r 0101011 2B output

OUTZ_L r 0101100 2C output

OUTZ_H r 0101101 2D output

r 0101110 2E Reserved

0101111 2F Not Used

FF_WU_CFG rw 0110000 30 00000000

FF_WU_SRC rw 0110001 31 00000000

FF_WU_ACK r 0110010 32 dummy Dummy register

0110011 33 Not Used

FF_WU_THS_L rw 0110100 34 00000000

LIS3LV02DL Register mapping

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Registers marked as reserved must not be changed. The writing to those registers may cause

permanent damages to the device.

The content of the registers that are loaded at boot should not be changed. They contain the

factory calibration values. Their content is automatically restored when the device is powered-

up.

FF_WU_THS_H rw 0110101 35 00000000

FF_WU_DURATION rw 0110110 36 00000000

0110111 37 Not Used

DD_CFG rw 0111000 38 00000000

DD_SRC rw 0111001 39 00000000

DD_ACK r 0111010 3A dummy Dummy register

0111011 3B Not Used

DD_THSI_L rw 0111100 3C 00000000

DD_THSI_H rw 0111101 3D 00000000

DD_THSE_L rw 0111110 3E 00000000

DD_THSE_H rw 0111111 3F 00000000

1000000-1111111 40-7F Reserved

Table 7. Registers address map (continued)

Reg. Name Type

Default Comment

Binary Hex

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7 Register Description

The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The registers 7.2 to 7.7 contain the factory calibration values, it is not

necessary to change their value for normal device operation.

7.1 WHO_AM_I (0Fh)

Addressing this register the physical address of the device is returned. For LIS3LV02DL the

physical address assigned in factory is 3Ah.

7.2 OFFSET_X (16h)

7.3 OFFSET_Y (17h)

7.4 OFFSET_Z (18h)

W7 W6 W5 W4 W3 W2 W1 W0

W7, W0 LIS3LV02DL Physical Address equal to 3Ah

OX7 OX6 OX5 OX4 OX3 OX2 OX1 OX0

OX7, OX0 Digital Offset Trimming for X-Axis

OY7 OY6 OY5 OY4 OY3 OY2 OY1 OY0

OY7, OY0 Digital Offset Trimming for Y-Axis

OZ7OZ6OZ5OZ4OZ3OZ2OZ1OZ0

OZ7, OZ0 Digital Offset Trimming for Z-Axis

LIS3LV02DL Register Description

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7.5 GAIN_X (19h)

7.6 GAIN_Y (1Ah)

7.7 GAIN_Z (1Bh)

7.8 CTRL_REG1 (20h)

PD1, PD0 bit allows to turn on the turn the device out of power-down mode. The device is in

power-down mode when PD1, PD0= “00” (default value after boot). The device is in normal

mode when either PD1 or PD0 is set to 1.

DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The

default value is 00 which corresponds to a data-rate of 40Hz. By changing the content of DF1,

DF0 to “01”, “10” and “11” the selected data-rate will be set respectively equal to 160Hz, 640Hz

and to 2560Hz.

GX7 GX6 GX5 GX4 GX3 GX2 GX1 GX0

GX7, GX0 Digital Gain Trimming for X-Axis

GY7GY6GY5GY4GY3GY2GY1GY0

GY7, GY0 Digital Gain Trimming for Y-Axis

GZ7GZ6GZ5GZ4GZ3GZ2GZ1GZ0

GZ7, GZ0 Digital Gain Trimming for Z-Axis

PD1 PD0 DF1 DF0 ST Zen Yen Xen

PD1, PD0 Power Down Control

(00: power-down mode; 01, 10, 11: device on)

DF1, DF0 Decimation Factor Control

(00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8)

ST Self Test Enable

(0: normal mode; 1: self-test active)

Zen Z-axis enable

(0: axis off; 1: axis on)

Ye n Y-axis enable

(0: axis off; 1: axis on)

Xen X-axis enable

(0: axis off; 1: axis on)

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ST bit is used to activate the self test function. When the bit is set to one, an output change will

occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to check the

functionality of the whole measurement chain.

Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1.

Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1.

Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.

7.9 CTRL_REG2 (21h)

FS bit is used to select Full Scale value. After the device power-up the default full scale value is

+/-2g. In order to obtain a +/-6g full scale it is necessary to set FS bit to ‘1’.

BDU bit is used to inhibit output registers update until both upper and lower register parts are

read. In default mode (BDU= ‘0’) the output register values are updated continuously. If for any

reason it is not sure to read faster than output data rate it is recommended to set BDU bit to ‘1’.

In this way the content of output registers is not updated until both MSB and LSB are read

avoiding to read values related to different sample time.

BLE bit is used to select Big Endian or Little Endian representation for output registers. In Big

Endian’s one MSB acceleration value is located at addresses 28h (X-axis), 2Ah (Y-axis) and

2Ch (Z-axis) while LSB acceleration value is located at addresses 29h (X-axis), 2Bh (Y-axis)

and 2Dh (Z-axis). In Little Endian representation (Default, BLE=‘0‘) the order is inverted (refer

to data register description for more details).

BOOT bit is used to refresh the content of internal registers stored in the flash memory block.

At the device power up the content of the flash memory block is transferred to the internal

registers related to trimming functions to permit a good behavior of the device itself. If for any

reason the content of trimming registers was changed it is sufficient to use this bit to restore

correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied inside

corresponding internal registers and it is used to calibrate the device. These values are factory

FS BDU BLE BOOT IEN DRDY SIM DAS

FS Full Scale selection

(0: ±2g; 1: ±6g)

BDU Block Data Update

(0: continuous update; 1: output registers not updated until MSB and LSB reading)

BLE Big/Little Endian selection

(0: little endian; 1: big endian)

BOOT Reboot memory content

IEN Interrupt ENable

(0: data ready on RDY pad; 1: int req on RDY pad)

DRDY Enable Data-Ready generation

SIM SPI Serial Interface Mode selection

(0: 4-wire interface; 1: 3-wire interface)

DAS Data Alignment Selection

(0: 12 bit right justified; 1: 16 bit left justified)

LIS3LV02DL Register Description

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trimmed and they are different for every accelerometer. They permit a good behavior of the

device and normally they have not to be changed. At the end of the boot process the BOOT bit

is set again to ‘0’.

IEN bit is used to switch the value present on data-ready pad between Data-Ready signal and

Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to modify

DRDY bit to enable Data-Ready signal generation.

DRDY bit is used to enable Data-Ready (RDY/INT) pin activation. If DRDY bit is ‘0’ (default

value) on Data-Ready pad a ‘0’ value is present. If a Data-Ready signal is desired it is

necessary to set to ‘1’ DRDY bit. Data-Ready signal goes to ‘1’ whenever a new data is

available for all the enabled axis. For example if Z-axis is disabled, Data-Ready signal goes to

‘1’ when new values are available for both X and Y axis. Data-Ready signal comes back to ‘0’

when all the registers containing values of the enabled axis are read. To be sure not to loose

any data coming from the accelerometer data registers must be read before a new Data-Ready

rising edge is generated. In this case Data-ready signal will have the same frequency of the

data rate chosen.

SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire

interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire

interface mode output data are sent to SDA_SDI pad.

DAS bit permits to decide between 12 bit right justified and 16 bit left justified representation of

data coming from the device. The first case is the default case and the most significant bits are

replaced by the bit representing the sign.

7.10 CTRL_REG3 (22h)

FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the

sensor

CFS1, CFS0 bits defines the coefficient Hpc to be used to calculate the -3dB cut-off frequency

of the high pass filter:

ECK HPDD HPFF FDS res res CFS1 CFS0

ECK External Clock. Default value: 0

(0: clock from internal oscillator; 1: clock from external pad)

HPDD High Pass filter enabled for Direction Detection. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPFF High Pass filter enabled for Free-Fall and Wake-Up. Default value: 0

(0: filter bypassed; 1: filter enabled)

FDS Filtered Data Selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter)

CFS1, CFS0

High-pass filter Cut-off Frequency Selection. Default value: 00

(00: Hpc=512

01: Hpc=1024

10: Hpc=2048

11: Hpc=4096)

fcutoff

0.318

Hpc

------------- ODRx

----------------

⋅=

26/36

7.11 HP_FILTER_RESET (23h)

Dummy register. Reading at this address zeroes instantaneously the content of the internal

high pass-filter. Read data is not significant.

7.12 STATUS_REG (27h)

7.13 OUTX_L (28h)

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the MSB

acceleration data and depends by bit DAS in CTR_REG2 reg as described in the following

section.

7.14 OUTX_H (29h)

When reading the register in “12 bit right justified” mode the most significant bits (15:12) are

replaced with bit 11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11).

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the LSB

acceleration data.

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

ZYXOR X, Y and Z axis Data Overrun

ZOR Z axis Data Overrun

YOR Y axis Data Overrun

XOR X axis Data Overrun

ZYXDA X, Y and Z axis new Data Available

ZDA Z axis new Data Available

YDA Y axis new Data Available

XDA X axis new Data Available

XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

XD7, XD0 X axis acceleration data LSB

XD15 XD14 XD13 XD12 XD11 XD10 XD9 XD8

XD15, XD8 X axis acceleration data MSB

LIS3LV02DL Register Description

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7.15 OUTY_L (2Ah)

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the MSB

acceleration data and depends by bit DAS in CTR_REG2 reg as described in the following

section.

7.16 OUTY_H (2Bh)

When reading the register in “12 bit right justified” mode the most significant bits (15:12) are

replaced with bit 11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11).

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the LSB

acceleration data.

7.17 OUTZ_L (2Ch)

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the MSB

acceleration data and depends by bit DAS in CTR_REG2 reg as described in the following

section.

7.18 OUTZ_H (2Dh)

When reading the register in “12 bit right justified” mode the most significant bits (15:12) are

replaced with bit 11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11).

In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the LSB

acceleration data

YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

YD7, YD0 Y axis acceleration data LSB

YD15 YD14 YD13 YD12 YD11 YD10 YD9 YD8

YD15, YD8 Y axis acceleration data MSB

ZD7 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0

ZD7, ZD0 Z axis acceleration data LSB

ZD15 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8

ZD15, ZD8 Z axis acceleration data MSB

28/36

7.19 FF_WU_CFG (30h)

Free-fall and inertial wake-up configuration register.

AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

AOI

And/Or combination of Interrupt events interrupt request. Default value: 0.

(0: OR combination of interrupt events;

1: AND combination of interrupt events)

LIR

Latch interrupt request. Default value: 0.

(0: interrupt request not latched;

1: interrupt request latched)

ZHIE

Enable Interrupt request on Z high event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

Enable Interrupt request on Z low event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE

Enable Interrupt request on Y high event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

YLIE

Enable Interrupt request on Y low event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

XHIE

Enable Interrupt request on X high event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

XLIE

Enable Interrupt request on X low event. Default value: 0.

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

LIS3LV02DL Register Description

29/36

7.20 FF_WU_SRC (31h)

7.21 FF_WU_ACK (32h)

Dummy register. If LIR bit in FF_WU_CFG=1 allows the refresh of FF_WU_SRC. Read data is

not significant.

X IA ZHZLYHYLXHXL

Interrupt Active. Default value: 0

(0: no interrupt has been generated;

1: one or more interrupt event has been generated)

ZH Z High. Default value: 0

(0: no interrupt; 1: ZH event has occurred)

ZL Z Low. Default value: 0

(0: no interrupt; 1: ZL event has occurred)

YH Y High. Default value: 0

(0: no interrupt; 1: YH event has occurred)

YL Y Low. Default value: 0

(0: no interrupt; 1: YL event has occurred)

XH X High. Default value: 0

(0: no interrupt; 1: XH event has occurred)

XL X Low. Default value: 0

(0: no interrupt; 1: XL event has occurred)

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7.22 FF_WU_THS_L (34h)

7.23 FF_WU_THS_H (35h)

7.24 FF_WU_DURATION (36h)

Set the minimum duration of the free-fall/wake-up event to be recognized.

THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0

THS7, THS0 Free-fall / Inertial Wake Up Acceleration Threshold LSB

THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8

THS15, THS8 Free-fall / Inertial Wake Up Acceleration Threshold MSB

FWD7 FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0

FWD7, FWD0 Minimum duration of the Free-fall/Wake-up event

Duration s() FF_WU_Duration (Dec)

ODR

-----------------------------------------------------------=

LIS3LV02DL Register Description

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7.25 DD_CFG (38h)

Direction-detector configuration register

IEND LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

IEND

Interrupt enable on Direction change. Default value: 0

(0: disabled;

1: interrupt signal enabled)

LIR

Latch Interrupt request into DD_SRC reg with the DD_SRC reg cleared by reading

DD_ACK reg. Default value: 0.

(0: interrupt request not latched;

1: interrupt request latched)

ZHIE

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

YLIE

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

XHIE

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

XLIE

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

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7.26 DD_SRC (39h)

Direction detector source register

7.27 DD_ACK (3Ah)

Dummy register. If LIR bit in DD_CFG=1 allows the refresh of DD_SRC. Read data is not

significant.

X IA ZHZLYHYLXHXL

Interrupt event from direction change.

(0: no direction changes detected;

1: direction has changed from previous measurement)

Z High. Default value: 0

(0: Z below THSI threshold;

1: Z accel. exceeding THSE threshold along positive direction of acceleration axis)

Z Low. Default value: 0

(0: Z below THSI threshold;

1: Z accel. exceeding THSE threshold along negative direction of acceleration axis)

Y High. Default value: 0

(0: Y below THSI threshold;

1: Y accel. exceeding THSE threshold along positive direction of acceleration axis)

Y Low. Default value: 0

(0: Y below THSI threshold;

1: Y accel. exceeding THSE threshold along negative direction of acceleration axis)

X High. Default value: 0

(0: X below THSI threshold;

1: X accel. exceeding THSE threshold along positive direction of acceleration axis)

X Low. Default value: 0

(0: X below THSI threshold;

1: X accel. exceeding THSE threshold along negative direction of acceleration axis)

LIS3LV02DL Register Description

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7.28 DD_THSI_L (3Ch)

7.29 DD_THSI_H (3Dh)

7.30 DD_THSE_L (3Eh)

7.31 DD_THSE_H (3Fh)

THSI7 THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0

THSI7, THSI0 Direction detection Internal Threshold LSB

THSI15 THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8

THSI15, THSI8 Direction detection Internal Threshold MSB

THSE7 THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0

THSE7, THSE0 Direction detection External Threshold LSB

THSE15 THSE14 THSE13 THSE12 THSE11 THSE10 THSE9 THSE8

THSE15, THSE8 Direction detection External Threshold MSB

Package Information LIS3LV02DL

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8 Package Information

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.

These packages have a Lead-free second level interconnect. The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 10. LGA-16 Mechanical Data & Package Dimensions

OUTLINE AND

MECHANICAL DATA

DIM.

mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A1 0.92 1 0.0394

A2 0.7 0.0276

A3 0.180 0.220 0.260 0.0071 0.0087 0.0102

D1 4.250 4.400 4.550 0.1673 0.1732 0.1791

E1 7.350 7.500 7.650 0.2894 0.2953 0.3012

e1.0 0.0394

d0.3 0.0118

L1 5.000 0.1969

N2.5 0.0984

N1 1.2 0.0472

P1 0.965 0.975 0.985 0.0380 0.0384 0.0388

P2 0.64 0.65 0.66 0.0252 0.0256 0.0260

T1 0.75 0.8 0.85 0.0295 0.0315 0.0335

T2 0.45 0.5 0.55 0.0177 0.0197 0.0217

R1.200 1.600 0.0472 0.0630

h0.150 0.0059

k0.050 0.0020

i0.100 0.0039

s0.100 0.0039

LGA16 (4.4x7.5x1mm)

Land Grid Array Package

7863679 B

P2 L1

BACi

12 4 56

91011121314

Detail A

Metal Pad

seating plane

Solder mask

opening

BACh

BACi

(4 x)

LIS3LV02DL Revision history

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9 Revision history

Table 8. Document revision history

Date Revision Changes

15-Feb-2006 1 Initial release.

LIS3LV02DL

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