8303G–AVR– 11 /20 13
Features
•High Performance, Low Power AVR® 8-bit Microcontroller
•Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
•High Endurance, Non-volatile Memory Segments
– 16K Bytes of In-System, Self-Programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 256 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 1K Byte of Internal SRAM
– Data retention: 20 years at 85C / 100 years at 25C
– Programming Lock for Self-Programming Flash & EEPROM Data Security
•Peripheral Features
– Dedicated Hardware and QTouch® Library Support for Capacitive Touch Sensing
– One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each
– 12-channel, 10-bit ADC
– Programmable Ultra Low Power Watchdog Timer
– On-chip Analog Comparator
– Two Full Duplex USARTs with Start Frame Detection
– Universal Serial Interface
– Slave I2C Serial Interface
•Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Internal and External Interrupt Sources
• Pin Change Interrupt on 18 Pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Supply Voltage Sampling
– Calibrated 8MHz Oscillator with Temperature Calibration Option
– Calibrated 32kHz Ultra Low Power Oscillator
– On-chip Temperature Sensor
•I/O and Packages
– 18 Programmable I/O Lines
– 20-pad QFN/MLF, and 20-pin SOIC
•Operating Voltage:
– 1.8 – 5.5V
•Speed Grade:
– 0 – 2MHz @ 1.8 – 5.5V
– 0 – 8MHz @ 2.7 – 5.5V
– 0 – 12MHz @ 4.5 – 5.5V
•Temperature Range: -40C to +85C
•Low Power Consumption
– Active Mode: 0.2mA at 1.8V and 1MHz
– Idle Mode: 30µA at 1.8V and 1MHz
– Power-Down Mode (WDT Enabled): 1µA at 1.8V
– Power-Down Mode (WDT Disabled): 100nA at 1.8V
8-bit Atmel tinyAVR Microcontroller with
16K Bytes In-System Programmable Flash
ATtiny1634
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1. Pin Configurations
Figure 1-1. Pinout of ATtiny1634
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
NOTE
Bottom pad should be
soldered to ground.
(PCINT1/AIN0) PA1
(PCINT0/AREF) PA0
GND
VCC
PC5 (XTAL1/CLKI/PCINT17)
PC0 (ADC9/OC0A/XCK0/PCINT12)
PC1 (ADC10/ICP1/SCL/USCK/XCK1/PCINT13)
PC2 (ADC11/CLKO/INT0/PCINT14)
PC3 (RESET/dW/PCINT15)
PC4 (XTAL2/PCINT16)
PA7 (PCINT7/RXD0/ADC4)
PB0 (PCINT8/TXD0/ADC5)
PB1 (ADC6/DI/SDA/RXD1/PCINT9)
PB2 (ADC7/DO/TXD1/PCINT10)
PB3 (ADC8/OC1A/PCINT11)
(PCINT6/OC1B/ADC3) PA6
(PCINT5/OC0B/ADC2) PA5
(PCINT4/T0/ADC1) PA4
(PCINT3/T1/SNS/ADC0) PA3
(PCINT2/AIN1) PA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
(PCINT8/TXD0/ADC5) PB0
(PCINT7/RXD0/ADC4) PA7
(PCINT6/OC1B/ADC3) PA6
(PCINT5/OC0B/ADC2) PA5
(PCINT4/T0/ADC1) PA4
(PCINT3/T1/SNS/ADC0) PA3
(PCINT2/AIN1) PA2
(PCINT1/AIN0) PA1
(PCINT0/AREF) PA0
GND
PB1 (ADC6/DI/SDA/RXD1/PCINT9)
PB2 (ADC7/DO/TXD1/PCINT10)
PB3 (ADC8/OC1A/PCINT11)
PC0 (ADC9/OC0A/XCK0/PCINT12)
PC1 (ADC10/ICP1/SCL/USCK/XCK1/PCINT13)
PC2 (ADC11/CLKO/INT0/PCINT14)
PC3 (RESET/dW/PCINT15)
PC4 (XTAL2/PCINT16)
PC5 (XTAL1/CLKI/PCINT17)
VCC
SOIC
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1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 XTAL1
Input to the inverting amplifier of the oscillator and the internal clock circuit. This is an alternative pin configuration
of PC5.
1.1.4 XTAL2
Output from the inverting amplifier of the oscillator. Alternative pin configuration of PC4.
1.1.5 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 24-5
on page 231. Shorter pulses are not guaranteed to generate a reset.
The reset pi n can also be used as a (weak) I/O pin.
1.1.6 Port A (PA7:PA0)
This is an 8-bit, bi-direc tional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the
following drive characteristics:
• PA7, PA4:PA0: Symmetrical, with standard sink and source capability
• PA6, PA5: Asymmetrical, with high sink and standard source capability
As inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port A” on
page 62.
1.1.7 Port B (PB3:PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit).Output buffers have the
following drive characteristics:
• PB3: Asymmetrical, with high sink and standard source capability
• PB2:PB0: Symmetrical, with standard sink and source capability
As inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port B” on
page 65.
1.1.8 Port C (PC5:PC0)
This is a 6-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the
following drive characteristics:
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• PC5:PC1: Symmetrical, with standard sink and source capability
• PC0: Asymmetrical, with high sink and standard source capability
As inputs, port pins that are externally pulled low will s ource current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port C” on
page 67.
2. Overview
ATtiny1634 is a low-power CMOS 8-bit microcontrolle rs based on the AVR enhanced RISC architecture. By exe-
cuting powerful instructions in a si ngle clock cycle, the ATtiny1634 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
DEBUG
INTERFACE
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
VCC RESET GND
8-BIT DATA BUS
CPU CORE
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
POWER
SUPERVISION:
POR
BOD
RESET
ISP
INTERFACE
PORT A PORT CPORT B
VOLTAGE
REFERENCE
MULTIPLEXER
ANALOG
COMPARATOR
ADC
TEMPERATURE
SENSOR
TWO-WIRE
INTERFACE
USART0
TOUCH
SENSING
EEPROM
ON-CHIP
DEBUGGER
PC[5:0]PB[3:0]
PA[7:0]
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
USI
USART1
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The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logi c Unit (ALU), allowing two independent r egisters to be accessed in a single
instruction, ex ecuted in one clock cycle. The resu lting architecture is compact and code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny1634 provides the following features:
• 16K bytes of in-system programmable Flash
• 1K bytes of SRAM data memory
• 256 bytes of EEPROM data memory
• 18 general purpo se I/O lines
• 32 general purpose working registers
• An 8-bit timer/counter with two PWM channels
• A16-bit timer/counter with two PWM channels
• Internal and external interrupts
• A 10-bit ADC with 5 internal and 12 external channels
• An ultra-low power, programmable watchdog timer with internal oscillator
• Two programmable USART’s with start frame detection
• A slave Two-Wire Interface (TWI)
• A Universal Serial Interface (USI) with start condition detector
• A calibrated 8MHz oscillator
• A calibrated 32kHz, ultra low power oscillator
• Four software selectable power saving modes.
The device includes the following modes for saving power:
• Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
• ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all
I/O modules except the ADC
• Power-down mode: registers keep their contents and all chip fu nctions are disabled until the next interrupt or
hardware reset
• Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program mem-
ory can be re-programmed in-system through a serial interface, by a conventional non-volatile memory
programmer or by an on-chip boot code, running on the AVR core.
The ATtiny1634 AVR is supported by a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators and evaluation kits.
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3. General Information
3.1 Resources
A comprehensive set of drivers, applicat ion notes, data sheets and de scriptions on deve lopment tools are available
for download at http://www.atmel.com/avr.
3.2 Code Examples
This documentatio n contains simple co de examples that briefly show how to use variou s parts of the de vice. These
code examples assume that the part spe cific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handlin g in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instruct ions m ust
be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined
with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcon-
trollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Librar y and using the App lication Pro gram-
ming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 10 0 ye ar s at 25 ° C.
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
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4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and pa rallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program an d data. Instructions in the Program m emory are executed with a single level pip elining.
While one instruction is being executed, the next instruction is pre-fetched fro m the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable
Flash mem or y.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculat ions. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unco nditional jump and call instructions, capable of directly addressing
the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also
exist. The actual instruction set varies, as some devices only implement a part of the instruction set.
INTERRUPT
UNIT
STATUS AND
CONTROL
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
PROGRAM
COUNTER
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
DIRECT ADDRESSING
INDIRECT ADDRESSING
8-BIT DATA BUS
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During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the us age of the SRAM. A ll user program s must in itialize th e SP in the Res et routine (before sub-
routines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interr upt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector positio n. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Reg-
ister File, 0x20 - 0x5F. In addition, the ATtiny1634 has Extended I/O Space from 0x60 - 0xF F in SRAM wh er e on ly
the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.2 ALU – Arithmetic Logic Unit
The high-performa nce AVR ALU operates in direct connection with all the 32 general purpose wor king registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See external document “AVR Instruction Set” and “Instruction
Set Summary” on page 275 section for more information.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for alte ring program flow in order to perform conditional ope rations. Note that the Status
Register is updated after all ALU operations. This will in many cases remove the need for using the dedicated com-
pare instructions, resulting in faste r and more compact code. See external document “AVR Instruction Se t” and
“Instruction Set Summary” on page 275 section for more information.
The Status Register is neither automatically stored when entering an interrupt routine, no r re sto r ed w he n re tu rn in g
from an interrupt. This must be handled by software.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor-
mance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.
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Figure 4-2. General Purpose Working Registers
Most of the instructions oper a ting on the Register File have direct access to all registers, and most of them are sin-
gle cycle instructions.
As shown in Figure 4-2 , each register is also assigned a Da ta memory ad dress, mappi ng them dir ectly into th e first
32 locations of the user Data Space. Although no t being physically implemented as SRAM locations, this memory
organization provides great flexibility in acces s of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
4.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have added functions to their gener al purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as
described in Figure 4-3 below.
70Addr. Special Function
R0 0x00
R1 0x01
R2 0x02
R3 0x03
…...
R12 0x0C
R13 0x0D
R14 0x0E
R15 0x0F
R16 0x10
R17 0x11
…...
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
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Figure 4-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement, automatic incre-
ment, and automatic decr ement (see the instruction set reference for details).
4.5 Stack Pointer
The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and sub-
routine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack
grows from higher memory locations to lo wer memo ry locations. This means that the PUSH instructions decreases
and the POP instruction increases the stack pointer value.
The stack pointer points to the area of data memory where subrou tine and in terru pt stacks are locate d. This s tack
space must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by
one when data is fetched with the POP instruction. It is decreme nted by two w hen the return address is put on the
stack by a subroutin e call or a jum p to an interrupt ser vice routine, and incremented by two when data is fetched by
a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack point er is typica lly implemen ted as two 8- bit registers in the I/O register file. The width of the stack
pointer and the number of bits implemented is device dependent. In some AVR devices all data memory can be
addressed using SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be se t to point above the I/O re giste r areas, the minimum value being th e lowest address of
SRAM. See Table 5-2 on page 16.
4.6 Instruction Execution Timing
This section describes the ge neral access timing concepts for in struction exec ution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelini ng con cept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cos t, func tions per clocks, and functions per power-unit.
15 0
X-register 7XH 07 XL 0
R27 R26
15 0
Y-register 7YH 07 YL 0
R29 R28
15 0
Z-register 7ZH 07 ZL 0
R31 R30
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Figure 4-4. The Parallel Instructio n F etc he s and In str uc tio n Exe cut ion s
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the de st ina tio n re gis te r.
Figure 4-5. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several di fferen t inter rupt sources. The se interrupts and the separate Reset Vector each have a
separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in “Interrupts” on page 47. T he list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0.
When an in terr up t occurs, the G lob a l In te rr u pt En able I- bit is cleared an d a ll in te rr up ts a re d i sa bled. T h e us er soft-
ware can write logic one to the I-bit to enab le nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and har dware clears th e correspon ding Interru pt Flag. Inte rrupt Flags can a lso be cle ared by writ-
ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
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The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec-
essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an int er ru pt rou tin e. This m ust be ha nd le d by softw ar e.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Note: See “Code Examples” on page 6.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-
ing interrupts, as shown in the following examp le.
Note: See “Code Examples” on page 6.
4.7.1 Interrupt Response T ime
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector addre ss for the actual interr upt handlin g routine is executed. During this four clock cycle
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
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period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interr upt occurs when the MCU is in slee p mode, the interr upt exe-
cution response time is increa sed by four cl ock cycles. This increa se comes in additio n to the start-up time from the
selected sleep mode.
A return from an interrup t handling routine takes four clock cycles. During the se four clock cycles, the Program
Counter (two bytes) is popped ba ck fro m the Stack, the St a ck Pointe r is increme nted by two, and the I-b it in SREG
is set.
4.8 Register Description
4.8.1 CCP – Configuration Change Protection Register
• Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction
cycles. All interr up ts ar e ign or e d du rin g t he se cy cles . Af te r these cycles interrupts are automatically handled again
by the CPU, and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP0 will read as one as long as the protected feature is
enabled, while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are in recognised.
Notes: 1. Only WDE and WDP[3:0] bits are protected in WDTCSR.
4.8.2 SPH and SPL — Stack Pointe r Regist e rs
• Bits 10:0 – SP[10:0]: S tack Pointer
The Stack Pointer register points to the top of the stack, which is implemented growing from higher memory loca-
tions to lower memory locations. Hence, a stack PUSH command decreases the Stack Pointer.
The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts ar e en able d.
Bit 76543210
0x2F (0x4F) CCP[7:0] CCP
Read/WriteWWWWWWWR/W
Initial Value00000000
Table 4-1. Signatures Recognised by the Configuration Change Protection Register
Signature Registers Description
0xD8 CLKSR, CLKPR, WDTCSR(1) Protected I/O register
Initial Value 00000RAMENDRAMENDRAMEND
Read/Write RRRRRR/WR/WR/W
Bit 151413121110 9 8
0x3E (0x5E) –––––
SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Bit 76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
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4.8.3 SREG – Status Register
• Bit 7 – I: Globa l Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter-
rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper-
ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BC D arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Fla g N and the Two’s Comp lement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Descrip-
tion” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N ind icates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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5. Memories
The AVR architecture makes a distinction between program memory and data memory, locating each memory
type in a separate address space. Executable code is located in non-volatile program memory (Flash), whereas
data can be placed in either volatile (SRAM) or non-volatile memory (EEPROM). See Figure 5-1, below.
Figure 5-1. Memory Overview.
All memory spaces are linear and regular.
5.1 Program Memory (Flash)
ATtiny1634 contains 16K byte of on-chip, in-system reprogra mmable Flash memory for program storage. Flash
memories are non-volatile, i.e. they retain stored information even when not po wered.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8192 x 16 bits. The Program Counter
(PC) is 13 bits wide, thus capable of addressing all 8192 locations of program memory, as illustrated in Table 5-1,
below.
Constant tables can be allocated within the entire address space of program memory. See instructions LPM (Load
Program Memory), and SPM (Store Program Memory) in “Instruction Set Summary” on page 275. Flash program
memory can also be programmed from an external device, as described in “External Programming” on page 214.
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 10.
The Flash memory has a minimum endurance of 10,000 write/erase cycles.
GENERAL PURPOSE
REGISTER FILE
I/O REGISTER FILE
EXTENDED
I/O REGISTER FILE
DATA MEMORY
DATA MEMORY
PROGRAM MEMORY
FLASH SRAM EEPROM
Table 5-1. Size of Program Memory (Flash).
Device Flash Size Address Range
ATtiny1634 16KB 8192 words 0x0000 – 0x1FFF
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5.2 Data Memory (SRAM) and Register Files
Table 5-2 shows how the d ata memory and register file s of ATtiny1634 are organized . These memory areas are
volatile, i.e. they do not retain information when power is removed.
Note: 1. Also known as data address. This mode of addressing covers the entire data memory and register area. The
address is contained in a 16-bit area of two-word instructions.
2. Also known as direct I/O address. This mode of addressing covers part of the register area, only. It is used by
instructions where the address is embedded in the instruction word.
The 1280 memory locations in clude the general pu rpose register file , I/O register file, extended I/O register file, and
the internal data memory.
For compatibility with future devices, reserved bits should be written to zero, if accessed. Reserved I/O memory
addresses should never be written .
5.2.1 General Purpose Register File
The first 32 locations are reserved for the general purpo se register file. These registers are described in de tail in
“General Purpose Register File” on page 8.
5.2.2 I/O Register File
Following the general purpose register file, the next 64 locations are reserved for I/O registers. Registers in this
area are used mainly for communicating with I/O and periphera l units of the device. Data can be transferred
between I/O space and the general purpose register file using instructions such as IN, OUT, LD, ST, and
derivatives.
All I/O registers in this area can be accessed with the instructions IN and OUT. These I/O specific instructions
address the first location in the I/O register area as 0x00 and the last as 0x3F.
The low 32 registers (address range 0x00...0x1F) are accessible by some bit-specific instructions. In these regis-
ters, bits are easily set and cleared using SBI and CBI, while bit-conditional branches are readily constructe d using
instructions SBIC, SBIS, SBRC, and SBRS.
Registers in this area ma y also be accessed with instructions LD/LDD/LDS and ST/STD/STS. These instructions
treat the entire volatile memory as one data space and, therefore, address I/O registers starting at 0x20.
See “Instruction Set Summary” on page 275.
ATtiny1634 also contains thre e general purpose I/O registers that can b e used for storing any information. See
GPIOR0, GPIOR1 and GPIOR2 in “Re gister Su mmary” on pag e 273. These ge neral p ur pose I/O re gisters a re pa r-
ticularly useful for storing global v ariables and status flags, since they are accessible to bit-specific instructions
such as SBI, CBI, SBIC, SBIS, SBRC, and SBRS.
Table 5-2. Layout of Data Me m or y an d Re gis ter Area .
Device Memory Area Size Long Address
(1) Short Address (2)
ATtiny1634
General purpose register file 32B 0x0000 – 0x001F n/a
I/O register file 64B 0x0020 – 0x005F 0x00 – 0x3F
Extended I/O register file 160B 0x0060 – 0x00FF n/a
Data SRAM 1024B 0x0100 – 0x04FF n/a
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5.2.3 Extended I/O Register File
Following the standar d I/O regist er file, th e next 160 locations are reserved for extended I/O registers. ATtiny1634
is a complex microcontroller with more peripher al units than can be addressed with the IN and OUT instr uctions.
Registers in the extended I/O area must be accessed us ing instructions LD/LDD/LDS and ST/STD/STS. See
“Instruction Set Summary” on page 275.
See “Register Summary” on page 273 for a list of I/O registers.
5.2.4 Data Memory (SRAM)
Following the general purpose register file and the I/O register files, the remaining 10 24 loca tions are reserve d for
the internal data SRAM.
There are five addressing modes available:
• Direct. This mode of addressing reaches the entire data space.
• Indirect.
• Indirect with Displacement. This mode of addressing reaches 63 address locations from the base address given
by the Y- or Z-register.
• Indirect with Pre-decrement. In this mode the address register is automatically decremented before access.
Address pointer registers (X, Y, and Z) are located in the general purpose register file, in registers R26 to R31.
See “General Purpose Register File” on page 8.
• Indirect with Post-increment. In this mode the address register is automatically incremented after access.
Address pointer registers (X, Y, and Z) are located in the general purpose register file, in registers R26 to R31.
See “General Purpose Register File” on page 8.
All addressing modes can b e used on the en tire volatile me mory, inclu ding the general p urpose registe r file, the I/O
register files and the data memory.
Internal SRAM is accessed in two clkCPU cycles, as illustrated in Figure 5-2, below.
Figure 5-2. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction Next Instruction
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5.3 Data Memory (EEPROM)
ATtiny1634 contains 256 bytes of non-volatile data memory. This EEPROM is organized as a separate data space,
in which single bytes can be read and written. All access registers are located in the I/O space.
The EEPROM memory layout is summarised in Table 5-3, below.
The internal 8MHz oscillator is used to time EEPROM operations. The frequency of the oscillator must be within
the requirements described in “OSCCAL0 – Oscillator Calibration Register” on page 32.
When powered by heavily filtered supplies, the supply voltage, VCC, is likely to rise or fall slowly on power-up and
power-down. Slow rise and fall times may p ut the device in a state where it is running at supp ly voltages lower than
specified. To avoid problems in situations like this, see “Preventing EEPROM Corruption” on page 19.
The EEPROM has a minimum endurance of 100,000 write/erase cycles.
5.3.1 Programming Methods
There are two methods for EEPROM programming:
• Atomic byte programming. This is the simple mode of programming, where target locations are erased and
written in a single operation. In this mode of operation the target is guaranteed to always be erased before
writing but programmin times are longer.
• Split byte programming. It is p ossible to sp lit the era se and write cycle in two different operation s. This is useful
when short access times are required, for example when supply voltage is falling. In order to take advantage of
this method target location s must be erased before writin g to them. This can be don e at times when the system
allows time-critical operations, typically at start-up and initialisation.
The programming method is selected using the EEPROM Programming Mode bits (EEPM1 and EEPM0) in
EEPROM Control Register (EECR). See Table 5-4 on page 23. Write and erase times are given in the same table.
Since EEPROM programming takes some time the application must wa it for one operation to complete before
starting the next. This can be done by either polling the EEPROM Program Enable bit (EEPE) in EEPROM Control
Register (EECR), or via the EEPROM Ready Interrupt . The EEPROM interrupt is controlled by the EEPROM
Ready Interrupt Enable (EERIE) bit in EECR.
5.3.2 Read
To read an EEPROM memory location follow the procedure below:
1. Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no
other EEPROM operations are in process. If set, wait to clear.
2. Write target address to EEPROM Address Registers (EEARH/EEARL).
3. Start the read operation by setting the EEPROM Read Enable bit (EERE) in the EEPROM Control Regis-
ter (EECR). During the read operation, the CPU is halted for four clock cycles before executing the next
instruction.
4. Read data from the EEPROM Data Register (EEDR).
Table 5-3. Size of Non-Volatile Data Memory (EEPROM).
Device EEPROM Size Address Range
ATtiny1634 256B 0x00 – 0xFF
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5.3.3 Erase
In order to prevent unintentional EEPROM writes, a specific procedure must be followed to erase memory loca-
tions. To erase an EEPROM memory location follow the procedure below:
1. Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no
other EEPROM operations are in process. If set, wait to clear.
2. Set mode of pr ogrammi ng to era se by writing EEPROM Pro gramming Mode bit s ( EEPM0 and EEPM 1) in
EEPROM Control Register (EECR).
3. Write target address to EEPROM Address Registers (EEARH/EEARL).
4. Enable erase by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register
(EECR). Within four clock cycles, start the erase operation by setting the EEPROM Program Enable bit
(EEPE) in the EEPROM Control Register (EECR). During the erase operation, the CPU is halted for two
clock cycles before executing the next instru ct ion .
The EEPE bit remains set until the erase operation has completed. While the device is busy programming, it is not
possible to perfor m an y oth e r EEPRO M op e ra tio ns .
5.3.4 Write
In order to prevent unintentional EEPROM writes, a specific procedure must be followed to write to memory
locations.
Before writing data to EEPROM the target location must be erased. This can be done either in the same operation
or as part of a split operation. Writing to an unerased EEPROM location will result in corrupted data.
To write an EEPROM memory location follow the procedure below:
1. Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no
other EEPROM operations are in process. If set, wait to clear.
2. Set mode of programming by writing EEPROM Programming Mode bits (EEPM0 and EEPM1) in
EEPROM Control Register (EECR). Alternatively, data can be written in one operation or the write proce-
dure can be split up in erase, only, and write, only.
3. Write target address to EEPROM Address Registers (EEARH/EEARL).
4. Write target data to EEPROM Data Register (EEDR).
5. Enable write by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control Register
(EECR). Within four clock cycles, start the write operation by setting the EEPROM Program Enable bit
(EEPE) in the EEPROM Control Register (EECR). During the write operation, the CPU is halted for two
clock cycles before executing the next instru ct ion .
The EEPE bit remains set until the write operation has completed. While the device is busy with programming, it is
not possible to do any other EEPROM operations.
5.3.5 Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupt ed be caus e the s upply volt age is t oo low for the CPU
and the EEPROM to operate pro per ly. These issue s are the same as for board level systems using EEPROM, and
the same design solutions should be applied.
At low supply voltages data in EEPROM can be corrupted in two ways:
• The supply voltage is too low to maintain proper operation of an otherwise legitimate EEPROM program
sequence.
• The supply voltage is too low for the CPU and instructions may be executed incorrectly.
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EEPROM data corruption is avoided by keeping the device in reset during periods of insufficient power supply volt-
age. This is easily done by enabling the internal Brown-Out Detector (BOD). If BOD detection levels are not
sufficient for the design, an external reset circuit for low V CC can be used.
Provided that supply voltage is sufficient, an EEPROM write operation will be completed even when a reset occurs.
5.3.6 Program Examples
The following code examples show one assembly and one C function for erase, write, or atomic write of the
EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no
interrupts occur during execution of these functions.
Note: See “Code Examples” on page 6.
Note: See “Code Examples” on page 6.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR, EEPE
rjmp EEPROM_write
; Set Programming mode
ldi r16, (0<<EEPM1)|(0<<EEPM0)
out EECR, r16
; Set up address (r18:r17) in address registers
out EEARH, r18
out EEARL, r17
; Write data (r19) to data register
out EEDR, r19
; Write logical one to EEMPE
sbi EECR, EEMPE
; Start eeprom write by setting EEPE
sbi EECR, EEPE
ret
C Code Example
void EEPROM_write(unsigned int ucAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE));
/* Set Programming mode */
EECR = (0<<EEPM1)|(0<<EEPM0);
/* Set up address and data registers */
EEAR = ucAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
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The next code examples show assem bly and C functions for reading the EEPROM. The examples assume that
interrupts are controlled so that no interrupts will occur during execution of these functions.
Note: See “Code Examples” on page 6.
Note: See “Code Examples” on page 6.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR, EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address registers
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR, EERE
; Read data from data register
in r16, EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int ucAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE));
/* Set up address register */
EEAR = ucAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
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5.4 Register Description
5.4.1 EEARL – EEPROM Address Register Low
• Bits 7:0 – EEAR[7:0]: EEPROM Address
The EEPROM address register is required by the read and write operations to indicate the memory location that is
being accesse d.
EEPROM data bytes are addressed linearly over the entire memory range (0...[256-1]). The initial value of these
bits is undefined and a legitimate value must therefore be written to the register before EEPROM is accessed.
Devices with 256 bytes of EEPROM, or less, do not require a high address registers (EEARH). In such devices the
high address register is therefore left out but, for compatibility issues, the remaining register is still referred to as
the low byte of the EEPROM address register (EEARL).
Devices that to do not fill an entire address byte, i.e. devices with an EEPROM size not equal to 256, implement
read-only bits in the unused lo cations. Unused bits are located in the most significant end of the address register
and they always read zero.
5.4.2 EEDR – EEPROM Data Register
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For EEPROM write operations, EEDR contains the data to be written to the EEPROM address given in the EEAR
Register. For EEPROM read operations, EEDR contains the data read out from the EEPROM address given by
EEAR.
5.4.3 EECR – EEPROM Control Register
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
EEPROM programming mode bits define the action that will be triggered when EE PE is written. Data can be pro-
grammed in a single atomic operat ion, where the pr evious value is auto matically erased befor e the new value is
Bit 76543210
0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X X
Bit 76543210
0x1D (0x3D) EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x1C (0x3C) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X 0 0 X 0
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programmed, or Erase and Write can be split in two different operations. The programming times for the different
modes are shown in Table 5-4.
When EEPE is set any write to EEPMn will be ignored.
During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing this bit to one enables the EEPROM Ready Interrupt. Provided the I-bit in SREG is set, the EEPROM
Ready Interrupt is triggered when non-volatile memory is ready for programming.
Writing this bit to zero disables the EEPROM Ready Interrupt.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be pro-
grammed. Hardware clears the EEMPE bit to zero after four clock cycles.
If EEMPE is zero the EEPE bit will have no effect.
• Bit 1 – EEPE: EEPROM Program Enable
This is the programming enable signal of the EEPROM. The EEMPE bit must be set before EEPE is written, or
EEPROM will not be programmed.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bit settings. When EEPE has
been set, the CPU is halted for two cycles before the next instruction is executed. After the write access time has
elapsed, the EEPE bit is cleared by hardware.
Note that an EEPROM write operation blocks all software programming of Flash, fuse bits, and lock bits.
• Bit 0 – EERE: EEPROM Read Enable
This is the read strobe of the EEPROM. When the target addr ess has been set up in the EEAR, the EERE bit must
be written to one to trigger the EEPROM read operation.
EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM
is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it not possi-
ble to read the EEPROM, or to change the address register (EEAR).
5.4.4 GPIOR2 – General Purpo se I/O Regi st er 2
Table 5-4. EEPROM Programming Mode Bits and Programming Times
EEPM1 EEPM0 Programming Time Operation
0 0 3.4 ms Atomic (erase and write in one ope ration)
0 1 1.8 ms Erase, only
1 0 1.8 ms Write, only
1 1 – Reserved
Bit 76543210
0x16 (0x36) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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This register may be used freely for storing any kind of data.
5.4.5 GPIOR1 – General Purpo se I/O Regi st er 1
This register may be used freely for storing any kind of data.
5.4.6 GPIOR0 – General Purpo se I/O Regi st er 0
This register may be used freely for storing any kind of data.
6. Clock System
Figure 6-1 presents the principal clock systems and their distribution in ATtiny1634. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted
by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep
Modes” on page 34. The clock systems is detailed below.
Bit 76543210
0x15 (0x35) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x14 (0x34) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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Figure 6-1. Clock Distribution
6.1 Clock Subsystems
The clock subsystems are detailed in the sections below.
6.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concer ned with operation of the AVR core. Examples of such mod-
ules are the General Purpose Register F ile, the Status Register and the Data m emory holding the Stack Pointer.
Halting the CPU clock inhibits the core from performing general operations and calculations.
6.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the
External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing
such interrupts to be detected even if the I/O clock is halted.
6.1.3 Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the
CPU clock.
General I/O
Modules CPU Core RAM
clkI/O AVR Clock
Control Unit
clkCPU
Flash and
EEPROM
clkFLASH
Source clock
Watchdog Timer
32 kHz ULP Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated
Internal Oscillator
Calibrated RC
Oscillator
External Clock
ADC
clkADC
Crystal
Oscillator
System Clock
Prescaler
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6.1.4 ADC Clock – clkADC
The ADC is prov ide d with a d ed ica te d c lock domain. Th is a llows halting the CPU and I/O clocks in order to reduce
noise generated by digita l circuitry. This gives more accurate ADC conversion results.
6.2 Clock Sources
The device can use any of the following sources for the system clock:
• External Clock (see page 26)
• Calibrated Internal 8MHz Oscillator (see page 27)
• Internal 32kHz Ultra Low Power (ULP) Oscillator (see page 27)
• Crystal Oscillator / Ceramic Resonator (see page 27)
The clock source is selected using either CKSEL bits in the CLKSR register or CKSEL fuses. The difference
between CKSEL fuses and bits is that CKSEL fuses are automatically loaded to CKSEL bits at device power on or
reset. The initial value of CKSEL bits is therefore determined by CKSEL fuses.
CKSEL fuse bits can be read by firmware (see “Reading Lock, Fuse and Signature Data from Software” on page
211), but firmware can not write to fuse bits. Therefore, the CKSEL bits must be used if system clock sour ce needs
to be changed at run-time. The clock system has been designed to guarantee glitch-free performance when
switching between clock sources. See “CLKSR – Clock Setting Register” on page 29.
When the device wakes up from power-down the selected clock source is used to time the start-up, e nsuring stable
oscillator operation before instruction execution starts. When the CPU starts from reset, the internal 32kHz oscilla-
tor is used fo r gene rating an addition al delay , allow ing su pply voltage to reach a stable level before normal device
operation is started.
System clock alternatives are discussed in the following sections.
6.2.1 External Clock
To drive the devic e from an ext er na l cl oc k source, CLKI should be connected as shown in Figure 6-2 on page 26.
To ensure stable operation of the MCU it is required to avoid sudden changes in the external clock frequency . A
variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
required to ensure that the MCU is kept in Reset during such changes in the clock frequency.
Stable operation for large step changes in system clock frequency is guaranteed when using the system clock
prescaler. See “System Clock Prescaler” on page 28.
Figure 6-2. External Clock Drive Configuration
Start-up time for this clock source is determined by the SUT bit, as shown in Table 6-2 on page 30.
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
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6.2.2 Calibrated Internal 8MHz Oscillator
The internal 8MHz oscillator operates with no external components and, by default, provides a clock source with an
approximate frequency of 8MHz. Though voltage and temperature dependent, this clock can be very accurately
calibrated by the user. See Table 24-2 on page 230, “Calibrated Oscillator Frequency (Nominal = 1MHz) vs . VC C”
on page 271, and “Calibrated Oscillator Frequency (Nominal = 1MHz) vs. Temperature” on page 271 for more
details.
During re set, hardwa re loads th e pre-prog rammed ca libration value into the OSCCAL0 register and thereby auto-
matically calibrates the oscillator. The accuracy of this calibration is referred to as “Factory Calibration” in Table 24-
2 on page 230. For more information on automatic loading of pre-programmed calibration value, see section “Cali-
bration Bytes” on page 211.
It is possible to reach higher accuracies than factory defaults, especially when the application allows temperature
and voltage ranges to be narrowed. The firmware can reprogram the calibration data in OSCCAL0 either at start-
up or during run -tim e. Th e con tin uo us , ru n- tim e ca libr at ion me th od allo ws fir mw ar e to mo nit or volt ag e a nd temp er -
ature and compensate for any detected variations. See “OSCCAL0 – Oscillator Calibration Register” on page 32,
“Temperature Measur ement” on page 1 95, and Table 19-3 on page 196. The accuracy of this calibration is referred
to as “User Calibration” in Table 24-2 on page 230.
The oscillator temperature calibration registers, OSCTCAL0A and OSCTCAL0B, can be used for one-time temper-
ature calibration of oscillator frequency. See “OSCTCAL0A – Oscillator Te mperature Calibration Register A” on
page 33 and “OSCTCAL0B – Oscillator Temperature Calibration Register B” on page 33. During reset, hardware
loads the pre-programmed calibration values into OSCTCAL0A and OSCTCAL0B registers.
Start-up time for this clock source is determined by the SUT bit, as shown in Table 6-2 on page 30.
Supply voltage restrictions apply for running the device at this clock frequency. See “Speed” on page 229.
6.2.3 Internal 32kHz Ultra Low Power (ULP) Oscillator
The internal 32kHz oscillator is a low power oscillator that operates with no external components. It provides a
clock source with an approximate freq uency of 32kHz. The frequency depen ds on supply voltage , temperature and
batch variations. See Table 24-3 on page 231 for accuracy details.
During re set, hardwa re loads th e pre-prog rammed ca libration value into the OSCCAL1 register and thereby auto-
matically calibrates the oscillator. The accuracy of this calibration is referred to as “Factory Calibration” in Table 24-
3 on page 231. For more information on automatic loading of pre-programmed calibration value, see section “Cali-
bration Bytes” on page 211.
When this oscillator is used as the chip clock, it will still be used for the Watchdog Timer and for the Reset Time-
out.
Start-up time for this clock source is determined by the SUT bit, as shown in Table 6-2 on page 30.
6.2.4 Crystal Oscillator / Ceramic Resonator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which c an be configured for use as
an on-chip oscillator, as shown in Figure 6-3. Either a quartz crystal or a ceramic resonator may be used.
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Figure 6-3. Crystal Oscillator Connections
Capacitors C1 and C2 should always be equal, both for crystals and resonators. The optimal value of the capaci-
tors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of
the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-1, below.
For ceramic resonators, the capacitor values given by the manufacturer should be used.
The oscillator can operate in different modes, each optimized for a specific frequency range. See Table 6-4 on
page 31.
Start-up time for this clock source is determined by the SUT bit, as shown in Table 6-2 on page 30.
6.2.5 Default Clock Settings
The device is shipped with following fuse settings:
• Calibrated Internal 8MHz Oscillator (see CKSEL bits on page 30)
• Longest possible start-up time (see SUT bit on page 29)
• System clock prescaler set to 8 (see CKDIV8 fuse bit on page 210)
The default setting gives a 1MHz system clock and ensures all users can make their desired clock source setting
using an in-system or high-voltage programmer.
6.3 System Clock Prescaler
The ATtiny1634 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 31. This
feature can be used to decrease power consumption when the requirement for processing power is low. This can
be used with all clock source options, and it will affect the clock frequency of the CPU and a ll synchronous periph-
erals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 6-4 on page 31.
6.3.1 Switching Prescaler Setting
When switching between prescaler settings, the System Clock Prescaler ensures that no glitch occurs in the clock
system and that no interme diate frequency is higher th an neither the clock frequency corr esponding to the pre vious
setting, nor the clock frequency corresponding to the new setting.
Table 6-1. Crystal Oscillator Operating Modes
Frequency Range Recommended C1 and C2 Note
< 1MHz – Crystals, only. Not ceramic resonators.
> 1MHz 12 – 22 pF
XTAL2
XTAL1
GND
C2
C1
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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster
than the CPU's clock freq uency. Hence, it is not poss ible to determine the state of the prescaler - even if it were
readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock fre-
quency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2
is the period corresponding to the new prescaler setting.
6.4 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT_IO bit has to be pro-
grammed. Th e CKOUT fus e de te rm in es the initial value of the CKOUT_IO bit that is loaded to the CLKSR register
when the device is powered up or has been reset. The clock output can be switched at run-time by setting the
CKOUT_IO bit in CLKSR as described in chapter “CLKSR – Clock Setting Register” on page 29.
This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not
be output during reset and that the normal operation of the I/O pin will be overridden when the fu se is programmed.
Any clock source, including the internal oscillators, can be selected when the cloc k is output on CLKO. If the Sys-
tem Clock Prescaler is used, it is the divided system clock that is output.
6.5 Register Description
6.5.1 CLKSR – Clock Setting Register
• Bit 7 – OSCRDY: Oscillator Ready
This bit is set when oscillator time-out is complete. When OSCRDY is set the oscillator is stable and the clock
source can be changed safely.
• Bit 6 – CSTR: Clock Select Trigger
This bit triggers the clock selection. It can be used to enable the oscillator in advance and select the clock source,
before the oscillator is stable.
If CSTR is set at the same time as the CKSEL bits are written, the contents are directly copied to the CKSEL regis-
ter and the system clock is immediately switched.
If CKSEL bits are written without setting CSTR, the oscillator selected by the CKSEL bits is enabled, but the sys-
tem clock is not switched yet.
• Bit 5 – CKOUT_IO: Clock Output
This bit enables the clock output buffer. The CKOUT fuse determines the initial value of the CK OUT_IO bit that is
loaded to the CLKSR register when the device is powered up or has been reset
• Bit 4 – SUT: Start-Up Time
The SUT and CKSEL bits define the start-up time of the device, as shown in Table 6-2, below. The initial value of
the SUT bit is determin ed by the SUT fuse. The SUT fuse is loaded to the SUT bit when the device is powered up
or has been reset.
Bit 76543210
0x32 (0x52) OSCRDY CSTR CKOUT_IO SUT CKSEL3 CKSEL2 CKSEL1 CKSEL0 CLKSR
Read/Write R W R R R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
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Note: 1. Device start-up time from power-down sleep mode.
2. When BOD has been disabled by software, the wake-up time from sleep mode will be approximately 60µs to
ensure the BOD is w ork in g corre ctl y before MCU continues executing code.
3. Device start-up time after reset.
4. The device is shipped with this option selected.
5. This option is not suitable for use with crystals.
6. This option should not be used when operating close to the maximum frequency of the device, and only if fre-
quency stability at start-up is not important for the application.
7. This option is intended for use with ceramic resonators and will ensure frequency stability at start-up. It can also be
used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at
start-up is not important for the application.
• Bits 3:0 – CKSEL[3:0]: Clock Select Bits
These bits select the clock source of the system clock and can be written at run-time. The clock system ensures
glitch free switching of the clock source. CKSEL fuses determine the initial value of the CKSEL bits when the
device is powered up or reset.
The clock alternatives are shown in Table 6-3 below.
Table 6-2. Device Start-up Times
SUT CKSEL Clock From Power-Down (1)(2) From Reset (3)
0 (4)
0000 External 6 CK 22 CK + 16ms
0010 (4) Internal 8MHz 6 CK 20 CK + 16ms
0100 Internal 32kHz 6 CK 22 CK + 16ms
0001
0011
0101 ... 0111 Reserved
1XX0 Ceramic resonator (5) 258 CK (6) 274 CK + 16ms
1XX1 Crystal oscillator 16K CK 16K CK + 16 ms
10000 ... 0111
1XX1 Reserved
1XX0 Ceramic resonator 1K CK (7) 1K CK +16ms
Table 6-3. Device Clocking Options
CKSEL[3:0] (1) Frequency Device Clocking Option
0000 Any External Clock (see page 26)
0010 8MHz Calibrated Internal 8MHz Oscillator (see page 27) (2)
0100 32kHz Internal 32kHz Ultra Low Power (ULP) Oscillator (see page 27)
00X1
0101 ... 0111 —Reserved
100X 0.4...0.9MHz
Crystal Oscillator / Ceramic Resonator (see page 27)
101X 0.9...3MHz
110X 3...8MHz
111X > 8MHz
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Note: 1. For all fuses “1” means unprogrammed and “0” means programmed.
2. This is the default setting. The device is shipped with this fuse combination.
To avoid unintentional switching of clock source, a protected change seq uence must be followed to change the
CKSEL bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP.
2. Within four instruction cycles, write the CKSEL bits with the desired value.
6.5.2 CLKPR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the
master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 6-4 on page 31.
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1. Write the signature for change enable of protected I/O register to register CCP.
2. Within four instruction cycles, write the desired value to CLKPS bits.
Interrupts must be disabled when changing prescaler setting to make sure the wr ite procedure is not interrupted.
Bit 76543210
0x33 (0x53) – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
Table 6-4. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0000 1
(1)
0001 2
0010 4
0011 8
(2)
0100 16
0101 32
0110 64
0111 128
1000 256
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Note: 1. This is the initial value when CKDIV8 fuse has been unprogrammed.
2. This is the initial value when CKDIV8 fuse has been programmed. The device is shipped with the CKDIV8 Fuse
programmed.
The initial value o f clock prescaler bits is de termined by the CKDIV8 fuse (see Table 22-5 on page 210). When
CKDIV8 is unprogrammed, the system clock prescaler is set to one and, when programmed, to eight. Any value
can be written to the CLKPS bits regardless of the CKDIV8 fuse bit setting.
When CKDIV8 is programmed the initial value of CLKPS bits give a clock division factor of eight at start up. This is
useful when the selected clock source has a higher frequency than allowed under present operating conditions.
See “Speed” on page 229.
6.5.3 OSCCAL0 – Oscillator Calibration Register
Although temperature slope and frequency are in part controlled by registers OSCTCAL0A and OSCTCAL0B it is
possible to replace factory calibration by simply writing to this register alone. Optimal accuracy is achieved whe n
OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bits 7:0 – CAL0[7:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the internal 8MHz oscillator and to remove process variations from
the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip
reset, giving the factory calibrated frequency specified in Table 24-2 on page 230.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies specified in Table 24-2 on page 230. Calibration outside that range is not guaranteed.
The lowest oscillator fre quency is reached by programming these bits to zero. Increasing the register value
increases the oscillator frequency. A typical frequency response curve is shown in “Calibrated Oscillator Frequency
(Nominal = 8MHz) vs. OSCCAL Value” on page 270.
Note that this oscillator is used to time EEPROM and Flash write accesses, and write times will be affected accord-
ingly. Do not calibrate to more than 8.8MHz if EEPROM or Flash is to be written. Otherwise, the EEPROM or Flash
write may fail.
To ensure stable operation of the MCU the calibration value shou ld be changed in small steps. A step change in
frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Also, the difference
between two consecutive register values sho uld not e xceed 0x20. If these limits are exceeded the MCU must be
kept in reset during changes to clock frequency.
1001
Reserved
1010
1011
1100
1101
1110
1111
Table 6-4. Clock Prescaler Select (Continued)
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
Bit 76543210
(0x63) CAL07 CAL06 CAL05 CAL04 CAL03 CAL02 CAL01 CAL00 OSCCAL0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
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6.5.4 OSCTCAL0A – Oscillator Temperature Calibration Register A
This register is used for changing t he temperature slope and frequency of the internal 8MHz oscillator. A pre-pro-
grammed calibration value is automatica lly written to this register during chip reset, giving the factory calibrated
frequency specified in Table 24-2 on page 230.
This register need not be updated if factory defaults in OSCCAL0 are overwritten although optimal accuracy is
achieved when OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bit 7 – Sign of Oscillator Temperature Calibration Value
This is the sign bit of the calibration data.
• Bits 6:0 – Oscillator Temperature Calibration Value
These bits contain the numerical value of the calibra tion data.
6.5.5 OSCTCAL0B – Oscillator Temperature Calibration Register B
A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory cal-
ibrated frequency specified in Table 24-2 on page 230.
This register need not be updated if factory defaults in OSCCAL0 are overwritten although optimal accuracy is
achieved when OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bit 7 – Temperature Compensat ion Enable
When this bit is set the contents of registers OSCTCAL0A and OSCTCAL0B are used for calibration. When this bit
is cleared the tempe rature compensation hardware is disabled and registers OSCTCAL0A and OSCTCAL0B have
no effect on the frequency of the internal 8MHz oscillator.
Note that tempera ture compensation ha s a large effect on oscillator frequency and , hence, when en abled or dis-
abled the OSCCAL0 register must also be adjusted to compensate for this effect.
• Bits 6:0 – Temperature Compensation Step Adjust
These bits control the step size of the calibration data in OSCTCAL0A. The larges t step size is achieved for 0x00
and smallest step size for 0x7F.
6.5.6 OSCCAL1 – Oscillator Calibration Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 76543210
(0x64) Oscillator Temperature Calibration Data OSCTCAL0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 76543210
(0x65) Oscillator Temperature Calibration Data OSCTCAL0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 76543210
(0x66) – – – – – – CAL11 CAL10 OSCCAL1
Read/Write RRRRRRR/WR/W
Initial Value Device Specific Calibration Value
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• Bits 1:0 – CAL1[1:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the internal 32kHz oscillator and to remove process variations from
the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip
reset, giving the factory calibrated frequency as specified in Table 24-3 on page 231.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies as specified in Table 24-3 on page 231. Calibration outside that range is not guaranteed.
The lowest oscillator fre quency is reached by programming these bits to zero. Increasing the register value
increases the oscillator frequency.
7. Power Management and Sleep Modes
The high performance and industr y leading code efficiency makes the AVR microcontrollers an ideal choise for low
power applications. In addition, sleep modes enable the application to shut down unused modules in the M CU,
thereby saving power. Th e AVR provides various sleep modes allowing the user to tailo r the power consumption to
the application’s requirements.
7.1 Sleep Modes
Figure 6-1 on page 25 presents the different clock systems and their distribution in ATtiny1634. The figure is help-
ful in selecting an appr opriate sleep mode . Table 7-1 shows the di fferent sleep mo des and the sources th at may be
used for wake up.
Note: 1. Start frame detection, only.
2. Start condition, only.
3. Address match interrupt, only.
4. For INT0 level interrupt, only.
To enter a sleep mode, the SE bit in MCUCR must be set and a SLEEP instruction must be executed. The SMn
bits in MCUCR select which sleep mode will be activated by the SLEEP instruction. See Table 7-2 on page 37 for
a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruc-
tion following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Oscillators Active Clock Domains Wak e-up Sources
Main Clock
Source Enabled
clkCPU
clkFLASH
clkIO
clkADC
Watchdog
Interrupt
INT0 and
Pin Change
SPM/EEPROM
Ready Interrupt
ADC Interrupt
USART
USI
TWI Slave
Other I/O
Idle X XXXXXXXXXX
ADC Noise
Reduction XXXX
(4) XXX
(1) X (2) X (3)
Standby X X X (4) X (1) X (2) X (3)
Power-down X X (4) X (1) X (2) X (3)
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Note that if a level triggered interrupt is used for wake-up the changed level must be he ld for some time to wake up
the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 48 for details.
7.1.1 Idle Mode
This sleep mode basically halts clkCPU and clkFLASH, while allowing other clocks to run. In Idle Mode, the CPU is
stopped but the following peripherals continu e to operate:
• Watchdog and interrupt system
• Analog comparator, and ADC
• USART, TWI, and timer/counters
Idle mode allows the MCU to wake up from external triggered interrupts as well as internal ones, such as Timer
Overflow. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered
down by setting the ACD bit in AC SRA. See “ACSRA – Analog Comparator Control and Status Regis ter” on page
182. This will reduce power consumption in Idle mode.
If the ADC is enabled, a conversion starts automatically when this mode is entered.
7.1.2 ADC Noise Reduction Mode
This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing other clocks to run. In ADC Noise Reduction
mode, the CPU is stopped but the following peripherals continue to operate:
• Watchdog (if enabled), and external interrupts
•ADC
• USART start frame detector, and TWI
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
The following events can wake up the MCU:
• Watchdog reset, external reset, and brown-out reset
• External level interrupt on INT0, and pin change interrupt
• ADC conversion complete interrupt, and SPM/EEPROM ready interrupt
• USI start condition, USART start frame detection, and TWI address match
7.1.3 Power-Down Mode
This sleep mode halts all generated clocks, allowing operation of asynchronous modules, only. In Power-down
Mode the oscillator is stopped, while the following peripherals continue to operate:
• Watchdog (if enabled), external interrupts
The following events can wake up the MCU:
• Watchdog reset, external reset, and brown-out reset
• External level interrupt on INT0, and pin change interrupt
• USI start condition, USART start frame detection, and TWI address match
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7.1.4 Standby Mode
Standby Mode is identical to power-down, with the except ion that the oscillator is kept running. From Standby
mode, the device wakes up in six clock cycles.
7.2 Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 38, provides a method to
reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is
stopped then:
• The current state of the peripheral is frozen.
• The associated registers can not be read or written.
• Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the
peripheral and puts it in the same state as before shutdown.
Peripheral shutdo wn can be used in Idle mode and Active mode to significantly reduce the over all power consump-
tion. In all other sleep modes, the clock is already stopped.
7.3 Minimizing Power Consumption
There are seve ral issu es to consid er wh en tr yi ng to mini mize the p ower consumption in an AVR contro lled syste m.
In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as
few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular,
the following modules may need special consideration when trying to achieve the lowest possible power
consumption.
7.3.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
See “Analog to Digital Converter” on page 185 for details on ADC operation.
7.3.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is
automatically disabled. Howev er, if the Analog Comparator is set up to use the Internal Voltage Re ference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will
be enabled, independ ent of sle ep mode. See “Analo g Comparat or” on pa ge 181 for details on how to configure the
Analog Comparator.
7.3.3 Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detec-
tor is enabled by the BODPD Fuses, it will be enabled in all sleep modes, and hence, always consume power. In
the deeper sleep modes, this will contribute significantly to the total current consumption. If the Brown-out Detector
is needed in the application, this module can also be set to Sampled BOD mode to save power. See “Brown-Out
Detection” on page 41 for details on how to configure the Brown-out Detector.
7.3.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detect ion, the Analog Comparator
or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
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before the output is u sed. If the refe re nce is kept o n in sleep mode, the output can be used immedia tely. Se e Inte r-
nal Bandgap Reference in Table 24-5 on page 231 for details on the start-up time.
7.3.5 W atchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute to the total current consumption. See “Watchdog Timer” on page 43 for details on how to configure
the Watchdog Timer.
7.3.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing
is then to ensure that no pins drive resistive loads. In sleep modes where b oth the I/O clock (clk I/O) and the ADC
clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed
by the input logic when not needed. In some cases, the input logic is ne eded fo r dete cting wake-up condition s, and
it will then be enabled. See the section “Digital Input Enable and Sleep Modes” on pa ge 58 for details on which pins
are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to
VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Register (DIDR0). See “DIDR0 – Digital Input Disable Register 0” on page 200 for details.
7.3.7 On-chip Debug System
If the On-chip de bug system is e nab led by the DWEN Fuse an d th e chip enter s sle ep mo de, the m ain clo ck so ur ce
is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the
total current consumption.
7.4 Register Description
7.4.1 MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
• Bits 7, 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 6:5 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between available sleep modes, as shown in Table 7-2.
Bit 76543210
0x36 (0x56) –SM1SM0SE – –
ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value00000000
Table 7-2. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
0 1 ADC Noise Reduction
1 0 Power-down
1 1 Standby(1)
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Note: 1. Only recommended with external crystal or resonator selected as clock source
• Bit 4 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is exe-
cuted. To avoid the MCU entering the sleep mode unless it is the program mer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
7.4.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock sig-
nals to be disabled.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit and will always read zero.
• Bit 6 – PRTWI: Power Reduction Two-Wire Interface
Writing a logic one to this bit shuts down the Two-Wire Interfac e module.
• Bit 5 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Cou nter1 mod ule. When the Timer /Co unter1 is enabled , opera-
tion will continue like before the shutdown.
• Bit 4 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Cou nter0 mod ule. When the Timer /Co unter0 is enabled , opera-
tion will continue like before the shutdown.
• Bit 3 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI
again, the USI should be re initialized to ensure proper operation.
• Bit 2 – PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART1 module. When the USART1 is enabled, operation will con-
tinue like before the shutdown.
• Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART0 module. When the USART0 is enabled, operation will con-
tinue like before the shutdown.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog com-
parator cannot be used when the ADC is shut down.
Bit 76543 2 1 0
0x34 (0x54) – PRTWI PRTIM1 PRTIM0 PRUSI PRUSART1 PRUSART0 PRADC PRR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value00000 0 0 0
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8. System Control and Reset
8.1 Resetting the AVR
During reset, all I/O registers are se t to th eir in itial values , a nd the pr ogr am star ts e xecut ion from the Re se t Vecto r.
The instruction placed at the Reset Vector should be a JMP (two-word, direct jump) instruction to the reset han-
dling routine, although other one- or two-word jump instructions can be used. If the program never enables an
interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the reset circuitry are defined in
section “System and Reset” on page 231.
Figure 8-1. Reset Logic
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not
require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the
power to reach a stable level before normal operatio n starts.
8.2 Reset Sources
The ATtiny1634 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT)
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length when RESET function is enabled
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled
• Brown-out Reset. The MCU is reset when the supply volt age VCC is below the Brown-out Reset threshold (VBOT)
and the Brown-out Detector is enabled
8.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is de fined in “Sys-
tem and Reset” on page 231. The POR is a ctivated whenever V CC is below the detection level. The POR circuit can
be used to trigger the Start-up Reset, as well as to detect a failure in supply voltag e.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise.
The reset signal is activated again, without any delay, when VCC decreases below the detection level.
DATA BU S
RESET FLAG REGISTER
RESET FLAG REGISTER
(RSTFLR)
(RSTFLR)
POWER-ON
POWER-ON
RESET CIRCUIT
RESET CIRCUIT
PULL-UP
PULL-UP
RESISTOR
RESISTOR
BODLEVEL2...0
BODLEVEL2...0
V
CC
CC
SPIKE
SPIKE
FILTER
FILTER
RESET
RESET
EXTERNAL
EXTERNAL
RESET CIRCUIT
RESET CIRCUIT
BROWN OUT
BROWN OUT
RESET CIRCUIT
RESET CIRCUIT
RSTDISBL
RSTDISBL
WATCHDOG
WATCHDOG
TIMER
TIMER
DELAY
DELAY
COUNTERS
COUNTERS
S
R
Q
WATCHDOG
WATCHDOG
OSCILLATOR
OSCILLATOR
CLOCK
CLOCK
GENERATOR
GENERATOR
BORF
PORF
EXTRF
WDRF
INTERNAL
INTERNAL
RESET
RESET
CK
CK
TIMEOUT
TIMEOUT
COUNTER RESET
COUNTER RESET
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Figure 8-2. MCU Start-up, RESET Tied to VCC
Figure 8-3. MCU Start-up, RESET Extended Externally
8.2.2 External Reset
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum
pulse width (see section “System and Reset” on page 231) will generate a reset, even if the clock is not running.
Shorter pulses are not guarantee d to genera te a rese t. Wh en the applied signa l reach es the Re se t Thre shold Volt-
age – VRST – on its positive edge, the delay counter starts the MCU after the time-out period – tTOUT – has expired.
External reset is ignored dur ing Power -on sta rt-u p coun t. After Powe r-on reset the inter nal r eset is extended on ly if
RESET pin is low when the initial Power-on delay count is complete. See Figure 8-2 and Figure 8-3.
Figure 8-4. External Reset During Operation
V
TIME-OUT
RESET
RESET
TOUT
INTERNAL
t
VPOT
VRST
CC
V
TIME-OUT
TOUT
TOUT
INTERNAL
CC
t
VPOT
VRST
> t
RESET
RESET
CC
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8.2.3 W atchdog Reset
When the Watchdog times out, it will generate a short reset pulse. On the falling edge of this pulse, the delay timer
starts counting the time-out period tTOUT. See page 43 for details on operation of the Watchdog Timer and Table
24-5 on page 231 for details on reset time-out.
Figure 8-5. Watchdog Reset During Operation
8.2.4 Brown-Out Detection
The Brown-Out Detection (BOD) circuit monitors that the VCC level is kept above a configurable trigger level, VBOT.
When the BOD is enabled, a BOD reset will be given when VCC falls and remains below the trigger level for the
length of the detection tim e, tBOD. The reset is ke pt active until VCC aga in rises above the trigger level.
Figure 8-6. Brown-out Detection reset.
The BOD circuit will not detect a drop in VCC unless the voltage stays below the trigger level for the detection time,
tBOD (see “System and Reset” on page 231).
The BOD circuit has three modes of operation:
•Disabled: In this mode of operation VCC is not monitored and, hence, it is recommended only for applications
where the power supply remains stable.
CK
CC
VCC
TIME-OUT
INTERNAL
RESET
VBOT- VBOT+
tTOUT
tBOD
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•Enabled: In this mode the VCC level is continuously monitored. If VCC drops below VBOT for at least tBOD a
brown-out reset will be generated.
•Sampled: In this mode the VCC level is sampled on each negative edge of a 1kHz clock that has been derive d
from the 32kHz ULP oscillator . Between each sample the BOD is turned of f. Compared to the mode where BOD
is constantly enabled this mode of operation reduces power consumption but fails to detect drops in VCC
between two positive edges of the 1kHz clock. When a brown-out is detected in this mode, the BOD circuit is
set to enabled mode to ensure that the device is kept in reset until VCC has risen ab ove VBOT . The BOD will
return to sampled mode after reset has been released and the fuses have been read in.
The BOD mode of operation is selected using BODACT and BODPD fuse bits. The BODACT fuse bits determine
how the BOD operates in active and idle mode, as shown in Table 8-1.
The BODPD fuse bits determine the mode of operation in all sleep modes except idle mode, as shown in Table 8-
2.
See “Fuse Bits” on page 209.
8.3 Internal Voltage Reference
ATtiny1634 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be
used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and
temperature.
8.3.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given
in “System and Reset” on page 231. To save power, the reference is not always turned on. The reference is on
during the following situations:
1. When the BOD is enabled (see “Brown-Out Detection” on page 41).
2. When the internal reference is connected to the Analog Comparator (by setting the ACBG bit in ACSRA).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the referenc e to start up befor e the output from t he Analog Comparat or or ADC is used. To r educe power con-
Table 8-1. Setting BOD Mode of Operation in Active and Idle Modes
BODACT1 BODACT0 Mode of Operation
00 Reserved
01 Sampled
10 Enabled
1 1 Disabled
Table 8-2. Setting BOD Mode of Operation in Sleep Modes Other Than Idle
BODPD1 BODPD0 Mode of Operation
00 Reserved
01 Sampled
10 Enabled
1 1 Disabled
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sumption in Power-down mode, the user can avoid the thre e conditions above to ensure that the re ference is
turned off before entering Power-down mode.
8.4 Watchdog Timer
The Watchdog Timer is clocked from the internal 32kHz ultra low power oscillator (see page 27). By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as show n in Table 8-5 on page 46. The
WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is dis-
abled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another Watchdog Reset, the ATtiny1634 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-5 on page 46.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very h elpful
when using the Watchdog to wake-up from Power- down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety
levels are sele cted by the fuse WDTON as shown in Table 8-3 See “Timed Sequences for Changing the Configu-
ration of the Watchdog Timer” on page 43 for details.
Figure 8-7. Watchdog Timer
8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate procedures ar e
described for each level.
• Safety Level 1
In this mode, the Watchd og Timer is initia lly disabled, bu t can be enabled by writin g the WDE bit to one without
any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer, th e following procedure must be followed:
Table 8-3. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON Safety
Level WDT Initial
State How to Disable the
WDT How to Change Time-
out
Unprogrammed 1 Disabled Timed sequence No limitations
Programmed 2 Enabled Always enabled Timed sequence
OSC/512
OSC/1K
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
MCU RESET
WATCHDOG
PRESCALER
32 kHz
ULP OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUX
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a. Write the signature for change enable of protected I/O re gisters to register CCP
b. Within four instruction cycles, in th e sam e oper at ion , writ e WDE an d WDP bits
• Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed
sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the
following procedure must be followed:
a. Write the signature for change enable of protected I/O re gisters to register CCP
b. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
8.4.2 Code Examples
The following code example shows how to turn o ff the WDT. The example assumes that interrupts are controlled
(e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Note: See “Code Examples” on page 6.
8.5 Register Description
8.5.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny1634 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occu rs. The bit is reset by a Power-on Reset, or by writin g a logic zero to the
flag.
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in r16, RSTFLR
andi r16, ~(1<<WDRF)
out RSTFLR, r16
; Write signature for change enable of protected I/O register
ldi r16, 0xD8
out CCP, r16
; Within four instruction cycles, turn off WDT
ldi r16, (0<<WDE)
out WDTCSR, r16
ret
Bit 76543210
0x35 (0x55) – – – – WDRF BORF EXTRF PORF MCUSR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
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• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as
early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can
be found by examining the Reset Flags.
8.5.2 WDTCSR – Watchdog Timer Control and Status Register
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Time r is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-o ut Inter-
rupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out
Interrupt is enab led. In this mode the correspondin g interrupt is executed instead of a re set if a timeout in the
Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time -out occurs. This is use ful for keeping the
Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a
reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt.
• Bit 4 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny1634 and will always read as zero.
• Bit 3 – WDE: Watchdog Enable
This bit enables and disables the Watchdog Timer. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 43.
Bit 76543210
0x30 (0x50) WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 WDTCSR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 X 0 0 0
Table 8-4. Watchdog Timer Configuration
WDE WDIE Watchdog Tim e r State Action on Time- ou t
0 0 Stopped None
0 1 Running Interrupt
1 0 Running Reset
1 1 Running Interrupt
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• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3 - 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The di fferent
prescaling values and th eir corresponding Timeout Periods are shown in Table 8-5.
Note: 1. If selected, one of the valid settings below 0b1010 will be used.
Table 8-5. Watchdog Timer Prescale Select
WDP3 WDP2 WDP1 WDP0 WDT Oscillator Cycles Typical Time-out @VCC = 5V
0 0 0 0 512 cycles 16 ms
0 0 0 1 1K cycles 32 ms
0 0 1 0 2K cycles 64 ms
0 0 1 1 4K cycles 0.125 s
0 1 0 0 8K cycles 0.25 s
0 1 0 1 16K cycles 0.5 s
0 1 1 0 32K cycles 1.0 s
0 1 1 1 64K cycles 2.0 s
1 0 0 0 128K cycles 4.0 s
1 0 0 1 256K cycles 8.0 s
1010
Reserved(1)
1011
1100
1101
1110
1111
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9. Interrupts
This section describes the specifics of the interrupt ha ndling as performed in ATtiny1634. F or a general explana-
tion of the AVR interrupt hand ling, see “Reset and Interrupt Handling” on page 11.
9.1 Interrupt Vectors
The interrupt vectors of ATtiny1634 are described in Table 9-1, below.
Table 9-1. Reset and Interrupt Vectors
Vector No. Program Address Label Interrupt Source
1 0x0000 RESET External Pin, Power-on Reset,
Brown-out Reset, Watchdog Reset
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 PCINT0 Pin Change Interrupt Request 0
4 0x0006 PCINT1 Pin Change Interrupt Request 1
5 0x0008 PCINT2 Pin Change Interrupt Request 2
6 0x000A WDT Watchdog T ime-out
7 0x000C TIM1_CAPT Timer/Counter1 Input Capture
8 0x000E TIM1_COMPA Timer/Counter1 Compare Match A
9 0x0010 TIM1_COMPB T imer/Counter1 Compare Match B
10 0x0012 TIM1_OVF Timer/Counter1 Overflow
11 0x0014 TIM0_COMPA Timer/Counter0 Compare Match A
12 0x0016 TIM0_COMPB T imer/Counter0 Compare Match B
13 0x0018 TIM0_OVF Timer/Counter0 Overflow
14 0x001A ANA_COMP Analog Comparator
15 0x0 01C ADC_READY ADC Conversion Complete
16 0x001E USART0_RXS USART0 Rx Start
17 0x0020 USART0_RXC USART0 Rx Complete
18 0x0022 USART0_DRE USART0 Data Register Empty
19 0x0024 USART0_TXC USART0 Tx Complete
20 0x0026 USART1_RXS USART1 Rx Start
21 0x0028 USART1_RXC USART1 Rx Complete
22 0x002A USART1_DRE USART1 Data Register Empty
23 0x002C USART1_TXC USART1 Tx Complete
24 0x002E USI_STR USI START
25 0x0030 USI_OVF USI Overflow
26 0x0032 TWI Two-Wire Interface
27 0x0034 EE_RDY EEPROM Ready
28 0x0036 QTRIP QTRIP QTouch
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In case the program never enables an interrupt so urce, the Interrupt Vectors will not be used and, consequently,
regular program code can be placed at these locations.
A typical and general setup for interrupt vector addresses in ATtiny1634 is shown in th e program example below.
Note: See “Code Examples” on page 6.
9.2 External Interrupts
External Interrupts are triggered by the INT0 pin, or by any of the PCINTn pins. Note that, if enabled, the interrupts
will trigger even if the INTn or PCINTn pins are config ured as outputs. This feature provides a way of generating
software inter ru pt s.
Assembly Code Example
.org 0x0000 ;Set address of next statement
jmp RESET ; Address 0x0000
jmp INT0_ISR ; Address 0x0002
jmp PCINT0_ISR ; Address 0x0004
jmp PCINT1_ISR ; Address 0x0006
jmp PCINT2_ISR ; Address 0x0008
jmp WDT_ISR ; Address 0x000A
jmp TIM1_CAPT_ISR ; Address 0x000C
jmp TIM1_COMPA_ISR ; Address 0x000E
jmp TIM1_COMPB_ISR ; Address 0x0010
jmp TIM1_OVF_ISR ; Address 0x0012
jmp TIM0_COMPA_ISR ; Address 0x0014
jmp TIM0_COMPB_ISR ; Address 0x0016
jmp TIM0_OVF_ISR ; Address 0x0018
jmp ANA_COMP_ISR ; Address 0x001A
jmp ADC_ISR ; Address 0x001C
jmp USART0_RXS_ISR ; Address 0x001E
jmp USART0_RXC_ISR ; Address 0x0020
jmp USART0_DRE_ISR ; Address 0x0022
jmp USART0_TXC_ISR ; Address 0x0024
jmp USART1_RXS_ISR ; Address 0x0026
jmp USART1_RXC_ISR ; Address 0x0028
jmp USART1_DRE_ISR ; Address 0x002A
jmp USART1_TXC_ISR ; Address 0x002C
jmp USI_START_ISR ; Address 0x002E
jmp USI_OVF_ISR ; Address 0x0030
jmp TWI_ISR ; Address 0x0032
jmp EE_RDY_ISR ; Address 0x0034
jmp QTRIP_ISR ; Address 0x0036
RESET: ; Main program start
<instr> ; Address 0x0038
...
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The pin change interrupts trigger as follows:
• Pin Change Interrupt 0 (PCI0): triggers if any enabled PCINT[7:0] pin toggles
• Pin Change Interrupt 1 (PCI1): triggers if any enabled PCINT[11:8] pin toggles
• Pin Change Interrupt 2 (PCI2): triggers if any enabled PCINT[17:12] pin toggles
Registers PCMSK0, PCMSK1, and PCMSK2 control which pins contribute to the pin change interrupts.
Pin change interrupts on PCINT[17:0] are detected asynchronously, which means that these interrupts can be
used for waking the part also from sleep modes other than Idle mode.
External interrupt INT0 can be triggered by a falling or rising edge, or a low level. See “MCUCR – MCU Control
Register” o n page 3 7. When INT0 is enabled and configured as level triggered, the interrup t will trigger as long as
the pin is held low.
Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, as described
in “Clock System” on page 24.
9.2.1 Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for
waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be he ld long
enough for the MCU to com plete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL fuses, as described in “Clock System” on page 24.
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be
diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2 Pin Change Interrupt Timing
A timing example of a pin change interrupt is shown in Figure 9-1.
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Figure 9-1. Timing of pin change interrupts
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0) pin_sync pcint_syn
pin_lat
D Q
LE
pcint_setflag PCIF
clk clk
PCINT(0) in PCMSK(x)
pcint_in_(0) 0
x
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9.3 Register Description
9.3.1 MCUCR – MCU Control Register
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
External Interrupt 0 is triggered by activity on pin INT0, provided that the SREG I-flag and the corresponding inter-
rupt mask are set . The co nd itio ns req uir ed to trigger the interrupt are defined in Table 9-2.
Note: 1. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
9.3.2 GIMSK – General Interrupt Mask Register
• Bits 7, 2:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
The external interrupt for pin INT0 is enabled when this bit and the I-bit in the Status Register (SREG) are set. The
trigger condition s ar e se t with th e ISC0 n bit s.
Activity on the pin will cause an interrupt request even if INT0 has been configured as an output.
• Bit 5 – PCIE2: Pin Change Interrupt Enable 2
When this bit and the I-bit of SREG are set the Pin Change Interrupt 2 is enabled. Any ch ange on an enabled
PCINT[17:12] pin will cause a PCINT2 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK2 – Pin Change Mask Register 2” on page 52.
• Bit 4 – PCIE1: Pin Change Interrupt Enable 1
When this bit and the I-bit of SREG are set the Pin Change Interrupt 1 is enabled. Any ch ange on an enabled
PCINT[11:8] pin will cause a PCINT1 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK1 – Pin Change Mask Register 1” on page 53.
Bit 76543210
0x36 (0x56) –SM1 SM0 SE –– ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value00000000
Table 9-2. External Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request (1)
0 1 Any logical change on INT0 generates an interrupt request (2)
1 0 The falling edge of INT0 generates an interrupt request (2)
1 1 The rising edge of INT0 generates an interrupt request (2)
Bit 76543210
0x3C (0x5C) – INT0 PCIE2 PCIE1 PCIE0 – – – GIMSK
Read/Write R R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0
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• Bit 3 – PCIE0: Pin Change Interrupt Enable 0
When this bit and the I-bit of SREG are set the Pin Change Interrupt 0 is enabled. Any ch ange on an enabled
PCINT[7:0] pin will cause a PCINT0 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK0 – Pin Change Mask Register 0” on page 53.
9.3.3 GIFR – General Interrupt Flag Register
• Bits 7, 2:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
This bit is set when activity on INT0 has triggered an interrupt request. Provided that the I-bit in SREG and the
INT0 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared whe n the inte rr upt ser v ice ro utine is e x ec uted. Alternatively, th e flag ca n be cle ar ed b y wr iting a
logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF2: Pin Change Interrupt Flag 2
This bit is set when a logic change on any PCINT[17:12] pin has triggered an interru pt request. Provided that the I-
bit in SREG and the PCIE2 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Altern ative ly, the flag ca n be clear ed by writin g a lo gical
one to it.
• Bit 4 – PCIF1: Pin Change Interrupt Flag 1
This bit is set when a logic change on any PCINT[ 11:8] pin has triggered an interrupt request. Provided that the I-
bit in SREG and the PCIE1 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Altern ative ly, the flag ca n be clear ed by writin g a lo gical
one to it.
• Bit 3 – PCIF0: Pin Change Interrupt Flag 0
This bit is set when a logic change on any PCINT[7:0] pin has triggered an interrupt request. Provided that the I-bit
in SREG and the PCIE0 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Altern ative ly, the flag ca n be clear ed by writin g a lo gical
one to it.
9.3.4 PCMSK2 – Pin Change Mask Register 2
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 76543210
0x3B (0x5B) – INTF0 PCIF2 PCIF1 PCIF0 – – – GIFR
Read/Write R R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x29 (0x49) – – PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 PCMSK2
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bits 5:0 – PCINT[17:12]: Pin Change Enable Mask 17:12
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrup t on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
9.3.5 PCMSK1 – Pin Change Mask Register 1
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrup t on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
9.3.6 PCMSK0 – Pin Change Mask Register 0
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrup t on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x28 (0x48) – – – – PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x27 (0x47) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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10. I/O Ports
10.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one p ort pin can be ch an ged with out un intentio nally cha ngi ng the dir ection of any oth er pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/dis-
abling of pull-up resistors (if configured as input). Most output buffers have symmetrical drive characteristics with
both high sink and source capability, while some are asymmetrical and have high sink and standard source capa-
bility. The pin drive r is strong enough to drive L ED displays directly. All port pins have individually selectable pull-up
resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as
indicated in Figure 10-1 on page 5 4. See “ Electrical Characteri stics” on page 228 for a comp lete list of paramete rs.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents the number-
ing letter for the port, and a lower case “n” represents the bit number. However, when using th e register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here docu-
mented generally as PORTxn. The physical I/O Registers and bit locations are listed in “” on page 70.
Four I/O memory address locations are allocat ed for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, Pull-up Enable Register – PU Ex, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register, the Data Direction Register, and the Pull-Up Enable Register are
read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit
in the Data Register.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 54. Most port pins
are multiplexed with alternate functions for th e peripheral features on the device. How each alter nate function in ter-
feres with the port pin is described in “Alte rnate Port Functions” on page 59 . Refer to the individual module se ctions
for a full descrip tio n of th e alt er na te fun ctio ns .
Note that enabling the alte rnate function of some of the por t pins does not affect the use of the other pins in the port
as general digital I/O.
10.2 Ports as Gen eral Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
Pxn
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Figure 10-2. General Digital I/O(1)
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP
are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of fou r regi ster bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description”
on page 71, the DDxn bits ar e accessed at the DDRx I/O addr ess, the PORTxn bits at the PORTx I/O address, the
PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one whe n the pin is configured as an output pin, the port pin is drive n high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
SYNCHRONIZER
clkI/O: I/O CLOCK
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
QD
CLR
PORTxn
Q
QD
CLR
DDxn
PINxn
DATA B US
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WEx
REx
RESET
Q
QD
CLR
PUExn
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
RDx: READ DDRx
WEx: WRITE PUEx
REx: READ PUEx
WPx: WRITE PINx REGISTER
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The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to
be written logic zero.
Table 10-1 summarizes the co ntrol signals for the pin value.
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic on e to PINxn t oggles the v alue of POR Txn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Break-Before-Make Switching
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period
lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4MHz and the
DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of
PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximu m DDRxn toggle frequency is two system clock cycles. The
Break-Before-Make mode applies to the entire port a nd it is activated by the BBMx bit. For more details, see
“PORTCR – Port Control Register” on page 71.
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
Table 10-1. Port Pin Configurations
DDxn PORTxn PUExn I/O Pull-up Comment
0X0Input No Tri-state (hi-Z)
0X1Input Yes Sources current if pulled low externally
100Output No Output low (sink)
101Output Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active.
Sources current through the internal pull-up
resistor and consumes power constantly
110Output No Output high (source)
111Output Yes Output high (source) and internal pull-up active
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Figure 10-3. Switching Between Input and Output in Break-Before-Make- Mode
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 10-2 on page 55, the PINxn Register bit and the preceding latch constitute a synchronizer. This is
needed to avoid metastability if the physical pin changes value near the edge of the internal clock, bu t it also int ro -
duces a delay. Figure 10 -4 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minim um propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first fallin g edge of the system clock. The latch is closed wh en
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5
on page 58. The out instruction sets the “SYNC LATCH” signal at the positive edge o f the clock. In this case, the
delay tpd through the synchronizer is one system clock period.
out DDRx, r16 nop
0x02 0x01
SYSTEM CLK
INSTRUCTIONS
DDRx
intermediate tri-state cycle
out DDRx, r17
0x55
PORTx
0x01
intermediate tri-state cycle
Px0
Px1
tri-state
tri-statetri-state
0x01
r17
0x02
r16
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
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Figure 10-5. Synchronization when Reading a Software Assigned Pin Value
10.2.5 Digital Input Enable and Sleep Modes
As shown in Fig ure 10-2 on pa ge 55, the digital input signal can be clamped to ground at the input of the schmitt-
trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby
modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close
to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled,
SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in
“Alternate Port Functions” on page 59.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or An y Logic Change on Pin” while the external interrupt is not enabled, the corresp onding
External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these
sleep mode produces the requested logic change.
10.2.6 Unconnected Pins
If some pins are unused, it is recommende d to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle
mode).
The simplest me thod to ensure a d efined level of an unused pin, is to ena ble the internal p ull-up. In this case, th e
pull-up will be disabled during reset. If low pow er consumption during reset is important, it is recommended to us e
an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this
may cause excessive currents if the pin is accidentally configured as an output.
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
tpd
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10.2.7 Program Examples
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from
4 to 5 as input with a pull-up assigned to por t pin 4. The resu lting pin values are read back again, but as previously
discussed, a nop instruction is included to be able to read back the va lue recen tly assigned to some of th e pin s.
Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits
are correctly set, defining bit 2 and 3 as low and redefin ing bits 0 and 1 as strong high drivers.
Note: See “Code Examples” on page 6.
10.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-6 below is shown how
the port pin control signals from the simplified Figure 10-2 on page 55 can be overridden by alternate functions.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PA4)|(1<<PA1)|(1<<PA0)
ldi r17,(1<<DDA3)|(1<<DDA2)|(1<<DDA1)|(1<<DDA0)
out PORTA,r16
out DDRA,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINA
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTA = (1<<PA4)|(1<<PA1)|(1<<PA0);
DDRA = (1<<DDA3)|(1<<DDA2)|(1<<DDA1)|(1<<DDA0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINA;
...
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Figure 10-6. Alternate Port Functions(1)
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP
are common to all ports. All other signals are unique for each pin.
The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microc on-
troller family. Some overriding signals may not be present in all port pins.
clk
RPx
RRx
WRx
RDx
WDx
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
QD
CLR
Q
QD
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA B U S
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx: WRITE PINx
WPx
REx: READ PUEx
WEx: WRITE PUEx
WEx
REx
RESET
Q
QD
CLR
PUExn
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Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-6 are not
shown in the succeeding tables. Th e overriding signals ar e generate d internally in th e modules having the alternate
function.
The following subsections shortly de scri be th e a ltern ate fu nctions for ea ch p ort, an d rela te the overrid ing signa ls to
the alternate function. Refer to the alternate function description for further details.
Table 10-2. Generic Description of Overriding Signals for Alternate Functions
Signal Name Full Name Description
PUOE Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
PUExn = 0b1.
PUOV Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the PUExn Register
bits.
DDOE Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
DDOV Data Direction
Override Value
If DDOE is set, the Ou tput Driver is enabled/disab led when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
PVOE Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
PVOV Port Value
Override Value If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
PTOE Port Toggle
Override Enable If PTOE is set, the PORTxn Register bit is inverted.
DIEOE Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digi tal Input Enable
is determined by MCU state (Normal mode, sleep mode).
DIEOV Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
DI Digital Input
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the schmitt-trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
AIO Analog
Input/Output
This is the Analog Input/Output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
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10.3.1 Alternate Functions of Port A
The Port A pins with alternate function are shown in Ta b l e 10 -3 .
• Port A, Bit 0 – AREF/PCINT0
• AREF: External Analog Refere nce for ADC. Pullup and output driver are disabled on PA0 when the pin is used
as an external re fe re nc e or Inte rn al Voltage Ref er ence wit h ex te rn al capacito r at th e AR EF pi n.
• PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 1 – AIN0/PCINT1
• AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comp arator.
• PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 2 – AIN1/PCINT2
• AIN1: Analog Comp arator Negative Input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comp arator.
• PCINT2: Pin Change Interrupt source 2. The PA2 pin can serve as an external interrupt source for pin change
interrupt 0.
Table 10-3. Port A Pins Alternate Functions
Port Pin Alternate Function
PA0 AREF: External Analog Reference
PCINT0:Pin Change Interrupt 0, Source 0
PA1 AIN0: Analog Comparator, Positive Inpu t
PCINT1:Pin Change Interrupt 0, Source 1
PA2 AIN1: Analog Comparator, Negative Input
PCINT2:Pin Change Interrupt 0, Source 2
PA3
ADC0: ADC Input Channel 0
SNS: Sense Line for Capacitive Measurement
T1: Timer/Counter1 Clock Source
PCINT3:Pin Change Interrupt 0, Source 3
PA4 ADC1: ADC Input Channel 1
T0: Timer/Counter0 Clock Source.
PCINT4:Pin Change Interrupt 0, Source 4
PA5 ADC2: ADC Input Channel 2
OC0B: Ti mer/Counter0 Compare Match B Output
PCINT5:Pin Change Interrupt 0, Source 5
PA6 ADC3: ADC Input Channel 3
OC1B: Timer/Counter1 Compare Match B Output
PCINT6:Pin Change Interrupt 0, Source 6
PA7 ADC4: ADC Input Channel 4
RXD0: UART0 Data Receiver
PCINT7:Pin Change Interrupt 0, Source 7
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• Port A, Bit 3 – ADC0/T1/PCINT3
• ADC0: Analog to Digit al Converter, Channel 0.
• SNS: Sense line for capacitive measurement using QTouch technology. Connected to CS.
• T1: Timer/Counter1 counter source.
• PCINT3: Pin Change Interrupt source 3. The PA3 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 4 – ADC1/T0/PCINT4
• ADC1: Analog to Digit al Converter, Channel 1.
• T0: Timer/Counter0 counter source.
• PCINT4: Pin Change Interrupt source 4. The PA4 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 5 – ADC2/OC0B/PCINT5
• ADC2: Analog to Digit al Converter, Channel 2.
• OC0B: Output Compare Match output: The PA5 pin can serve as an external output for the Timer/Counter0
Compare Match B. The PA5 pin has to be configured as an output (DDA5 set (one)) to serve this function. The
OC0B pin is also the output pin for the PWM mode timer function.
• PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 6 – ADC3/OC1B/PCINT6
• ADC3: Analog to Digit al Converter, Channel 3.
• OC1B, Output Compare Match output: The PA6 pin can serve as an external output for the Timer/Counter1
Compare Match B. The pin has to be configured as an ou tput (DDA6 set (one)) to serve this function. This is
also the output pin for the PWM mode timer function.
• PCINT6: Pin Change Interrupt source 6. The PA6 pin can serve as an external interrupt source for pin change
interrupt 0.
• Port A, Bit 7 – ADC4/RXD0/PCINT7
• ADC4: Analog to Digit al Converter, Channel 4.
• RXD0: UART0 Data Receiver.
• PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt source for pin change
interrupt 0.
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Table 10-4 and Ta ble 10-6 re late the alte rnate fun ctions of Port A to the overriding signals shown in Figure 10-6 on
page 60.
Table 10-4. Overriding Signals for Alternate Functions in PA[7:5]
Signal
Name PA7/ADC4/RXD0/PCINT7 PA6/ADC3/OC1B/PCINT6 PA5/ADC2/OC0B/PCINT5
PUOE RXD0_OE 0 0
PUOV PUEA7 0 0
DDOE RXD0_EN 0 0
DDOV 0 0 0
PVOE 0 OC1B Enable OC0B Enable
PVOV 0 OC1B OC0B
PTOE 0 0 0
DIEOE (PCINT7 • PCIE0) + ADC4D (PCINT6 • PCIE0) + ADC3D (PCINT5 • PCIE) + ADC2D
DIEOV PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0
DI RXD0/PCINT7 Input PCINT6 Input PCINT5 Input
AIO ADC4 Input ADC3 Input ADC2 Input
Table 10-5. Overriding Signals for Alternate Functions in PA[4:2]
Signal
Name PA4/ADC1/T0/PCINT4 PA3/ADC0/SNS/T1/PCINT3 PA2/AIN1/PCINT2
PUOE 0 0 0
PUOV 0 0 0
DDOE 0 0 0
DDOV 0 0 0
PVOE 0 0 0
PVOV 0 0 0
PTOE 0 0 0
DIEOE (PCINT4 • PCIE0) + ADC1D (PCINT3 • PCIE0) + ADC0D (PCINT2 • PCI0) + AIN1D
DIEOV PCINT4 • PCIE0 PCINT3 • PCIE0 PCINT2 • PCIE0
DI T0/PCINT4 input T1/PCINT3 Input PCINT2 Input
AIO ADC1 Input ADC0 or SNS Input Analog Comparator
Negative Input
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10.3.2 Alternate Functions of Port B
The Port B pins with alternate function are shown in Ta b l e 10 -7 .
• Port B, Bit 0 – ADC5/TXD0/PCINT8
• ADC5: Analog to Digit al Converter, Channel 5.
• TXD0: UART0 Data Transmitter.
• PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external interrupt source for pin change
interrupt 1.
• Port B, Bit 1 – ADC6/RXD1/DI/SDA/PCINT9
Table 10-6. Overriding Signals for Alternate Functions in PA[1:0]
Signal
Name PA1/AIN0/PCINT1 PA0/AREF/PCINT0
PUOE 0 RESET • (REFS1 • REFS0 + REFS1 • REFS0)
PUOV 0 0
DDOE 0 RESET • (REFS1 • REFS0 + REFS1 • REFS0)
DDOV 0 0
PVOE 0 RESET • (REFS1 • REFS0 + REFS1 • REFS0)
PVOV 0 0
PTOE 0 0
DIEOE (PCINT1 • PCIE0) + AIN0D (PCINT0 • PCIE0) + AREFD
DIEOV PCINT1 • PCIE0 PCINT0 • PCIE0
DI PCINT1 Input PCINT0 Input
AIO Analog Comparator Positive Input Analog Reference
Table 10-7. Port B Pins Alternate Functions
Port Pin Alternate Function
PB0 ADC5: ADC Input Channel 5
TXD0: UART0 Data Transmitter
PCINT8:Pin Change Interrupt 1, Source 8
PB1
ADC6: ADC Input Channel 6
RXD1: UART1 Data Receiver
DI: USI Data Input (Three Wire Mode)
SDA: USI Data Input (Two Wire Mode)
PCINT9:Pin Change Interrupt 1, Source 9
PB2
ADC7: ADC Input Channel 7
TXD1: UART1 Data Transmitter
DO: USI Data Output (Three Wire Mode)
PCINT10:Pin Change Interrupt 1, Source 10
PB3 ADC8: ADC Input Channel 8
OC1A: Ti mer/Counter1 Compare Match A output
PCINT11:Pin Change Interrupt 1, Source 11
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• ADC6: Analog to Digit al Converter, Channel 6.
• RXD1: UART1 Data Receiver.
• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin
must be configure as an input for DI function .
• SDA: Two-wire mode Serial Interface Data.
• PCINT9: Pin Change Interrupt source 9. The PB1 pin can serve as an external interrupt source for pin change
interrupt 1.
• Port B, Bit 2 – ADC7/TXD1/DO/PCINT10
• ADC7: Analog to Digit al Converter, Channel 7.
• TXD1: UART1 Data Transmitter.
• DO: Data Output in USI Thre e-wire mode. Da ta outpu t (DO) overrid es PORTB2 value and it is driven to the port
when the data direction bit DDB2 is set (one). However the POR TB2 bit still controls the pullup, enabling pullup
if direction is input and PORTB2 is set (one).
• PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin
change interrupt 1.
• Port B, Bit 3 – ADC8/OC1A/PCINT11
• ADC8: Analog to Digit al Converter, Channel 8.
• OC1A, Output Compare Match output: The PB3 pi n can serve as an external outp ut for the Timer/Counter1
Compare Match A. The pin has to be configured as an ou tput (DDB3 set (one)) to serve this function. This is
also the output pin for the PWM mode timer function.
• PCINT11: Pin Chang e Interrupt source 11. The PB3 pin can serve as an external interrupt source for pin change
interrupt 1.
Table 10-8 on page 66 and Table 10-9 on page 67 relate the alternat e func tions of Port B to th e ov erridi ng signa ls
shown in Figure 10-6 on page 60.
Table 10-8. Overriding Signals for Alternate Functions in PB[3:2]
Signal
Name PB3/ADC8/OC1A/PCINT11 PB2/ADC7/TXD1/DO/PCINT10
PUOE 0 TXD1_OE
PUOV 0 0
DDOE 0 TXD1_OE
DDOV 0 0
PVOE OC1A Enable TXD1_OE + USI_THREE_WIRE
PVOV OC1A (TXD1_OE • TXD_PVOV) + (TXD1_OE • DO)
PTOE 0 0
DIEOE PCINT11 • PCIE1 + ADC8D PCINT10 • PCIE1 + ADC7D
DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 + INT0
DI PCINT11 Input PCINT10 Input
AIO ADC8 Input ADC7 Input
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10.3.3 Alternate Functions of Port C
The Port C pins with alternate function are shown in Table 10 -7 .
Table 10-9. Overriding Signals for Alternate Functions in PB[1:0]
Signal
Name PB1/ADC5/RXD1/DI/SDA/PCINT9 PB0/ADC4/TXD0/PCINT8
PUOE RXD1_OE TXD0_OE
PUOV PUEB1 0
DDOE RXD1_EN + USI_TWO_WIRE TXD0_OE
DDOV RXD1_EN) • (SDA + PORTB1) • DDB1
PVOE RXD1_EN) • USI_TWO_WIRE • DDB1 TXD0_OE
PVOV 0 TXD0_PVOV
PTOE 0 0
DIEOE USISIE + (PCINT9 • PCIE1) + ADC6D (PCINT8 • PCIE1) + ADC5D
DIEOV USISIE + (PCINT9 • PCIE1) PCINT8 • PCIE1
DI RXD1/DI/SDA/PCINT9 Input PCINT8 Input
AIO ADC6 Input ADC5 Input
Table 10-10. Port C Pins Alternate Functions
Port Pin Alternate Function
PC0
ADC9: ADC Input Channel 9
XCK0: USART 0 Transfer Clock (Synchronous Mode)
OC0A: Ti mer/Counter0 Compare Match A Output
PCINT12:Pin Change Interrupt 2, Source 12
PC1
ADC10: ADC Input Channel 10
XCK1: USART 1 Transfer Clock (Synchronous Mode)
USCK: USI Clock (Three-Wire Mode)
SCL: USI Clock (Two-Wire Mode)
ICP1: Timer/Counter1 Input Capture Pin
PCINT13:Pin Change Interrupt 2, Source 13
PC2
ADC11: ADC Input Channel 11
INT0: External Interrupt 0 Input
CLKO: System Clock Output
PCINT14:Pin Change Interrupt 2, Source 14
PC3 RESET:Reset Pin
dW: debugWire I/O
PCINT15:Pin Change Interrupt 2, Source 15
PC4 XTAL2: Crystal Oscillator Output
PCINT16:Pin Change Interrupt 2, Source 16
PC5 XTAL1: Crystal Oscillator Input
CLKI: External Clock Input
PCINT17:Pin Change Interrupt 2, Source 17
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• Port C, Bit 0 – ADC9/XCK0/OC0A/PCINT12
• ADC9: Analog to Digit al Converter, Channel 9.
• XCK0: USART0 Transfer Clock used only by Synchronous Transfer mode.
• OC0A: Output Compare Match output: The PC0 pin can serve as an external output for the Timer/Counter0
Compare Match A. The PC0 pin has to be configured as an output (DDC0 set (one)) to serve this function. The
OC0A pin is also the output pin for the PWM mode timer function.
• PCINT12: Pin Change Interrupt sou rce 12. The PC0 pin can serve as an external interrupt source for pin
change interrupt 1.
• Port C, Bit 1 – ADC10/XCK1/USCK/SCL/ICP1/PCIN T13
• ADC10: Analog to Digital Converter, Channel 10.
• XCK1: USART1 Transfer Clock used only by Synchronous Transfer mode.
• USCK: Three-wire mode Universal Serial Interface Clock.
• SCL: Two-wire mode Serial Clock for USI Two-wire mode.
• ICP1: Input Capture Pin. The PC1 pin can act as an Input Capture Pin for Timer/Counter1.
• PCINT13: Pin Change Interrupt sou rce 13. The PC1 pin can serve as an external interrupt source for pin
change interrupt 1.
• Port C, Bit 2 – ADC11/INT0/CLKO/PCINT14
• ADC11: Analog to Digital Converter, Channel 11.
• INT0: External Interrupt Request 0.
• CLKO: System Clock Output. The system clock can be output on the PC2 pin. The system clock will be output if
the CKOUT fuse is programmed, regardless of the PORTC2 and DDC2 settings. It will also be output during
reset.
• PCINT14: Pin Change Interrupt sou rce 14. The PC2 pin can serve as an external interrupt source for pin
change interrupt 1.
• Port C, Bit 3 – RESET/dW/PCINT15
• RESET: External Reset input is active low and enabled by unprogramming (“1”) the RST D ISB L Fuse. Pullup is
activated and output driver and digital input are deactivated when the pin is used as the RESET pin.
• dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the
debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND
(open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between
target a nd emulator.
• PCINT15: Pin Change Interrupt sou rce 15. The PC3 pin can serve as an external interrupt source for pin
change interrupt 1.
• Port C, Bit 4 – XTAL2/PCINT16
• XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources ex cept internal calibrated
oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using
internal calibrated oscillator as a chip clock source, PC4 serves as an ordinary I/O pin.
• PCINT16: Pin Change Interrupt sou rce 16. The PC4 pin can serve as an external interrupt source for pin
change interrupt 1.
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• Port C, Bi t 5 – XTAL1/CLKI/PCINT17
• XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibrated oscillator. When
used as a clock pin, the pin can not be used as an I/O pin. When using internal calibrated oscillator as a chip
clock source, PC5 serves as an ordinary I/O pin.
• CLKI: Clock Input from an external clock source, see “External Clock” on page 26.
• PCINT17: Pin Change Interrupt sou rce 17. The PC5 pin can serve as an external interrupt source for pin
change interrupt 1.
Table 10-4 and Ta ble 10-6 re late the alte rnate fun ctions of Port A to the overriding signals shown in Figure 10-6 on
page 60.
Notes: 1. EXT_CLOCK = external clock is selected as system clock.
2. EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock.
3. RSTDISBL is 1 when the Fuse is “0” (Programmed).
4. DebugWIRE is enabled when DWEN Fuse is programmed and Lock bits are unprogrammed.
Table 10-11. Overriding Signals for Alternate Functions in PC[5:3]
Signal
Name PC5/XTAL1/CLKI/PCINT17 PC4/XTAL2/ PCINT16 PC3/RESET/dW/ PCINT15
PUOE EXT_CLOCK (1) +
EXT_OSC (2) EXT_OSC (2) RSTDISBL(3) +
DEBUGWIRE_ENABLE (4)
PUOV 0 0 1
DDOE EXT_CLOCK (1) +
EXT_OSC (2) EXT_OSC (2) RSTDISBL(3) +
DEBUGWIRE_ENABLE (4)
DDOV 0 0 DEBUGWIRE_ENABLE (4) •
debugWire Transmit
PVOE EXT_CLOCK (1) +
EXT_OSC (2) EXT_OSC (2) RSTDISBL(3) +
DEBUGWIRE_ENABLE (4)
PVOV 0 0 0
PTOE 0 0 0
DIEOE EXT_CLOCK (1) +
EXT_OSC (2) + (PCINT17 •
PCIE2)
EXT_OSC (2) + PCINT16 •
PCIE2
RSTDISBL(3) +
DEBUGWIRE_ENABLE (4) +
PCINT15 • PCIE2
DIEOV
(EXT_CLOCK(1) •
PWR_DOWN) +
(EXT_CLOCK (1) •
EXT_CLOCK (1) • PCINT17 •
PCIE2)
EXT_OSC (2) • PCINT16 •
PCIE2
DEBUGWIRE_ENABLE (4) +
(RSTDISBL(3) • PCINT15 •
PCIE2)
DI CLOCK/PCINT17 Input PCINT16 Input dW/PCINT15 Input
AIO XTAL1 XTAL2
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Table 10-12. Overriding Signals for Alternate Functions in PC[2:0]
Signal
Name PC2/ADC11/INT0/CLKO/
PCINT14 PC1/ADC10/XCK1/USCK/
SCL/ICP1/PCINT13 PC0/ADC9/XCK0/
OC0A/PCINT12
PUOE CKOUT_IO USI_TWO_WIRE 0
PUOV 0 0 0
DDOE CKOUT_IO USI_TWO_WIRE 0
DDOV 1 (USI_SCL_HOLD +
PORTC1) • DDC1 0
PVOE CKOUT_IO XCKO1_PVOE +
USI_TWO_WIRE • DDC1 XCKO0_PVOE + OC0A
Enable
PVOV CKOUT_IO • System Clock XCKO1_PVOV XCKO0_PVOV + OC0A
PTOE 0 USI_PTOE 0
DIEOE INT0 + (PCINT14 • PCIE2) +
ADC11D
XCK1 Input Enable +
USISIE + (PCINT13 •
PCIE2) + ADC10D
XCK0 Input Enable +
(PCINT12 • PCIE2) +
ADC9D
DIEOV INT0 + (PCINT14 • PCIE2) USISIE + (PCINT13 •
PCIE2) PCINT12 • PCIE2
DI INT0/PCINT14 input XCK1/USCK/SCL/ICP1/
PCINT13 Input XCK0/PCINT12 Input
AIO ADC11 Input ADC10 Input ADC9 Input
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10.4 Register Description
10.4.1 PORTCR – Port Control Register
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – BBMC: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port C. The intermediate tri-state cycle
is then inserted when writing DDRCn to make an output. For further information, see “Break-Before-Make Switch-
ing” on page 56.
• Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The intermediate tri-state cycle
is then inserted when writing DDRBn to make an output. For further information, see “Break-Before-Make Switch-
ing” on page 56.
• Bit 0 – BBMA: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port A. The intermediate tri-state cycle
is then inserted when writing DDRAn to make an output. For further information, see “Break-Before-Make Switch-
ing” on page 56.
10.4.2 PUEA – Port A Pull-up Enable Control Register
10.4.3 PORTA – Port A Data Register
10.4.4 DDRA – Port A Data Direct ion Register
10.4.5 PINA – Port A Input Pins
Bit 7 6 5 4 3 2 1 0
0x13 (0x33) – – – – – BBMC BBMB BBMA PORTCR
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x12 (0x32) PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 PUEA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x11 (0x31) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x10 (0x30) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0F (0x2F) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
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10.4.6 PUEB – Port B Pull-up Enable Control Register
10.4.7 PORTB – Port B Data Register
10.4.8 DDRB – Port B Data Direct ion Register
10.4.9 PINB – Port B Input Pins
10.4.10 PUEC – Port C Pull-up Enable Control Register
10.4.11 PORTC – Port C Data Register
10.4.12 DDRC – Port C Data Direction Register
10.4.13 PINC – Port C Input Pins
Bit 76543210
0x0E (0x2E) – – – – PUEB3 PUEB2 PUEB1 PUEB0 PUEB
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0D (0x2D) – – – – PORTB3 PORTB2 PORTB1 PORTB0 PORTB
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0C (0x2C) – – – – DDB3 DDB2 DDB1 DDB0 DDRB
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0B (0x2B) – – – – PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 N/A N/A N/A N/A
Bit 76543210
0x0A (0x2A) – – PUEC5 PUEC4 PUEC3 PUEC2 PUEC1 PUEC0 PUEC
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x09 (0x29) – – PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x08 (0x28) – – DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x07 (0x27) – – PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 N/A N/A N/A N/A N/A N/A
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11. 8-bit Timer/Counter0 with PWM
11.1 Features
•Two Independent Output Compare Units
•Double Buffered Output Compare Registers
•Clear Timer on Compare Match (Auto Reload)
•Glitch Free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Gene rator
•Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
11.2 Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units,
and with PWM support. It allows accurate program execution timing (event management) an d wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 11-1 on page 73. For the actual placement
of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown
in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 84.
Figure 11-1. 8-bit Timer/Counter Block Diagram
Clock Select
Timer/Counter
DATA B U S
OCRnA
OCRnB
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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11.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in Figure 11-1) signals are all visible in the Timer Interrupt Flag Register (TIFR). All
interrupts are individually masked with the Timer Interrupt Ma sk Re gister (T IMSK). TIFR an d TIMS K are n ot shown
in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increme nt (or decrement)
its value. The Timer /Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Ge nerator to gen erate a PWM or vari able fre-
quency output on the Output Compare pins (OC0 A and OC0B). See “Output Co mpare Uni t” on page 75 for details.
The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an
Output Compare interrupt request.
11.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compa re
Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 11-1 are also used extensively throughout the documen t.
11.3 Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS0[2:0]) bits located in the Time r/Coun ter Co ntrol Reg-
ister (TCCR0B). For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 117.
11.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-2 on page 75
shows a block diagram of the counter and its surroundings.
Table 11-1. Definitions
Constant Description
BOTTOM The counter reaches BOTTOM when it becomes 0x00
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register . The assignment depends on the mode of operation
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Figure 11-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T0 in the following.
top Signalize that TCNT0 has reache d maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of ope ration used, the counter is cl eared, incremen ted, or decremen ted at each time r clock
(clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can
be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A) and the WGM02 bit loc a te d in th e Time r/Coun te r Control Register B (TCCR0B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Out-
put Compare output OC0A. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 78.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM0[1:0]
bits. TOV0 can be used for generating a CPU interrupt.
11.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B).
Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Com-
pare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output
Compare Flag generates an Ou tput Compare interrupt. The Output Comp are Flag is automatically cleared when
the interrupt is executed. Alternatively, the flag can be cleared by software by wr iting a logical one to its I/O bit loca-
tion. The Wave form Ge nerator uses the match sig nal to generate an output acco rding to op erating mod e set by the
WGM0[2:0] b its and Compar e Outp ut mo de (CO M0x 1:0) bits. Th e max and botto m sign als are used by the Wa ve-
form Generator for handling the special cases of the extreme values in some modes of operation. See “Modes of
Operation” on page 78.
Figure 11-3 on page 76 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clkTn
bottom
direction
clear
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Figure 11-3. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buff-
ering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-leng th, non-symmetrical PWM pulses, thereby making the
output glitch-free.
The OCR0x Register access may seem complex, but this is not case. Whe n the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly.
11.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comp arator can be f orced by writing a one to
the Force Output Compare (0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer,
but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x[1:0] bits settings define
whether the OC 0x pin is set, cle ar ed or to gg led ).
11.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0
without triggering an interrupt when the Timer/Counter clock is enabled.
11.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Com par e Match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is down-counting.
The setup of the OC0x should be performe d before setting the Da ta Direction Regist er for the port pin to outpu t.
The easiest way of setting the OC0x value is to use the Force Output Com pare (0x) strobe bits in Normal mode.
The OC0x Registers keep their values even when changing between Waveform Generation modes.
OCFn x (Int.R eq.)
= (8-bit C omparator )
OCRnx
OCnx
DA TA B US
TCNTn
WGMn[1:0]
Waveform Generator
top
FOCn
COMnX[1:0]
bottom
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Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the
COM0x[1:0] bits will take effect immediately.
11.6 Compare Match Output Unit
The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0]
bits for defining the Output Com pare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control
the OC0x pin output source. Figure 11-4 on page 77 shows a simplified schematic of the logic affected by the
COM0x[1:0] bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of
the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits ar e shown. When
referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset
occur, the OC0x Re gis ter is reset to “0”.
Figure 11-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either
of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be
set as output before the OC0x value is visible on the pin. The port override fun ction is independent of the Wave-
form Generation mode.
The design of th e Output Compare pin logic allows initialization o f the OC0x state before the output is ena bled.
Note that some COM0x[1:0] bit settings are reserved for certain modes of operation, see “Register Description” on
page 84
11.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed
on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 84.
For fast PWM mode, refer to Table 11-3 on page 84, and for phase correct PWM refer to Table 11-4 on page 84.
PORT
DDR
DQ
DQ
OCn
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA B U S
FOCn
clkI/O
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A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the 0x strobe bits.
11.7 Modes of Operation
The mode of ope ration, i.e., the behavior of the Timer/Counter an d the Output Compare pin s, is defined by the
combination of the Waveform Generation mode (W GM0[2:0]) and Compare Output mode (COM0x[1:0]) bits. The
Compare Output mode bits do not affect the coun ting sequence, while the Wavefo rm Generation mode bits do.
The COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or
toggled at a Compare Match (See “Modes of Operation” on page 78).
For detailed timing information refer to Figure 11-8 on page 82, Figure 11-9 on page 82, Figure 11-10 on page 83
and Figure 11-11 on pa ge 83 in “Timer/Counter Timing Diagrams” on page 82.
11.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM0[2:0] = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
11.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM 0[2:0] = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hen ce also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of countin g external events.
The timing diagram for the CTC mode is shown in Figure 11-5 on page 78. The counter value (TCNT0) increases
until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleare d.
Figure 11-5. CTC Mode, Timing Diagram
An interrupt can be g en erated e ach time the coun te r valu e r each es the TOP value b y using the OCF0A Fl ag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
TCNTn
OCn
(Toggle)
OC nx Interrupt F lag S et
1 4
Period 2 3
( CO Mnx [1 : 0 ] = 1)
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care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) an d wrap around starting at 0x00 before the Compare Match can occur.
For generating a wavefo rm output in CTC mode, the OC0A output can be set to toggle its logical level on each
Compare Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1). The OC0A value will
not be visible on the port pin unless the data direction for t he pin is set to outp ut. The waveform g enerated will ha ve
a maximum frequency of 0 = fclk_I/O/2 whe n OCR0A is se t to zero ( 0x00). Th e wavefor m frequ en cy is defined by the
following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
11.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM wave-
form generation option. The fast PWM differs from the other PWM option by its single- slope ope ration. Th e counter
counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and
OCR0A when WGM0[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on
the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the
output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating fre-
quency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope
operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows p hysically small sized external components (coils, capacitors) , and therefore
reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-6 on
page 80. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non -inverted and inverted PWM outputs. T he small horizontal line marks on the TCNT0
slopes represent Compare Matches between OCR0x and TCNT0.
fOCnx fclk_I/O
2N1OCRnx+
--------------------------------------------------=
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Figure 11-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is se t e ach time th e cou nter re aches TOP. If the in terr up t is enab led , the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one allowes the OC0A pin to toggle on Compare Matches
if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-3 on page 84). The actual
OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-
form is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0,
and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special case s when generating a PWM wavefor m output in
the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A[1:0] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle
its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generate d will have a maximum fre-
quency of 0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except
the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
11.7.4 Pha se Correct PWM Mode
The phase correct PWM mode (WGM 0[2:0] = 1 or 5) provides a high reso lution phase corr ect PWM waveform gen-
eration option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly
from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and
OCR0A when WGM0[2:0] = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on
the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-
TCNTn
OC R nx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCn
OCn
( CO Mnx [1 : 0 ] = 2)
( CO Mnx [1 : 0 ] = 3)
OC R nx Interrupt F lag S et
4 5 6 7
fOCnxPWM fclk_I/O
N256
------------------=
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counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maxi-
mum operation freq uency than single slope operation. Howe ver, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 11-7 on page 81. The TCNT0 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverte d PWM outputs. The sma ll horizontal line marks on th e TCNT0 slopes represe nt Compare Matche s
between OCR0x and TCNT0.
Figure 11-7. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase corr ect PWM mode, the com pare unit allows gen eration of PWM waveform s on the OC0x pins. Se tting
the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to togg le on Compare Matches if
the WGM02 bit is set. This option is not available for the OC0B pin (See Tab le 11-4 on page 84). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by cleari ng (or setting) the OC0x Register at the Comp are Match betwee n OCR0x and TCNT0 when the
counter increments, and settin g (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024 ).
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Update
fOCnxPCPWM fclk_I/O
N510
------------------=
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The extrem e value s f or th e O CR0A Register re pr esent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 11-7 on pa ge 81 OCn has a tr ansition from hi gh to low even thou gh there is
no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. T here are two cases
that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in Figure 11-7 on page 81. When the OCR0A value is MAX the OCn
pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM
the OCn value at MAX must correspond to the result of an up-counting Compare Match.
• The timer star ts counting from a value higher than the one in OCR0A, and for that reason misse s the Compare
Match and hence the OCn change that would have happened on the way up.
11.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal
in the follow ing figures. Th e figures inclu de information on when Interrupt Flags are set. Figure 11-8 on page 82
contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX
value in all modes other than phase cor rect PWM mode.
Figure 11-8. Timer/Counte r T imin g Dia gr am, no Pre sca ling
Figure 11-9 on page 82 shows the same timing data, but with the prescaler enabled.
Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 11-10 on page 83 shows the setting of OCF0B in all modes and OCF 0A in all mode s except CTC mo de and
PWM mode, where OCR0A is TOP.
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
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Figure 11-10. Timer/Coun ter T i ming Dia gr am , Set tin g of OCF 0x, with Pre sca le r (fclk_I/O/8)
Figure 11-11 on page 83 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM
mode where OCR0A is TOP.
Figure 11-11. Timer/Counte r T imin g Dia gr am , Cle ar Tim er on Comp ar e M atc h mo d e, with Pre sca ler (f clk_I/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clkI/O/8)
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11.9 Register Description
11.9.1 TCCR0A – Ti mer/Coun ter Control Register A
• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are set, the
OC0A output overrides the norma l port fu nctionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0 A[1:0] bits depends on the W GM0[2:0] bit setting.
Table 11-2 shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode
(non-PWM).
Table 11-3 shows COM0A[1:0] bit functionality when WGM0[1:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 79 for more details.
Table 11-4 shows COM0A[1 :0] bit functionality when WGM0[2:0] bits are set to phase correct PWM mode.
Bit 7 6 5 4 3 2 1 0
0x1B (0x3B) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 11-2. Compare Output Mode, non-PWM Mode
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Togg le OC0A on Compare Match
1 0 Clear OC0A on Compare Match
1 1 Set OC0A on Compare Match
Table 11-3. Compare Output Mode, Fast PWM Mode (1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected
01
WGM02 = 0: Normal Port Op eration, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
10
Clear OC0A on Compare Match
Set OC0A at BOTTOM (non-inverting mode)
11
Set OC0A on Compare Match
Clear OC0A at BOTTOM (inverting mode)
Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
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Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 80 for more details.
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0] bits are set, the
OC0B output overrides the norma l port fu nctionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0 B[1:0] bits depends on the W GM0[2:0] bit setting.
Table 11-5 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode
(non-PWM).
Table 11-6 shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 79 for more details.
01
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
10
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
11
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Table 11-5. Compare Output Mode, non-PWM Mode
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on Compare Match
1 0 Clear OC0B on Compare Match
1 1 Set OC0B on Compare Match
Table 11-6. Compare Output Mode, Fast PWM Mode (1)
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
01Reserved
10
Clear OC0B on Compare Match, set OC0B at BOTTOM
(non-inverting mode)
11
Set OC0B on Compare Match, clear OC0B at BOTTOM
(inverting mode)
Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1 COM0A0 Description
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Table 11-7 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 80 for more details.
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 11-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation”
on page 78).
Note: 1. MAX = 0xFF
BOTTOM = 0x00
11.9.2 TCCR0B – Ti mer/Coun ter Control Register B
Table 11-7. Compare Output Mode, Phase Correct PWM Mode(1)
COM0B1 COM0B0 Description
0 0 Normal port operation, OC0B disconnected.
01Reserved
10
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
11
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 11-8. Waveform Generation Mode Bit Description
Mode WGM02 WGM01 WGM00 Timer/Counter
Mode of Operation TOP Update of
OCRx at TOV Flag
Set on(1)
0 0 0 0 Normal 0xFF Immediate MAX
1001
PWM, Phase
Correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF BOTTOM MAX
4100Reserved –– –
5101
PWM, Phase
Correct OCRA TOP BOTTOM
6110Reserved –– –
7111Fast PWM OCRABOTTOMTOP
Bit 7 6 5 4 3 2 1 0
0x1A (0x3A) FOC0AFOC0B – – WGM02CS02CS01CS00TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode . When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0A output is changed according to its COM0A[1:0] bits setting. Note that
the FOC0A bit is implemented as a strobe . Therefore it is the valu e present i n the COM0A[1:0] bits that deter mines
the effect of the fo rce d com pare .
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode . When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that
the FOC0B bit is implemented as a strobe . Therefore it is the valu e present i n the COM0B[1:0] bits that deter mines
the effect of the fo rce d com pare .
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny1634 and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 84.
• Bits 2:0 – CS0[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Time r/Counter.
If external pin modes are used for the Timer/Counter0, transitio ns on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
Table 11-9. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (T imer/Counter stopped)
001clk
I/O/(No prescaling)
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (From prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on fa lling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
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11.9.3 TCNT0 – Timer/Count e r Re gi st er
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writin g t o t he T CNT 0 Re gister blocks ( rem ov es) the Compare Match on the following timer clock. Modify-
ing the counter (TC NT0) while the counter is running, in troduces a risk of missing a Compare Matc h between
TCNT0 and the OCR0x Registers.
11.9.4 OCR0A – Output Compare Register A
The Output Com pare Register A contains an 8-bit v alue that is continuously compared with the counter value
(TCNT0). A match can be used to genera te an Outp ut Compare inter ru pt, or to gene rate a waveform outpu t on the
OC0A pin.
11.9.5 OCR0B – Output Compare Register B
The Output Com pare Register B contains an 8-bit v alue that is continuously compared with the counter value
(TCNT0). A match can be used to genera te an Outp ut Compare inter ru pt, or to gene rate a waveform outpu t on the
OC0B pin.
11.9.6 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer /Counter Compare
Match B interru pt is enabled. The co rresponding in terrupt is executed if a Compare Match in Timer/Counter occurs,
i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Regis ter is set, th e Time r/Co unter0 Overf low inter -
rupt is enabled. The corresponding in terrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR.
• Bit 0 – OCIE0A: Timer/Counter0 Output Compar e Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I- bit in the Status Register is set, the Timer/Coun ter0 Compare
Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0
occurs, i.e., whe n the OCF0A bit is set in the Timer/Counter0 Interr upt Flag Register – TIFR.
Bit 76543210
0x19 (0x39) TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x18 (0x38) OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x17 (0x37) OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x3A (0x5A) TOIE1 OCIE1A OCIE1B –ICIE1 OCIE0B TOIE0 OCIE0A TIMSK
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value00000000
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11.9.7 TIFR – Timer/Counter0 Interrupt Flag Register
• Bit 2 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer /Count er and the data in OCR0B – Output
Compare Register0 B. OCF0B is clear ed by ha rdware when executing the correspon ding inte rrupt hand ling ve ctor.
Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt En able ), and OCF0 B are se t, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set whe n an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
correspon ding interr upt handlin g vector. Alte rnative ly, TOV0 is clea red by writin g a logic one to the flag. When the
SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer /Counter0 Overflow
interrupt is executed.
The setting of this fla g is dep endent of the WGM0[2 :0] bit setting . See Table 11-8 on page 86 and “Waveform Gen-
eration Mode Bit Description” on page 86.
• Bit 0 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Out-
put Compare Register0. OCF0A is cleared by hardw are when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare Ma tch Interrupt Enable), and OCF0A ar e set, the Timer/Counter0 Compa re Match Inter-
rupt is executed.
Bit 76543210
0x39 (0x59) TOV1 OCF1B OCF1A –ICF1 OCF0B TOV0 OCF0A TIFR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value00000000
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12. 16-bit Timer/Counter1
12.1 Features
•True 16-bit Design (i.e., Allows 16-bit PWM)
•Two independent Output Compare Units
•Double Buffered Output Compare Registers
•One Input Capture Unit
•Input Capture Noise Canceler
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Variable PWM Period
•Frequency Gene rator
•External Event Counter
•Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
12.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement.
A simplified block d iagram o f the 16-bit T imer/Counter is sh own in F igur e 12-1 on p age 9 0. For actual placemen t of
I/O pins, refer to “Pinout of ATtiny1634” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins,
are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on
page 111.
Figure 12-1. 16-bit Timer/Counter Block Diagram
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clkTn
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Most register and bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number, an d a lower case “x” replaces the Output Compare unit channel. However, when using the
register or bit defines in a program , the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1
counter value and so on.
12.2.1 Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section “Accessing 16-bit Registers” on page 107. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in
the figure) signals are all visible in the Timer Interrupt F lag Register (TIFR). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increme nt (or decrement)
its value. The Timer /Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT1).
The double buffered Output Compar e Registers (OCR1A/B) ar e compared with the Timer/Counter value at all time.
The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency out-
put on the Output Compare p in (OC1A/B). See “Output Com pare Uni ts” on pag e 95. The compare match event will
also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Comp are interrupt reque st.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 181).
The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise
spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM
mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.
12.2.2 Definitions
The following definitions are used extensively throughout the section:
12.2.3 Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of 16-bit AVR Timer/Counter.
This 16-bit Timer/Counter is fully compatible with the earlier version regarding:
• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers.
Table 12-1. Definitions
Constant Description
BOTTOM The counter reaches BOTTOM when it becomes 0x00
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned a fixed value or the value stored in a
register. The assignment depends on the mode of operation. See Table 12-5 on page
112
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• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
• Interrupt Vectors.
The following control bits have been renamed, but retained the same functionality and register locations:
• PWM10 is changed to WGM10.
• PWM11 is changed to WGM11.
• CTC1 is changed to WGM12.
The following bits have been added to the 16-bit Timer/Counter Control Registers:
• 1A and 1B are added to TCCR1A.
• WGM13 is added to TCCR1B.
The 16-bit Timer/Counter has improvements that will affect backward compatibility in some special cases.
12.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS1[2:0]) bits located in the Timer/Counter control Reg-
ister B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter Prescaler ” on page 117.
12.4 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12- 2 shows
a block diagram of the counter and its surroundings.
Figure 12-2. Counter Unit Block Diagram
Description of internal signals used in Figure 12-2:
Count Increment or decrement TCNT1 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT1 (set all bits to zero).
clkT1Timer/Counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
TEMP (8-bit)
DATA B US
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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The 16-bit coun ter is mapped into tw o 8-bit I/O memo ry locations: Counter High (TCNT1H) containing the upper
eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value
when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit coun ter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that
will give unpredictable results. The special cases are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS1[2:0]). When no clock source is selected (CS1[2:0] = 0) the timer is stopped. However, the TCNT1 value can
be accessed by the CPU, independent of whether clkT1 is present o r not. A CPU writ e ov errides (ha s pr iority over )
all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM1[3:0]) located
in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between
how the counter behaves (c ounts) and how waveforms are generated on the Output Compare outputs OC1x. For
more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page
98.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM1[3:0]
bits. TOV1 can be used for generating a CPU interrupt.
12.5 Input Capture Unit
The Timer/Count er incorporates an Input Capture unit tha t can capture external events and give them a time-
stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via
the ICP1 pin or alternativ ely, via the analog-comparato r unit. The time-stam ps can then be used to calculate fr e-
quency, duty-cycle, and other featur es of the signal applie d. Alterna ti vely the time-stamps can be used for creating
a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-3 on pa ge 94. The elements of the
block diagram that are not dir ectly a part of the In put Capture un it are gr ay sh aded. The small “n” in register an d bit
names indicates the Timer/Counter number.
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Figure 12-3. Input Capture Unit Block Dia gr am
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Inp ut Capture Register
(ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is cop ied into ICR1
Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture inter rupt. The ICF1 flag is auto-
matically cleared when th e interrupt is executed . Alternative ly the ICF1 flag can be clea re d by software b y writing a
logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and
then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register
(TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for
defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM1[3:0]) bits must be set
before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be
written to the ICR1H I/O location before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-b it Registers” on page 107.
12.5.1 Input Capture Trigger Source
The main trigg er so urce for the In put Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively
use the Analog Compar ator ou tput as trig ge r source fo r the Inpu t Ca pture u nit. The A nalo g Compar ator is sele cted
as trigger source by setting the Analo g Comparator Input Ca pture (ACIC) bit in the Analog Comparator Control and
Status Register (ACSRA). Be aware that chan ging trigger source can trigg er a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the T1 pin (Figu re 13-2 on page 11 8). The edge detector is also identical. However, when the
noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four
ICFn (Int.Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA B U S (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACIC* ICNC ICES
ACO*
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system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the
Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
12.5.2 Noise Canceler
The noise canceler uses a simp le digital filtering technique to im prove noise immunity. Consec utive samples are
monitored in a pipeline four units deep. The sign al going to the edge detecter is allowed to change only when all
four samples ar e eq u al.
The noise canceler is enable d by setting the Input Capture Nois e Canceler (ICNC1) bit in Timer/Counter Co ntrol
Register B (TCCR1B). When enabled, the noise canceler introduces an additional delay of four system clock
cycles to a change applied to the input and before ICR1 is updated.
The noise canceler uses the system clock directly and is therefore not affected by the prescaler.
12.5.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time bet ween two events is critical. If the processor has not read the captured valu e in the
ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the m aximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a
change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt ha ndler is
used).
12.6 Output Compare Units
The 16-bit comparator con tinuously co mpares TCNT1 with the Output Comp are Register ( OCR1x). If TCNT equals
OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock
cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Co mpa re interr up t. The OCF1 x flag
is automatically cleared when the inter rupt is executed . Alternatively the OCF1x flag can be cleared by softwa re by
writing a logical one to its I/O bit location. The Waveform Generator uses the ma tch signal to generate an output
according to operating mode set by the Waveform Generation mode (WGM1[3:0]) bits and Compare Output mode
(COM1x[1:0]) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of Operation” on page 98).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolu-
tion). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the
Waveform Generator.
Figure 12-4 on page 96 shows a block diagra m of the Output C ompare unit. The small “n” in the regist er and bit
names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
The element s of th e blo ck dia gr a m th at ar e no t dir ec tly a pa rt of the Outp u t Com p ar e un it ar e gr ay sh ad e d.
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Figure 12-4. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. Whe n the double buffering is enabled, the
CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x
directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is
not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Registe r since the
compare of all 16 bits is done continuously. The high byte (OCR1 xH) has to be written first. When the high byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x
buffer or OCR1x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 107.
12.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer,
but the OC1x pin will be updated as if a real compare match had occurred (the COM1x[1:0] bits settings define
whether the OC 1x pin is set, cle ar ed or to gg led ).
OCFnx (Int.Req.)
=
(16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA B US
(8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
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12.6.2 Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without trigger-
ing an interrupt when the Timer/Counter clock is enabled.
12.6.3 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether
the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will
be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performe d before setting the Da ta Direction Regist er for the port pin to outpu t.
The easiest way of setting the OC1x value is to use the Force Output Com pare (1x) strobe bits in Normal mode.
The OC1x Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COM1x[1:0] bits are not double buffered together with the compare value. Changing the
COM1x[1:0] bits will take effect immediately.
12.7 Compare Match Output Unit
The Compare Output Mode (COM1x[1:0]) bits have two functions. The Waveform Generator uses the COM1x[1:0]
bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x[1:0] bits con-
trol the OC1x pin output source. Figure 12-5 on page 98 shows a simplified schematic of the logic affected by the
COM1x[1:0] bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of
the general I/O port control registers (DDR and PORT) that are affected by the COM1x[1:0] bits are s hown. When
referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset
occur, the OC1x Re gis ter is reset to “0”.
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Figure 12-5. Compare Match Output Unit, Schematic (non-PWM Mode)
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either
of the COM1x[1:0] bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be
set as output before the OC1x value is visibl e on th e pin. T he p ort o verr ide fu nction is gener ally in dep enden t o f the
Waveform Generation mode, but there are some exceptions. See Table 12-2 on page 111, Table 12-3 on page
111 and Table 12-4 on page 112 for details.
The design of th e Output Compare pin logic allows initialization o f the OC1x state before the output is ena bled.
Note that some COM1x[1:0] bit settin gs ar e reser ved for ce rtain modes of o peratio n. See “Register Description” on
page 111
The COM1x[1:0] bits have no effect on the Input Captur e un it.
12.7.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM1x[1 :0] bits differently in normal, CTC, and PWM modes. For all modes,
setting the COM1x[1:0] = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed
on the next compare match. For compare output actions in the non-PWM modes re fer to Table 12-2 on page 111.
For fast PWM mode refer to Ta ble 12-3 on page 111, and for phase cor rect and ph ase and freque ncy corr ect PWM
refer to Table 12-4 on page 112.
A change of the COM1x[1:0] bits state will have effect at the first compare match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the 1x strobe bits.
12.8 Modes of Operation
The mode of ope ration, i.e., the behavior of the Timer/Counter an d the Output Compare pin s, is defined by the
combination of the Waveform Generation mode (W GM1[3:0]) and Compare Output mode (COM1x[1:0]) bits. The
Compare Output mode bits do not affect the coun ting sequence, while the Wavefo rm Generation mode bits do.
The COM1x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BU S
FOCnx
clkI/O
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inverted PWM). For non-PWM modes the COM1x[1:0] bits control whether the output should be set, cleared or tog-
gle at a compare match (“Compare Match Output Unit” on page 97)
For detailed timing informa tio n re fe r to “Timer/Counter Timing Diagrams” on page 106.
12.8.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM1[3:0] = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/ Coun-
ter Overflow Flag (TOV1) will be set in the same timer c lock cy cle as the TCN T1 becomes zero. The TOV1 flag in
this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exce ed the re so lution of the counter. If the interval between even ts are too long , the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
12.8.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Com par e or CTC m ode ( WGM1[3 :0] = 4 or 12) , the OCR1A or ICR1 Register are used to manip-
ulate the counter r esolutio n. In CTC mo d e the co unter is clear ed to zero w hen the cou nter value (T CNT1 ) ma tches
either the OCR1A (WGM1[3:0] = 4) or the ICR1 (WGM1[3:0] = 12). The OCR1A or ICR1 define the top value for
the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the op e ra tio n of co un tin g ex te rn al ev en ts.
The timing diagram for the CTC mode is shown in Figure 12-6 on page 99. The counter value (TCNT1) increases
until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 12-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or
ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt han dler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new valu e written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4
Period
2 3
(COMnA[1:0] = 1)
100
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not desirable. An alternative will then be to use the fast PWM mode us ing OCR1A for defining TOP (WGM1[3:0] =
15) since the OCR1A then will be double buffered.
For generating a wavefo rm output in CTC mode, the OC1A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM1A[1:0] = 1). The OC1A value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform
generated will have a maximum frequency of 1A = fclk_I/O/2 when OCR1A is set to ze ro (0 x0 00 0). T he wa ve form fr e-
quency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
12.8.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM1[3:0] = 5, 6, 7, 14, or 15) provides a high frequency
PWM waveform generation option. Th e fast PWM differs from the other PWM options by its single-slope operation.
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-invertin g Compare Output mode,
the Output Compare (O C1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM.
In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-
slope operation, the operating frequency of the fast PWM mode can be twice as high as the p hase correct and
phase and frequency correct PWM mo des that use dual- slope opera tion. This high fr equen cy make s the fa st PWM
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolu tion for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The mini-
mum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or
OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM 1[3:0] = 5, 6, or 7), the value in ICR1 (WGM1[3:0] = 14), or the value in OCR1A
(WGM1[3:0] = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 12-7 on page 101. The fig ure shows fast PWM mode when OCR1A or ICR1 is used
to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram inclu des non-inverted and invert ed PWM outputs. The small horizon tal line marks on the
TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when
a compare match occurs.
fOCnA fclk_I/O
2 N 1 OCRnA+
---------------------------------------------------=
RFPWM TOP 1+log 2log
-----------------------------------=
101
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Figure 12-7. Fast PWM Mode, Timing Diagram
The Timer/Counte r Over flow Flag (TOV1) is set each time the counter re ache s TOP. In addition the OC1A or ICF1
flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP
value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com-
pare values.
When chang in g th e T O P v alu e th e pr og ra m m us t e n sur e th at the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare R egisters, a compare match will
never occur between the TCNT1 and the OCR1 x. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1
Register is not dou ble bu ffered. This means tha t if ICR1 is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of
TCNT1. The result will then be that the co unter will miss the compare match at the TOP value. The counter will
then have to cou n t to th e MA X valu e (0 xF F FF) and wra p ar ou n d sta rt ing at 0x0000 befo re the c omp ar e ma tch can
occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written
anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The
OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle
the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the
TOV1 flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM1x[1:0] to three (see Table 12-3 on page 111). The actual OC1x value will only be visible on the port pin if
the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the
OC1x Register at th e tim er clock cycle th e counter is cleared (changes from TOP to BOTTOM).
TCNTn
OC R nx/T OP Update and
TOVn Interrupt Flag Set and
OC nA Interrupt F lag S et
or IC F n Interrupt F lag Set
(Interrupt on T O P )
1 7
Period
2 3 4 5 6 8
OCnx
OCnx
( CO Mnx [1 : 0 ] = 2)
( CO Mnx [1 : 0 ] = 3)
102
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The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM wave form output in
the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending
on the polarity of the ou tp ut set by th e CO M1 x[ 1:0 ] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle
its logical level on each compare match (COM1A[1:0] = 1). The waveform generated will have a maximum fre-
quency of 1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is simila r to the OC1A toggle in CTC
mode, except the double buffer feature of the Output Comp are unit is enabled in the fast PWM mode.
12.8.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM1[3:0] = 1, 2, 3, 10, or 11) provides
a high resolution phase cor rect PWM waveform generation option . The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dua l-slope operation. The counter co unts repeatedly from BOT-
TOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is
16-bit (ICR1 or OCR1 A se t to MAX). The PWM r esolu ti on in bits ca n be ca lcu lated by using the follo win g equa tio n:
In phase corr ect PWM mo de the counter is in cr emented u nt il the counter value m atches eith er one of th e fixed val-
ues 0x00FF, 0x01FF, or 0x03FF (WGM1[3:0] = 1, 2, or 3), the value in ICR1 (WGM1[3:0] = 10), or the value in
OCR1A (WGM1[3:0] = 11). The counter has then reached the TOP and changes the count direction. The TCNT1
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figu re 12-8 on page 103 . The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non -inverted and inverted PWM outputs. The sma ll horizontal line marks on the TCNT1 slopes
represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare
match occurs.
fOCnxPWM fclk_I/O
N1TOP+
-----------------------------------=
RPCPWM TOP 1+log 2log
-----------------------------------=
103
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Figure 12-8. Phase Correct PWM Mode , Tim in g Dia gr am
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as
the OCR1x Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to gener-
ate an interrupt each time the counter reaches the TOP or BOTTOM value.
When chang in g th e T O P v alu e th e pr og ra m m us t e n sur e th at the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare R egisters, a compare match will
never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are
masked to zero when any o f the OCR1x Registers are written. As the third per iod shown in Figure 12-8 on page
103 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result
in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since
the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-
ing slope is determined by the previou s TOP value, while the length of the rising slope is determined by the new
TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length
gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when chang-
ing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase corr ect PWM mode, the comp are units allow gener ation of PWM waveforms on the OC1x pins. Setting
the COM1x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM1x[1:0] to three (See Table 12-4 on p age 112). The actual OC1x value will only be visible on the
port pin if the data directio n for the port pin is set as output (DDR_OC1x). The PWM waveform is ge nerated by set-
ting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter
increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the
counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the
following equation:
OC R nx/TOP Update and
OC nA Interrupt F lag S et
or IC F n Interrupt F lag S et
(Interrupt on T O P )
1 2 3 4
TOVn Interrupt Flag Set
( Interrupt on B ottom)
TCNTn
Period
OCnx
OCnx
( CO Mnx [1 : 0 ] = 2)
( CO Mnx [1 : 0 ] = 3)
fOCnxPCPWM fclk_I/O
2NTOP
----------------------------=
104
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The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent spe cial cases wh en gener ating a PWM waveform output in
the phase correct PWM mode. If the OC R1x is set equal to B OTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
12.8.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode
(WGM1[3:0] = 8 or 9) provides a high resolution ph ase and frequency correct PWM waveform generation option.
The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope opera-
tion. The counter counts rep eatedly from BOTTOM (0x0000) to TOP and th en from TOP to BOTTOM. In non-
inverting Compare Output mo de, the Output Compare (OC1x) is cleared on the compare match between TCNT1
and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared
to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCR1x Register is updated by the OCR1x Buffer Register, (see Figur e 12-8 on page 103 and Fi gure 12 -9 on page
105).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum reso lution is 16-bit
(ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICR1 (WGM1[3:0] = 8), or the value in OCR1A (WGM1[3:0] = 9). The counter has then reached the TOP
and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing dia-
gram for the phase correct and frequency correct PWM mode is shown on Figure 12-9 on page 105. The figure
shows phase and fr equen cy corr ect PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is
in the timing diagram shown as a histogram for illustrating th e dual-slope operation. T he diagram includes non-
inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare
matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs.
RPFCPWM TOP 1+log 2log
-----------------------------------=
105
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Figure 12-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated
with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the
OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an inter-
rupt each time the counter reaches the TOP or BOTTOM value.
When chang in g th e T O P v alu e th e pr og ra m m us t e n sur e th at the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare R egisters, a compare match will
never occur between the TCNT1 and the OCR1x.
As Figure 12-9 on page 105 shows the output generated is, in contrast to the phase correct mode, symmetrical in
all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will
always be equal. This gives sym metrical output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x
pins. Setting the COM1x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be
generated by setting the COM1x[1:0] to three (See Table 12-4 on page 112). The actual OC1x value will only be
visible on the port pin if the data direction for the port pi n is set as outp ut (DDR_OC1x). The PWM waveform is gen-
erated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the
counter increm ents, and clearing (o r setting) the OC1x Re gister at compare mat ch between OCR1x an d TCNT1
when the counte r decrements . The PWM frequency for the output when using phase and frequency correct PWM
can be calculate d by the fo llowin g equ at ion :
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
OC R nx/T OP Updateand
TOVn Interrupt Flag Set
( Interrupt on B ottom)
OC nA Interrupt F lag S et
or IC F n Interrupt F lag Set
(Interrupt on T O P )
1 2 3 4
TCNTn
Period
OCnx
OCnx
( CO Mnx [1 : 0 ] = 2)
( CO Mnx [1 : 0 ] = 3)
fOCnxPFCPWM fclk_I/O
2NTOP
----------------------------=
106
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The extreme values for the OCR1x Register represents special cases when generating a PWM wave form output in
the phase correct PWM mode. If the OC R1x is set equal to B OTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
12.9 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal
in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Reg-
ister is updated with the OCR1x buffer value (only for modes utilizing double buffering). F igure 12-10 shows a
timing diagram for the setting of OCF1x.
Figure 12-10. T im er /Coun te r T imin g Dia gr am , Set ting of OCF1x, no Prescalin g
Figure 12-11 on page 106 shows the same timing data, but with the prescaler enabled.
Figure 12-11. Timer/Coun te r T imin g Diagr am , Set tin g of OCF 1x, with Pre sca le r (fclk_I/O/8)
Figure 12-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct
PWM mode the O CR1x Register is updated at BOTTOM. The timing diagra ms will be the same, but TOP should
clk
Tn
(clkI/O/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx V alue
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clkI/O/8)
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be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the
TOV1 flag at BOTTOM.
Figure 12-12. T im er /Co un ter T imin g Dia gr am , no Presca ling
Figure 12-13 on page 107 shows the same timing data, but with the prescaler enabled.
Figure 12-13. Timer/Counter Timing Dia gram, with Prescaler (fclk_I/O/8)
12.10 Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit
register for temporary sto ring of the high byte of the 16 -bit a ccess. The same te mporary r egister is sh ared b etween
all 16-bit registers within each 16-bit timer. Accessing the lo w byte triggers the 16-bit read or write operation. When
the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
TOVn
(FPWM)
and ICFn
(if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O
TOVn (FPWM)
and ICFn (if used
as T OP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
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byte written are both copi ed into th e 16-b it register in the same cloc k cycle. When the low byte of a 1 6-bit register is
read by the CPU, the high byte of the 16-bit reg ister is copied into the tempora ry register in the same clock cycle as
the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does
not involve using the temporary register.
To do a 16-bit write, the high byte must be written befor e the low byte. For a 16-bit re ad, th e low byte must be read
before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates
the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers.
Note that when using “C”, the compiler handles the 16-bit access.
Note: See “Code Examples” on page 6.
The assembly code exampl e returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrup t occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the
same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted.
Therefore, when both the ma in code a nd the in te rr upt code update the temporary r eg ister , the m ain code must di s-
able the interrupts du ring the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Examples
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Examples
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
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Note: See “Code Examples” on page 6.
The assembly code exampl e returns the TCNT1 value in the r17:r16 register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the
OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example
TIM16_ReadTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore global interrupt flag
out SREG,r18
ret
C Code Example
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
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Note: See “Code Examples” on page 6.
The assembly code exampl e requires that the r17:r16 register pair contains the value to be written to TCNT1.
12.10.1 Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte
only needs to be written once. However, note that the same rule of atomic operation described previously also
applies in this case.
Assembly Code Example
TIM16_WriteTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
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12.11 Register Description
12.11.1 T CCR 1A – Timer/Counter1 Control Register A
• Bits 7:6 – COM1A[1:0]: Compare Output Mode for Channel A
• Bits 5:4 – COM1B[1:0]: Compare Output Mode for Channel B
The COM1A[1:0] and COM1B[1:0] control the Output Compare pins (OC1A and OC1B respectively) behavior. If
one or both of the COM1A[1:0] bits are written to one, the OC1A output overrides th e normal port functionality of
the I/O pin it is co nnected to . If o ne or b oth of the COM1 B[1 :0] bit are written to one, the OC1B output overrid es the
normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is dependent of the
WGM1[3:0] bits setting.
Table 12-2 shows COM1x[1:0] bit func tionality when WGM1[3:0] bits are set to a Normal or a CTC mo de (non-
PWM).
Table 12-3 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare
match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 100 for more details.
Bit 7 6 5 43210
(0x72) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 12-2. Compare Output Mode, non-PWM
COM1A1
COM1B1 COM1A0
COM1B0 Description
0 0 Normal port operati on, OC1A/OC1B disconnected
0 1 Toggle OC1 A/OC1B on Compare Match
10
Clear OC1A/OC1B on Compare Match
(Set output to low leve l)
11
Set OC1A/OC1B on Compare Match
(Set output to high level).
Table 12-3. Compare Output Mode, Fast PWM(1)
COM1A1
COM1B1 COM1A0
COM1B0 Description
0 0 Normal port operati on, OC1A/OC1B disconnected
01
WGM13=0: Normal port operation, OC1A/OC1B disconnected
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved
10
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at
BOTTOM (non-inverting mode)
11
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at
BOTTOM (inverting mode)
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Table 12-4 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to phase correct or phase and fre-
quency correct PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM
Mode” on page 102 for more details.
• Bits 1:0 – WGM1[1:0]: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what
type of waveform generation to be used, see Table 12-5 on page 112. Modes of oper ation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of
Pulse Width Modulation (PWM) modes. ( “Modes of Operation” on page 98).
Table 12-4. Compare Output Mode, Phase Correct and Phase & Frequency Correct PWM(1)
COM1A1
COM1B1 COM1A0
COM1B0 Description
0 0 Normal port operati on, OC1A/OC1B disconnected
01
WGM13=0: Normal port operation, OC1A/OC1B disconnected
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved
10
Clear OC1A/OC1B on Compare Match when up-counting
Set OC1A/OC1B on Compare Match when downcounting
11
Set OC1A/OC1B on Compare Match when up-counting
Clear OC1A/OC1B on Compare Match when downcounting
Table 12-5. Waveform Generation Modes
Mode WGM1
[3:0] Mode of
Operation TOP Update of
OCR1x at TOV1 Flag
Set on
0 0000 Normal 0xFFFF Immediate MAX
1 0001 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0010 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0011 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
40100CTC (
Clear Timer on Compare) OCR1A Immediate MAX
5 0101 Fast PWM, 8-bit 0x00FF TOP TOP
6 0110 Fast PWM, 9-bit 0x01FF TOP TOP
7 0111 Fast PWM, 10-bit 0x03FF TOP TOP
8 1000 PWM, Phase & Freq. Correct ICR1 BOTTOM BOTTOM
9 1001 PWM, Phase & Freq. Correct OCR1A BOTTOM BOTTOM
10 1010 PWM, Phase Correct ICR1 TOP BOTTOM
11 1011 PWM, Phase Correct OCR1A TOP BOTTOM
12 1100 CTC (Clear Timer on Compare) ICR1 Immediate MAX
13 1101 Reserved – – –
14 1110 Fast PWM ICR1 TOP TOP
15 1111 Fast PWM OCR1A TOP TOP
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12.11.2 T CCR 1B – Timer/Counter1 Control Register B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input
from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of
the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the
noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to tr igger a capture event. When the ICES1
bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising
(positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Reg-
ister (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture
Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny1634 and will always read as zero.
• Bits 4:3 – WGM1[3:2]: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what
type of waveform generation to be used, see Table 12-5 on page 112. Modes of oper ation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of
Pulse Width Modulation (PWM) modes. ( “Modes of Operation” on page 98).
• Bits 2:0 – CS1[2:0]: Clock Select Bits
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 12-10 and Figure
12-11.
Bit 76543210
(0x71) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 12-6. Clock Select Bit Description
CS12 CS11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
001clk
I/O/1 (No prescaling)
010clk
I/O/8 (From prescaler)
011clk
I/O/64 (From prescaler)
100clk
I/O/256 (From prescaler)
101clk
I/O/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.
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If external pin modes are used for the Timer/Counter1, transitio ns on the T1 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
12.11.3 T CCR 1C – Timer/Counter1 Control Register C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are o nly active when the WGM1[3:0] bits specifies a non-PWM mode. However, for ensur-
ing compatibility with future devices, these bits must be set to zero when TCCR1B is written when operating in a
PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the
Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x[1:0] bits that
determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match
(CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
12.11.4 TCNT1H and TCNT1L – Ti mer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneou sly when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See
“Accessing 16-bit Registers” on page 107.
Modifying the counter (TCNT1) while th e cou nter is ru nnin g in trod uces a r isk o f missing a co mpa re ma tch b etween
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the comp are match on the following timer clock for all compare
units.
12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
Bit 76543210
(0x70) FOC1A FOC1B – – – – – – TCCR1C
Read/Write W W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x6F) TCNT1[15:8] TCNT1H
(0x6E) TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x6D) OCR1A[15:8] OCR1AH
(0x6C) OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to genera te an Outp ut Compare inter ru pt, or to gene rate a waveform outpu t on the
OC1x pin.
The Output Compare Register s are 16-bit in size. To e nsure that both the h igh and low byte s are writte n simultane-
ously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shar ed by all the other 16-bit registers. See “Accessing 16-bit Registers” on
page 107.
12.11.7 ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneou sly
when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. “Accessing 16-bit Register s” on page
107.
12.11.8 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 47) is
executed w he n the TOV1 flag, located in TIFR, is set.
• Bit 6 – OCIE1A: Ti mer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter-
rupts” on page 47) is executed when the OCF1A flag, located in TIFR, is set.
• Bit 5 – OCIE1B: Ti mer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter-
rupts” on page 47) is executed when the OCF1B flag, located in TIFR, is set.
Bit 76543210
(0x6B) OCR1B[15:8] OCR1BH
(0x6A) OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x69) ICR1[15:8] ICR1H
(0x68) ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
0x3A (0x5A) TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A TIMSK
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 4 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny1634 and will always read as zero.
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page
47) is executed when the ICF1 Flag, located in TIFR, is set.
12.11.9 TIFR – Timer/Counter Interrupt Flag Register
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dep endent of the WGM1[3:0] bits setting. In Normal a nd CT C modes, the TOV1 flag is set
when the timer overflows. See Table 1 2-5 o n pa ge 11 2 fo r the TOV1 flag behavior when using another WGM1[3:0]
bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1
can be cleared by writin g a log ic on e to its bit locat ion .
• Bit 6 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
Note that a Forced Output Compare (1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed . Alternatively,
OCF1B can be cleared by writing a logi c one to its bit location.
• Bit 5 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A
(OCR1A).
Note that a Forced Output Compare (1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed . Alternatively,
OCF1A can be cleared by writing a logi c one to its bit location.
• Bit 4 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny1634 and will always read as zero.
• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the
WGM1[3:0] to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be
cleared by writing a logic one to its bit location.
Bit 765432 10
0x39 (0x59) TOV1 OCF1B OCF1A – ICF1 OCF0B TOV0 OCF0A TIFR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value000000 00
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13. T imer/Counter Prescaler
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the tim er/counters can have different
prescaler settings. The description below applies to both timer/counters. Tn is used as a general name, where n =
0, 1.
The fastest timer/counter operation is achieved when the timer/counter is clocked directly by the system clock.
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock taps are:
•f
CLK_I/O/8
•f
CLK_I/O/64
•f
CLK_I/O/256
•f
CLK_I/O/1024
Figure 13-1 shows a block diagram of the timer/counter prescaler.
Figure 13-1. Prescaler for Time r/Counter0
Note: 1. The synchronization logic on the input pin (Tn) is shown in Figure 13-2 on page 118.
13.1 Prescaler Reset
The prescaler is free running, i.e. it operates independently of the clock se lect log ic of the timer/counter. Since the
prescaler is not affected by the clock selection of timer/counters the state of the prescaler will have implications
where a prescaled clock is u sed. One example of presca ling artifacts occurs when the timer/counter is enabled
while clocked by the prescaler. The time between timer/counter enable and the first count can be from 1 to N+1
system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
To avoid prescaling artifacts, the Presca ler Reset can be used for synchronizing the timer/counter to pro gram
execution.
PSR10
CLEAR
Tn
clk
I/O
CSn0
CSn1
CSn2
clk
Tn
0
10-BIT PRESCALER
TIMER/COUNTER
CLOCK SOURCE
CK/8
CK/64
CK/256
CK/1024
SYNC
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13.2 External Clock Source
An external clock source applied to th e Tn pin can be used as timer/counte r clock (clkTn). The Tn pin is sampled
once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed
through the edge detector. Figure 13-2 shows a block diagram of the Tn synchronization and edge detector logic.
Figure 13-2. Tn Pin Sampling
The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the
high period of the internal system clock.
Depending on the Clock Select bits of the time r/coun te r, the e dge de te ctor ge ner ates one clk Tn pulse for each pos-
itive or negative edge it detects.
The synchronization and ed ge detector logic in troduces a de lay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
To ensure correct sa mpling, each half period of the external clock app lied must be longer than one system clock
cycle. Given a 50/50 duty cycle the external clock must be guaranteed to have less than half the system clock fre-
quency (fExtClk < f clk_I/O/2). Since the edge detector uses sam pling, the Nyquist sampling theorem states that the
maximum frequency of an external clock it can detect is half the sampling frequency. However, due to variation of
the system clock frequency and duty cycle caused by oscillator source tolerances, it is recommended that maxi-
mum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be pre sca le d.
13.3 Register Description
13.3.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TS M bit to one activates th e Timer/Cou nter Synch ronization m ode. In this mode, th e value that is writ-
ten to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Tim er/Counter is halted and can be configured without th e risk of advancing during conf igura-
tion. When the TSM bit is written to zero, the PSR10 bit is cleared by hard wa re, a nd the Timer/Counter start
counting.
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
DQDQ
LE
DQ
Tn
clk
I/O
Bit 7 6 5 4 3 2 1 0
(0x67) TSM – – – – – – PSR10 GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
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• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hard-
ware, except if the TSM bit is set.
14. I2C Compatible, Two-Wire Slave Interface
14.1 Features
•I2C compatible
•SMBus compatible (with reservations)
•100kHz and 400kHz support at low system clock frequencies
•Slew-Rate Limi ted Output Drivers
•Input Filter provides noise suppression
•7-bit, and General Call Address Recognition in Hard ware
•Address mask register for address masking or dual add ress match
•10-bit addr essing supported
•Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
•Operates in all sleep modes, including Power Down
•Slave Arbitration allows support for SMBus Address Resolve Protoco l (ARP)
14.2 Overview
The Two-Wire Interface (TWI) is a bi- directional, bus communica tion interface, which us es only two wires. The TWI
is I2C compatible and, with reservations, SMBus compatible (see “Compatibility with SMBus” on page 125).
A device connected to the bus must act as a master or slave.The master initiates a data transaction by addressing
a slave on the bus, and telling whether it wants to transmit or receive data. One bus can have several masters, and
an arbitration process handles priority if two or more masters try to transmit at the same time.
The TWI module in ATtiny1634 implements slave functionality, only. Lost arbitration, errors, collisions and clock
holds on the bus are detected in hardware and indicated in separate status flags.
Both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is also supported. A
dedicated address mask reg ister can act as a second address match register or as a mask register for the slave
address to match on a range of addresses. The slave logic continues to o perate in all sleep modes, including
Power down. This enables the slave to wake up from sleep on T WI address match. It is possible to disabl e the
address matching and let this be handled in software instead. This allows the slave to detect and respond to sev-
eral addresses. Smart Mode can be enabled to auto trigger operations and reduce software complexity.
The TWI module includes bus state logic that collects information to detect START and STOP conditions, bus col-
lision and bus errors. The bus state logic continues to operate in all sleep modes including Power down.
14.3 General TWI Bus Concepts
The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a serial clock line (SCL)
and a serial data line (SDA). The two lines are open collector lines (wired-AND), and pull-up resistors (Rp) are the
only external components needed to drive the bus. The pull-up resistors will provide a high level on the lines when
none of the connected devices ar e driving the bus. A constant current source can be used as an alternative to the
pull-up resistors.
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus. A device con-
nected to the bus can be a master or slave, where the master controls the bus and all communication.
Figure 14-1 illustrates the TWI bus topology.
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Figure 14-1. TWI Bus Topology
A unique address is assigned to all slave devices connected to the bus, and the master will use this to address a
slave and initiate a data transaction. 7-bit or 10-bit addressing can be used.
Several masters ca n be connected to the same bus, and this is called a multi-master environment. An arbitration
mechanism is provided for resolving bus ownership be tween masters since o nly one master device may own the
bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by responding to more
than one address.
Figure 14-2 shows a TWI transaction.
Figure 14-2. Basic TWI Transac tion Dia gr am To polo gy
A master indicates the start of transaction by issuing a START condition (S) on the bus. An address packet with a
slave address (ADDRESS) and an indication whether the master wishes to read or write data (R/W), is then sent.
After all data packets (DATA) are transferred, the master issues a STOP condition (P) on the bus to end the trans-
action. The receiver must acknowledge (A) or not-acknowledge (A) each byte received.
The master provides th e clock signal for the transaction, bu t a device connected to the bu s is allowed to stretch the
low level period of the clock to decrease the clock speed.
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14.3.1 Electrical Characteristics
The TWI follows the electrical specifications and timing of I2C and SMBus. See “Two-Wire Serial Interface” on
page 233 and “Compatibility with SMBus” on page 125.
14.3.2 START and STOP Conditions
Two unique bu s conditions are used for marking the beginnin g (START) and end (STO P) of a transaction. Th e
master issues a START condition(S) by indicating a high to low transition on the SDA line while the SCL line is kept
high. The master completes the transaction by issuing a STOP condition (P), indicated by a low to high transition
on the SDA line while SCL line is kept high.
Figure 14-3. START and STOP Conditions
Multiple START conditions can be issued during a single transaction. A START condition not directly following a
STOP condition, are named a Repeated START condition (Sr).
14.3.3 Bit Transfer
As illustrated by Figure 14-4 a bit transferred on the SDA line must be stable for the entire high period of the SCL
line. Conseque ntly the SDA valu e can on ly be chang ed duri n g th e low period o f the cloc k. This is ensured in hard-
ware by the TWI module.
Figure 14-4. Data Validity
Combining bit transfers results in the formation of address and data packets. These packets consist of 8 data bits
(one byte) with the most significant bit transferred first, plus a single bit not-acknowledge (NACK) or acknowledge
(ACK) response. The addressed device signals ACK by pulling the SCL line low, and NACK by leaving the line
SCL high during the ninth clock cycle.
14.3.4 Address Packet
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by
the Master. A slave recognizing its address will ACK the address by pulling the data line low the next SCL cycle,
while all other slaves should keep the TWI lines released, and wait for the next START and address. The 7-bit
address, the R/W bit and the acknowledge bit combined is the ad dress packet. On ly one address pack et for each
START condition is given, also when 10-bit addressing is used.
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The R/W specifies the dire ction of the transaction. If the R/W bit is low, it indicates a Master Write transaction, and
the master will transmit its data after the slave has acknowledged its address. Opposite, for a Master Read opera-
tion the slave will start to transmit data after acknowledging its address.
14.3.5 Data Packet
Data packets succeed an address packet or another data packet. All data packets are nine bits long, consisting of
one data byte and an acknowledge bit. The direction bit in the previous address packet determines the direction in
which the data is transferred.
14.3.6 Transaction
A transaction is the complete transfer from a START to a STOP condition, including any Repeated START condi-
tions in between. The TWI standard de fines three fundamental tra nsaction modes: Master Write, Master Read, and
combine d transaction.
Figure 14-5 illustrates the Master Write transaction. The master initiates the transaction by issuing a START condi-
tion (S) followed by an address packet with direction bit set to zero (ADDRESS+W).
Figure 14-5. Master Write Transaction
Given that the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will
ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by
issuing a STOP condition (P) directly after th e address packe t. There ar e no limitations to th e number of data pa ck-
ets that can be transferred. If the slave signal a NACK to the data, the master must assume that the slave cannot
receive any more data and terminate the transaction.
Figure 14-6 illustrates the Master Read transaction. The master initiates the transaction by issuing a START condi-
tion followed by an address packet with direction bit set to one (ADRESS+R). The addressed slave must
acknowledge the address for the master to be allowed to continue the transaction.
Figure 14-6. Master Read Transaction
Given that the slave acknowledges the address, the master can start receiving data from the slave. There are no
limitations to the number of data packe ts that can be transferred. The slave transmits the data while the master sig-
nals ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a STOP
condition.
Figure 14-7 illustrates a combined transaction. A combined transaction consists of several read and write transac-
tions separated by a Repeated START conditions (Sr).
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Figure 14-7. Combined Transaction
14.3.7 Clock and Clock Stretching
All devices connected to the bus ar e allowed to stretch t he low period of the clock to slow down the overall clock
frequency or to insert wait states while proce ssing data. A device that needs to stretch the clock can do this by
holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined as shown in Figure 14-8.
Figure 14-8. Clock Stretching
If the device is in a sleep mod e and a START conditio n is detected the clock is stretched during the wake -up period
for the device.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the
slave to run at a lower system clock frequency. However, the overall performance of the bus will be reduced
accordingly. Both the master and slave device can randomly stretch the clock on a byte level basis before and after
the ACK/NACK bit. This provides time to process incoming or prepare outgoing data, or performing other time crit-
ical tasks.
In the case where the slave is stretching the clock the master will be forced into a wait-state until the slave is ready
and vice versa.
14.3.8 Arbitration
A master can only start a bus transaction if it has detected that the bus is idle. As the TWI bus is a multi master
bus, it is possible that two devices initiate a transaction at the same time. This results in multiple masters owning
the bus simultaneously. This is solved using an arbitration scheme where the master loses control of th e bus if it is
not able to tran smit a high level on the SDA line. The masters who lose arbitration must then wa it until the bus
becomes idle (i.e. wait for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not
involved in the arbitration procedure.
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Figure 14-9. TWI Arbitration
Figure 14-9 shows an example where two TWI master s are contendin g for bus ownersh ip. Both devices are able to
issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while
DEVICE2 is transmitting a low level.
alternativeArbitration between a r epeated START conditio n and a data bit, a STOP condition and a data bit, or a
repeated START condition and STOP condition are not allowed and will require special handling by software.
14.3.9 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to con-
trol the SCL line at the same time. The algorithm is based on the same principles used for clock stretching
previously describ ed. Figu re 14-10 shows an example whe re two masters are competing for the control over the
bus clock. The SCL line is the wired-AND result of the two masters clock outputs.
Figure 14-10. Clock Synchroniz ation
A high to low transition on the SCL line will force the line low for all masters on the bus and they start timing their
low clock period. The timing length of the low clock period can vary between the masters. When a master
(DEVICE1 in this case) has completed its low period it releases the SCL line. However, the SCL line will not go
high before all masters have released it. Consequently the SCL line will be held low by the device with the longest
low period (DEVICE2). Devices with shorter low periods must insert a wait-state until the clock is released. All mas-
ters start their high period when the SCL line is released by all devices and has become high. The device which
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first completes its high period (DEVICE1) forces the clock line low and the p roce dure a re then repea te d. Th e result
of this is that the device with the shortest clock period determines the high period while the low period of the clock
is determined by the longest clock period.
14.3.10 Compatibility with SMBus
As with any other I2C-compliant interface there are known compatib ility issues the designer should be aware of
before connecting a TWI device to SM Bus devices. For use in SMBus environments, the following should be
noted:
• All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to both supply voltage
and ground. See Figure 10-1 on page 54. This is in contradiction to the requirements of the SMBus
specifications. As a result, supply voltage mustn’t be removed from the AVR or the protection diodes will pull the
bus lines down. Power down and sleep modes is not a problem, provided supply voltages rema in.
• The data hold time of the TWI is lower than specified for SMBus.
• SMBus has a low speed limit, while I2C hasn’t. As a master in an SMBus environment, the A VR must make sure
bus speed does not drop below specifications, since lower bus speeds trigger timeouts in SMBus slaves. If the
AVR is configured a slave there is a possibility of a bus lockup, since the TWI module doesn't identify timeouts.
14.4 TWI Slave Operation
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate interrupt flags for Data
Interrupt and Address/Stop Interrupt. Interrupt flags can be set to trigger the TWI interrupt, or be used for polled
operation. There are dedicated status flags for indicating ACK/NACK received, clock hold, collision, bus error and
read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle any data,
and will in most cases require software interaction. Figure 14-11. shows the TWI slave operation. The diamond
shapes symbols (SW) indicate where software interaction is required.
Figure 14-11. TWI Slave Oper at ion
The number of interrupts generated is kept at a minimum by automatic hand ling of most conditions . Quick Com-
mand can be enabled to auto trigger operations and reduce software complexity.
Promiscuous Mode can be enabled to allow the slave to respond to all received addresses.
14.4.1 Receiving Address Packets
When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens,
the successive address byte will be received and checked by the address match logic, and the slave will ACK the
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correct address. If the received address is not a match, the slave will not acknowledge the address and wait for a
new START condition.
The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid address packet is
detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition, is an illegal operation and the Bus Error flag is set.
The R/W Direction flag reflects the direction bit received with the address. This can be read by software to deter-
mine the type of operatio n currently in progress.
Depending on the R/W direction bit and bus condition one of four distinct cases (1 to 4) arises following the
address packet. The different cases must be handled in software.
14.4.1.1 Case 1: Address packet accepted - Direction bit set
If the R/W Direction flag is set, this indicates a master read operation. The SCL line is forced low, stretching the
bus clock. If ACK is sent by the slave, the slave hardware will set the Data Interrupt Flag indicating data is needed
for transmit. If NACK is sent by the slave, the slave will wait for a new START condition and address match.
14.4.1.2 Case 2: Address packet accepted - Direction bit cleared
If the R/W Direction flag is cleared this indicates a master write operation . The SCL line is forced low, stretching the
bus clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, Repeated START or STOP
can be received after this. If NACK is indicated the slave will wait for a new START condition and address match.
14.4.1.3 Case 3: Collision
If the slave is not able to send a high level or NAC K, the Collision flag is set and it will disable the data and
acknowledge output from the slave logic. T he clock hold is released. A START or repeated START condition will
be accepted.
14.4.1.4 Case 4: STOP condition received.
Operation is the same as case 1 or 2 above with one exception. When the STOP condition is received, the Slave
Address/Stop flag will be set indicating that a STOP condition and not an address match occurred.
14.4.2 Receiving Data Packet s
The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received the Data Interrupt
Flag is set, and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a STOP or
Repeated START condition.
14.4.3 Transmitting Data Packets
The slave will know when an address packet, with R/W direction bit set, has been successfully received. It can then
start sending data by writing to the Slave Data register. When a data packet transmission is completed, the Data
Interrupt Flag is set. If the master indicates NACK, the slave must stop transmitting data, and expect a STOP or
Repeated START condition.
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14.5 Register Description
14.5.1 TWSCRA – TWI Slave Control Register A
• Bit 7– TWSHE: TWI SDA Hold Time Enable
When this bit is set each negative transition of SCL triggers an additional internal delay, before the device is
allowed to change the SDA line. The added delay is a pproximately 50ns in length. This may be useful in SMBus
systems.
• Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 5 – TWDIE: TWI Data Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the data interrupt flag
(TWDIF) in TWSSRA is set.
• Bit 4 – TWASIE: TWI Address/Stop Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the address/stop interrupt
flag (TWASIF) in TWSSRA is set.
• Bit 3 – TWEN: Two-Wire Interface Enable
When this bit is set the slave Two-Wire Inter face is enabled.
• Bit 2 – TWSIE: TWI Stop Interrupt Enable
Setting the Stop Interrupt Enable (TWSIE) bit will set the TWASIF in the TWSSRA register when a STOP condition
is detected.
• Bit 1 – TWPME: TWI Promiscuous Mode Enable
When this bit is set the address match logic of the slave TWI responds to all received addresses. When this bit is
cleared the address match logic uses the TWSA register to determine which address to recognize as its own.
• Bit 0 – TWSME: TWI Smart Mode Enable
When this bit is set the TWI slave enters Smart Mode, where the Acknowledge Action is sent immediately after the
TWI data register (TWSD) has been read. Acknowledge Action is defined by the TWAA bit in TWSCRB.
When this bit is cleared the Acknowledge Action is sent after TWCMDn bits in TWSCRB are written to 1X.
14.5.2 TWSCRB – TWI Slave Control Register B
• Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 76543210
(0x7F) TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME TWSCRA
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x7E) – – – – – TWAA TWCMD1 TWCMD0 TWSCRB
Read/Write RRRRRR/WWW
Initial Value 00000000
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• Bit 2 – TWAA: TWI Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte has been received from the mas-
ter. Depending on the TWSME bit in TWSCRA the Acknowledge Action is executed either when a valid command
has been written to TWCMDn bits, or when the data register ha s been read. Acknowledge action is also executed
if clearing TWAIF flag after address match or TWDIF flag during master transmit. See Table 14-1 for details.
• Bits 1:0 – TWCMD[1:0]: TWI Command
Writing these bits triggers the slave operation as defined by Table 14-2. The type of operation de pends on th e TWI
slave interrupt flags, TWDIF and TWASIF. The Acknowledge Action is only executed when the sla ve re ce ives da ta
bytes or address byte from the master.
Writing the TWCMD bits will automatically release the SCL line and clear the TWCH and slave interrupt flags.
TWAA and TWCMDn bits can be written at the same time. Acknowledge Action will then be executed before the
command is triggered.
The TWCMDn bits are str obed and always read zero.
14.5.3 TWSSRA – TWI Slave Status Register A
Table 14-1. Acknowledge Action of TWI Slave
TWAA Action TWSME When
0 Send ACK 0 When TWCMDn bits are written to 10 or 11
1 When TWSD is read
1 Send NACK 0 When TWCMDn bits are written to 10 or 11
1 When TWSD is read
Table 14-2. T W I Slav e Com m a nd
TWCMD[1:0] TWDIR Operation
00 X No action
01 X Reserved
10
Used to complete transaction
0 Execute Acknowledge Action, then wait for any START (S/Sr) condition
1 Wait for any START (S/Sr) condition
11
Used in response to an Address Byte (TWASIF is set)
0 Execute Acknowledge Action, then receive next byte
1 Execute Acknowledge Action, then set TW DIF
Used in response to a Data Byte (TWDIF is set)
0 Execute Acknowledge Action, then wa it for next byte
1 No action
Bit 76543210
(0x7D) TWDIF TWASIF TWCH TWRA TWC TWBE TWDIR TWAS TWSSRA
Read/Write R/W R/W R R R/W R/W R R
Initial Value 00000000
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• Bit 7 – TWDIF: TWI Data Interrupt Flag
This flag is set when a data byte has been successfully received, i.e. no bus errors or collisions have occurred dur-
ing the operation. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL
line is released by clearing the interrupt flags.
Writing a one to this bit will c lear the flag. This flag is also automatically cleared w hen writing a valid command to
the TWCMDn bits in TWSCRB.
• Bit 6 – TWASIF: TWI Address/Stop Interrupt Flag
This flag is set when the slave detects that a valid address has been received, or whe n a transmit collision has
been detected. Whe n this flag is set th e slave forces the SCL line low, stretching the TWI clock period. The SCL
line is released by clearing the interrupt flags.
If TWASIE in TWSCRA is set, a STOP condition on the bus will also set TWASIF. STOP condition will set the flag
only if system clock is faster than the minimum bus free time between STOP and START.
Writing a one to this bit will c lear the flag. This flag is also automatically cleared w hen writing a valid command to
the TWCMDn bits in TWSCRB.
• Bit 5 – TWCH: TWI Clock Hold
This bit is set when the slave is holding the SCL line low.
This bit is read-only, and set when TWDIF or TWASIF is set. The bit can be cleared indirectly by clearing the inter-
rupt flags and releasing the SCL line.
• Bit 4 – TWRA: TWI Receive Acknowledge
This bit contains the most recently received acknowledge bit from the master.
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and, when one, the
most recent acknowledge bit was NACK.
• Bit 3 – TWC: TWI Collision
This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a collision is detected,
the slave will commence its normal operation, and disable data and acknowledge output. No low values are shifted
out onto the SDA line.
This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or Repeated START
condition is detected.
• Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occured during a transfer. An illegal bus condition occurs if a
Repeated START or STOP condition is detected, and the number of bits from the previous START condition is not
a multiple of nine.
This bit is cleared by writing a on e to it.
• Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicate s the di rection bit fr om the last addr ess packet received fr om a master. Whe n this bit is one, a mas-
ter read operation is in progress. When the bit is zero a master write operation is in progress.
• Bit 0 – TWAS: TWI Address or Stop
This bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to be set. If one,
address detection caused TWASIF to be set.
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14.5.4 TWSA – TWI Slave Address Register
The slave address register conta ins the TWI slave address used by the slave ad dress match logic to d etermine if a
master has addressed the slave. When using 7-bit or 10-bit ad dress recognition mode, the high seven bits of the
address register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA0) is used for general
call address recognition. Setting TWSA0 enables general call address recognition logic.
When using 10-bit addressing the address match logic only support hardware address recognition of the first byte
of a 10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 of the slave address. The
next byte received is then bits 7 to 0 in the 10-bit address, but this must be handled by software.
When the address ma tch logic detects that a valid address byte h as been received, the TWASIF is set and th e
TWDIR flag is updated.
If TWPME in TWSCRA is set, the address match logic responds to all addre sses transmitted on the TWI bus.
TWSA is not used in this mode.
14.5.5 TWSD – TWI Slave Data Register
The data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD
register and to/from the bus. Therefo re, the data register cannot be a ccessed during byte transfers. This is pro-
tected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when
TWCH is set.
When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte trans-
fer is started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the
acknowledge bit from the master. The TWDIF and the TWCH bits are then set.
When a master write s data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in
the data register. If Smart M ode is enabled, reading the data re gister will trigger the bus operation, as set by the
TWAA bit in TWSCRB.
Accessing TWSD will clear the slave interrupt flags and the TWCH bit.
14.5.6 TWSAM – TWI Slave Address Mask Register
• Bits 7:1 – TWSAM[7:1]: TWI Address Mask
These bits can act as a second address match register, or an address mask register, depending on the TWAE
setting.
If TWAE is set to zero, TWSAM can be loaded with a 7 -bit slave address ma sk. Each bit i n TWSAM can mask (dis-
able) the corresponding address bit in the TWSA register. If the mask bit is one the address match between the
incoming address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match.
Bit 76543210
(0x7C) TWSA[7:0] TWSA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
(0x7A) TWSD[7:0] TWSD
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
(0x7B) TWSAM[7:1] TWAE TWSAM
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
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If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to th e TWSA register. In this
mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.
• Bit 0 – TWAE: TWI Address Enable
By default, this bit is zero and the TWSAM bits acts as an address mask to the TWSA register. If this bit is set to
one, the slave address match logic responds to the two unique addresses in TWSA and TWSAM.
15. USI – Universal Serial Interface
15.1 Features
•Two-wire Synchronous Data Transfer (Master or Slave )
•Three-wire Synchronou s Data Transfer (Master o r Slave)
•Data Received Interrupt
•Wakeup from Idle Mo de
•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
•Two-wire Start Condition Detector with Interrupt Capability
15.2 Overview
The Universal Serial Interface (USI) provides basic hardware resources for serial communication. Combined with a
minimum of control software, the USI allows significantly hig her tr ansfer rate s and uses less cod e spa ce th an solu-
tions based on software, only. The USI hardware also in cludes interrupts to minimize the processor load. A
simplified block diagram of the USI is shown in Figure 15-1.
Figure 15-1. Universal Serial Interface, Block Diagram
Incoming and outgoing data is contained in the 8-bit USI Data Register (USIDR). It is directly accessible via the
data bus but a copy of the contents is a lso placed in the USI Buffer Register (USIBR) wher e it can be retrieved
later. If USIDR is read directly, it must be done as quickly as possible to ensure that no data is lost.
DATA BUS
USIPF
USITC
USICLK
USICS0
USICS1
USIOIFUSIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE Bit7
Two-wire Clock
Control Unit
DO (Output only)
DI/SDA (Input/Open Drain)
USCK/SCL (Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
USIBR
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Depending on the mode operation, the most significant bit of USIDR is connected to one of two output pins. A
transparent latch between th e outp ut of USIDR and the output pin delays the change of data output to the opposite
clock edge of the data inpu t sam p ling .
Regardless of the mode of operation, the serial input is always sampled from the Data Input (DI) pin.
The 4-bit counter can be read and written via the data bus, and it can generate an overflow interrupt. Both USIDR
and the counter are clocke d simultaneou sly by th e same clock source. This allows the co unter to count the n umber
of bits received or transmitted and generate an interrupt when the transfer is complete.
When an external clock source is selecte d the counter counts both clo ck edges, me aning it reg isters th e number of
clock edges and not the number of data bits. The clock can be selected from three different sources:
•The USCK pin
• Timer/Counter0 Compare Match
• Software
The two-wire clock control unit can be con figured to generat e an interrupt when a star t condition has been detected
on the two-wire bus. By holding the cloc k pin low after a start condition is detected, or after the counter overflows,
the unit can also be used to generate wait states.
The USI connects to I/O pins of the device as listed in Table 15-1, below. For I/O pin placement, see “Pinout of
ATtiny1634” on page 2.
Device-specific I/O Register and bit locations are listed in the “Register Descriptions” on page 140.
15.3 Three-wire Mode
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the
slave select (SS) pin functionality. However, this feature can be implemented in software, if necessary. Pin names
used in this mode are DI, DO, and USCK. See Table 15-1.
Figure 15-2 on page 133 shows two USI units operating in three-wire mode, one as master and one as slave. The
two USI Data Registers are interconnected in such a way that after eight USCK clocks, the data in each register
has been interchanged.The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt)
Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the
master device software by toggling the USCK pin, or by writing a one to bit USITC bit in USICR.
Table 15-1.
Three-Wire Mode Two-Wire Mode Pin
Data Input (DI) Serial Data (SDA) PB1
Data Output (DO) – PB2
Clock (USCK) Serial Clock (SCL) PC1
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Figure 15-2. Three-wire Mode Operation, Simplified Diagram
The three-wire mode timing is shown in Figure 15-3. At the top of the figure is a USCK cyc le referenc e. One bit is
shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external
clock modes. In external clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (USIDR
is shifted by one) at negative edges. In external clock mode 1 (USICS0 = 1) the opposite edges are used. In other
words, data is sampled at negative and output is changed at positive edges. The USI clock mod es co rres pond s to
the SPI data mode 0 and 1.
Figure 15-3. Three-wire Mode, Timing Diagram
Referring to the timing diagram in Figure 15-3, a bus transfer involves the following steps:
1. The slave and master devices set up th eir dat a outp ut s and, depen ding on the proto col used, enable th eir
output drivers (mark A and B). The output is set up by writing the data to be transmitted to USIDR. The
output is enabled by setting the bit corresponding to DO in the data direction register (DDRx) of the port.
Note that there is not a preferred order of po ints A and B in the figure, but both must be at least one half
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxn
MSB
MSB
654321LSB
1 2 3 4 5 6 7 8
654321LSB
USCK
USCK
DO
DI
DCBA E
CYCLE ( Reference )
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USCK cycle before point C, where the data is sampled. This is in order to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
2. The master software generates a clock pulse by tog gling the USCK line twice (C a nd D). T he bit value on
the data input pin (DI) is sampled by the USI on the first edge (C), and the data output is changed on the
opposite edge (D). The 4-bit counter counts both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer has
been completed. If USI Buffer Registers are not used the dat a bytes that h ave been transfer red must now
be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it
is set to Idle mode. Depending on the protocol used the slave device can now set its output to high
impedance.
15.4 Two-wire Mode
The USI two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and
without input noise filtering. Pin names used in this mode are SCL and SDA. See Table 15-1 on page 132.
Figure 15-4 shows two USI units operating in two-wire mode, one as master and one as slave. Only the physical
layer is shown, since the system operation is highly dependent of the communication scheme used. The main dif-
ferences between the master and slave operation at this level is the serial clock generation which is always done
by the master. Only the slave uses the clock control unit.
Figure 15-4. Two-wire Mode Operation, Simplified Diagram
Clock generation must be imp lemented in software, but the shift o peration is done automatically in both de vices.
Note that clocking only on negative edges for shifting data is of practical use in this mode. The slave can insert wait
states at start or end of transfer by forcing the SCL clock low. This means that the master must always check if the
SCL line was actually released after it has generated a positive edge.
MASTER
SLAVE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA
SCL
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Two-wire Clock
Control Unit
HOLD
SCL
PORTxn
SDA
SCL
VCC
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Since the clock also increment s the counter, a counter ove rflow can be used to indicate that the tra nsfer is com-
pleted. The clock is generated by the master by toggling the USCK pin via the PORT register.
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be imple-
mented to control the data flow.
Figure 15-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 15-5), a bus transfer involves the following steps:
1. The sta rt condition is genera ted by the master by forcing the SDA low line while keeping the SCL line high
(A). SDA can be forced low either by writing a zero to bit 7 of USIDR, or by setting the corresponding bit in
the PORT register to zero. Note that the data direction re gister (DDRx) bit mus t be se t to one fo r the out-
put to be enabled. The start detector logic of the slave device (see Figure 15-6 on page 136) detects the
start condition and sets the USISIF Flag. The flag can generate an interrupt, if necessary.
2. The start detector will hold the SCL line low after the master has forced a negative edge on this line (B).
This allows the slave to wake up from sleep or complete other t asks before setting up USIDR to receive
the address. This is done by clearing the start condition flag and resetting the counter.
3. The master sets the first bit to be transferred and releases the SCL line (C). The slave samples the data
and shifts it into USIDR at the positive edge of the SCL clock.
4. After eight bits containing slave address an d data direction (read or write) have been transferred, the
slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has
addressed, it releases the SCL line and waits for a new start condition.
5. When the slave is addr essed, it holds the SDA line low during the ackn ow led gm e nt cycle be fo re ho ldin g
the SCL line low again (i.e., the USI Counter Register must be set to 14 before releasing SCL at (D)) .
Depending on the R/W bit the master or slave enables its output. If the bit is set, a master read operation
is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowl-
edge (E).
6. Multiple bytes can now be transmitted, all in same direction, until a stop cond itio n is give n by the mast er
(F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last received. When the
master does a read operation it must terminate the operation by forcing the acknowledge bit low after the last byte
transmitted.
15.4.1 Start Condition Detector
The start condition detector is shown in Figure 15-6. The SDA line is delayed (in the range of 50 to 300 ns) to
ensure valid sampling of the SCL line. The start condition detector is only enab le d in t wo -wir e m od e.
PS ADDRESS
1 - 7 8 9
R/W ACK ACK
1 - 8 9
DATA ACK
1 - 8 9
DATA
SDA
SCL
A B D EC F
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Figure 15-6. Start Condition Detector, Logic Diagram
The start condition detector works asynchronously and can therefore wake up the processor from power-down
sleep mode. H oweve r, the pr otocol used might have restrictions on the SCL hold time. Therefore, when using this
feature the oscillator start-up time (set by CKSEL fuses, see “Clock Sources” on page 26) must also be taken into
consideration. Refer to the description of the USISIF bit on page 181 for further details.
15.4.2 Clock speed considerations
Maximum frequency for SCL and SCK is fCK / 2. This is also th e maximum data transm it and receive rate in both
two- and three-wire mode. In two-wire slave mode the Two-wire Clock Control Unit will hold the SCL low until the
slave is ready to receive more data. This may reduce the actual data rate in two-wire mode.
15.5 Alternative Use
The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below
are some examples.
15.5.1 Half-Duplex Asynchronous Data Transfer
Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher perfor-
mance UART than by software, only.
15.5.2 4-Bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. N ote that if the counter is clocked
externally, both clock edges will increment the counter value.
15.5.3 12-Bit Timer/Counter
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter .
15.5.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag
and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit.
15.5.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR
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15.6 Program Examples
15.6.1 Example: SPI Master Operation
The following code demonstrates how to use the USI module as a SPI Master:
See “Code Examples” on page 6.
The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and
USCK pins have been enabled as outputs in the data direction register (DDRx). The value stored in register r16
prior to the function is called is transferred to the slave device, and when the transfer is completed the data
received from the slave is stored back into register r16.
The first two instructions clear the USI Counter Overflow Flag and the USI counter val ue. Th e next two in stru ctio ns
set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The transfer loop is then
repeated 16 times.
Assembly Code Example
SPITransfer:
out USIDR,r16
ldi r16,(1<<USIOIF)
out USISR,r16
ldi r17,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
out USICR,r17
in r16, USISR
sbrs r16, USIOIF
rjmp SPITransfer_loop
in r16,USIDR
ret
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15.6.2 Example: Full-Speed SPI Master
The following code demonstrates how to use the USI as an SPI master with maximum speed (fSCK = fCK/2).
See “Code Examples” on page 6.
Assembly Code Example
SPITransfer_Fast:
out USIDR,r16
ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
out USICR,r16 ; MSB
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16
out USICR,r17
out USICR,r16 ; LSB
out USICR,r17
in r16,USIDR
ret
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15.6.3 Example: SPI Slave Operation
The following code demonstrates how to use the USI module as a SPI Slave.
See “Code Examples” on page 6.
The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and
USCK pins have been en abled as ou tputs in the port da ta dir ection register. The val ue stored in register r16 prior to
the function is called is transferred to the master device, and when the transfer is completed the data received from
the master is stored back into the register r16.
Note that the first two instructions are for initializatio n, only, and need only be executed once. These instructio ns
set three-wire mode and positive edg e clock. The loop is repeated until the USI Counter Overflow Flag is set.
Assembly Code Example
init:
ldi r16,(1<<USIWM0)|(1<<USICS1)
out USICR,r16
...
SlaveSPITransfer:
out USIDR,r16
ldi r16,(1<<USIOIF)
out USISR,r16
SlaveSPITransfer_loop:
in r16, USISR
sbrs r16, USIOIF
rjmp SlaveSPITransfer_loop
in r16,USIDR
ret
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15.7 Register Descriptions
15.7.1 USICR – USI Control Register
The USI Control Register includes bits for interrupt enable, settin g the wire mode, selecting the clock and clock
strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt and USISIE and
the Global Interrupt Enable Flag are set to one the interrupt will be executed immediately. Refer to the USISIF bit
description on page 142 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and USIOIE and the
Global Interrupt Enable Flag are set to one the interrupt will be executed immediate ly. Refer to the USIOIF bit
description on page 143 for further details.
• Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used, as shown in Table 15-2 on pag e 141.
Basically, only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the
mode selected and will always have the same function. The counter and USI Data Register can therefore be
clocked externally and data input sampled, even when outputs are disabled.
Bit 76543210
0x2A (0x4A) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0
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Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion
between the modes of operation.
• Bits 3:2 – USICS[1:0]: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the out-
put is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source
(USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is
transparent and therefore the output is changed immediately.
Clearing the U SICS[1:0] bits enables software strobe option. When using this option, writing a one to the USICLK
bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is
no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit.
Table 15-2. Relationship between USIWM[1:0] and USI Operation
USIWM1 USIWM0 Description
00
Outputs, clock hold, and start detector disa b le d.
Port pins operate as normal.
01
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORTA
register. However, the corresponding DDRA bi t still controls the data direction.
When the port pin is set as input the pin pull-up is controlled by the PORTA bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port
operation. When opera ting as master, clock pulses are software generated by
toggling the PORTA register, while the data direction is set to output. The
USITC bit in the USICR Register can be used for this purp ose.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
use open-collector output drives. The output drivers are enabled by setting the
corresponding bit for SDA and SCL in the DDRA register.
When the output driver is enabled for the SDA pin, the output driver will force
the line SDA low if the output of the USI Data Register or the corresponding
bit in the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e.,
it is released). When the SCL pin output driver is enabled the SCL line will be
forced low if the corresponding bit in the PORTA register is zero, or by the start
detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the
output is enabled. Clearing the Start Condition Flag (USISIF) release s th e l ine.
The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on
the SDA and SCL port pin are disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also
held low when a counter overflow occurs, and until the Counter Overflow Flag
(USIOIF) is cleared.
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Table 15-3 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI
Data Register an d th e 4- bit coun ter.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the counter to increment by
one, provided that the software clock strobe option has been selected by writing USICS[1:0] bits to zero. The out-
put will change immediately when the clock strobe is executed, i.e., during the same instruction cycle. The value
shifted into the USI Data Register is sampled the previous instruction cycle.
When an exter n al c lock source is sele cte d (U SICS1 = 1) , th e USI CLK function is ch an ged fr om a clo ck s tr ob e to a
Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-
bit counter (see Table 15-3).
The bit will be read as zero.
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to th is bit location toggle s the USCK/SCL valu e either from 0 to 1, or from 1 to 0. The toggling is inde-
pendent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the
corresponding DDR p in must be set as outp ut (to one). T his feature allows easy clo ck generatio n when imple ment-
ing master devices.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC
strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when oper-
ating as a master device.
The bit will read as zero.
15.7.2 USISR – USI Status Register
The Status Register contains interrupt flags, line status flags and the counter value.
• Bit 7 – USISIF: S tart Condition Interrupt Flag
When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has been detected. When
three-wire mode or output disable mode has been selected any edge on the SCK pin will set the flag.
If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is
set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start
detection hold of USCL in two-wire mode.
Table 15-3. Re lat i on ship betw ee n th e USICS1:0 and USICLK Se ttin g
USICS1 USICS0 USICLK Clock Source 4-bit Counter Clock Source
0 0 0 No Clock No Clock
0 0 1 Software clock strobe (USICLK) Software clock strobe (USICLK)
0 1 X Timer/Counter0 Compare Match A Timer/Counter0 Compare Match
1 0 0 External, positive edge External, both edges
1 1 0 External, negative edge External, both edges
1 0 1 External, positive edge Software clock strobe (USITC)
1 1 1 External, negative edge Software clock strobe (USITC)
Bit 7 6 5 4 3 2 1 0
0x2B (0x4B) USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 USISR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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A start condition interrupt will wakeup the proces sor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the USIOIE bit in
USICR and the Global Interrupt Enable Flag are set an interrupt will also be generated when the flag is set. The
flag will only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold
of SCL in two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been detected. The flag is
cleared by writing a one to this bit. Note that this is not an interrupt flag. This signal is useful when implemen ting
two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The flag is only valid
when two-wire mode is used. This signal is use ful when implementing Two-wire bus master arbitration.
• Bits 3:0 – USICNT[3:0]: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the
CPU.
The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a
Timer/Counter0 Compare Match, o r by softwa re using USICLK or USIT C strobe bits. The clock source depends on
the setting of the USICS[1:0] bits.
For external clock operation a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by choosing an external clock source (USICS1 = 1) and writing a one to
the USICLK bit.
Note that even when no wire mode is selected (USIWM[1:0] = 0) the external clock input (USCK/SCL) can s till be
used by the counter.
15.7.3 USIDR – USI Data Register
The USI Data Register can be accessed directly but a copy of the data can also be found in the USI Buffer
Register.
Depending on the USICS[1:0] bits of the USI Control Register a (left) shift operation may be performed. The shift
operation can be synchronised to an external clock edge, to a Timer/Counter0 Compare Match, or directly to soft-
ware via the USICLK bit. If a serial clock occurs at the same cycle the register is written, the register will contain the
value written and no shift is performed.
Note that even when no wir e mode is selected (USIWM[1:0] = 0) both the external data input (DI/SDA) and the
external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to the most significant
bit (bit 7) of the USI Data Register. The output latch ensures that da ta inpu t is sampled and data output is ch an ged
on opposite clock edges. The latch is open (transparent) during the first half of a serial clock cycle when an exter-
Bit 7 6 5 4 3 2 1 0
0x2C (0x4C) MSB LSB USIDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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nal clock source is selected (USICS1 = 1) and constantly open when an internal clock source is used (USICS1 =
0). The output will be changed immediately when a new MSB is written as long as the latch is open.
Note that the Data Direction Register bit corresponding to the output pin must be set to one in order to enable da ta
output from the USI Data Register.
15.7.4 USIBR – USI Buffer Register
Instead of reading data from the USI Data Register the USI Buffer Register can be used. This makes controlling
the USI less time critical and gives the CPU more time to handle other program tasks. USI flags as set similarly as
when reading the USIDR register.
The content of the USI Data Register is loaded to the USI Buffer Register when the tran sfer has been completed.
Bit 7 6 5 4 3 2 1 0
0x2D (0x4D) MSB LSB USIBR
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
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16. USART (USART0 & USART1)
16.1 Features
•Full Duplex Operation (Indep endent Serial Receive and Tra nsmit Registers)
•Asynchronous or Synchronous Operation
•Master or Slave Clocked Synchronous Oper ation
•High Resolution Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
•Odd or Even Parity Generation and Parity Check Supported by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communication Mode
•Double Speed Asynchronous Communication Mode
•Start F rame Detection
16.2 USART0 and USART1
The ATtiny1634 has two Universal Synchronous and Asynchron ous serial Receiver and Transmitters; USART0
and USART1.
The functionality for all USART’s is described below, most register and bit references in this section are written in
general form. A lower case “n” replaces the USART number.
USART0 and USART1 have different I/O registers as shown in “Register Summary” on page 273.
16.3 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial
communication device.
A simplified block diagram of the USART Transmitter is shown in Figure 16-1 on page 146. CPU accessible I/O
Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in “PRR – Power Reduction Register” on page 38 must be dis-
abled by writing a logical zero to it.
The Power Reducion USART1 bit, PRUSART1, in “PRR – Power Reduction Register” on page 38 must be dis-
abled by writing a logical zero to it.
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Figure 16-1. USART Block Diagram()
For USART pin placement, see Figure 1-1 on page 2 and “Alternate Port Functions” on page 59.
The dashed boxes in the block diagram of Figure 16-1 illustrate the three main parts of the USART, as fol-
lows(listed from the top):
• Clock generator
• Transmitter
• Receiver
The clock generation logic consists of synchronization logic (f or external clock input in synchronous slave opera-
tion), and the baud rat e ge n er at or. Th e tra n sfe r clo ck pin (X CKn ) is only used in synchronous tran sfe r m od e.
The transmitter consists of a single write buffer, a serial shift register, a parity generator and control logic for han-
dling different serial frame forma ts. The write buffer allows a continuous transfer of data with out delay between
frames.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD
PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
UCSRD
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
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The receiver is the m ost comp lex pa rt of the USART modu le due to its clock and data recovery units. The recovery
units are used for asynchronous data reception. In addition to the recovery units, the receiver includes a parity
checker, control logic, a ahift register and a two level receive buffer (UDRn). The receiver supports the same frame
formats as the transmitter, and can detect the following errors:
• Frame Error
• Data Overrun Error
• Parity Errors.
In order for the USART to be operative the USARTn powe r reducion bit must be disabled. See “PRR – Power
Reduction Register” on page 38.
16.4 Clock Generation
The clock generation logic creates the base clock for the transmitter and receiver. A block diagram of the clock
generation logic is shown in Figure 16-2.
Figure 16-2. Clock Generation Logic, Block Diagram
Signal description for Figure 16-2:
txclk Transmitter clock (Internal Signal)
rxclk Receiver base clock (Internal Signal)
xcki Input from XCKn pin (internal Signal). Used for synchronous slave operation
xcko Clock output to XCKn (Internal Signal). Used for synchronous master operation
fOSC XTAL pin frequency (System Clock)
The USART supports four modes of clock operation, as follows:
• Normal asynchronous mode
• Double speed asynchronous mode
• Master synchronous mode
• Slave synchronous mode
The UMSELn bit selects between asynchronous and synchronous operation. In asynchronous mode, the speed is
controlled by the U2X bit.
Prescaling
Down-Counter /2
UBRR
/4 /2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK rxclk
0
1
1
0
Edge
Detector
UCPOL
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In synchronous mode, the direction bit of the XCKn pin (DDR_XCKn) in the Data Direction Register where the
XCKn pin is located (DDRx) controls whether the clock source is internal (master mode), or external (slave mode).
The XCKn pin is active in synchronous mode, only.
16.4.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The
description in this section refers to Figure 16-2 on page 147.
The USART Baud Rate Reg ister ( UBRRn) a nd the do wn-cou nter connected to it functio n as a programmable pres-
caler, or baud rate generator. The down-counter, running at system clock (fosc) is loaded with the UBRRn value
each time the counter has counted down to zero, or when UBRRnL is written.
A clock is generated each time the counter reaches zero. This is the baud rate generator clock output and has a
frequency of fosc/(UBRRn+1). Depending on the mode of operation the transmitter divides the baud rate generator
clock output by 2, 8 or 16. The baud rate ge nerator output is used directly by th e receiver’s clock and data recovery
units. However, the recovery units use a state machine that uses 2, 8 or 16 states, depending on mode set by
UMSELn, U2Xn and DDR_XCKn bits.
Table 1 6-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn
value for each mode of oper ation using an internally generated clock source.
Note: 1. Baud rate is defined as the transfer rate in bits per second (bps)
Signal description for Table 16-1:
BAUD Baud rate (in bits per second, bps)
fOSC System oscillator clock frequency
UBRR Contents of the UBRRHn and UBRRLn registers, (0-4095)
Some examples of UBRRn values for selected system clock frequencies are shown in “Examples of Baud Rate
Setting” on page 163.
16.4.2 Double Sp eed Operation
The transfer rate can be doubled by set ting the U2Xn bi t. Setting this bit only has effect in asynchronous mode of
operation. In synchronous mode of operation this bit should be cleared.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note, however, that in this case the receiver will use half the number of samples,
only. In double speed mode, the number of data and clock recovery sampels are reduced from 16 to 8, and there-
fore a more accurate baud rate setting and system clock are required.
There are no downsides for the transmitter.
Table 16-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Baud Rate(1) UBRR Value
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
BAUD fOSC
16 UBRRn1+
------------------------------------------=
UBRRnfOSC
16BAUD
------------------------1–=
BAUD fOSC
8UBRRn1+
---------------------------------------=
UBRRnfOSC
8BAUD
-------------------- 1–=
BAUD fOSC
2UBRRn1+
---------------------------------------=
UBRRnfOSC
2BAUD
-------------------- 1–=
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16.4.3 External Clock
External clocking is used in synchronous slave modes of operation. To minimize the chance of meta-stability, the
external clock input from the XCK pin is sampled by a synchronization register. The output from the synchroniza-
tion register then passes through an edge detector before it is used by the transmitter and receiver. This process
introduces a delay of two CPU clocks, and ther efore the ma ximum exter nal clock frequency is l imited b y the follow-
ing equation:
Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin
to avoid possible data loss due to frequency variations.
16.4.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock
output (Master). The dependency between the clock edges and data sampling or data change is the same. The
basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the da ta output
(TxDn) is changed.
Figure 16-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data
change. As Figure 16-3 on page 149 shows, when UCPOLn is zero the data will be changed at rising XCKn edge
and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at
rising XCKn edge.
16.5 Frame Formats
A serial frame is defined to be one character of data bits with synchronizatio n bit s ( sta rt a nd stop bits), and option-
ally a parity bit for error checking. The USART accepts all 30 co mbinations of the following as valid frame formats:
• Start bit: 1
• Data bits: 5, 6, 7, 8, or 9
• Parity bit: no, even, or odd parity
• Stop bits: 1, or 2
fXCKn fOSC
4
-----------
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
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A frame begins with the start bit followed by the least significant data bit. Then follows the other data bits, the last
one being the most significan t bi t. If enab led , the par ity b it is inserted after the data bits, before the stop bits. When
a complete frame has been transmitted it can be directly followed by a new frame, or the communication line can
be set to an idle (high) state.
Figure 16-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional.
Figure 16-4. Frame Formats
Signal description for Figure 16-4:
St Start bit (always low)
(n) Data bits (0 to 4/5/6/7/8)
PParity bit, if enabled (odd or even)
Sp Stop bit (always high)
IDLE No transfers on the communication line (RxDn or TxDn). (high)
The frame format used by the USART is set by the UCSZn, UPMn and USBSn bits, as follows:
• The USART Character SiZe bits (UCSZn) select the number of data bits in the frame
•The USART Parity Mode bits (UPMn) choose the type of parity bit
• The selection between one or two stop bits is done by the USART Stop Bit Select bit (USBSn). The receiver
ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop
bit is zero.
The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all
ongoing communication for both the receiver and transmitter.
16.5.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclu-
sive or is inverted. The relation between the parity bit and data bits is as follows:
... where:
PEVEN Parity bit using even parity
PODD Parity bit using odd parity
dnData bit n of the character
If used, the parity bit is located between the last data bit and the first stop bit of a serial frame.
10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)
FRAME
PEVEN dn1–d3d2d1d00=
PODD dn1–d3d2d1d01=
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16.6 USART Initialization
The USART has to be initialized be fore any communica tion can take place. The initialization process normally con-
sists of setting the baud rate, setting frame format and, depending on the method of use, enabling the transmitter
or the receiver. For interrupt driven USART operation, the global interrupt flag should be cleared and the USART
interrupts should be disabled.
Before re-initializa ting baud rate or frame format, it shoul d be che cked that th ere are no ongoing transmission s dur-
ing the period the registers are changed. The TXCn flag can be used to check that the transmitter has completed
all transfers, and the RXCn flag can be used to check that there are no un read data in the receive buffer. Note that,
if used, the TXCn flag must be cleared before each transmission (before UDRn is written).
The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume asynchronous operation using po lling (no interrupts enabled) and a fixed
frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is
assumed to be stored in the r17:r16 Registers.
Note: 1. See “Code Examples” on page 6.
More advanced initialization routines can be made that include frame format as parameters, disable interrupts and
so on. However, m any applications use a fixed setting of the baud and control registers, and for these types of
applications the initialization code can be placed directly in th e main rou tine, or be combined with initialization code
for other I/O modules.
Assembly Code Example(1)
USART_Init:
; Set baud rate
out UBRRnH, r17
out UBRRnL, r16
; Enable receiver and transmitter
ldi r16, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r16
; Set frame format: 8data, 2stop bit
ldi r16, (1<<USBSn)|(3<<UCSZn0)
out UCSRnC,r16
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
/* Set baud rate */
UBRRnH = (unsigned char)(baud>>8);
UBRRnL = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set frame format: 8data, 2stop bit */
UCSRnC = (1<<USBSn)|(3<<UCSZn0);
}
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16.7 Data Transmission – The USART Transmitter
The USART transmitter is enabled by setting the Transmit Enable bit (TXENn). When the transmitter is enabled,
the normal port operation of the TxDn pin is overridden by the USART and given the function as the transmitter’s
serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmis-
sions. If synchronous operation is used, the clock on the XCKn pin will be overridden and used as transmission
clock.
16.7.1 Sending Frames with 5 to 8 Data Bits
A data transmission is initiated by loading the transmit buffer with the data to be transmitte d. The CPU can load the
transmit buffer by writing to the UDRn register. The buffered data in the transmit buffer will be moved to the shift
register when the it is ready to send a new frame. The shift register is loaded with new data if it is in idle state (no
ongoing transmission), or immediately after the last stop bi t of the previous frame is transmitted. When the shift
register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Rate Register, the
U2Xn bit or by XCKn, depending on the mode of operation.
The following code examples show a simple USART transmit function based on polling of the Data Register Empty
flag (UDREn). When using frames with less than eight bits, the most significant bits written to UDRn are ignored.
The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is
assumed to be stored in register R16
Note: 1. See “Code Examples” on page 6.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with
new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into
the buffer.
Assembly Code Example(1)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
;
/* Put data into buffer, sends the data */
UDRn = data;
}
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16.7.2 Sending Frames with 9 Data Bit
If 9-bit characte rs are used, the ninth bit must b e written to the TXB8 bit in UCSRnB b efore the low byte of th e char-
acter is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For
the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
Notes: 1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRnB
is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization.
2. See “Code Examples” on page 6.
The ninth bit can be used for indicating an address frame when using multi processor communication mode or for
other protocol handling as for ex ample synchronization.
16.7.3 Transmitter Flags and In terrupts
The USART transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit
Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty flag (UDREn) indicates whether the transmit buffer is ready to receive new data. This bit
is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that
has not yet been moved into the shift register. For compatibility with future devices, always write this bit to zero.
Assembly Code Example(1)(2)
USART_Transmit:
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Copy 9th bit from r17 to TXB8
cbi UCSRnB,TXB8
sbrc r17,0
sbi UCSRnB,TXB8
; Put LSB data (r16) into buffer, sends the data
out UDRn,r16
ret
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn))) )
;
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRnB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDRn = data;
}
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When the Data Register Empty Interrupt Enable bit (UDRIEn) is set, the USART Data Register Empty Interrupt will
be executed as long as UDREn is set (and provided that global interrupts are enabled). UDREn is cleared by writ-
ing UDRn. When interrupt-driven data transmission is used, the Da ta Register Empt y interrupt rout ine must either
write new data to UDRn in order to clear UDREn o r disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete flag (TXCn) is set when the entire frame in the transmit shift register has been shifted out
and there are no new data currently present in the transmit buffer. The TXCn flag is automatically cleared when a
transmit complete interrupt is executed, or it can be cleared by writing a one to its location. The TXCn flag is useful
in half-duplex communication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable bit (TXCIEn) is set, the U SART Transmit Complete Interrupt will be
executed whe n the TXCn flag be comes set (and pr ovided that global in terrupts are enab led). When the tran smit
complete interrupt is used, the interrupt handling routine does not have to clear the TXCn flag, since this is done
automatically when the interrupt is executed.
16.7.4 Parity Generator
The Parity Generator calculates the pa rity bit for the se ri a l fr ame da ta. When pa rity bit is enable d ( UPM n1 = 1), the
transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.
16.7.5 Disabling the Transmitter
Clearing TXENn will disable the transmitter but the change will not become effective before any ongoing and pend-
ing transmissions are completed, i.e. not before the transmit shift register and transmit buffer register are cleared of
data to be transmitted. When disabled, the transmitter will no longer override the TxDn pin.
16.8 Data Reception – The USART Receiver
The USART receiver is enabled by wr it ing the Receive Enable bit (RXENn). When the rece iver is enabled, the no r-
mal operation of the RxDn pin is overridden by the USART and given the function as the receive r’s serial input. The
baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If
synchronous operation is used, the clock on the XCKn pin will be used as transfer clock.
16.8.1 Receiving Frames with 5 to 8 Data Bits
The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled
at the baud rate, or XCKn clock, and then shifted into the receive shift register until the first stop bit of a frame is
received. A second stop bit will be ignored by the receiver. When the first stop bit is received, i.e., a complete serial
frame is present in the receive shift register, the contents of it will be moved into the receive buffer. The receive
buffer can then be read by reading UDRn.
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The following code example shows a simple USART receive function based on polling of the Receive Complete
flag (RXCn). When using fram es with less than eight bits the most significant bits of the data read from the UDRn
will be masked to zero. The USART has to be initialized before the function can be used.
Note: 1. See “Code Examples” on page 6.
The function simply waits for dat a to be present in the receive buffer by checking the RXCn Flag, be fore reading
the buffer and returning the value.
16.8.2 Receiving Frames with 9 Data Bits
If 9-bit characters are used the ninth bit must be read from the RXB8n bit before reading the low bits from UDRn.
This rule applies to the FEn, DORn and UPEn status flags, as well. Status bits must be read before data from
UDRn, since reading UDRn will change the state of the receive buffer FIFO and, consequently, state of TXB8n, FE,
DORn and UPEn bits.
The following code example shows a simple USART receive function that handles both nine bit characters and the
status bits.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
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Note: 1. See “Code Examples” on page 6.
The receive function example reads all the I/O Registers into the Register File before any computation is done.
This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early
as possible.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
in r18, UCSRnA
in r17, UCSRnB
in r16, UDRn
; If error, return -1
andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr r17
andi r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRnA;
resh = UCSRnB;
resl = UDRn;
/* If error, return -1 */
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
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16.8.3 Receive Compete Flag and Interrupt
The USART receiver has on e fla g th at ind ica te s the rec eiv er stat e.
The Receive C omp lete flag (RXCn) indic ates if th ere are unrea d da ta pr esen t in t he rec eive buff er. T his f lag is set
when unread data exist in the receive buffer, a nd cleared wh en the receive buffer is empty (i.e., it does not contain
any unread data). If the receiver is disabled (RXENn = 0), the receive buffer will be flushed and, consequently, the
RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) is set, the USART Receive Complete interrupt will be exe-
cuted as long as the RXCn flag is set (a n d pr ov ide d tha t global interrupts are enabled). When interrupt-driven da ta
reception is used, the rece ive complete routine must read the received data from UDRn in order to clear the RXCn
flag, otherwise a new interrupt will occur once the interrupt routine terminates.
16.8.4 Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn).
All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer
together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCS-
RnA must be read be fore the rec eive buff er (UDRn) , since reading the UDRn I/O location changes the buffer read
location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upw ard compatibility of future
USART implemen ta tio ns . None of th e Err or Flag s can ge ne r ate inte rr upts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive
buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the
stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions
and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver
ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writ-
ing to UCSRnA.
The Data Over Ru n ( DO R n) F lag in dica te s d a ta loss due to a receiver buffer full condition. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last
read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag in dicates that the next frame in the re ceive buffer had a Par ity Error wh en received. If
Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set
this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 150 and “Parity
Checker” on page 157.
16.8.5 Parity Checker
The parity checker is active when the high USART Parity Mode bit (UPMn1) is set. The type of parity check to be
performed (odd or even) is selected by the UPMn0 bit . When enabled, the parity checker calcu lates the parity of
the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. Th e Par ity Er ror flag ( UPEn ) can
then be read by software to check if the frame had a parity error.
If parity checking is enabled, the UPEn bit is set if the next character that ca n be read from the receive b uffer h ad a
parity error when received. This bit is valid until the receive buffer (UDRn) is read.
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16.8.6 Disabling the Receiver
Unlike the transmitter, the receiver is disabled immediately and any data from ongoing receptions will be lost.
When disabled (RXENn = 0), the receiver will no longer override the normal function of the RxDn port pin and the
FIFO buffer is flushed, with any remaining data in the buffer lost.
16.8.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents.
Unread data will be lost. To flush the buffer during normal operation, due to for instance an error condition, read the
UDRn until the RXCn flag is cleared.
The following code example shows how to flush the receive buffer.
Note: 1. See “Code Examples” on page 6.
16.9 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clo ck to the incoming asynchro-
nous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit,
thereby improving the noise immunity of the receiver. The asynchronous reception operational range depends on
the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
16.9.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes the internal clock to the incoming serial frames. Figure 16-5 illustrates the
sampling pro cess of th e start b it of an in coming f rame. In normal mode the sample rate is 16 times the baud rate,
in double speed mode eight times. The horizontal arrows illustrate the sync hronization variation due to the sam-
pling process. Note the larger time variation when using the double speed mode of operatio n (U2Xn = 1) . Samp les
denoted zero are samples done when the RxDn line is idle (i .e., no communication activity).
Assembly Code Example(1)
USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
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Figure 16-5. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) tra nsition on the RxD n line, the start bit detection
sequence is initiated. In Figure 16 -5, samples are indicated with number s inside boxes and sample number 1
denotes the first zero-sample. The clock recovery logic then uses samples 8, 9, and 10 (in normal mode), or sam-
ples 4, 5, and 6 (in double speed mode), to decide if a valid start bit is received. If two or more of these three
samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the r eceiver sta rts
looking for the next high to low-transition. If, however, a vali d start bit is detected, the clock recovery logic is syn-
chronized and the data recovery can begin . The synchronization process is repeate d for ea ch sta rt bit.
16.9.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a
state machine that has 16 states for each bit in normal mode and eight states for each bit in double speed mode.
Figure 16-6 shows the sampling of the data bits and the parity bit. Each of the samples is given a number th at is
equal to the state of the recovery unit.
Figure 16-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. In the figure, the center samples are emphasized by having the sample
number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels,
the received bit is registered to be a logic one. If two, or all three samples have low levels, the received bit is regis-
tered to be a logic zero. This majority voting process acts as a low pass filter for the incoming signal on the RxDn
pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the receiver only uses the first stop bit of a frame.
Figure 16-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame.
12345678 9 10 11 12 13 14 15 16 12
STARTIDLE
00
BIT 0
3
1234 5 678120
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12345678 9 10 11 12 13 14 15 16 1
BIT n
1234 5 6781
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
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Figure 16-7. Stop Bit Sampling and Next Start Bit Sampling
The stop bit is subject to the same majority voting as the other bits in the frame. If the stop bit is registered to have
a logic low value, the Frame Error flag (FEn) will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. In normal spee d mod e, the first low level samp le can be at po int marked ( A) in Fig ure 16 -7 . In do u-
ble speed mode the first low level must be delayed to (B). Point (C) marks the full length of a stop bit.
The early start bit detection influences the operational range of the receiver.
16.9.3 Asynchronous Operational Range
The operational range of the receiver depends on the mismatch between the received bit rate and the internally
generated baud rate. If the transmitter is sending fram es at too fast or too slow bit rates, or the intern ally generated
baud rate of the receiver does not have a similar base frequ ency (see Table 16-2 on page 160), the receiver will
not be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate.
... where:
DSum of character size and parity size (D = 5 to 10 bit)
SSamples per bit, 16 for normal speed mode, or 8 for double speed mode.
SFFirst sample number used for majority voting, 8 (normal speed), or 4 (double)
SMMiddle sample number for majority voting, 9 (normal speed), or 5 (double speed)
Rslow The ratio of the slowest incoming data rate that can be accepted with respect to
the receiver baud rate.
Rfast The ratio of the fastest incoming data rate that can be accepted with respect to
the receiver baud rate.
Table 16-2 on page 160 and Table 16-3 on page 161 list the maximum receiver baud rate error that can be toler-
ated. Note that Normal Speed mode has higher toleration of baud rate variations.
12345678 9 10 0/1 0/1 0/1
STOP 1
1234 5 6 0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A) (B) (C)
Table 16-2. Recommended Maximum Receiver Baud Rate Error in Normal Speed Mode.
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
5 93.20 106.67 +6.67/-6.8 ± 3.0
6 9 4.12 105.79 +5.79/-5.88 ± 2.5
7 9 4. 81 105.11 +5.11/-5.19 ± 2.0
Rslow D1+S
S1–DSSF
++
-------------------------------------------=
Rfast D2+S
D1+SS
M
+
-----------------------------------=
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The recommendations of the maximum receiver baud rate error are made under the assumption that the receiver
and transmitter divide the maximum total error equally.
There are two possible sources for the receivers baud rate error:
• The system clock of the receiver will always have some minor instability over the supply voltage range and the
temperature range
• The second source for error is more controllable. The baud rate generator can not always do an exact division
of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low
error should be used, if possible
16.9.4 Start Frame Detection
The USART start frame detector can wake up the MCU from Power-down, Standby or ADC Noise Reduction sleep
mode when it detects a start bit.
When a high-to-low transition is detected on RxDn, the internal 8 MHz o scillator is powered up and the USART
clock is enabled. After start-up the re st of the data frame can be received, provided that the baud r ate is slow
enough in relation to the internal 8 MHz oscillator start-up time. Start-up time of the internal 8 MHz oscillator varies
with supply voltage and temperature.
The USART start frame detection works both in asynchronous and synchronou s modes. It is enabled by writning
the Start Frame Detection Enable bit (SFDEn). If the USART Start Interrupt Enable (RXSIE) bit is set, the USART
Receive Start Interrupt is generated immediately when start is detected.
When using the feature without start interrupt, the start detection logic activates the internal 8 MHz oscillator and
the USART clock while the frame is being received, only. Other clocks remain stopped until the Receive Complete
Interrupt wakes up the MCU.
The maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from, as
follows:
• Idle or ADC Noise Reduction sleep mode: system clock frequency divided by four.
• S tandby or Power-down: 500 kbps.
8 9 5.36 104.58 +4.58/-4.54 ± 2.0
9 9 5.81 104.14 +4.14/-4.19 ± 1.5
10 96.17 103.78 +3.78/-3.83 ± 1.5
Table 16-3. Recommended Maximum Receiver Baud Rate Error in Double Speed Mode.
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Tota l Error (%) Recommended Max
Receiver Error (%)
5 94.12 105.66 + 5.66/-5.88 ± 2.5
6 94.92 104.92 + 4.92/-5.08 ± 2.0
7 95.52 104,35 + 4.35/-4.48 ± 1.5
8 96.00 103.90 + 3.90/-4.00 ± 1.5
9 96.39 103.53 + 3.53/-3.61 ± 1.5
10 96.70 103.23 +3.23/-3.30 ± 1.0
Table 16-2. Recommended Maximum Receiver Baud Rate Error in Normal Speed Mode.
D
# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max
Receiver Error (%)
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The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up from, as
follows:
• Idle sleep mode: the same as in active mode.
• Other sleep modes: see Table 16-4 and Table 16-5.
16.10 Multi-processor Communication Mode
Setting the Multi-processor Commun ication Mode bit (MPCMn) enables a filtering function of incoming frames
received by the USART receiver. Frames that do not contain address information will be ignored and not put into
the receive buffer. In a system with multiple MCUs that communicate via the same serial bus this effectively
reduces the number of incom ing frames that has to be handled by the CPU. Th e transmitter is unaffected by the
MPCMn bit, but has to be used differently when it is a part of a system utilizing the multi-processor communication
mode.
If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame
contains data or address information. If the receiver is set up for frames with nine data bits, then the ninth bit
(RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is
one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
The multi-processor co mmunication mode enables sever al slave MCUs to receive data from a master MCU. This is
done by first decoding an addr ess fra me to find ou t which MCU has been addressed. If a particular slave MCU has
Table 16-4. Maximum Total Baudrate Error in Normal Speed Mode
Baudrate
Frame Size
5678910
0 – 28.8 kbps +6.67
-5.88 +5.79
-5.08 +5.11
-4.48 +4.58
-4.00 +4.14
-3.61 +3.78
-3.30
38.4 kbps +6.63
-5.88 +5.75
-5.08 +5.08
-4.48 +4.55
-4.00 +4.12
-3.61 +3.76
-3.30
57.6 kbps +6.10
-5.88 +5.30
-5.08 +4.69
-4.48 +4.20
-4.00 +3.80
-3.61 +3.47
-3.30
76.8 kbps +5.59
-5.88 +4.85
-5.08 +4.29
-4.48 +3.85
-4.00 +3.48
-3.61 +3.18
-3.30
115.2 kbps +4.57
-5.88 +3.97
-5.08 +3.51
-4.48 +3.15
-4.00 +2.86
-3.61 +2.61
-3.30
Table 16-5. Maximum Total Baudrate Error in Double Speed Mode
Baudrate
Frame Size
5678910
0 – 57.6 kbps +5.66
-4.00 +4.92
-3.45 +4.35
-3.03 +3.90
-2.70 +3.53
-2.44 +3.23
-2.22
76.8 kbps +5.59
-4.00 +4.85
-3.45 +4.29
-3.03 +3.85
-2.70 +3.48
-2.44 +3.18
-2.22
115.2 kbps +4.57
-4.00 +3.97
-3.45 +3.51
-3.03 +3.15
-2.70 +2.86
-2.44 +2.61
-2.22
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been addressed, it will receive the following data frames as normal, while the other slav e MCUs will ignore the
received frames until another address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format. The ninth bit (TXB8) must be set
when an address frame is transmitted, an d cleared when a data frame is transmitted. In this case, the slave MCUs
must be set to use a 9-bit character frame format.
The following procedure should be used to exchange data in multi-processor communication mode:
1. All slave MCUs are set to multi-processor communication mode (MPCMn = 1)
2. The master MCU sends an add ress frame, and all slaves receive and read this frame. In the slave MCUs,
the RXCn flag is set as normal
3. Each slave MCU reads UDRn an d determines if it has bee n selected. If so, it clears the MPCMn bit. Else, it
waits for the next address byte and keeps the MPCMn setting
4. The addressed MCU will receive all data frames until a new address frame is received. The other slave
MCUs, which still have the MPCMn bit set, will ignore the data frames
5. When the last data frame is received by the addressed MCU it sets the MPCMn bit and wait s for a new
address frame from master. The process then repeats from step 2
It is possible but impractical to use any of the 5- to 8-bit character frame formats, since the receiver must change
between using n and n+1 character frame formats. This makes full-duplex operation difficult since the transmitter
and receiver use the same character size setting. If 5- to 8-bit character frames are used, the transmitter must be
set to use two stop bits, since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instr uctions (SBI and CBI) to set or clear the MPCMn bit. Th e MPCMn bit shares the
same I/O location as the TXCn flag and this might accidentally be cleared when using SBI or CBI instructions.
16.11 Examples of Baud Rate Setting
Commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in “Exam-
ples of Baud Ra te Setting” on page 163. UBRR values which yield an actual baud rate differing less than 0.5%
from the target baud rate, are shown in bold. Higher error ratings are acceptable, but the receiver will have less
noise resistan ce wh en th e error r atings a re hi gh, e specially for large ser ial frames (see “Asynchrono us Operat ional
Range” on page 160). The error values are calculated using the following equation:
Error[%] BaudRateClosest Match
BaudRate
-------------------------------------------------------- 1–
100%=
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Table 16-6. Examples of UBRR Settings for Commonly Used Oscillator Frequencies
Baud
Rate
(bps)
fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.0000MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%
4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%
9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%
14.4k 3 8.5% 8 -3.5% 70.0% 15 0.0% 8 -3.5% 16 2.1%
19.2k 2 8.5% 6 -7.0% 50.0% 11 0.0% 6 -7.0% 12 0.2%
28.8k 1 8.5% 3 8.5% 30.0% 70.0% 3 8.5% 8 -3.5%
38.4k 1 -18.6% 2 8.5% 20.0% 50.0% 2 8.5% 6 -7.0%
57.6k 0 8.5% 1 8.5% 10.0% 30.0% 1 8.5% 3 8.5%
76.8k – – 1 -18.6% 1 -25.0% 20.0% 1 -18.6% 2 8.5%
115.2k – – 0 8.5% 00.0% 10.0% 0 8.5% 1 8.5%
230.4k – – – – – – 00.0% – – – –
250k––––––––––00.0%
Max. (1) 62.5 kbps 125 kbps 11 5.2 kbps 230.4 kbps 125 kbps 250 kbps
1. UBRR = 0, Error = 0.0%
Table 16-7. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 3.6864MH z f osc = 4.0000MHz fosc = 7.3728MHz
U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1U2Xn = 0U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%
4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%
9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0%
14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%
19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%
28.8k 70.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%
38.4k 50.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%
57.6k 30.0% 70.0% 3 8.5% 8 -3.5% 70.0% 15 0.0%
76.8k 20.0% 50.0% 2 8.5% 6 -7.0% 50.0% 11 0.0%
115.2k 10.0% 30.0% 1 8.5% 3 8.5% 30.0% 70.0%
230.4k 00.0% 10.0% 0 8.5% 1 8.5% 10.0% 30.0%
250k 0 -7.8% 1 -7.8% 00.0% 10.0% 1 -7.8% 3 -7.8%
0.5M – – 0 -7.8% – – 00.0% 0 -7.8% 1 -7.8%
1M ––––––––––0-7.8%
Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps
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1. UBRR = 0, Error = 0.0%
Table 16-8. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.7456MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%
4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%
9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%
14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%
19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%
28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%
38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%
57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%
76.8k 6 -7.0% 12 0.2% 80.0% 17 0.0% 11 0.0% 23 0.0%
115.2k 3 8.5% 8 -3.5% 50.0% 11 0.0% 70.0% 15 0.0%
230.4k 1 8.5% 3 8.5% 20.0% 50.0% 30.0% 70.0%
250k 10.0% 30.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%
0.5M 00.0% 10.0% – – 2 -7.8% 1 -7.8% 3 -7.8%
1M – – 00.0% – – – – 0 -7.8% 1 -7.8%
Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps
1. UBRR = 0, Error = 0.0%
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Table 16-9. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
Baud
Rate
(bps)
fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz
U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1
UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error
2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%
4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%
9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%
14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%
19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%
28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%
38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%
57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%
76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%
115.2k 8 -3.5% 16 2.1% 90.0% 19 0.0% 10 -1.4% 21 -1.4%
230.4k 3 8.5% 8 -3.5% 40.0% 90.0% 4 8.5% 10 -1.4%
250k 30.0% 70.0% 4 -7.8% 8 2.4% 40.0% 90.0%
0.5M 10.0% 30.0% – – 4 -7.8% – – 40.0%
1M 00.0% 10.0%––––––––
Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps
1. UBRR = 0, Error = 0.0%
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16.12 Register Description
16.12.1 UDRn – USART I/O Data Register
The USART transmit data buffer and USART receive data buffer registers share the same I/O address, referred to
as USART Data Register, or UDRn. Data written to UDRn goes to the Transmit Data Buffer register (TXB). Read-
ing UDR returns the contents of the Receive Data Buffer register (RXB).
For 5-, 6-, or 7-bit characters the upper, unused bits will be ignored by the transmitter an d set to zero by the
receiver.
The transmit buffer can only be written when the UDREn flag is set. Data written to UDRn when the UDREn flag is
not set will be ignored. When the transmitter is enabled and data is written to the transmit buffer, the transmitter will
load the data into the transmit shift register when it is empty. The data is then serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, Read-Modify-Write instructions (SBI and CBI) should not be
used to access this location. Care should also be taken wh en using bit test instructions (SBIC and SBIS), since
these also chan ge the state of the FIFO.
16.12.2 UCSRnA – USART Control and Status Register A
• Bit 7 – RXCn: USART Receive Complete
This flag is set when there is unread data in the receive buffer, and cleared when the receive buffer is empty (i.e.,
does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently
the RXCn flag will become zero. The flag can be used to generate a Receive Complete interrupt (see RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data
currently prese nt in the transm it buffer (UDRn) . The TXCn flag bit is automatically cleared when a transmit com-
plete interrupt is executed, or it can be cleared by wri ting a one to its bit location. The flag can generate a Transmit
Complete interrupt (see TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
Bit 76543210
0x20 (0x40) RXB[7:0] UDR0 (Read)
0x20 (0x40) TXB[7:0] UDR0 (Write)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x73) RXB[7:0] UDR1 (Read)
(0x73) TXB[7:0] UDR1 (Write)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x26 (0x46) RXC0 TXC0n UDRE0n FE0 DOR0 UPE0 U2X0 MPCM0 UCSR0A
Read/WriteRR/WRRRRR/WR/W
Initial Value00100000
Bit 76543210
(0x79) RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 UCSR1A
Read/WriteRR/WRRRRR/WR/W
Initial Value00100000
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This flag indicates the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty,
and therefore ready to be written. The UDREn flag can gen erate a Da ta Register Empty interrupt ( see UDRIEn bit).
The UDREn flag is set after a reset to indicate that the transmitter is ready.
• Bit 4 – FEn: Frame Error
This flag is set if the next character in th e receive buffer had a frame erro r when received (i .e. when the first stop bit
of the next character in the receive bu ffer is zero). This bit is valid until the receive buffer (UDRn) is read. Th e FEn
bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing the register.
• Bit 3 – DORn: Data OverRun
This bit is set if a Data Over Run condition is detected. A data o verrun occurs when the re ceive buffer is full (two
characters), there is a new character waiting in the receive shift register, and a new start bit is detected. This bit is
valid until the receive buffer (UDRn) is read.
Always set this bit to zero when writing the register.
• Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a parity error when received and the parity checking
was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read.
Always set this bit to zero when writing the register.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doublin g the transfer
rate for asynchronous commu nication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication Mode. When the bit is written to one, all the incoming frames
received by the USART receiver that do not contain address information will be ignored. The transmitter is unaf-
fected by the MPCMn bit. For more detailed information, se e “ Multi-proce ssor Communicatio n Mode” on page 162 .
16.12.3 UCSRnB – USART Control and Status Register B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag.
A USART Receive Comple te interrupt will be generated only if the RXCIEn bit, the Global Interrupt Flag, and the
RXCn bits are set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag.
Bit 76543210
0x25 (0x45) RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 UCSR0B
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value00000000
Bit 76543210
(0x78) RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 UCSR1B
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value00000000
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A USART Transmit Complete interrupt will be generated only if the TXCIEn bit, the Global Interrupt Flag, and the
TXCn bit are set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn flag.
A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag
in SREG is written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver. When enabled, the receiver will override normal port operation
for the RxDn pin.
Writing this bit to zero disables the receiver. Disabling the receiver will flush the rece ive buffer, invalidating FEn,
DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. When enabled, the transmitter will override normal port
operation for the TxDn pin.
Writing this bit to zero disables the transmitter. Disabling the transmitter will become effective after ongoing and
pending transmissions are comp leted, i.e., when the transmit shift register and transmit buffer register do not con-
tain data to be transmitted. When disabled, the transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bit combined with the UCSZn[1:0] bits set the number of data bits (Character SiZe) in the frame the
receiver and tran sm itte r us e.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when o perating with seria l frames with n ine data bits. It mu st
be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth da ta bit in th e cha r act er to be tr an smitted when operating with serial frames with nine da ta bits.
It must be written before writing the low bits to UDRn.
16.12.4 UCSRnC – USART Control and Status Register C
• Bits 7:6 – UMSELn[1:0]: USART Mode Select
These bits select the mode of operation of the USART, as shown in Table 16-10.
Bit 7 6543210
0x24 (0x44) UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 UCSR0C
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value0 0000110
Bit 7 6543210
(0x77) UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 UCSR1C
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value0 0000110
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Note: 1. For full description of the Master SPI Mode (MSPIM) Operation, see “USART in SPI Mode” on page 173.
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically gener-
ate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for
the incoming da ta and com p ar e it to the UPMn setting. If a mismatch is detected, the UPEn flag is set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting.
• Bits 2:1 – UCSZn[1:0]: Character Size
The UCSZn[1:0] bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Char acte r Size) in a
frame the Receiver and Transmitter use. See Table 16-13.
Table 16-10. UMSELn Bit Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
10Reserved
1 1 Master SPI (MSPIM)(1)
Table 16-11. Parity Mode Selection
UPMn1 UPMn0 Parity Mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 16-12. USBSn Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 16-13. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
100Reserved
101Reserved
110Reserved
1 1 1 9-bit
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• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn
bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn).
16.12.5 UCSRnD – USART Control and Status Register D
• Bit 7 – RXSIEn: USART RX Start Interrupt Enable
Writing this bit to one enables the interrupt on the RXSn flag. In sleep modes this bit enables start frame detector
that can wake up the MCU when a start condition is detected on the RxDn line.
The USART RX Start Interrupt is generated only, if the RXSIEn bit, the Global Interrupt Enable flag , and RXSn are
set.
• Bit 6 – RXSn: USART RX Start
This flag is set when a start condition is detected on the RxDn line. If the RXSIEn bit and the Global Interrupt
Enable flag are set, an RX Start Interrupt will be generated when this flag is set. The flag can only be cleared by
writing a logical one to the RXSn bit location.
If the start frame detector is enabled and the Global Interrupt Enable Flag is set, the RX Start Interrupt will wake up
the MCU from all sleep modes.
• Bit 5 – SFDEn: Start Frame Detection Enable
Writing this bit to one enables the USART Start Frame Detection mode. The start frame de tector is able to wake up
the MCU from sleep mode when a start condition, i.e. a high (IDLE) to low (START) transition, is detected on the
RxDn line.
Table 16-14. Clock Polarity Settings
UCPOLn Transmitted Data Changed
(Output of TxDn Pin) Received Data Sampled
(Input on RxDn Pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge
Bit 76543210
0x23 (0x43) RXSIE0 RXS0 SFDE0 – – – – – UCSR0D
Read/WriteR/WR/WRRRRRR
Initial Value00100000
Bit 76543210
(0x76) RXSIE1 RXS1 SFDE1 – – – – – UCSR1D
Read/WriteR/WR/WRRRRRR
Initial Value00100000
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For more information, see “Start Frame Detection” on page 161.
• Bits 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny1634 and will always read as zero.
16.12.6 UBRRnL and UBRRnH – USART Baud Rate Registers
• Bits 15:12 – Res: Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when
UBRRnH is written.
• Bits 11:0 – UBRR[11:0]: USAR T Baud Rate Register
This is a 12-bit register which contains the USART baud rate. UBRRnH contains the four most significant bits, and
UBRRnL contains the eight least significant bits of the USART baud rate.
Writing UBRRnL will trigger an immediate update of the baud rate prescaler. Ongoing transmissions by the trans-
mitter and receiver will be corrupted when the baud rate is changed.
Table 16-15. USART Start Frame Detection modes
SFDEn RXSIEn RXCIEn Description
0 X X Start frame detector disabled
100Reserved
101
Start frame detector enabled. RXCn flag
wakes up MCU from all sleep modes
110
Start frame detector enabled. RXSn flag
wakes up MCU from all sleep modes
111
Start frame detector enabled. Both
RXCn and RXSn wake up the MCU from
all sleep modes
Initial Value00000000
Read/Write R R R R R/W R/W R/W R/W
Bit 151413121110 9 8
0x22 (0x42) – – – – UBRR0[11:8] UBRR0H
0x21 (0x41) UBRR0[7:0] UBRR0L
Bit 76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Initial Value00000000
Read/Write R R R R R/W R/W R/W R/W
Bit 151413121110 9 8
(0x75) – – – – UBRR1[11:8] UBRR1H
(0x74) UBRR1[7:0] UBRR1L
Bit 76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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17. USART in SPI Mode
17.1 Features
•Full Duplex, Three-wire Synchronous Data Tra nsfer
•Master Operation
•Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
•LSB First or MSB First Data Transfer (Configurable Data Order)
•Queued Operation (Double Buffered)
•High Resolution Baud Rate Generator
•High Speed Operation (fXCKmax = fCK/2)
•Flexible Interrupt Generation
17.2 Overview
The Universal Sync hronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master
SPI compliant mode of operation.
Setting both UMSELn[1:0] bits to one enables the USART in MSPIM logic. In this mode of operation the SPI mas-
ter control logic takes direct control over the USART resources. These resources include the transmitter an d
receiver shift register and buffers, and the baud rate generator. The parity generato r and checker, the data and
clock recovery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced
by a common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers
changes when using MSPIM.
17.3 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. For USART MSPIM mode of
operation only intern al clock generation (i.e. maste r operation) is su pported. Therefor e, for the USART in MSPIM to
operate correctly, the Data Direction Register (DDRx) where the XCK pin is located must be configured to set the
pin as output (DDR_XCKn = 1) . Preferably the DDR_XCKn should be set up before the USART in MSPIM is
enabled (i.e. before TXENn and RXENn bits are set).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The
baud rate or UBRR setting can therefore be calculated using the same equations, see Table 17-1:
Note: 1. The baud rate is defined as the transfer rate in bits per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC System oscillator clock frequency
UBRRn Contents of UBRRnH and UBRRnL, (0-4095)
17.4 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined
by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 17-1. Data bits are
Table 17-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Calculating Baud Rate(1) Calculating UBRR Value
Synchronous Master
mode
BAUD fOSC
2UBRRn1+
---------------------------------------=
UBRRnfOSC
2BAUD
-------------------- 1–=
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shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabi-
lize. The UCPOLn and UCPHAn functionality is summarized in Table 17-2. Note th at changing the setting of an y of
these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Figure 17-1. UCPHAn and UCPOLn data transfer timing diagrams.
17.5 Frame Formats
A serial frame for the MSPIM is defined to be one characte r of 8 data bits. The USART in MSPIM mode has two
valid frame formats:
• 8-bit data with MSB first
• 8-bit data with LSB first
A frame starts wit h the least or mos t signif icant da ta bit . Then follows the next data bits, up to a total of eight, end-
ing with the most or leas t significant bit, accordingly. When a comple te frame is transmitted, a new fram e can
directly follow it, or the communication line can be set to an idle (high) state.
The UDORDn bit sets the frame format used by the USART in MSPIM mode. The receiver and transmitter use the
same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the
receiver and tran sm itte r .
16-bit data transfer can be achieved by writing two data bytes to UDRn. A USART Transmit Complete interrupt will
then signal that the 16-bit value has been shifted out.
17.5.1 USART MSPIM Initialization
The USART in MSPIM mode has to be initialized before any communication can take place. The initialization pro-
cess normally consists of setting the baud rate, setting master mode of operation, setting fram e format and
Table 17-2. UCPOLn and UCPHAn Functionality
UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)
1 1 3 Setup (Falling) Sample (Rising)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0 UCPHA=1
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enabling the transmitter and the rece iver. Only the transmitter can operate independently. For interrupt dr iven
USART operation, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when doing
the initialization.
Note: To ensure immediate initializatio n of the XCKn output the baud-rate register (UBRRn) must be zero at the time the
transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired
value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before
enabling the transmi tter is not necessary if the initialization is done immediatel y after a reset since UBRRn is reset to
zero.
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongo-
ing transmissions during the period the registers are changed. The TXC n flag can be used to check that the
transmitter has completed all transfers, and the RXCn flag can be used to check that there are no unread data in
the receive buffer. Note that the TXCn flag must be cleared before each transm is sion (b ef or e UDRn is written), if it
is used for this purpose.
The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parame-
ter. For the assembly code, the baud rate parameter is assumed to be stored in registers R17:R16.
Assembly Code Example(1)
USART_Init:
clr r18
out UBRRnH,r18
out UBRRnL,r18
; Setting the XCKn port pin as output, enables master mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18
; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18
; Set baud rate.
; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!
out UBRRnH, r17
out UBRRnL, r18
ret
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Note: 1. See “Code Examples” on page 6.
17.6 Data Transfer
Using the USART in MSPI mode requires the transmitter to be enabled, i.e. the TXENn bit to be set. When the
transmitter is en able d, th e normal port operation of the TxDn pin is overridden and given the function as the trans-
mitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit. When the receiver is
enabled, the normal pin operation o f the RxDn pin is overridden and given the function as the receiver's serial
input. The XCKn will in both cases be used as the transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to UDRn. This
is the case for both sending and re ceiving data since the transmitter controls the transfer clock. The data written to
UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame.
Note: To keep the input buffer in sync with the number of data bytes transmitted, UDRn must be read once for each byte
transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the character last
received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1 first, then byte
2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not
byte 1.
The following code examples show a simple USART in MSPIM mode transfer function based on polling of the Data
Register Empty flag (UDREn) and the Receive Complete flag (RXCn). The USART has to be initialized before the
function can be used. For the assembly code, the data to be sent is assumed to be stored in register R16 and the
data received will be available in the same register (R16) after the function returns.
C Code Example(1)
void USART_Init( unsigned int baud )
{
UBRRn = 0;
/* Setting the XCKn port pin as output, enables master mode. */
XCKn_DDR |= (1<<XCKn);
/* Set MSPI mode of operation and SPI data mode 0. */
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Enable receiver and transmitter. */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set baud rate. */
/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled
*/
UBRRn = baud;
}
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The function simply waits for the transmit buffer to be empty by checking the UDREn flag, before loading it with
new data to be transmitted. The function then waits for data to be present in the receive buffe r by checking the
RXCn flag, before reading the buffer and returning the value..
Note: 1. See “Code Examples” on page 6.
17.6.1 Transmitter and Receiver Flags and Interrupts
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in func-
tion to the norma l USART operation . Howeve r, the receiver error status flags (FEn, DORn, and PEn) are not in use
and always read zero.
17.6.2 Disabling the Transmitte r o r Re ce iv er
The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART
operation.
Assembly Code Example(1)
USART_MSPIM_Transfer:
; Wait for empty transmit buffer
sbis UCSRnA, UDREn
rjmp USART_MSPIM_Transfer
; Put data (r16) into buffer, sends the data
out UDRn,r16
; Wait for data to be received
USART_MSPIM_Wait_RXCn:
sbis UCSRnA, RXCn
rjmp USART_MSPIM_Wait_RXCn
; Get and return received data from buffer
in r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) );
/* Put data into buffer, sends the data */
UDRn = data;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
return UDRn;
}
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17.7 Compatibility with AVR SPI
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
• Master mode timing d iagram
• The UCPOLn bit functionality is identical to the SPI CPOL bit
• The UCPHAn bit functionality is identical to the SPI CPHA bit
• The UDORDn bit functionality is identical to the SPI DORD bit
However, since the USART in MSPIM mode reuses the USART reso urces, the use of the USART in MSPIM mode
is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only mas-
ter operation is supported by the USART in MSPIM mode, the following features differ between the two modules:
• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer.
• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting
UBRRn accord ing ly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPI M m od e and the SPI pin s is sho wn in Ta b l e 17 -3 .
17.8 Register Description
The following sectio n descr ib es th e re gis te rs use d for SPI oper a tion using the USART .
17.8.1 UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART
operation. See “UDRn – USART I/O Data Register” on page 167.
17.8.2 UCSRnA – USART MSPIM Control and Status Register n A
• Bit 7 – RXCn: USART Receive Complete
Table 17-3. Comparison of USART in MSPIM mode and SPI pins.
USART_MSPIM SPI Comment
TxDn MOSI Master out, only
RxDn MISO Master in, only
XCKn SCK Functionally identical
(N/A) SS Not supported by USART in MSPIM
Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn – – – – – UCSRnA
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
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This flag is set when ther e is unread d ata in the re ceive bu ffer. The flag is cleared when the receive buffer is empty
(i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and conse-
quently the flag will become zero.
This flag can be used to generate a Receive Complete interrupt (see RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data in
the transmit buffer (UDRn). The flag is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location.
This flag can generate a Transmit Complete interrupt (see TXCIEn bit).
• Bit 5 – UDREn: USART Data Register Empty
This flag indicates the transmit buffer (UDRn) is ready to receive new data. If the flag is one, the buffer is empty,
and ready to be written. The fla g is set after a reset to indicate that the transmitter is ready.
The flag can generate a Data Register Empty interrupt (see UDRIEn bit).
• Bits 4:0 – Reserved Bits in MSPI mode
In MSPI mode these bits are reserved for future use. For compatibility with future devices, these bits must be writ-
ten zero.
17.8.3 UCSRnB – USART MSPIM Control and Status Register n B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag. A USART Receive Complete interrupt will be generated
only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UD REn flag. A Data R egister Empty interrupt will be generated only
if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDR En bit is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. When enabled, the receiver over rid es norma l
port operation for the RxDn pin.
Disabling the receiver will flush the receive buffer.
Enabling the receiver, only, and leaving the transmitter disabled has no meaning in MSPI mode since only master
mode is supported and it is the transmitter that controls the transfer clock.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one en ables the USART Transmitter . Whe n enabled, the tran smitter over rides norma l port opera-
tion for the TxDn pin.
Bit 7 6 5 4 3 210
RXCIEn TXCIEn UDRIE RXENn TXENn – – – UCSRnB
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0
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Disabling the transmitter will not become effective until on going and pending transmissions are completed, i.e.,
when the transmit shift register and transmit buffer register do not contain data to be transmitted. When disabled,
the transmitter will no longer override the TxDn pin.
• Bits 2:0 – Reserved Bits in MSPI mode
In MSPI mode these bits are reserved for future use. For compatibility with future devices, these bits must be writ-
ten zero.
17.8.4 UCSRnC – USART MSPIM Control and Status Register n C
• Bits 7:6 – UMSELn[1:0]: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 17-4. The MSPIM is enabled when both
UMSEL bits are set to one.
See “UCSRnC – USART Control and Status Register C” on page 169 for full description of the normal USART
operation.
Bits UDORDn, UCPHAn, and UCPOLn may be set in the same write operation where the MSPIM is enabled.
• Bits 5:3 – Reserved Bits in MSPI mode
In MSPI mode these bits are reserved for future use. For compatibility with future devices, these bits must be writ-
ten zero.
• Bit 2 – UDORDn: Data Order
When set, the LSB of the data word is transmitted first.
When cleared, the MSB of the data word is transmitted first.
See “Frame Formats” on page 174 for details.
• Bit 1 – UCPHAn: Clock Phase
This bit determines if data is sampled on the leading (first), or tailing (last) edge of XCKn.
See “SPI Data Modes and Timing” on page 173 for details.
• Bit 0 – UCPOLn: Clock Polarity
This bit sets the polarity of th e XCKn clock. The comb ination of UCPOLn and UCPHAn bi ts determine th e timing of
the data transfer.
See Table 17-2 on page 174 for details.
Bit 76543210
UMSELn1 UMSELn0 – – – UDORDn UCPHAn UCPOLn UCSRnC
Read/Write R/W R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 17-4. UMSELn Bit Settings
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
1 0 (Reserved)
1 1 Master SPI (MSPIM)
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17.8.5 UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to norma l USART operation.
See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 172.
18. Analog Comparator
The analog compa rato r com par es th e inpu t valu es on th e positive pin AIN0 and negative pin AIN1. When the volt-
age on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output,
ACO, is set. The compara tor can trigger a separate inte rrupt, exclusive to the Analog Comp arator. The user can
select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its sur-
rounding logic is shown in Figure 18-1.
Figure 18-1. Analog Comparator Block Diagram
Notes: 1. See Table 18-1 on page 182.
For pin placements, see Fig ure 1-1 on page 2.
The ADC Power Reduction bit, PRADC, must be disabled in order to use the ADC input multiplexer. This is done
by clearing the PRADC bit in the Powe r Reduction Register, PRR. See “PRR – Power Reduction Register” on page
38 for more details.
18.1 Analog Comparator Multiplexed Input
When the Analog to Digital Converter (ADC) is configurated as single ended input channel, it is possible to select
any of the ADC[11:0] pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to
select this input, and consequently, the ADC must be switc hed off to utilize this feature. If the Analog Comparator
Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero),
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
(1)
ACIC
To T/C1 Capture
Trigger MUX
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MUX[3:0] in ADMUX select the input pin to replace the negative input to the analog comp arator, as shown in Table
18-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the analog comparator.
18.2 Register Description
18.2.1 ACSRA – Analog Comparator Control and Status Register
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any
time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When chang-
ing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSRA. Otherwise
an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed, internal bandgap reference voltage re places the posi tive input to the Analog Compar a-
tor. When this bit is cleared, AIN0 is applied to th e positive input of the Analog Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization
introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and
ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI
is cleared by hardware when exe cuting the corr esponding interrupt handling vector . Alternatively, ACI is cleare d by
writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and th e I-bi t in the Status Register is set, the Analog Comparator interrupt is
activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the inpu t capture function in Timer/Counter1 to be triggered by the Analog
Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making
the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt.
When written logic zero, no connection between the Analog Comparator and the input capture function exists. To
make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK) must be set.
Table 18-1. Analog Comparator Multiplexed Input
ACME ADEN Analog Comparator Negative Input
0XAIN1
1 0 ADC multiplexer. See Table 19-4 on page 197
11AIN1
Bit 76543210
0x06 (0x26) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSRA
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 N/A 0 0 0 0 0
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• Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings
are shown in Table 18-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSRA Register. Otherwise an interrupt can occur when the bits are changed.
18.2.2 ACSRB – Analog Comparator Control and Status Register B
• Bit 7 – HSEL: Hysteresis Select
When this bit is written logic one, the hysteresis of the analog comparator is en abled. The level of hysteresis is
selected by the HLEV bit.
• Bit 6 – HLEV: Hysteresis Level
When enabled via the HSEL bit, the level of hysteresis can be set using the HLEV bit, as shown in Table 18-3.
• Bit 5 – ACLP
This bit is reserved for QTouch, always write as zero.
• Bit 4 – Reserved
This bit is reserved and will always read zero.
• Bit 3 – ACCE
This bit is reserved for QTouch, always write as zero.
• Bit 2 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switch ed off (ADEN in ADCSRA is zero), the ADC multiplexer
selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the neg-
ative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed
Input” on page 181.
Table 18-2. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggl e.
01Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Output Edge.
Bit 76543210
0x05 (0x25) HSEL HLEV ACLP – ACCE ACME ACIRS1 ACIRS0 ACSRB
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value00000000
Table 18-3. Selecting Level of Analog Comparator Hysteresis
HSEL HLEV Hysteresis of Analog Comparator
0 X Not enabled
1020 mV
150 mV
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• Bit 1 – ACIRS1
This bit is reserved for QTouch, always write as zero.
• Bit 0 – ACIRS0
This bit is reserved for QTouch, always write as zero.
18.2.3 DIDR0 – Digital Input Disable Register
• Bits 2:1 – AIN1D, AIN0D: AIN1 and AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer o n the AIN1/0 pin is disabled . The cor respond ing PIN Re g-
ister bit will always read as zero when this bit is set. When used as an analog input but not required as a digital
input the power consumption in the digital input buffer can be reduced by writing this bit to logic o ne.
Bit 76543210
(0x60) ADC4D ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D AREFD DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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19. Analog to Digital Converter
19.1 Features
•10-bit Resolution
•1 LSB Integral Non-linearity
•± 2 LSB Absolute Accuracy
•13 µs Conversion Time
•15 kSPS at Maximum Resolution
•12 Multiplexed Single Ended Input Channe ls
•Temperature Sensor Input Channel
•Optional Left Adjustment for ADC Result Readout
•0 - VCC ADC Input Voltage Range
•1.1V ADC Reference Voltage
•Free Running o r Single Conversion Mode
•ADC Start Conversion by Auto Triggering on Interrupt Sources
•Interrupt on ADC Conversion Complete
•Sleep Mode Noise Canceler
19.2 Overview
ATtiny1634 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a
13 channel analog multiplexer, which allows the ADC to measure the voltage at 12 single-ended input pins, or from
one internal, single-ended voltage channel coming from the internal temperature sensor. Single-ended voltage
inputs are referred to 0V (GND).
The ADC contains a Sa m ple an d Hold circuit whic h e nsur es that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 19-1 on page 186.
Internal reference voltage of nominally 1.1V is provided on-chip. Alternatively, VCC can be used as reference volt-
age for single ended channels. There is also an optio n to use a n external volta ge refere nce and tur n-off the internal
voltage reference.
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Figure 19-1. Analog to Digital Converter Block Schematic
19.3 Operation
In order to be ab le to use the ADC th e Power Red uction b it, PRADC, in the Po wer Redu ction Register must b e dis-
abled. This is done by clearing the PRADC bit. See “PRR – Power Red uction Register” on page 38 for more
details.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and in put channel sele c-
tions will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC converts an analog input voltage to a 10-bit digital value using successive approximation. The minimum
value represents GND and the maximum value represents the reference voltage. The ADC voltage reference is
selected by writin g the REFS[1:0] bits in the ADMUX register. Alternativ es are the VCC supply pin, the AR EF pin
and the internal 1.1V volta ge reference.
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX) ADC CTRL. & STATUS A
REGISTER (ADCSRA) ADC DATA REGISTER
(ADCH/ADCL)
ADIE
ADATE
ADSC
ADEN
ADIF ADIF
MUX[4:0]
ADPS0
ADPS1
ADPS2
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
1.1V
MUX DECODER
VCC
REFS[1:0]
ADLAR
CHANNEL SELECTION
ADC MULTIPLEXER
OUTPUT
PRESCALER
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
START
TEMPERATURE
SENSOR
ADC12
BIN
POS.
INPUT
MUX
ADC CTRL. & STATUS B
REGISTER (ADCSRB)
AREF
INPUT
MUX
ADC3ADC3
ADC2ADC2
ADC1ADC1
ADC0ADC0
AGND
ADC7ADC7
ADC6ADC6
ADC5ADC5
ADC4ADC4
ADC9ADC9
ADC11 ADC11
ADC8ADC8
ADC10ADC10
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The analog input channe l is selected by writing to the MUX bits in ADMUX. An y of the ADC input pins can be
selected as single ended inputs to the ADC.
The ADC generates a 10-bit result which is pr esented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADCSRB.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH, only. Other-
wise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same
conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read,
and a conversion completes before ADCH is read, neither register is updated and the result from the conv ersion is
lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggere d when a conversion completes. When ADC access to the
data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
19.4 Starting a Conversion
Make sure the ADC is po we re d by clea r ing th e AD C Power Reduction bit, PRADC, in the Power Reduction Regis-
ter, PRR (see “PRR – Power Reduction Register” on page 38).
A single conversion is started by writin g a logical one to the ADC Sta rt Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differ-
ent data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enab le bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigge r
Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive
edge occurs on the select ed trigge r signa l, the ADC pr esca ler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a
new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge
will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt
Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Inter-
rupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 19-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START CLKADC
.
.
.
.EDGE
DETECTOR
ADATE
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ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is
cleared or not.
If Auto Triggering is enabled, sing le conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
19.5 Prescaling and Conversion Timing
By default, the successive approximation circuitry requir es an input clock frequency between 50kHz an d 200kHz to
get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be
higher than 200kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than
1MHz.
Figure 19-3. ADC Prescaler
The ADC module contains a prescaler, as illustrated in Figure 19-3 on page 188, which generates an acceptable
ADC clock frequency from any CPU frequ ency ab ove 1 00kHz . The p rescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The
prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the follow-
ing rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarised in Table 19-1 on page 191. The first conversion
after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog
circuitry, as shown in Figure 19-4 below.
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START
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Figure 19-4. ADC Timing Diagram, Firs t Conversion (Single Conversion Mode)
The actual sample-and- ho ld takes pl ace 1.5 ADC clock cycles after the start of a normal conve rsion and 13.5 ADC
clock cycles after the start of a first conversion. See Figure 19-5. When a conversion is complete, the result is writ-
ten to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The
software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
Figure 19-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, th e prescaler is reset whe n the trigger event occurs, as shown in Figu re 19-6 below.
This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes
place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles
are used for synchronization logic.
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1212
13 14 15 16 17 18 19 20 21 22 23 24 25 1 2
First Conversion Next
Conversion
3
MUX and REFS
Update MUX and REFS
Update
Conversion
Complete
123456789 10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete MUX and REFS
Update
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Figure 19-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. See Figure 19-7.
Figure 19-7. ADC Timing Diagram, Free Running Conversion
1 2 3 4 5 6 7 8 910 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number 12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
12 13 14
Sign and MSB of Result
LSB of Result
A
DC Clock
A
DSC
A
DIF
A
DCH
A
DCL
C
ycle Number 12
One Conversion Next Conversion
34
Conversion
Complete Sample & Ho
ld
MUX and REFS
Update
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For a summary of conversion times, see Table 19-1.
19.6 Changing Channel or Reference Selection
The MUX[3:0] and REFS[1:0] bits in the ADMUX Register are sing le buffered thro ugh a temporar y register to which
the CPU has random access. This ensures that the channels and reference selection only takes place at a safe
point during the conversion. The channel and reference selection is continuously updated until a conversion is
started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling
time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes
(ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is
written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC
clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indetermin ist ic. Spe cia l car e must be ta ke n
when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is
changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX
can be safely updated in the following ways:
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
19.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure that the correct
channel is selected:
• In Single Conversio n mode, always select the channel before starting the conversion. The channel selection
may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for
the conversio n to comp le te befo re cha n gin g th e chan ne l sele ctio n .
• In Free Running mode , always select the channel before starting the first conversion. The channel selection
may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for
the first conversion to complete, and then change the channel selection. Since the next conversion has alread y
started automatically, the next result will reflect the previous channel selection. Subsequent conversions will
reflect the new channel selection.
Table 19-1. ADC Conversion Time
Condition Sample & Hold (Cycles fro m
Start of Conversion) Conversion Time (Cycles)
First conversion 13.5 25
Normal conversions 1.5 13
Auto Trigge red conversions 2 13.5
Free Running conversi on 2.5 14
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19.6.2 ADC Voltage Reference
The ADC reference voltage ( VREF) indicates the conversion range for the ADC. Single ended channels that exceed
VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external
AREF pin. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an intern al
amplifier.
The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is
advised to discard th is res ult.
19.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode. This reduces noise induced from
the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle
mode. To make use of this feature, the following procedure should be used:
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and
the ADC conversion complete interrupt must be enabled.
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been
halted.
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and
execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC
conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep
command is executed.
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle mode and ADC
Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid
excessive power consumption.
19.8 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 19-8. An analog source ap plied to ADCn
is subjected to the pin capacitanc e and input leakage of that pin, regardless of whether that channel is selected as
input for the ADC. When the channel is selected, the source must drive the S/H capacit or th ro ug h t he se rie s r es is-
tance (combin e d re sist an ce in the inpu t pa th) .
The ADC is optimized for analog sign als with an o utput impeda nce o f a pproxima te ly 1 0k or less. If such a source
is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will
depend on ho w lon g time the sour ce n ee ds to char ge th e S/H capacitor, which can vary widely. The user is recom-
mended to only use low impedance sources with slowly varying signals, since this minimizes the required charge
transfer to the S/H capacitor.
In order to avoid distortion from unpredictable signal convolution, signal compo nents higher than the Nyquist fre-
quency (fADC/2) should not be present. The user is advised to remove high frequency components with a low-pass
filter before applying the signals as inputs to the ADC.
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Figure 19-8. Analog Input Circuitry
Note: The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or p arasitic
capacitance inside the device. The value given is worst case.
19.9 Noise Canceling Techn iques
Digital circuitry inside and outside the device generates EMI which might affe ct the accuracy of analog measure-
ments. When conversion accuracy is critical, the noise level can be reduced by applying the following techn iques:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to VCC and GND pins as possible.
Where high ADC accuracy is requir ed it is re commend ed to u se ADC Noise Re duction Mode, as de scri bed in Sec-
tion 19.7 on page 192. This is especially the case when system clock frequency is above 1MHz, or when the ADC
is used for reading the internal temperature sensor, as described in Section 19.12 on page 195. A good system
design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction
Mode
19.10 ADC Accuracy Definitions
An n-bit single-ended ADC conver ts a voltage linearly betwee n GND and VREF in 2n steps (LSBs). The lowest code
is read as 0, and the highest code is read as 2n-1.
Several parameters describe th e deviation from the ideal behavior, as follows:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal
value: 0 LSB.
ADCn
IIH
1..100 kohm
CS/H = 14 pF
VCC/2
IIL
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Figure 19-9. Offset Error
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to
0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB
Figure 19-10. Gain Error
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an
actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Figure 19-11. Integral Non-linearity (INL)
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two
adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Output Code
VREF Input Voltage
Ideal ADC
Actual ADC
Offset
Error
Output Code
VREF Input Voltage
Ideal ADC
Actual ADC
Gain
Error
Output Code
VREF Input Voltage
Ideal ADC
Actual ADC
INL
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Figure 19-12. Differential Non-linearity (DNL)
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
• Absolute Accuracy: The maximum de viation of an actual (unadjuste d) transiti on comp ared to an ideal tr ansition
for any code. This is the co mp o und effect of offset, gain error, differential e rror, non-linearity, and quantization
error. Ideal value: ± 0.5 LSB.
19.11 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Data Registers
(ADCL, ADCH).
For single ended conversion, the result is
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 19-3 on page
196 and Table 19-4 on page 197). 0x000 represents analog ground, and 0x3FF represents the selected reference
voltage minus one LSB. The result is presented in one-sided form, from 0x3FF to 0x000.
19.12 Temperature Measurement
Temperature measurem ent is based on an on- chip sen sor, coup led to a sing le-end ed ADC-channel. The temper a-
ture sensor is enabled when ch ann el ADC12 is sele cted from the ADMUX register. When measuring temperature,
the internal voltage reference must be selected as ADC reference source. When enabled, the ADC converter can
be used in single conversion mode to measure the voltage over the temperature sensor.
The measured voltage has a linear relationship to temperature as shown in Table 19-2 The sensitivity is approxi-
mately 1 LSB/C and the accuracy depends on the method of user calibration. The temperature sensor should be
calibrated by firmware in order to reach reasonable accuracy. Typically, the measurement accuracy after a single
temperatur e calibration is ±10C, assumi ng calibration at room tempe rature. Better accu racies are achieved by
using two temperature points for calibration.
Output Code
0x3FF
0x000
0VREF Input Voltage
DNL
1 LSB
ADC VIN 1024
VREF
--------------------------=
Table 19-2. Temperature vs. Sensor Output Voltage (Typical)
Temperature -40C+25C+85C
ADC 235 LSB 300 LSB 360 LSB
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The values described in Table 19-2 are typical values, however, due to process variation the output voltage of the
temperature sensor varies from one chip to another. To achieve more accurate results, temperature measure-
ments can be calibrated in the application software. The sofware calibration can be done using the equation:
T = k * [(ADCH << 8) | ADCL] + TOS
where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is the temperature sen-
sor offset. Typic ally , k is very cl os e to 1. 0 an d in sin gle -poin t ca libr at i on the coef ficie n t ma y be omitt ed .
Factory calibration values can be used for calibration of temperature sensor data. The gain coefficient, k, is stored
as an unsigned, fixed p oint, two’s comp lement n umber an d of fset, TOS,as a signed, two’s comp leme nt inte ger. See
“Device Signature Imprint Table” on page 210.
19.13 Register Description
19.13.1 ADMUX – ADC Multiplexer Selection Register
• Bits 7:6 – REFS[1:0]: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 19-3.
If these bits are changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSR is set). Also note, that when these bits are changed, the next conversion will take 25 ADC clock
cycles.
It is recommended to force the ADC to perform a long conversion when changing multiplexer or voltage reference
settings. This can be done by first turning off the ADC, then changing refer ence settings and then turn on the ADC.
Alternatively, the first conversion results after changing reference settings should be discarded.
Internal voltage refere nce options may not be used if an external voltage is being applied to the AREF pin.
• Bit 5 – REFEN
This bit is reserved for QTouch, always write as zero.
• Bit 4 – ADC0EN
This bit is reserved for QTouch, always write as zero.
• Bits 3:0 – MUX[3:0]: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC, as shown in Table
19-4 on page 197. Selecting the channel ADC12 enables the temperature measurement. See Table 19-4 on page
197 for details.
Bit 76543210
0x04 (0x24) REFS1 REFS0 REFEN ADC0EN MUX3 MUX2 MUX1 MUX0 ADMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 19-3. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selectio n
00V
CC used as analog reference, disconnected from PA 0 (AREF)
0 1 External voltage reference at PA0 (AREF) pin
1 0 Internal 1.1V voltage reference
11Reserved
197
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Notes: 1. After switching to internal voltage reference the ADC requires a settling time of 1ms before measurements are sta-
ble. Conversions starting before this may not be reliable. The ADC must be enabled during the settling time.
2. See “Temperature Measurement” on page 195.
If these bits are changed during a conversion, the change will not go into effect until the conversion is complete
(ADIF in ADCSRA is set).
19.13.2 ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one en ables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a con-
version is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Convers ion mode, write this bit to o ne to start each conver sion. In Free Running mode, write this bit to
one to start the firs t conversion. The first conversion after ADSC ha s been written after the ADC has been enabled,
or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal
13. This first conversion performs initialization of the ADC.
Table 19-4. Single-Ended Input channel Selections.
MUX[3:0] Single Ended Input Pin
0000 ADC0 PA3
0001 ADC1 PA4
0010 ADC2 PA5
0011 ADC3 PA6
0100 ADC4 PA7
0101 ADC5 PB0
0110 ADC6 PB1
0111 ADC7 PB2
1000 ADC8 PB3
1001 ADC9 PC0
1010 ADC10 PC1
1011 ADC11 PC2
1100 Ground GND
1101 Internal 1. 1V re fe rence (1) (internal)
1110 Temperature sensor (2) (internal)
1111 Reserved Not connected
Bit 76543210
0x03 (0x23) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
198
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ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero.
Writing zero to this bit has no effect .
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive
edge of the selected trigger signal. The trigger sour ce is selected by setting the ADC Trigger Select bits, ADTS in
ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Com-
plete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the
flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can b e disabled. This also applies
if the SBI instruction is used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
• Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock to the ADC.
19.13.3 ADCL and ADCH – ADC Data Register
19.13.3.1 ADLAR = 0
Table 19-5. ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Bit 151413121110 9 8
0x01 (0x21) – – – – – – ADC9 ADC8 ADCH
0x00 (0x20) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/Write R R R R R R R R
RRRRRRRR
Initial Value00000000
00000000
199
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19.13.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is re quired , it is sufficient to read ADCH. Otherwise, ADCL must be read
first, then ADCH.
The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
• ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 195.
19.13.4 ADCSRB – ADC Control and Status Register B
• Bit 7 – VDEN
This bit is reserved for QTouch, always write as zero.
• Bit 6 – VDPD
This bit is reserved for QTouch, always write as zero.
• Bits 5:4 – Res: Reserved Bits
These are reserved bits in ATtiny1634. For compatibility with future devices always write these bits to zero.
• Bit 3 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to
ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC
Data Register immediately, regardless of any ongoing conversions. For a com ple the description of this bit, see
“ADCL and ADCH – ADC Data Register” on page 198.
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of
the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set,
Bit 151413121110 9 8
0x01 (0x21) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
0x00 (0x20) ADC1 ADC0 – – – – – – ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 76543210
0x02 (0x22) VDEN VDPD – – ADLAR ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R/W R/W R R R/W R/W R/W R/W
Initial Value00000000
200
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will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching
to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
19.13.5 DIDR0 – Digital Input Disable Register 0
• Bits 7:3 – ADC4D:ADC0D: ADC[4:0] Digital Input Disable
When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The correspond-
ing PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0]
pin and the digital input from this pin is not needed, this bit should be writte n logic one t o reduce po wer consum p-
tion in the digital input buffer.
19.13.6 DIDR1 – Digital Input Disable Register 1
• Bits 3:0 – ADC8D:ADC5D: ADC[8:5] Digital Input Disable
When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The correspond-
ing PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[8:5]
pin and the digital input from this pin is not needed, this bit should be writte n logic one t o reduce po wer consum p-
tion in the digital input buffer.
19.13.7 DIDR2 – Digital Input Disable Register 2
• Bits 2:0 – ADC11D:ADC9D: ADC[11:9] Digital Input Disable
When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The correspond-
ing PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[11:9]
pin and the digital input from this pin is not needed, this bit should be writte n logic one t o reduce po wer consum p-
tion in the digital input buffer.
Table 19-6. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free Running mode
0 0 1 Analog Comparator
0 1 0 External Interrupt Request 0
0 1 1 Timer/Counter0 Compare Match A
1 0 0 Timer/Counter0 Overflow
1 0 1 Timer/Counter1 Compare Match B
1 1 0 Timer/Counter1 Overflow
1 1 1 Timer/Counter1 Capture Event
Bit 76543210
(0x60) ADC4D ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D AREFD DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x61) – – – – ADC8D ADC7D ADC6D ADC5D DIDR1
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x62) – – – – – ADC11D ADC10D ADC9D DIDR2
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
201
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20. debugWIRE On-chip Debug System
20.1 Features
•Complete Program Flow Control
•Emulates All On-chip Functions, Both Digital a nd Analog , except RESET Pin
•Real-time Operation
•Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
•Unlimited Number of Program Break Poin ts (Using Software Break Points)
•Non-intrusive Operation
•Electrical Characteristic s Identical to Real Device
•Automatic Configuration System
•High-Speed Operation
•Programming of Non-volatile Memories
20.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, exe-
cute AVR instructions in the CPU and to program the different non-volatile memories.
20.3 Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE
system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-direc-
tional I/O pin with pull-up enabled and becomes the communicatio n ga te wa y bet ween tar ge t an d em u lator.
Figure 20-1 shows the schematic of a target MCU, with d ebugWIRE enabled, and the emulato r connector. The
system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses.
Figure 20-1. The debugWIRE Setup
When designing a system where debugWIRE will be us ed, the following must be observed:
• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the pull-up resistor is
optional.
• Connecting the RESET pin directly to VCC will not work.
d
W
GND
dW(RESET)
VCC
1.8 - 5.5
V
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• Capacitors inserted on the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
20.4 Software Break Points
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR
Studio® will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction
will be stored. When program execution is continued, the stored instruction will be executed before continuing from
the Program memory. A break can be inserted manually by putting the BREAK instruction in the program.
The Flash must be re-progra mmed each time a Break Point is ch anged. This is au toma tically handled by AVR Stu-
dio through the debugWIRE interface. The use of Break Points will therefore reduce the Falsh Data retention.
Devices used for debugging purposes should not be shipped to end customers.
20.5 Limitations of debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An
External Reset source is theref ore not supported when the debugWIRE is enabled.
The debugWIRE system a ccurately emulates all I/O fu nctions whe n running at full sp eed, i.e ., wh en the p rogram in
the CPU is running. When the CPU is stopped, care must be taken while accessing some of th e I/O Regis ters via
the debugger (AVR Studio). See the debugWIRE documentation for detailed description of the limitations.
The debugWIRE interface is asynchronous, which means that the debugger needs to synchronize to the system
clock. If the system clock is changed by software (e.g. by writing CLKPS bits) communication via debugWIRE may
fail. Also, clock frequencies below 100kHz may cause communication prob lems.
A programmed DW EN Fuse enables some pa rts of the clock system to be runnin g in all sleep modes. This will
increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not
used.
20.6 Register Description
The following sectio n de scr ib es the re gisters used with the de bugWire.
20.6.1 DWDR – debugWire Data Register
The DWDR Register provides a communication channel from the running program in the MCU to the debugger.
This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in
the normal operations.
Bit 76543210
0x2E (0x4E) DWDR[7:0] DWDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
203
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21. Self-Programming
21.1 Features
•Self-Programming Enables MCU to Erase, Write and Reprogram Application Memory
•Efficient Read-Modify-Write Support
•Lock Bits Allow Application Memory to Be Securely Closed for Fu rther Access
21.2 Overview
The device provides a self-programming mechanism for downloading and uploading program cod e by the MCU
itself. Self-Programming can use any available data interface and associated protocol to read code and write (pro-
gram) that code into program memory.
21.3 Lock Bits
Program memory can be protected from internal or external access. See “Lock Bits” on page 208.
21.4 Self-Programming the Flash
Program memory is updated in a page by page fashion. Before programming a page with the data stored in the
temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM
and the buffer can be filled either before the 4-Page Erase command or between a 4-Page Erase and a Page Write
operation:
1. Either, fill the buffer before a 4-Page Erase:
a. Fill temporary page buffer
b. Perform a 4-Page Erase
c. Perform a Page Write
2. Or, fill the buffer after 4-Page Erase:
a. Perform a 4-Page Erase
b. Fill temporary page buffer
c. Perform a Page Write
The 4-Page Erase command erases four program me mory pages at the same time. If only part of this section
needs to be changed, the rest must be stored before the erase, and then be re-written.
The temporary page buffer can be accessed in a random sequence.
The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”).
21.4.1 Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Since the Flash is organized in pages (see Table 23-1 on page 214), the Program Counter can be treated as hav-
ing two different sections. One section, consisting of the least significant bits, is addressing the words within a
page, while the most significant bits are addressing the pages. This is shown in Figure 21-1, below.
Bit 151413121110 9 8
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0
76543210
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Figure 21-1. Addressing the Flash During SPM Load & Write Operations
The 4-Page Erase command addresses several program memory pages simultaneously, as shown in Figure 21-2,
below.
Figure 21-2. Addressing the Flash During SPM 4-Page Erase
PROGRAM MEMORY
0115
Z - REGISTER
BIT
0
ZPAGEMSB
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
INSTRUCTION WORD
PA G E PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PA G E
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM
COUNTER
PROGRAM MEMORY
0115
Z - REGISTER
BIT
0
ZPAGEMSB
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
PA G E
PCWORDPCPAGE
PCMSB PAGEMSB
PROGRAM
COUNTER
205
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Variables used in above figures are explained in Table 21- 1, below.
Note that 4-Page Erase and Page Write operations address memory independently. Therefore the software must
make sure the Page Write command addresses a page previously erased by the 4-Page Erase command.
Although the least significant bit of the Z-register (Z0) should be zero for SPM, it should be noted that the LPM
instruction addresses the Flash byte-by-byte and uses Z0 as a byte select bit.
Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
21.4.2 4-Page Erase
This command erases four pages of program memory. To execute 4-Page Erase:
• Set up the address in the Z-pointe r
• Write “00000011” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. PCPAGE[1:0]
are ignored, as are other bits in the Z-pointer .
If an interrupt occurs during the timed sequence above the four cycle access cannot be guaranteed. In order to
ensure atomic operation interrupts should be disabled before writing to SPMCSR.
The CPU is halted during the 4-Page Erase operation.
21.4.3 Page Load
To write an instruction word:
• Set up the address in the Z-pointe r
• Set up the data in R1:R0
• Write “00000001” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
Table 21-1. Variables Used in Flash Addressing
Variable Description
PCPAGE
Program Counter page address. Selects program memory page for Page Load
& Page Write commands. Selects a block of program pages for the 4-Page
Erase operation.
See Table 23-1 on page 214
PCMSB The most significant bit of th e Program Counter.
See Table 23-1 on page 214
ZPCMSB The bit in the Z register that is mapped to PCMSB. Because Z[0] is not used,
ZPCMSB = PCMSB + 1. Z register bits above ZPCMSB are ignored
PCWORD Program Counter word address. Selects the word within a page. This is used
for filling the temporary buffer and must be zero during page write operations.
See Table 23-1 on page 214
PAGEMSB The most significant bit used to address the word within one page
ZPAGEMSB The bit in the Z register that is mapped to PAGEMSB. Because Z[0] is not used,
ZPAGEMSB = PAGEMSB + 1
206
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The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buf-
fer will auto-erase after a Page Write operation, o r by writing the CTPB bit in SPMCSR. It is also erased after a
system reset.
Note that it is not possible to write more than one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
21.4.4 Page Write
To execute Page Write:
• Set up the address in the Z-pointe r
• Write “00000101” to SPMCSR
• Execute an SPM instruction within four clock cycles after writing SPMCSR
The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must
be written to zero durin g this operation.
The CPU is halted during the Page Write operation.
21.4.5 SPMCSR Can Not Be Written When EEPROM is Programmed
Note that an EEPROM write operation will block all software programming to Flash. R eading fuses and lock bits
from software will also be prevented during the EEPROM write operation. It is recommended that the user checks
the status bit (EEPE) in EECR and verifies that it is cleared before writing to SPMCSR.
21.5 Preventing Flash Corruption
During periods of low VCC, th e Flash pr ogram ca n be corr upted bec ause the supply vo ltage is too low for the CPU
and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the
same design solutions should be applie d.
A Flash program corruption can be ca used by two situations when the voltag e is too low. First, a regular write
sequence to the Flash requires a m inimum voltage to operate correctly. Secondly, the CPU itself can execute
instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done
by enabling the inte rnal Brown-out Detector (BOD) if the operating voltage matches the detection level. If
not, an external low VCC reset p rotection circuit can be used. If a reset occur s while a wr ite op er ation is in
progress, the write operation will be completed provided that the power supply voltage is suf ficient.
2. Keep the AVR core in Power-down slee p mo de dur ing pe riods of low V CC. This will prevent the CPU from
attempting to decode and execute instructions, effectively prot ec tin g the SPMCSR Register and thus the
Flash from unintentional writes.
21.6 Programming Time for Flash when Using SPM
Flash access is timed using the internal, calibrated 8MHz oscillator. Typical Flash programming times for the CPU
are shown in Table 21-2.
Note: 1. Min and max programming times are per individual op eration.
Table 21-2. SPM Programming Time
Operation Min (1) Max (1)
SPM: Flash 4-Page Erase, Flash Page Write, and lock bit write 3.7 ms 4.5 ms
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21.7 Register Description
21.7.1 SPMCSR – Store Program Memory Co ntrol and Status Register
The Store Program Memory Cont rol and Status Register contains the control bits needed to control the Program
memory operations.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and always read as zero.
• Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set will return the selected
data (depending on Z-pointer value) from the device signature imprint table into the destination register. See
“Device Signature Imprint Table” on page 210.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the
data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction with in three cycles after RFLB a nd SPMEN are set in the SPMCSR Register, will read either
the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “SPMCSR Can
Not Be Written When EEPROM is Programmed” on page 206 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPME N, the next SPM instruction within four clock cycles executes
Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if
no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
An SPM instruction within four clock cycles of PGERS and SPMEN have been set starts 4-Page Erase. The page
address is taken from the high part of the Z-pointer. Data in R1 and R0 is ignored. This bit will auto-clear upon com-
pletion of a 4-Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during
the entire 4-Pa ge Eras e op er at ion .
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If set to one together with RSIG, C TPB, RFLB,
PGWRT or PGERS, the following LPM/SPM instruction will have a special meaning, as described elsewhere.
If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of
an SPM instruction, or if no SPM instruction is executed within four clock cycles. During 4-Page Erase and Page
Write, the SPMEN bit remains high until the operation is completed.
Bit 7 654 3210
0x37 (0x57) – – RSIG CTPB RFLB PGWRT PGERS SPMEN SPMCSR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
208
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22. Lock Bits, Fuse Bits and D evice Sig nature
22.1 Lock Bits
ATtiny1634 provides the program and data memory lock bits listed in Table 22-1.
Notes: 1. “1” means unprogrammed, “0” means programmed.
Lock bits can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in
Table 22-2.
Notes: 1. “1” means unprogrammed, “0” means programmed.
2. Program fuse bits before programming LB1 and LB2.
When programming the lock bits, the mode of protection can be increased, only. Writing the same, or lower, mode
of protection automatically results in maximum protection.
Lock bits can be erased to “1” with the Chip Erase command, on ly.
The ATtiny1634 has no separate bo ot loader section. The SPM instruction is enabled for the whole Flash if the
SELFPRGEN fuse is programmed (“0”) , ot he rwis e it is disab le d.
Table 22-1. Lock Bit Byte
Lock Bit Byte Bit No Description See Default Value ()
– 7 – 1 (unprogrammed)
– 6 – 1 (unprogrammed)
– 5 – 1 (unprogrammed)
– 4 – 1 (unprogrammed)
– 3 – 1 (unprogrammed)
– 2 – 1 (unprogrammed)
LB2 1 Lock bit Below 1 (unprogrammed)
LB1 0 1 (unprogrammed)
Table 22-2. Lock Bit Protection Modes.
Lock Bits (1)
Mode of ProtectionLB2 LB1
1 1 No memory lock features enabled
10
Further programming of Flash and EEPROM is disabled in parallel and serial
programming mode. Fuse bits are locked in both serial and parallel
programming mode (2)
01Reserved
00
Further reading and programming of Flash and EEPROM is disabled in
parallel and serial programming mode. Fuse bits are locked in both serial and
parallel programming mode (2)
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22.2 Fuse Bits
Fuse bits are described in Table 22-3, Table 22-4, and Table 22-5. Note that programmed fuses read as zero.
Notes: 1. Programming this fuse bit will change the functionality of the RESET pin and render further programming via the
serial interface impossible. The fuse bit can be unprogrammed using the parallel programming algorithm (see page
214).
2. This fuse bit is not accessible in serial programming mode.
3. This setting enables SPI programming.
4. This setting does not preserve EEPROM.
Table 22-3. Extended Fuse Byte
Bit # Bit Name Use See Default Value
7 – – 1 (unprogrammed)
6 – – 1 (unprogrammed)
5 – – 1 (unprogrammed)
4 BODPD1 Sets BOD mode of operation when
device is in sleep modes other than
idle Page 42 1 (unprogrammed)
3 BODPD0 1 (unprogrammed)
2BODACT1 Sets BOD mode of operation when
device is active or idle Page 42 1 (unprogrammed)
1 BODACT0 1 (unprogrammed)
0 SELFPRGEN Enables SPM instruction Page 203 1 (unprogrammed)
Table 22-4. High Fuse B yte
Bit # Bit Name Use See Default Value
7 RSTDISBL Disables external reset (1) Page 40 1 (unprogrammed)
6 DWEN Enables debugWIRE (1) Page 201 1 (unpro grammed)
5 SPIEN Enables serial programming and
downloading of data to device (2) 0 (programmed) (3)
4 WDTON Sets watchdog timer permanently on Page 45 1 (unprogrammed)
3 EESAVE Preserves EEPROM memory during
Chip Erase operation Page 216 1 (unprogrammed) (4)
2 BODLEVEL2
Sets BOD trigger level Page 232
1 (unprogrammed)
1 BODLEVEL1 1 (unprogrammed)
0 BODLEVEL0 1 (unprogrammed)
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Note: 1. Unprogramming this fuse at low voltages may result in overclocking . See Section 24.3 on page 229 for device
speed versus supply voltage.
2. This setting results in maximum start-up time for the default clock source.
3. This setting selects Calibrated Internal 8MHz Oscillator.
Fuse bits are locked when Lock Bit 1 (LB1) is programmed. Hence, fuse bits must be programmed before lock bits.
Fuse bits are not affected by a Chip Erase.
22.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the fuse values will have
no effect until the part leaves Programming mode. This does not apply to the EESAVE fuse, which will take effect
once it is programmed. The fuses are also latched on Power-up in Normal mode.
22.3 Device Signature Imprint Table
The device signature imprint table is a dedicated memory area used for storing miscellaneous device information,
such as the device signature and oscillator calibaration data. Most of this memory segment is reserved for internal
use, as outlined in Table 22-6.
Byte addresses are used when the device itself reads the data with the LPM command. External programming
devices must use word addresses.
Table 22-5. Low Fuse B yte
Bit # Bit Name Use See Default Value
7 CKDIV8 Divides clock by 8 (1) Page 28 0 (programmed)
6 CKOUT Outputs system clock on port pin Page 29 1 (unprogrammed)
5 – – 1 (unprogrammed)
4 SUT Sets system start-up time Page 30 0 (programmed) (2)
3 CKSEL3
Selects clock source Page 30
0 (programmed) (3)
2 CKSEL2 0 (programmed) (3)
1 CKSEL1 1 (unprogrammed) (3)
0 CKSEL0 0 (programmed) (3)
Table 22-6. Contents of Device Signature Imprint Table.
Word Address
(External) Byte Address
(Internal) Description
0x00 0x00 Signature byte 0 (1)
0x01 Calibration data for internal 8MHz oscillator (OSCCAL0) (2)
0x01 0x02 Signature byte 1 (1)
0x03 Oscillator temperature calibration data (OSCTCAL0A)
0x02 0x04 Signature byte 2 (1)
0x05 Oscillator temperature calibration data (OSCTCAL0B)
0x03 0x06 Reserved
0x07 Calibration data for internal 32kHz oscillator (OSCCAL1) (2)
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Notes: 1. For more information, see section “Signature Bytes” below.
2. For more information, see section “Calibration Bytes” below.
3. See “Temperature Measurement” on page 195.
4. Unsigned, fixed point, two’s complement: [0:(255/128)].
5. Signed integer , two’s complement: [-127:+128].
22.3.1 Signature Bytes
All Atmel microcontrollers have a three-b yte signature code wh ich identifies the device. Th is code can be read in
both serial and parallel mode, also when the device is locked.
Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data
from Software” on page 211.
The three signature bytes reside in a separate address space called the device signature imprint table. The signa-
ture data for ATtiny1634 is given in Table 22-7.
22.3.2 Calibration Bytes
The device signature imprint table of ATtiny1634 contains calibration data for the internal oscillators, as shown in
Table 22-6 on page 210. During reset, calibration data is automatically copied to the calibration registers
(OSCCAL0, OSCCAL1) to ensure correct frequency of the calibrated oscillators. See “OS CCAL0 – Oscillator Cali-
bration Register” on page 32, and “OSCCAL1 – Oscillator Calibration Register” on page 33.
Calibration bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data
from Software” on page 211.
22.4 Reading Lock, Fuse and Signature Dat a from Software
Fuse and lock bits can be read by device firmware. Programmed fuse and lock bits read zero. unprogrammed as
one. See “Lock Bits” on page 208 and “Fuse Bits” on page 209.
In addition, firmware can also read data from the device signature imprint table. See “Device Signature Imprint
Table” on page 210.
0x04 ...0x15 ... Reserved
... Reserved
0x16 0x2C Calibration data for temperature sensor (gain) (3)(4)
0x2D Calibration data for temperature sensor (offset) (3)(5)
0x17...0x3F ... Reserved
... Reserved
Table 22-6. Contents of Device Signature Imprint Table. (Continued)
Word Address
(External) Byte Address
(Internal) Description
Table 22-7. Device Signature Bytes
Part Signature Byte 0 Signature Byte 1 Signature Byte 0
ATtiny1634 0x1E 0x94 0x12
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22.4.1 Lock Bit Read
Lock bit values are returned in the destination register after an LPM instruction has been issued within three CPU
cycles after RFLB and SPMEN bits have been set in SPMCSR (see page 207). The RFLB and SPMEN bits auto-
matically clear upon completio n of reading the lock bits, or if no LPM instruction is executed within three CPU
cycles, or if no SPM instruction is execu ted within four CPU cycles. When RFLB and SPME N are cleared LPM
functions normally.
To read the lock bits, follow the below procedure:
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
If successful, the contents of the destination register are as follows.
See section “Lock Bits” on page 208 for more information.
22.4.2 Fuse Bit Read
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses
are different.
To read the Fuse Low Byte (FLB), follow the be low procedure:
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
If successful, the contents of the destination register are as follows.
For a detailed description and mapping of the Fuse Low Byte, see Table 22-5 on page 210.
To read the Fuse High Byte (FHB), replace the address in the Z-pointer with 0x0003 and repeat the procedure
above. If successful, the contents of the destina tion register are as follows.
For a detailed description and mapping of the Fuse High Byte, see Table 22-4 on page 209.
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous
procedure. If successful, the contents of the destination register are as follows.
Bit 76543210
Rd ––––––LB2LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 76543210
Rd FEB7 FEB6 FEB5 FEB4 FEB3 FEB2 FEB1 FEB0
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For a detailed description and mapping of the Fuse Extended Byte, see Table 22-3 on page 209.
22.4.3 Device Signature Imprint Table Read
To read the contents of the device signature imprint table, follow the below procedure:
1. Load the Z-pointer with the table index.
2. Set RSIG and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read table data from the LPM destination register.
If successful, the contents of the destination register are as described in section “Device Signature Imprint Table”
on page 210.
See program example below.
Note: See “Code Examples” on page 6.
Assembly Code Example
DSIT_read:
; Uses Z-pointer as table index
ldi ZH, 0
ldi ZL, 1
; Preload SPMCSR bits into R16, then write to SPMCSR
ldi r16, (1<<RSIG)|(1<<SPMEN)
out SPMCSR, r16
; Issue LPM. Table data will be returned into r17
lpm r17, Z
ret
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23. External Programming
This section describes how to program and verify Flash memory, EEPROM, lock bits, and fuse bits in ATtiny1634.
23.1 Memory Parametrics
Flash memor y pa ra me tr ics ar e su mm a ris ed in Table 23-1, below.
Note: 1. See Table 21-1 on page 205 .
EEPROM parametrics are summarised in Table 23-2 , below.
Note: 1. See Table 21-1 on page 205 .
23.2 Parallel Programming
Parallel programming signals and connections are illustrated in Figure 23-1, below.
Figure 23-1. Parallel Programming Signals
Table 23-1. F l as h Par am e tr ics
Device Flash Size Page Size PCWORD (1) Pages PCPAGE (1) PCMSB (1)
ATtiny1634 8K words
(16K bytes) 16 words PC[3:0] 512 PC[12:4] 12
Table 23-2. EEPROM Parametrics
Device EEPROM Size Page Size PCWORD (1) Pages PCPAGE (1) EEAMSB
ATtiny1634 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7
VCC
+5V
GND
CLKI
PC2
PC1
PC0
PB3
PB2
PB1
PA[7:0] DATA I/O
RESET
+12 V
BS1/PAGEL
XA0
XA1/BS2
OE
RDY/ BSY
WR
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Signals are described in Table 23-3, below. Pins not listed in the table are referenced by pin names.
Pulses are assumed to be at least 250 ns, unless otherwise noted.
Pins XA1 and XA0 determine th e act ion w hen CLKI is given a positive pulse, as shown in Table 23-5.
When pulsing WR or OE, the command loaded determines the action executed. The different command options
are shown in Table 23-6.
Table 23-3. Pin and Signal Names Used in Programming Mode
Signal Name Pin(s) I/O Function
RDY/BSY PC2 O 0: Device is busy programming,
1: Device is ready for new command
OE PC1 I Output enable (active low)
WR PC0 I Write pulse (active low)
BS1/PAGEL PB3 I Byte select 1 (0: low byte, 1: high byte) /
Program memory and EEPROM data page load
XA0 PB2 I XTAL action bit 0
XA1/BS2 PB1 I XTAL action bit 1 /
Byte Select 2 (0: low byte, 1: 2nd high byte)
DATA I/O PA[7:0] I/O Bi-directional data bus. Output when OE is low
Table 23-4. Pin Values Used to Enter Progr amming Mode
Pin Symbol Value
WR Prog_enable[3] 0
BS1 Prog_enable[2] 0
XA0 Prog_enable[1] 0
XA1 Prog_enable[0] 0
Table 23-5. XA1 and XA0 Coding
XA1 XA0 Action when CLKI is Pulsed
0 0 Load Flash or EEPROM address (high or low address byte, determined by BS1)
0 1 Load data (high or low data byte for Flash, determined by BS1)
1 0 Load command
1 1 No action, idle
Table 23-6. Command Byte Bit Coding
Command Byte Command
1000 0000 Chip Erase
0100 0000 Write fuse bits
0010 0000 Write lock bits
0001 0000 Write Flash
0001 0001 Write EEPROM
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23.2.1 Enter Programming Mode
The following algorithm puts the device in Parallel (High-voltage) Programming mode:
1. Set Prog_enable pins (see Table 23-4 on page 215) to “0000”, RESET pin to 0V and VCC to 0V.
2. Apply 4.5 – 5. 5V be twe e n VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs.
3. Wait 20 – 60 µs, and apply 11.5 – 12.5V to RESET.
4. Keep the Prog_enable pins unch anged for at least 10µs af ter the high volt age has been applied to ensure
Prog_enable signature has been latched.
5. Wait at least 300 µs before giving any parallel programming commands.
6. Exit programming mode by powering the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be
used:
1. Set Prog_enable pins (Table 23-4 on page 215) to “0000”, RESET pin to 0V and VCC to 0V.
2. Apply 4.5 – 5. 5V be twe e n VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 – 1.1V, apply 11.5 – 12.5V to RESET.
4. Keep the Prog_enable pins unch anged for at least 10µs af ter the high volt age has been applied to ensure
Prog_enable signature has been latched.
5. Wait until VCC actually reaches 4.5 – 5.5V before giving any parallel programming commands.
6. Exit programming mode by powering the device down or by bringing RESET pin to 0V.
23.2.2 Considerations for Efficient Programming
Loaded commands and addresses are retained in the device during programming. For efficient programming, the
following should be considered.
• When writing or reading multiple memory locations, the command needs only be loaded once
• Do not write the data value 0xFF, since this already is the contents of the entire Flash and EEPROM (unless the
EESAVE Fuse is programmed) after a Chip Erase
• Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or
256 byte EEPROM. This also applies to reading signature bytes
23.2.3 Chip Erase
A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. The Chip Erase command
will erase all Flash and EEPROM plus lock bits. If the EESAVE fuse is programmed, the EEPROM is not erased.
Lock bits are not reset until the program memory has been completely erased. Fuse bits are not changed.
0000 1000 Read signature bytes and calibration byte
0000 0100 Read fuse and lock bits
0000 0010 Read Flash
0000 0011 Read EEPROM
Table 23-6. Command Byte Bit Coding
Command Byte Command
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The Chip Erase command is loaded as follows:
1. Set XA1, XA0 to “10”. This enables command loading
2. Set BS1 to “0”
3. Set DATA to “1000 0000”. This is the command for Chip Erase
4. Give CLKI a positive pulse. This loads the command
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low
6. Wait until RDY/BSY goes high before loading a new command
23.2.4 Programming the Flash
Flash is organized in pages, as shown in Table 23-1 on page 214 . When prog ramming the F lash, the prog ram data
is first latched into a page buffer. This allows one page of program data to be program med simultaneously. The fol-
lowing procedure describes how to program the entire Flash memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give CLKI a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enab les address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 – 0xFF).
3. Give CLKI a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 23-3 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages
within the FLASH. This is illustrated in Figure 23-2 on page 218. Note that if less than eight bits are required to
address words in the page (pagesize < 256 ), the most significant bit(s) in the address low byte are used to
address the page when performing a Page Write.
G. Load Address High byte
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1. Set XA1, XA0 to “00”. This enab les address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.
2. Wait until RDY/BSY goes high (See Figure 23-3 for signal wave forms).
I. Repeat B through H until the entire Flash is programmed or until all data has been programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give CLKI a positive pulse. This loads the command, and the internal write signals are reset.
Flash page addressing is illustrated in Figure 23-2, below. Symbols used are described in Table 21-1 on page 205.
Figure 23-2. Addressing the Flash Which is Organized in Pages
Flash programming waveforms are illustrated in Figure 23-3, where XX means “don’t care” and letters refer to the
programming steps described earlier.
PROGRAM MEMORY
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
INSTRUCTION WORD
PA G E PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PA G E
PCWORDPCPAGE
PCMSBPAGEMSB
PROGRAM
COUNTER
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Figure 23-3. Flash Programming Waveforms
23.2.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 23-2 on page 214. When programming the EEPROM, the program
data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The program-
ming algorithm for the EEPROM data memory is as follows (see “Programming the Flash” on page 217 for details
on loading command, address and data):
• A: Load command “0001 0001”
• G: Load address high byte (0x00 – 0xFF)
• B: Load address low byte (0x00 – 0xFF)
• C: Load data (0x00 – 0xFF)
• E: Latch data (give PAGEL a positive pulse)
• K: Repeat steps B, C, and E until the entire buffer is filled
• L: Program EEPROM page:
– Set BS1 to “0”
–Give WR
a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low
– Wait until to RDY/BSY goes high before programming the next page (See Figure 23-4 for signal
waveforms)
EEPROM programming waveforms are illustrated in Figure 23-4, where XX means “don’t care” and letters refer to
the programming steps described above.
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x10 ADDR. LOW ADDR. HIGH
DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH
XA1
XA0
BS1
XTAL1
XX XX XX
ABCDEBCDEGH
F
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Figure 23-4. EEPROM Programming Waveforms
23.2.6 Reading the Flash
The algorithm for reading the Flash memory is as follows (see “Programming the Flash” on page 217 for details on
command and address loading):
• A: Load command “0000 0010”
• G: Load address high byte (0x00 – 0xFF)
• B: Load address low byte (0x00 – 0xFF)
•Set OE
to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA
• Set BS1 to “1”. The Flash word high byte can now be read at DATA
•Set OE
to “1”
23.2.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (see “Programming the Flash” on page 217 for
details on command and address loading):
• A: Load command “0000 0011”
• G: Load address high byte (0x00 – 0xFF)
• B: Load address low byte (0x00 – 0xFF)
•Set OE
to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA
•Set OE
to “1”
23.2.8 Programming Low Fuse Bits
The algorithm for program ming the low fuse bi ts is as follows (see “Pr ogramming the Flash” on page 217 for details
on command and data loading):
• A: Load command “0100 0000”
• C: Load data low byte. Bit n = “0” programs and bit n = “1” er ases the fuse bit
•Give WR
a negative pulse and wait for RDY/BSY to go high
RDY/BSY
WR
OE
RESET +12V
PAGEL
BS2
0x11 ADDR. HIGH
DATA ADDR. LOW DATA ADDR. LOW DATA XX
XA1
XA0
BS1
XTAL1
XX
AGBCEB C EL
K
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23.2.9 Programming High Fuse Bits
The algorithm for programming the high fuse bits is as follows (see “Programming the Flash” on page 217 for
details on command and data loading):
• A: Load command “0100 0000”
• C: Load data low byte. Bit n = “0” programs and bit n = “1” er ases the fuse bit
• Set BS1 to “1” and BS2 to “0”. This selects high data byte
•Give WR
a negative pulse and wait for RDY/BSY to go high
• Set BS1 to “0”. This selects low data byte
23.2.10 Programming Extended Fuse Bits
The algorithm for programming the extended fuse bits is as follows (see “Programming the Flash” on page 217 for
details on command and data loading):
• A: Load command “0100 0000”
• C: Load data low byte. Bit n = “0” programs and bit n = “1” er ases the fuse bit
• Set BS1 to “0” and BS2 to “1”. This selects extended data byte
•Give WR
a negative pulse and wait for RDY/BSY to go high
• Set BS2 to “0”. This selects low data byte
Fuse programming waveforms are illustrated in Figure 23-5, where XX means “don’t care” and letters refer to the
programming steps described above.
Figure 23-5. Fuses Programming Waveforms
23.2.11 Programming the Lock Bits
The algorithm for programming the lock bits is as follows (see “Programming the Flash” on page 217 for details on
command and da ta load in g) :
• A: Load command “0010 0000”
• C: Load data low byte. Bit n = “0” programs the Lock bit. If LB1 and LB2 have been programmed, it is not
possible to program the Lock Bits by any External Programming mode
RDY/BSY
WR
OE
RESET +12V
PAGEL
0x40
DATA DATA XX
XA1
XA0
BS1
XTAL1
AC
0x40 DATA XX
AC
Write Fuse Low byte Write Fuse high byte
0x40 DATA XX
AC
Write Extended Fuse byte
BS2
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•Give WR a negative pulse and wait for RDY/BSY to go high
Lock bits can only be cleared by executing Chip Erase.
23.2.12 Reading Fuse and Lock Bits
The algorithm for reading fuse and lock bits is as follows (see “Programming the Flash” on page 217 for details on
command loading):
• A: Load command “0000 0100”
•Set OE
to “0”, BS2 to “0” and BS1 to “0”. Low fuse bits can now be read at DATA (“0” means programmed)
•Set OE
to “0”, BS2 to “1” and BS1 to “1”. High fuse bits can now be read at DATA (“0” means programmed)
• Set OE to “0”, BS2 to “1”, and BS1 to “0”. Extended fuse bits can now be read at DATA (“0” means
programmed)
•Set OE
to “0”, BS2 to “0” and BS1 to “1”. Lock b its can now be read at DATA (“0” means programmed)
•Set OE
to “1”
Fuse and lock bit mapping is illustrated in Figure 23-6, below.
Figure 23-6. Mapping Between BS1, BS2 and the Fuse a nd Lock Bits During Read
23.2.13 Reading Signature Bytes
The algorithm for reading the signature bytes is as follows (see “Programming the Flash” on page 217 for details
on command and address loading):
1. A: Load command “0000 1000”
2. B: Load address low byte (0x00 – 0x02)
3. Set OE to “0”, and BS1 to “0”. The selected signature byte can now be read at DATA.
4. Set OE to “1”.
Lock Bits 0
1
BS2
Fuse High Byte
0
1
BS1
DATA
Fuse Low Byte 0
1
BS2
Extended Fuse Byte
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23.2.14 Reading the Calibration Byte
The algorithm for reading the calibration byte is as follows (see “Programming the Flash” on page 217 for details on
command and address loading):
1. A: Load command “0000 1000”.
2. B: Load address low byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The calibra tion byte can now be read at DATA.
4. Set OE to “1”.
23.3 Serial Programming
Flash and EEPROM memory arrays can both be programmed using the serial SPI bus while RESET is pulled to
GND. The seri al interf ace co nsists of pin s SCK, MOSI (input) and MISO (output). After RESET is set low, the Pro-
gramming Enable instruction needs to be executed before program/erase operations ca n be executed.
Serial programming signa ls and connections are illustrated in Figure 23-7, below. The pin ma pping is listed in
Table 23-7 on page 224.
Figure 23-7. Serial Programming Signals
Note: If the device is clocked by the internal oscillator th ere is no need to connect a clock source to the CLKI pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation and there
is no need to first execute the Chip Erase instruction. This applies for serial programming mode, only.
The Chip Erase operation turns the content of every memory location in Flash and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high period s for the serial clock
(SCK) input are defined as follows:
• Minimum low period of serial clock:
– 2 CPU clock cycles
• Minimum high period of serial clock:
– 2 CPU clock cycles
VCC
GND
CLKI
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
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23.3.1 Pin Mapping
The pin mapping is listed in Table 23-7. Note that not all parts use t he SPI pins dedicated for the internal SPI
interface.
23.3.2 Programming Algorithm
When writing serial data to the ATtiny16 34, da ta is clo cked on the rising ed ge o f SCK. When r eading data from the
ATtiny1634, data is clocked on the falling edge of SCK. See Fig ure 24-7 on page 238 and Figur e 24-8 on page 238
for timing details.
To program and verify the ATtiny1634 in the serial programming mod e, the following sequence is reco mmended
(See Table 23-8, “Serial Programming Instruction Set,” on page 225):
1. Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during po we r- up . In this
case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse
must be at least tRST plus two CPU clock cycles. See Table 24- 5 on page 231 for definition of minimum
pulse width on RESET pin, tRST
2. Wait for at least 20 ms and then enable serial programming by sending the Programming Enable serial
instruction to the MOSI pin
3. The serial programming instructions will not work if the communicat ion is out of synchronization. When in
sync, the second byte (0x53) will echo back when issuing the third byte of the Programming Enable
instruction
– Regardless if the echo is correct or not, all four bytes of the instruction must be transmitted
– If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable
command
4. The Flash is programmed one p age at a time. The memor y page is loaded one byte at a time by supplying
the 6 LSB of the address and data together with the Load Program Memory Page instruction.
– To ensure correct loading of the page, data low byte must be loaded before data high byte for a given
address is applied
– The Program Memory Page is stored by loading the Write Prog ram Memory Page instruction with the 7
MSB of the address
– If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page
(See Table 23-9). Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. The EEPROM can be programmed one byte or one page at a time.
–A: Byte programming. The EEPROM array is programmed one byte at a time by supplying the address
and data together with the Write instruction. EEPROM memory locations are automatically erased
before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM
before issuing the next byte (See Table 23-9). In a chip erased device, no 0xFFs in the da ta file(s) ne ed
to be programmed
–B: Page programming (the EEPROM array is programmed one page at a time). The memory page is
loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM memory page is stored by loading the Write
Table 23-7. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB1 I Serial Data in
MISO PB2 O Serial Data out
SCK PC1 I Serial Clock
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EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page
access only byte locations loaded with the Load EEPROM Memory Page instruction are altered and
the remaining locations remain unchanged. If polling (RDY/BSY) is not used, the user must wait at
least tWD_EEPROM before issuing the next b yte (See Ta ble 23-9). In a chip erased device, no 0xFF in the
data file(s) need to be programmed
6. Any memory location can be verified by using the Read instruction, which returns the content at the
selected address at the serial output pin (MISO)
7. At the end of the programming session, RESET can be set high to commence normal operation
8. Power-off sequence (if required): set RESET to “1”, and turn VCC powe r off
23.3.3 Programming Instruct ion Set
The instruction set for serial programming is described in Table 23-8 and Figure 23-8 on page 226.
Table 23-8. Serial Programming Instruction Set
Instruction/Operation
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Programming Enable $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte (1) $ 4D $00 Extended adr $00
Load Program Memory Page, High byte $48 $00 adr LSB high da ta byte in
Load Program Memory Page, Low byte $40 $00 adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 0000 000aa (2) data byte in
Read Instructions
Read Progra m Memory, High byte $28 adr MSB adr LSB h i g h data byte out
Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 0000 00aa (2) aaaa aaaa (2) data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 0000 000aa (2) data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Fuse Extended Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out
Writ e Instru cti on s (3)
Write Program Memory Page $4C adr MSB (4) adr LSB (4) $00
Write EEPROM Memory $C0 0000 00aa (2) aaaa aaaa (2) data byte in
Write EEPROM Memory Page (page access) $C2 0000 00aa (2) aaaa aa00 (2) $00
Write Lock bits (5) $AC $E0 $00 data byte in
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Notes: 1. Not all instructions are applicable for all parts.
2. a = address.
3. Instructions accessing program memory use a word address. This address may be rando m within the page range.
4. Word addressing.
5. To ensure future compatibility, unused fuses and lock bits should be unprogrammed (‘1’) .
If the LSB of RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’
before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 23-8 on page 226.
Figure 23-8. Serial Programming Instruction example
Write Fuse bit s (5) $AC $A0 $00 data byte in
Write Fuse High bits (5) $AC $A8 $00 data byte in
Write Fuse Extended Bits (5) $AC $A4 $00 data byte in
Table 23-8. Serial Programming Instruction Set (Continued)
Instruction/Operation
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Byte 1 Byte 2 Byte 3 Byte 4
Adr MSB
Adr LSB
Bit 15 B 0
Serial Programming Instruction
Program Memory/
EEPROM Memory
Page 0
Page 1
Page 2
Page N-1
Page Buffer
Write Program Memory Page/
Write EEPROM Memory Page
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1 Byte 2 Byte 3 Byte 4
Bit 15 B 0
Adr MSB
Adr LSB
Page Offset
Page Number
Adr
dr M
r MS
SB
A
A
Adr
dr LS
LSB
SB
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24. Electrical Characteristics
24.1 Absolute Maximum Ratings*
24.2 DC Characteristics
Operating Temperature............... .. ................. -55C to +125C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65C to +150C
Voltage on any Pin except RESET
with respect to Ground ................................ -0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin............................................... 40.0 mA
DC Current VCC and GND Pins ................................ 200.0 mA
Table 24-1. DC Characteristics. TA = -40C to +85C
Symbol Parameter Condition Min Typ (1) Max Units
VIL
Input Low Voltage VCC = 1.8 - 2.4V -0.5 0.2VCC (2) V
VCC = 2.4 - 5.5V -0.5 0.3VCC (2) V
Input Low Voltage,
RESET Pin as Reset (4) VCC = 1.8 - 5.5V -0.5 0.2VCC (2)
VIH
Input High-voltage
Except RESET pin VCC = 1.8 - 2.4V 0.7VCC(3) VCC +0.5 V
VCC = 2.4 - 5.5V 0.6VCC(3) VCC +0.5 V
Input High-voltage
RESET pin as Reset (4) VCC = 1.8 - 5.5V 0.9VCC(3) VCC +0.5 V
VOL Output Low Voltage(5)
Except RESET pin(7)
Standard I/O: IOL = 10 mA, VCC = 5V 0.6 V
High-sink I/O: IOL = 20 mA, VCC = 5V
Standard I/O: IOL = 5 mA, VCC = 3V 0.5 V
High-sink I/O: IOL = 10 mA, VCC = 3V
VOH Output High-voltage(6)
Except RESET pin(7) IOH = -10 mA, VCC = 5V 4.3 V
IOH = -5 mA, VCC = 3V 2.5 V
ILIL Input Leakage Current
I/O Pin Vcc = 5.5V, pin low (absolute value) < 0.05 1 (8) µA
ILIH Input Leakage Current
I/O Pin Vcc = 5.5V, pin high (absolute value) < 0.05 1 (8) µA
RPU Pull-up Resistor, I/O Pin VCC = 5.5V, input low 20 50 k
Pull-up Resistor, Reset Pin VCC = 5.5V, input low 30 60 k
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Notes: 1. Typical values at +25C.
2. “Max” means the highest value where the pin is guaranteed to be read as low.
3. “Min” means the lowest value where the pin is guaranteed to be read as high.
4. Not tested in production.
5. Although each I/O port can sink more than the test cond itions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the sum of all IOL (for all ports) should not exceed 100 mA. If IOL exceeds the test conditions, VOL
may exceed the related specification. Pins are not gua ranteed to sink current greater than the listed test condition.
6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the sum of all IOH (for all ports) should not exceed 100 mA. If IOH exceeds the test condition, VOH
may exceed the related specification. Pins are no t guaranteed to source current greater than the listed test condition.
7. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence,
has a weak drive strength as compared to regular I/O pins. See “Output Driver Strength” on page 256.
8. These are test limits, which account for leakage currents of the test environment. Actual device leakage currents are lower.
9. Values are with external clock using methods described in “Minimizing Power Consumption” on page 36. Power Reduction
is enabled (PRR = 0xFF) and there is no I/O drive.
10.Bod Disabled.
24.3 Speed
The maximum operating frequency of the device is dependent on supply voltage, V CC . The relatio nship between
supply voltage and maximum operating frequency is piecewise linear, as shown in Figure 24-1.
ICC
Supply Current,
Active Mode (9)
f = 1MHz, VCC = 2V 0.23 0.4 mA
f = 4MHz, VCC = 3V 1.3 1.7 mA
f = 8MHz, VCC = 5V 4.3 6 mA
Supply Current,
Idle Mode (9)
f = 1MHz, VCC = 2V 0.04 0.1 mA
f = 4MHz, VCC = 3V 0.26 0.4 mA
f = 8MHz, VCC = 5V 1.1 1.7 mA
Supply Current,
Power-Down Mode(10) WDT enabled, VCC = 3V 1.7 4 µA
WDT disabled, VCC = 3V 0.1 2 µA
Table 24-1. DC Characteristics. TA = -40C to +85C (Continued)
Symbol Parameter Condition Min Typ (1) Max Units
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Figure 24-1. Maximum Frequency vs. VCC
24.4 Clock
24.4.1 Accuracy of Calibrated 8MHz Oscillator
It is possible to manually calibrate the internal 8MHz oscillator to be more accurate than default factory calibration.
Note that the osc illator frequency depends on temp erature and voltage. Voltage and temperat ure characterist ics
can be found in “Calibrated Oscillator Frequency (Nominal = 1MHz) vs. VCC” on page 271 and “Calibrated Oscilla-
tor Frequency (Nominal = 1MHz) vs. Temperature” on page 271.
Notes: 1. See device ordering codes on page 277 for alternatives.
2. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
24.4.2 Accuracy of Calibrated 32kHz Oscillator
It is possible to manually calibrate the internal 32kHz oscillator to be more accurate than default factory calibration.
Note that the osc illator frequency depends on temp erature and voltage. Voltage and temperat ure characterist ics
2 MHz
1.8V 5.5V
4.5V
12 MHz
2.7V
8 MHz
Table 24-2. Calibration Accuracy of Internal 8MHz Oscillator
Calibration
Method Target
Frequency VCC Temperature Accuracy
Factory
Calibration 8.0M Hz 2.7 – 4V 0C to +85C±2%
(1)
25C to +85C±10%
(1)
User
Calibration Within:
7.3 – 8.1MHz Within:
1.8 – 5.5V Within:
-40C to +85C±1% (2)
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can be found in “ULP Oscillator Frequency (Nominal = 32kHz) vs. VCC” on page 272, and “ULP Oscillator Fre-
quency (Nominal = 32kHz) vs. Temperature” on page 272.
24.4.3 External Clock Drive
Figure 24-2. External Clock Drive Waveform
24.5 System and Reset
Table 24-3. Calibration Accuracy of Internal 32kHz Oscillator
Calibration
Method Target
Frequency VCC Temperature Accuracy
Factory
Calibration 32kHz 1.8 – 5.5V -40 C to +85C ±30%
Table 24-4. External Clock Drive Characteristics
Symbol Parameter
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/tCLCL Clock Frequency 0208012MHz
tCLCL Clock Period 500 125 83 ns
tCHCX High Time 200 40 20 ns
tCLCX Low Time 200 40 20 ns
tCLCH Rise T im e 2.0 1.6 0.5 s
tCHCL Fall Time 2.0 1.6 0.5 s
tCLCL Change in period from
one clock cycle to next 222%
VIL1
VIH1
Table 24-5. Reset, Brown-out, and Internal Voltage Characteristics
Symbol Parameter Condition Min Typ Max Units
VRST RESET pin threshold voltage 0.2VCC 0.9VCC V
tRST Minimum pulse width on
RESET pin
VCC = 1.8V
VCC = 3V
VCC = 5V
2000
700
400 ns
VHYST Brown-out Detector hysteresis 50 mV
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24.5.1 Power-On Reset
Note: 1. Values are guidelines only.
2. Threshold where device is released from reset when voltage is rising.
3. The Power-on Reset will not work unless the supply voltage has been below VPOA.
24.5.2 Brown-Out Detection
Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the
device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur
before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
tBOD Minimum pulse width on
Brown-out Reset 2µs
VBG Internal bandgap reference
voltage VCC = 2.7V
TA=25°C 1.0 1.1 1.2 V
tBG Internal bandgap reference
start-up time VCC = 2.7V
TA=25°C 40 70 µs
IBG Internal bandgap reference
current consumption VCC = 2.7V
TA=25°C 15 µA
Table 24-5. Reset, Brown-out, and Internal Voltage Characteristics (Continued)
Symbol Parameter Condition Min Typ Max Units
Table 24-6. Characteristics of Enhanced Power-On Reset. TA = -40 to +85C
Symbol Parameter Min(1) Typ(1) Max(1) Units
VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V
VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V
SRON Power-On Slope Rate 0.01 V/ms
Table 24-7. VBOT vs. BODLEVEL Fuse Coding
BODLEVEL[2:0] Fuses Min(1) Typ(1) Max(1) Units
11X 1.7 1.8 2.0
V101 2.5 2.7 2.9
100 4.1 4.3 4.5
0XX Reserved
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24.6 Two-Wire Serial Interface
The following data is based on simulations and characterisa ti ons. Para meters listed in Ta ble 24 -8 are not tested in produc-
tion. Symbols refer to Figure 24-3.
Notes: 1. fCK = CPU clock frequency.
Figure 24-3. Two-Wire Serial Bus Timing
Table 24-8. Two-Wire Serial Inte rface Characteristics
Symbol Parameter Condition Min Max Unit
VIL Input Low voltage -0.5 0.3 VCC V
VIH Input High voltage 0.7 VCC VCC + 0.5 V
VHYS Hysteresis of Schmitt-trigger inputs VCC 2.7V 0.05 VCC –V
VCC < 2.7V 0
VOL Output Low voltage 3mA sink current 0 0.4 V
tSP Spikes suppressed by input filter 0 50 ns
fSCL SCL clock frequency (1) fCK > max(16f SCL, 250kHz) 0 400 kHz
tHD:STA Hold time (repeated) START Condition 0.6 – µs
tLOW Low period of SCL clock 1.3 – µs
tHIGH High period of SCL clock 0.6 – µs
tSU:STA Set-up time for repeated START condition 0.6 – µs
tHD:DAT Data hold time 00.9µs
tSU:DAT Data setup time 100 – ns
tSU:STO Setup time for STOP condition 0.6 – µs
tBUF Bus free time between STOP and START condition 1.3 – µs
tSU:STA
tLOW
tHIGH
tLOW
tOF
tHD:STA tHD:DAT tSU:DAT tSU:STO
tBUF
SCL
SDA
tR
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24.7 Analog to Digital Converter
Table 24-9. ADC Characteristics, Single Ended Channels. T = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and Of fset
Errors)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz 2.0 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz 2.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
Noise Reduction Mode 1.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz
Noise Reduction Mode 2.0 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and
Gain Calibration)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz 1.0 LSB
Differential Non-linearity
(DNL) VREF = 4V, VCC = 4V,
ADC clock = 200kHz 0.5 LSB
Gain Error VREF = 4V, VCC = 4V,
ADC clock = 200kHz 2.0 LSB
Offset Error (Absolute) VREF = 4V, VCC = 4V,
ADC clock = 200kHz 1.5 LSB
Conversion Time Free Running Conversion 14 280 µs
Clock Frequency 50 1000 kHz
VIN Input Voltage GND VREF V
Input Bandwidth 38.5 kHz
AREF External Voltage Reference 2.0 VCC V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
ADC Conversion Output 0 1023 LSB
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24.8 Analog Comparator
24.9 Temperature Sensor
Note: 1. Firmware calculates temperature based on factory calibration value.
2. Min and max values are not guaranteed. Contact your local Atmel sales office if higher accuracy is required.
24.10 Parallel Programming
Figure 24-4. Parallel Programming Timing, Including some General Timing Requirements
Table 24-10. Analog Comparator Characteristics, TA = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 < 10 40 mV
ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 -50 50 nA
tAPD
Analog Propagation Delay
(from saturation to slight overdrive) VCC = 2.7V 75 0
ns
VCC = 4.0V 500
Analog Propagation Delay
(large step chang e) VCC = 2.7V 100
VCC = 4.0V 75
tDPD Digital Propagation Delay VCC = 1.8 - 5.5V 1 2 CLK
Table 24-11. Accuracy of Temperature Sensor at Factory Calibration
Symbol Parameter Condition Min Typ Max Units
ATS Accuracy VCC = 4.0, TA = 25C – 85C10 C
Data & Contol
(
DATA, XA0/1, BS1, BS2)
CLKI
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
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Figure 24-5. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Note: 1. The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 24-6. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
Note: 1. The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
CLKI
PAGEL
t
PLXH
XLXH
tt
XLPH
z
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) LOAD DATA
(LOW BYTE) LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
CLKI
OE
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE) READ DATA
(LOW BYTE) READ DATA
(HIGH BYTE) LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ
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Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Wr ite Lock bits commands.
2. tWLRH_CE is valid for the Chip Erase command.
Table 24-12. Parallel Programming Characteristics, TA = 25C, VCC = 5V
Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 A
tDVXH Data and Control Valid before CLKI High 67 ns
tXLXH CLKI Low to CLKI High 200 ns
tXHXL CLKI Pulse Width High 150 ns
tXLDX Data and Control Hold after CLKI Low 67 ns
tXLWL CLKI Low to WR Low 0 ns
tXLPH CLKI Lo w to PAGEL high 0 ns
tPLXH PAGEL low to CLKI high 150 ns
tBVPH BS1 Valid before PA GEL High 67 ns
tPHPL PAGEL Pulse Width High 150 ns
tPLBX BS1 Hold after PAGEL Low 67 ns
tWLBX BS2/1 Hold after WR Low 67 ns
tPLWL PAGEL Low to WR Low 67 ns
tBVWL BS1 Valid to WR Low 67 ns
tWLWH WR Pulse Width Low 150 ns
tWLRL WR Low to RDY/BSY Low 0 1 s
tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms
tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 3.7 9 ms
tXLOL CLKI Low to OE Low 0 ns
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns
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24.11 Serial Programming
Figure 24-7. Serial Programming Timing
Figure 24-8. Serial Programming Waveform
Table 24-13. Serial Programming Characteristics, TA = -40C to +85C
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency @ VCC = 1.8V - 5.5V 0 1 MHz
tCLCL Oscillator Period @ VCC = 1.8V - 5.5V 1000 ns
1/tCLCL Oscillator Frequency @ VCC = 4.5V - 5.5V 0 6 MHz
tCLCL Oscillator Period @ VCC = 4.5V - 5.5V 167 ns
tSHSL SCK Pulse Width High 2 tCLCL ns
tSLSH SCK Pulse Width Low 2 tCLCL ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
M
OSI
M
ISO
SCK
t
OVSH
t
SHSL
t
SLSH
t
SHOX
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
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25. Typical Characteristics
The data contained in this sectio n is largely based on simulations and chara cterization of similar devices in the
same process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturi ng. During characteri-
sation devices are operated at frequencies higher than test limits but they are not guaranteed to function properly
at frequencies higher than the ordering code indicates.
All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-
ups enabled. Current consumption is a function of several factors such as operating voltage, operating frequency,
loading of I/O pins, switching rate of I/O pins, code executed an d amb ien t temp er ature . The do mina ting fa cto rs are
operating voltage and fr equency.
A sine wave generator with ra il-to-rail output is used as clock source but current con sumption in Power-Down
mode is independent of clock selection. The difference between current consumption in Power-Down mode with
Watchdog Timer enabled and Powe r- Down mode with Watch dog Timer disabled represents the differential current
drawn by the Watchdog Timer.
The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:
where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin.
25.1 Current Consumption in Active Mode
Figure 25-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
ICP VCC CLf SW
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency [MHz]
ICC [mA]
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Figure 25-2. Active Supply Current vs. Frequency (1 - 12 MHz)
Figure 25-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz)
0
1
2
3
4
5
6
7
8
2
1
01
86420
Frequency [MHz]
ICC [mA]
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
85
25
-40
0
1
2
3
4
5
6
1,522,533,544,555,5
VCC [V]
ICC [mA]
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Figure 25-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz)
Figure 25-5. Active Supply Current vs. VCC (Internal Oscillator, 32kHz)
85
25
-40
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [mA]
85
25
-40
0
0,005
0,01
0,015
0,02
0,025
0,03
0,035
0,04
0,045
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [mA]
242
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.2 Current Consumption in Idle Mode
Figure 25-6. Idle Supply Current vs. Lo w Frequency (0.1 - 1.0 MHz)
Figure 25-7. Idle Supply Current vs. Fr eq ue n cy (1 - 12 MH z )
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
0,18
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency [MHz]
ICC [mA]
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
024681012
Frequency [MHz]
ICC [mA]
243
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-8. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz)
Figure 25-9. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz)
85
25
-40
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [mA]
85
25
-40
0
0,1
0,2
0,3
0,4
0,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
I
CC
[mA]
244
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-10. Idle Supply Current vs. VCC (Internal Oscillator, 32kHz)
25.3 Current Consumption in Standby Mode
Figure 25-11. Standby Supply Current vs. VCC (Watchdog Time r Enabled)
85
25
-40
0
0,01
0,02
0,03
0,04
0,05
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC
ICC
8MHz
32kHz
0
0,05
0,1
0,15
0,2
0,25
1,5 2 2,5 3 3,5 4 4,5 5 5,5
V
CC
[V]
I
CC
[mA]
245
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.4 Current Consumption in Power-down Mode
Figure 25-12. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
Figure 25-13. Power-down Supply Current vs. VCC (Wat ch do g T ime r Ena b l ed )
85
25
-40
0
0,2
0,4
0,6
0,8
1
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [uA]
85
25
-40
0
1
2
3
4
5
6
7
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [uA]
246
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.5 Current Consumption in Reset
Figure 25-14. Reset Current vs. Frequency (0.1 – 1MHz, Excluding Pull-Up Current)
Figure 25-15. Reset Current vs. Frequency (1 – 12MHz, Excluding Pull-Up Current)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency [MHz]
ICC [mA]
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
2
4
6
8
10
2
10
1
8
6
4
2
0
Frequency [MHz]
I
CC
[mA]
247
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-16. Reset Current vs. VCC (No Clock, excluding Reset Pull-Up Current)
25.6 Current Consumption of Peripheral Units
Figure 25-17. Current Consumption of Peripherals at 1MHz
85
25
-40
0
0,5
1
1,5
2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [mA]
T/C1
T/C0
ADC
AC
0
100
200
300
400
500
600
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [uA]
248
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-18. Watchdog Timer Current vs. VCC
Figure 25-19. Brownout Detector Current vs. VCC
85
25
-40
0
0,001
0,002
0,003
0,004
0,005
0,006
1,5 2 2,5 3 3,5 4 4,5 5 5,5
V
CC
Icc [mA]
85
25
-40
0
5
10
15
20
25
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [uA]
249
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-20. Sampled Brownout Detector Current vs. VCC
Figure 25-21. AREF External Reference Pin Current (V CC = 5V)
85
25
-40
0
1
2
3
4
5
6
7
8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
ICC [uA]
85
25
-40
0
20
40
60
80
100
120
140
160
1,5 2 2,5 3 3,5 4 4,5 5 5,5
AREF [V]
AREF pin current [uA]
250
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.7 Pull-up Resistors
Figure 25-22. I/ O pin Pull-u p Resistor Current vs. Inpu t Volt ag e (V CC = 1.8V)
Figure 25-23. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V)
0
10
20
30
40
50
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP [V]
IOP [uA]
25
-40
85
0
20
40
60
80
00,511,522,53
VOP [V]
IOP [uA]
25
-40
85
251
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-24. I/ O pin Pull-u p Resistor Current vs. Inpu t Volt ag e (V CC = 5V)
Figure 25-25. Reset Pull-up Resistor Current vs. Reset Pin Voltag e (V CC = 1.8V)
-0
20
40
60
80
100
120
140
0123456
VOP [V]
IOP [uA]
25
-40
85
25
-40
0
10
20
30
40
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET [V]
IRESET [uA]
85
252
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-26. Reset Pull-up Resistor Current vs. Reset Pin Voltag e (V CC = 2.7V)
Figure 25-27. Reset Pull-up Resistor Current vs. Reset Pin Voltag e (V CC = 5V)
0
10
20
30
40
50
60
0 0,5 1 1,5 2 2,5 3
VRESET [V]
IRESET [uA]
25
-40
85
0
20
40
60
80
100
120
0123456
VRESET [V]
IRESET [uA]
25
-40
85
253
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.8 Input Thresholds
Figure 25-28. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’)
Figure 25-29. VIL: Input Thresh o ld Volt ag e vs. VCC (I/O Pin, Read as ‘0’)
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
V
CC
[V]
Threshold [V]
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
Threshold [V]
254
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-30. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin)
Figure 25-31. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’)
85
25
-40
0
0,1
0,2
0,3
0,4
0,5
0,6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC
Hysteris [V]
[V]
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
Threshold [V]
255
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-32. VIL: Input Thresh o ld Volt ag e vs. VCC (Reset Pin as I/O, Read as ‘0’)
Figure 25-33. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O)
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,522,533,544,555,5
VCC [V]
Threshold [V]
85
25
-40
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1,522,533,544,555,5
V
CC
Hysteresis [V]
[V]
256
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.9 Output Driver Strength
Figure 25-34. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V)
Figure 25-35. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V)
85
25
-40
0
0,5
1
1,5
2
5
432
1
0
IOH [mA]
VOH [V]
85
25
-40
0
0,5
1
1,5
2
2,5
3
0
1
86
420
IOH [mA]
VOH [V]
257
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-36. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V)
Figure 25-37. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V)
85
25
-40
0
1
2
3
4
5
02510150
IOH [mA]
VOH [V]
85
25
-40
0
0,2
0,4
0,6
0,8
1
543210
I
OL
[mA]
V
OL
[V]
258
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-38. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V)
Figure 25-39. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V)
85
25
-40
0
0,2
0,4
0,6
0,8
1
0
1
8
6
42
0
IOL [mA]
VOL [V]
85
25
-40
0
0,2
0,4
0,6
0,8
1
0
2
51
0
150
IOL [mA]
VOL [V]
259
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-40. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 1.8V
Figure 25-41. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 3V
85
25
-40
0
0,5
1
1,5
2
18
,
06
,0
4,
02
,
0
0
IOH [mA]
VOH [V]
85
25
-40
0
0,5
1
1,5
2
2,5
3
18,06,04,0
2
,00
IOH [mA]
VOH [V]
260
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-42. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V
Figure 25-43. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 1.8V)
85
25
-40
0
1
2
3
4
5
18,06,04,02,00
IOH [mA]
VOH [V]
25
-40
0
0,2
0,4
0,6
0,8
1
18,06,04,02,00
IOL [mA]
VOL [V]
85
261
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-44. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 3V)
Figure 25-45. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V)
85
25
-40
0
0,2
0,4
0,6
0,8
1
25,115,00
IOL [mA]
VOL [V]
85
25
-40
0
0,2
0,4
0,6
0,8
1
00,511,522,533,54
IOL [mA]
VOL [V]
262
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.10 BOD
Figure 25-46. BOD Threshold vs Temperature (BODLEVEL = 4.3V)
Figure 25-47. BOD Threshold vs Temperature (BODLEVEL = 2.7V)
VCC RISING
VCC FALLING
4,16
4,18
4,2
4,22
4,24
4,26
4,28
4,3
4,32
-40-30-20-10 0 102030405060708090100
Temperature [C]
Threshold [V]
VCC RISING
VCC FALLING
2,62
2,64
2,66
2,68
2,7
2,72
2,74
2,76
-40-30-20-100 102030405060708090100
Temperature [C]
Threshold [V]
263
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-48. BOD Threshold vs Temperature (BODLEVEL = 1.8V)
Figure 25-49. Sampled BOD Threshold vs Temperature (BODLEVEL = 4.3V)
VCC RISING
VCC FALLING
1,75
1,76
1,77
1,78
1,79
1,8
1,81
1,82
-40-30-20-10 0 102030405060708090100
Temperature [C]
Threshold [V]
VCC RISING
VCC FALLING
4,25
4,26
4,27
4,28
4,29
4,3
4,31
4,32
4,33
-40-30-20-100 102030405060708090100
Temperature [C]
Threshold [V]
264
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-50. Sampled BOD Threshold vs Temperature (BODLEVEL = 2.7V)
Figure 25-51. Sampled BOD Threshold vs Temperature (BODLEVEL = 1.8V)
VCC RISING
VCC FALLING
2,7
2,71
2,72
2,73
2,74
2,75
2,76
-40-30-20-10 0 102030405060708090100
Temperature [C]
Threshold [V]
VCC RISING
VCC FALLING
1,77
1,775
1,78
1,785
1,79
1,795
1,8
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [C]
Threshold [V]
265
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.11 Bandgap Voltage
Figure 25-52. Bandgap Voltage vs. Supply Voltage
Figure 25-53. Bandgap Voltage vs. Temperature (VCC = 3.3V)
85
25
-40
1,04
1,045
1,05
1,055
1,06
1,065
1,07
1,075
1,08
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc [V]
Bandgap [V]
1,04
1,045
1,05
1,055
1,06
1,065
1,07
-40-30-20-100 102030405060708090100
Temperature [C]
Bandgap Voltage [V]
266
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.12 Reset
Figure 25-54. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’)
Figure 25-55. VIL: Input Thresh o ld Volt ag e vs. VCC (Reset Pin, Read as ‘0’)
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
Threshold [V]
85
25
-40
0
0,5
1
1,5
2
2,5
3
1,522,533,544,555,5
VCC [V]
Threshold [V]
267
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-56. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin )
Figure 25-57. Minimum Reset Pulse Width vs. VCC
85
25
-40
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
Hysteresis [V]
85
25
-40
0
500
1000
1500
2000
2500
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
Pulsewidth [ns]
268
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
25.13 Analog Comparator Offset
Figure 25-58. Analog Comparator Offset vs. VIN (VCC = 5V)
Figure 25-59. Analog Comparator Offset vs. VCC (VIN = 1.1V)
85
25
-40
0
2
4
6
8
10
12
14
16
00,511,522,533,544,55
Vin [V]
Offset [mV]
0
1
2
3
4
5
6
7
8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc [V]
Offset [mV]
85
25
-40
269
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-60. Analog Comparator Hysteresis vs. VIN (VCC = 5.0V)
25.14 Internal Oscillator Speed
Figure 25-61. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. VCC
85
25
-40
0
5
10
15
20
25
30
35
40
45
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5
Vin [V]
Hysteresis [mV]
85
25
-40
7,9
8
8,1
8,2
8,3
8,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
V
CC
[V]
F
RC
[MHz]
270
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-62. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. Temperature
Figure 25-63. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. OSCCAL Value
5.0 V
3.0 V
7,9
7,95
8
8,05
8,1
8,15
8,2
-40 -20 0 20 40 60 80 100
Temperature [°]
FRC [MHz]
0
2
4
6
8
10
12
14
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL [X1]
FRC [MHz]
271
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-64. Calibrated Oscillator Frequency (Nominal = 1MHz) vs. VCC
Figure 25-65. Calibrated Oscillator Frequency (Nominal = 1MHz) vs. Temperature
85
25
-40
0,97
0,98
0,99
1
1,01
1,02
1,03
1,04
1,05
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
FRC [MHz]
5.0 V
3.0 V
1.8 V
0,97
0,98
0,99
1
1,01
1,02
1,03
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°]
F
RC
[MHz]
272
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
Figure 25-66. ULP Oscillator Frequency (Nominal = 32kHz) vs. VCC
Figure 25-67. ULP Oscillator Frequency (Nominal = 32kHz) vs. Temperature
85
25
-40
28000
29000
30000
31000
32000
33000
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC [V]
FRC [Hz]
28000
29000
30000
31000
32000
33000
34000
-40-20 0 20406080100
Temperature [°]
FRC [Hz]
273
ATtiny1634 [DATASHEET]
8303G–AVR–11/2013
26. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s)
(0xFF)Reserved––––––––
(0xFE) Reserved – – – – – – – –
(0xFD) Reserved – – – – – – – –
(0xFC) Reserved – – – – – – – –
(0xFB) Reserved – – – – – – – –
(0xFA) Reserved – – – – – – – –
(0xF9) Reserved – – – – – – – –
... ... ... ... ... ... ... ... ... ... ...
(0x85) Reserved – – – – – – – –
(0x84) Reserved – – – – – – – –
(0x83) Reserved – – – – – – – –
(0x82) Reserved – – – – – – – –
(0x81) Reserved – – – – – – – –
(0x80) Reserved – – – – – – – –
(0x7F) TWSCRA TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME 127
(0x7E) TWSCRB TWAA TWCMD[1:0] 127
(0x7D) TWSSRA TWDIF TWASIF TWCH TWRA TWC TWBE TWDIR TWAS 128
(0x7C) TWSA TWI Slave Address Register 130
(0x7B) TWSAM TWI Slave Address Mask Register 130
(0x7A) TWSD TWI Slave Data Register 130
(0x79) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 167
(0x78) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 168
(0x77) UCSR1C UMSEL11 UMSEL10 UPM11 UPM01 USBS1 UCSZ11 UCSZ10 UCPOL1 169
(0x76) UCSR1D RXSIE1 RXS1 SFDE1 171
(0x75) UBRR1H USART1 Baud Rate Regi ster High Byte 172
(0x74) UBRR1L USART1 Baud Rate Register Low Byte 172
(0x73) UDR1 USART1 I/O Data Register 167
(0x72) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 ––WGM11WGM10 111
(0x71) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 113
(0x70) TCCR1C FOC1A FOC1B – – – – – – 114
(0x6F) TCNT1H Timer/Counter1 – Counter Register High Byte 114
(0x6E) TCNT1L Timer/Counter1 – Counter Register Low Byte 114
(0x6D) OCR1AH Timer/Counter1 – Compare Register A High Byte 114
(0x6C) OCR1AL Timer/Counter1 – Compare Register A Low Byte 114
(0x6B) OCR1BH Timer/Counter1 – Compare Register B High Byte 115
(0x6A) OCR1BL Timer/Counter1 – Compare Register B Low Byte 115
(0x69) ICR1H Timer /Counter1 – Input Capture Register High Byte 115
(0x68) ICR1L Timer/Counter1 – Input Capture Register Low Byte 115
(0x67) GTCCR TSM –––––– PSR10 118
(0x66) OSCCAL1 – – – – – –CAL11CAL10 33
(0x65) OSCTCAL0B Oscillator Temperature Compensation Re gister B 33
(0x64) OSCTCAL0A Oscillator Temperature Compensation Re gister A 33
(0x63) OSCCAL0 CAL07 CAL06 CAL05 CAL04 CAL03 CAL02 CAL01 CAL00 32
(0x62) DIDR2 – – – – – ADC11D ADC10D ADC9D 200
(0x61) DIDR1 – – – – ADC8D ADC7D ADC6D ADC5D 200
(0x60) DIDR0 ADC4D ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D AREFD 184, 200
0x3F (0x5F) SREG I T H S V N Z C 14
0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13
0x3C (0x5C) GIMSK – INT0 PCIE2 PCIE1 PCIE0 – – – 51
0x3B (0x5B) GIFR – INTF0 PCIF2 PCIF1 PCIF0 – – – 52
0x3A (0x5A) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 88, 115
0x39 (0x59) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 89, 116
0x38 (0x58) QTCSR QTouch Control and Status Register 6
0x37 (0x57) SPMCSR –– RSIG CTPB RFLB PGWRT PGERS SPMEN 207
0x36 (0x56) MCUCR –SM1SM0SE ––ISC01ISC00 37, 51
0x35 (0x55) MCUSR – – – – WDRF BORF EXTRF PORF 44
0x34 (0x54) PRR –PRTWI PRTIM0 PRTIM0 PRUSI PRUSART1 PRUSART0 PRADC 38
0x33 (0x53) CLKPR – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 31
0x32 (0x52) CLKSR O SCRDY CSTR CKOUT_IO SUT CKSEL3 CKSEL2 CKSEL1 CKSEL0 29
0x31 (0x51) Reserved – – – – – – – –
0x30 (0x50) WDTCSR WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 45
0x2F (0x4F) CCP CPU Change Protection Register 13
0x2E (0x4E) DWDR DWDR[7:0] 202
0x2D (0x4D) USIBR USI Buffer Register 144
0x2C (0x4C) USIDR USI Data Register 143
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
0x2B (0x4B) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 142
0x2A (0x4A) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 140
0x29 (0x49) PCMSK2 –– PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 52
0x28 (0x48) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 53
0x27 (0x47) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 53
0x26 (0x46) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM 167
0x25 (0x45) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TX B80 168
0x24 (0x44) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 169
0x23 (0x43) UCSR0D RXCIE0 RXS0 SFDE0 – – – – – 171
0x22 (0x42) UBRR0H – – – – USART0 Baud Rate Register High Byte 172
0x21 (0x41) UBRR0L USART0 Baud Rate Reg ister Low Byte 172
0x20 (0x40) UDR0 USART0 I/O Data Register 167
0x1F (0x3F) EEARH – – – – – – – –
0x1E (0x3E) EEARL EEAR[7:0] 22
0x1D (0x3D) EED R EEPROM Data Register 22
0x1C (0x3C) EECR –– EEPM1 EEPM0 EERIE EEMPE EEPE EERE 22
0x1B (0x3B) TCCR0A COM0A 1 COM0A0 COM0B1 COM0B0 ––WGM01WGM00 84
0x1A (0x3A) TCCR0B FOC0A FOC0B –– WGM02 CS02 CS01 CS00 86
0x19 (0x39) TCNT0 Timer/Counter0 88
0x18 (0x38) OCR0A Timer/Counter0 – Compare Register A 88
0x17 (0x37) OCR0B Timer/Counter0 – Compare Register B 88
0x16 (0x36) GPIOR2 General Purpose Register 2 23
0x15 (0x35) GPIOR1 General Purpose Register 1 24
0x14 (0x34) GPIOR0 General Purpose Register 0 24
0x13 (0x33) PORTCR – – – – – BBMC BBMB BBMA 71
0x12 (0x32) PUEA PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 71
0x11 (0x31) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 71
0x10 (0x30) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 71
0x0F (0x2F) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 71
0x0E (0x2E) PUEB – – – – PUEB3 PUEB2 PUEB1 PUEB0 72
0x0D (0x2D) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 72
0x0C (0x2C) DDRB – – – – DDB3 DDB2 DDB1 DDB0 72
0x0B (0x2B) PINB – – – – PINB3 PINB2 PINB1 PINB0 72
0x0A (0x2A) PUEC –– PUEC5 PUEC4 PUEC3 PUEC2 PUEC1 PUEC0 72
0x09 (0x29) PORTC –– PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 72
0x08 (0x28) DDRC –– DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 72
0x07 (0x27) PINC –– PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 72
0x06 (0x26) ACSRA ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 182
0x05 (0x25) ACSRB HSEL HLEV ACLP –ACCE ACME ACIRS1 ACIRS0 183
0x04 (0x24) ADMUX REFS1 REFS0 REFEN ADC0EN MUX3 MUX2 MUX1 MUX0 196
0x03 (0x23) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 197
0x02 (0x22) ADCSRB VDEN VDPD –– ADLAR ADTS2 ADTS1 ADTS0 199
0x01 (0x21) ADCH ADC Data Register High Byte 198
0x00 (0x20) ADCL ADC Data Registe r Low Byte 198
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s)
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27. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immedia te to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Regi sters Rd Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Sub tr act with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registe rs Rd Rd Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1
COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1
INC Rd Increment Rd Rd + 1 Z,N,V 1
DEC Rd Decrement Rd Rd 1 Z,N,V 1
TST Rd Test for Ze ro or Minus Rd Rd Rd Z,N,V 1
CLR Rd Clear Register Rd Rd Rd Z,N,V 1
SER Rd Set Register Rd 0xFF None 1
BRANCH INSTRUCTIONS
JMP k Direct Jump PC kNone3
RJMP k Relative Jump PC PC + k + 1 Non e 2
IJMP Indirect Jump to (Z) PC Z None 2
CALL k Direct Subrou tine PC kNone4
RCALL k Relative Su broutine Call PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ZNone3
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 Non e 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC P C + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 N one 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) 0None2
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1
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ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) TNone1
SEC Set Carry C 1C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1S1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Twos Complement Overflow. V 1V1
CLV Clear Twos Complement Overflow V 0 V 1
SET Set T in SREG T 1T1
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1H1
CLH Clear Half Carry Flag in SRE G H 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd KNone1
LD Rd, X Load Indire ct Rd (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2
LD Rd, Y Load Indire ct Rd (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2
LD Rd, Z Load Indirect Rd (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2
LDS Rd, k Load Direct fr om SRAM Rd (k) None 2
ST X, Rr Store Indirect (X) Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2
STS k, Rr Store Direct to SRAM (k) Rr None 2
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memo ry and Post-Inc Rd (Z), Z Z+1 None 3
SPM Store Program Memory (z) R1:R0 None
IN Rd, P In Port Rd PNone1
OUT P, Rr Out Port P Rr None 1
PUSH Rr Push Register on Stack STACK Rr No ne 2
POP Rd Pop Register from Stack Rd STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #Clocks
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28. Ordering Information
Notes: 1. For speed vs. supply voltage, see section 24.3 “Speed” on page 229.
2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. Denotes accuracy of the internal oscillator. See Table 24-2 on page 230.
4. Code indicators:
– U: matte tin
– R: tape & reel
5. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
28.1 ATtiny1634
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Accuracy (3) Ordering Code (4)
12 1.8 – 5.5 Industrial
(-40C to +85C) (5)
20M1
±10% ATtiny1634-MU
±2% ATtiny1634R-MU
±10% ATtiny1634-MUR
±2% ATtiny1634R-MUR
20S2
±10% ATtiny1634-SU
±2% ATtiny1634R-SU
±10% ATtiny1634-SUR
±2% ATtiny1634R-SUR
Package Type
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (QFN/MLF)
20S2 20-lead, 0.300" Wide Body, Plastic Gull Win g Small Outline Package (SOIC)
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29. Packaging Information
29.1 20M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, B
20M1
10/27/04
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A 0.70 0.75 0.80
A1 – 0.01 0.05
A2 0.20 REF
b 0.18 0.23 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
L 0.35 0.40 0.55
SIDE VIEW
Pin 1 ID
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
TOP VIEW
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E
e
A2
A1
A
D2
E2
0.08 C
L
1
2
3
b
1
2
3
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29.2 20S2
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30. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny1634 device.
30.1 ATtiny1634
30.1.1 Rev. B
•Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
1. Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
Port pin PB3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not
running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PB3 as an input, activate the watchdog
timer. The watchdog timer automatically enables the ULP oscillator.
30.1.2 Rev. A
•Flash / EEPROM Can Not Be Written When Supply Voltage Is Below 2.4V
•Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
1. Flash / EEPROM Can Not Be Written When Supply Voltage Is Below 2.4V
When supply voltage is below 2.4V write operations to Flash and EEPROM may fail.
Problem Fix / Workaround
Do not write to Flash or EEPROM when supply voltage is below 2.4V.
2. Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
Port pin PB3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not
running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PB3 as an input, activate the watchdog
timer. The watchdog timer automatically enables the ULP oscillator.
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31. Datasheet Revision History
31.1 Rev. 8303G – 11/2013
1. Removed references to Wafer Level Chip Scale Package option.
31.2 Rev. 8303F – 08/2013
1. Updated Bit 2 from the UCSR1C register from “USBSZ11” to “UCSZ11” in “Register Summary” on page
273.
31.3 Rev. 8303E – 01/2013
1. Updated:
– Applied the Atmel new brand template that includes new log and new addresses.
31.4 Rev. 8303D – 06/12
1. Updated:
–“Ordering Information” on page 277
2. Added:
– Wafer Level Chip Scale Package “Errata” on page 280
31.5 Rev. 8303C – 03/12
1. Updated:
–“Register Description” on page 167
–“Self-Programming” on page 203
31.6 Rev. 8303B – 03/12
1. Removed Preliminary status.
2. Added:
–“Typical Characteristics” on page 239
–“Temperature Sensor” on page 235
–“Rev. B” on page 280
3. Updated:
–“Pin Descriptions” on page 3
–“Calibrated Internal 8MHz Oscillator” on page 27
–“OSCTCAL0A – Oscillator Temperature Calibration Register A” on page 33
–“OSCTCAL0B – Oscillator Temperature Calibration Register B” on page 33
–“TWSCRA – TWI Slave Control Register A” on page 127
–“USART (USART0 & USART1)” on page 145
–“Temperature vs. Sensor Output Voltage (Typical)” on page 195
–“DC Characteristics” on page 228
–“Calibration Accuracy of Internal 32kHz Oscillator” on page 231
–“External Clock Drive Characteristics” on page 231
–“Reset, Brown-out, and Internal Voltage Characteristics” on page 231
–“Analog Comparator Char acteristics, TA = -40°C to +85°C” on page 235
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ATtiny1634 [DATASHEET]
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Table of Contents
Features .....................................................................................................1
1 Pin Configurations ...................................................................................2
1.1 Pin Descriptions .................................................................................................3
2 Overview ...................................................................................................4
3 General Information .................................................................................6
3.1 Resources .........................................................................................................6
3.2 Code Examples .................................................................................................6
3.3 Capacitive Touch Sensing .................................................................................6
3.4 Data Retention ...................................................................................................6
4CPU Core ...................................................................................................6
4.1 Architectural Overview .......................................................................................7
4.2 ALU – Arithmetic Logic Unit ...............................................................................8
4.3 Status Regist er ............ ... .... ... ... ... ... .... ... ................ ... .... ... ... ... ................ .... ... ... ..8
4.4 General Purpose Register File ..........................................................................8
4.5 Stack Pointer ...................................................................................................10
4.6 Instruction Execution Timing .... ... ................ .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...10
4.7 Reset and Interrupt Handling ...........................................................................11
4.8 Register Description ........................................................................................13
5 Memories .................................................................................................14
5.1 Program Memory (Flash) .................................................................................15
5.2 Data Memory (SRAM) and Register Files .......................................................16
5.3 Data Memory (EEPROM) ................................................................................18
5.4 Register Description ........................................................................................22
6 Clock System ..........................................................................................24
6.1 Clock Subsystems ....... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... ................. ... ...25
6.2 Clock Sources ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ................ ... .... ... ...26
6.3 Sys tem Clock Prescaler ................. .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...28
6.4 Clock Output Buffer ............ ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...29
6.5 Register Description ........................................................................................29
7 Power Management and Sleep Modes .................................................34
7.1 Sleep Modes ....................................................................................................34
7.2 Power Reduction Register ...............................................................................36
7.3 Minimizing Power Consumption ......................................................................36
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7.4 Register Description ........................................................................................37
8 System Control and Reset .....................................................................39
8.1 Resetting the AVR ...........................................................................................39
8.2 Reset Sources .................................................................................................39
8.3 Internal Voltage Reference ..............................................................................42
8.4 Watchdog Timer ..............................................................................................43
8.5 Register Description ........................................................................................44
9 Interrupts .................................................................................................47
9.1 Interrupt Vectors .......... ... .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ...47
9.2 External Interrupts ...........................................................................................48
9.3 Register Description ........................................................................................51
10 I/O Ports ..................................................................................................54
10.1 Overview ...... ............................. ............................................. .......................... 54
10.2 Ports as General Digital I/O .............................................................................54
10.3 Alternate Port Functions ..................................................................................59
10.4 Register Description ........................................................................................71
11 8-bit Timer/Counter0 with PWM ............................................................73
11.1 Features ..........................................................................................................73
11.2 Overview ...... ............................. ............................................. .......................... 73
11.3 Clock Sources ....... ... ... ... .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ...74
11.4 Counter Unit ....................................................................................................74
11.5 Output Compare Unit .......................................................................................75
11.6 Compare Match Output Unit ............................................................................77
11.7 Modes of Operation .........................................................................................78
11.8 Timer/Counter Timing Diagrams ..... .... ... ... ... ................. ... ... ... ... .... ................ ...82
11.9 Register Description ........................................................................................84
12 16-bit Timer/Counter1 ............................................................................90
12.1 Features ..........................................................................................................90
12.2 Overview ...... ............................. ............................................. .......................... 90
12.3 Timer/Counter Clock Sources .. ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ......92
12.4 Counter Unit ....................................................................................................92
12.5 Input Capture Unit . ... ... ... .... ................ ... ... ... .... ... ................ ... ... .... ... ................93
12.6 Output Compare Units .....................................................................................95
12.7 Compare Match Output Unit ............................................................................97
12.8 Modes of Operation .........................................................................................98
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12.9 Timer/Counter Timing Diagrams ..... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ....106
12.10 Accessing 16-bit Registers ............................................................................107
12.11 Register Description ......................................................................................111
13 Timer/Counter Prescaler ......................................................................117
13.1 Prescaler Reset . .... ... ... ................ ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... .117
13.2 External Clock Source ...................................................................................118
13.3 Register Description ......................................................................................118
14 I2C Compatible, Two-Wire Slave Interface .........................................119
14.1 Features ........................................................................................................119
14.2 Overview ...... ............................................. ............................................. ........ 119
14.3 General TWI Bus Concepts ...........................................................................119
14.4 TWI Slave Operation ... ... .... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... .125
14.5 Register Description ......................................................................................127
15 USI – Universal Serial Interface ..........................................................131
15.1 Features ........................................................................................................131
15.2 Overview ...... ............................................. ............................................. ........ 131
15.3 Three-wire Mode ...........................................................................................132
15.4 Two-wire Mode ............... .... ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... .134
15.5 Alternative Use ..............................................................................................136
15.6 Program Examples ........................................................................................137
15.7 Register Descriptions ....................................................................................140
16 USART (USART0 & USART1) ..............................................................145
16.1 Features ........................................................................................................145
16.2 USART0 and USART1 ..................................................................................145
16.3 Overview ...... ............................................. ............................................. ........ 145
16.4 Clock Generation ................ ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... ........147
16.5 Frame Formats ............... .... ... ... ... ... .... ... ... ................ .... ... ... ... ... .... ... ... ...........149
16.6 USART Initialization .......................................................................................151
16.7 Data Transmission – The USART Transmitter ..............................................152
16.8 Data Reception – The USART Receiver .......................................................154
16.9 Asynchronous Data Reception .............. ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .158
16.10 M ulti-processor Communic at ion Mode ..........................................................162
16.11 Examples of Baud Rate Setting .....................................................................163
16.12 Register Description ......................................................................................167
17 USART in SPI Mode ..............................................................................173
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17.1 Features ........................................................................................................173
17.2 Overview ...... ............................................. ............................................. ........ 173
17.3 Clock Generation ................ ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... ........173
17.4 SPI Data Modes and Timing ..........................................................................173
17.5 Frame Formats ............... .... ... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... .174
17.6 Data Transfer .................................................................................................176
17.7 Compatibility with AVR SPI ...........................................................................178
17.8 Register Description ......................................................................................178
18 Analog Comparator ..............................................................................181
18.1 Analog Comparator Multiplexed Input ...........................................................181
18.2 Register Description ......................................................................................182
19 Analog to Digital Converter .................................................................185
19.1 Features ........................................................................................................185
19.2 Overview ...... ............................................. ............................................. ........ 185
19.3 Operation .......................................................................................................186
19.4 Starting a Conversion ....................................................................................187
19.5 Prescaling and Conversion Timing ................................................................188
19.6 Changing Channel or Reference Selection ...................................................191
19.7 ADC Noise Canceler .....................................................................................192
19.8 Analog Input Circuitry ....................................................................................192
19.9 Noise Canceling Techniques .........................................................................193
19.10 ADC Accuracy Definitions .............................................................................193
19.11 ADC Conversion Result .................................................................................195
19.12 Temperature Measurement ............ .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .195
19.13 Register Description ......................................................................................196
20 debugWIRE On-chip Debug System ...................................................201
20.1 Features ........................................................................................................201
20.2 Overview ...... ............................................. ............................................. ........ 201
20.3 Physical Interface ..........................................................................................201
20.4 Software Break Points .............. ... ... ................. ... ... ... .... ... ... ... ... .... ... ... ...........202
20.5 Limitations of debugWIRE .............................................................................202
20.6 Register Description ......................................................................................202
21 Self-Programming ................................................................................203
21.1 Features ........................................................................................................203
21.2 Overview ...... ............................................. ............................................. ........ 203
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21.3 Lock Bits ........................................................................................................203
21.4 Self-Programming the Flash ..........................................................................203
21.5 Preventing Flash Corruption ..... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .206
21.6 Programming Time for Flash when Using SPM .............................................206
21.7 Register Description ......................................................................................207
22 Lock Bits, Fuse Bits and Device Signature .......................................208
22.1 Lock Bits ........................................................................................................208
22.2 Fuse Bits ......... ................ .... ... ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... .209
22.3 Device Signature Imprint Table .....................................................................210
22.4 Reading Lock, Fuse and Signature Data from Software ...............................211
23 External Programming .........................................................................214
23.1 Memory Parametrics .....................................................................................214
23.2 Parallel Programming .. ... .... ... ... ... ... ...............................................................214
23.3 Serial Programming .......................................................................................223
23.4 Programming Time for Flash and EEPROM ..................................................227
24 Electrical Characteristics ....................................................................228
24.1 Absolute Maximum Ratings* .........................................................................228
24.2 DC Characteristics .........................................................................................228
24.3 Speed ............................................................................................................229
24.4 Clock ......... .......................................................... ........................................... 230
24.5 System and Reset ....... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ....231
24.6 Two-Wire Serial Interface ...... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .233
24.7 Analog to Digital Converter ............................................................................234
24.8 Analog Comparator .......................................................................................235
24.9 Temperature Sensor ......................................................................................235
24.10 Parallel Programming ............... ... ... .... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... .235
24.11 Serial Programming .......................................................................................238
25 Typical Characteristics ........................................................................239
25.1 Current Consumption in Active Mode ............................................................239
25.2 Current Consumption in Idle Mode ................................................................242
25.3 Current Consumption in Standby Mode ........................................................244
25.4 Current Consumption in Power-down Mode ..................................................245
25.5 Current Consumption in Reset ......................................................................246
25.6 Current Consumption of Peripheral Units ......................................................247
25.7 Pull-up Resistors ......... ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... .250
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25.8 Input Thresholds ............. .... ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ...........253
25.9 Output Driver Strength ...................................................................................256
25.10 BOD ...............................................................................................................262
25.11 Bandgap Voltage ...........................................................................................265
25.12 Reset .............................................................................................................266
25.13 Analog Comparator Offset .............................................................................268
25.14 Internal Oscillator Speed ...............................................................................269
26 Register Summary ................................................................................273
27 Instruction Set Summary .....................................................................275
28 Ordering Information ...........................................................................277
28.1 ATtiny1634 ....................................................................................................277
29 Packaging Information .........................................................................278
29.1 20M1 ......... .......................... ......................... ............................. ..................... 278
29.2 20S2 ..............................................................................................................279
30 Errata .....................................................................................................280
30.1 ATtiny1634 ....................................................................................................280
31 Datasheet Revision History .................................................................281
31.1 Rev. 8303G – 11/2013 ..................................................................................281
31.2 Rev. 8303F – 08/2013 ...................................................................................281
31.3 Rev. 8303E – 01/2013 ........ ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .281
31.4 Rev. 8303D – 06/12 ............................ ... ... ... .... ... ... ... .... ................ ... ... ... .... ... .281
31.5 Rev. 8303C – 03/12 ............................ ... ... ... .... ... ... ... .... ................ ... ... ... .... ... .281
31.6 Rev. 8303B – 03/12 .. ... ... .... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ....281
31.7 Rev. 8303A – 11/11 .. ... ... .... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ....282
Table of Contents.......................................................................................i
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