8-Channel/4-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F
Rev. F
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FEATURES
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Low on resistance (270 Ω typical)
Fast switching times
tON: 230 ns maximum
tOFF: 130 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
Break-before-make construction
TTL and CMOS compatible inputs
APPLICATIONS
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
GENERAL DESCRIPTION
The ADG508F and ADG509F are CMOS analog multi-
plexers, with the ADG508F comprising eight single channels
and the ADG509F comprising four differential channels. These
multiplexers provide fault protection. Using a series n-channel,
p-channel, n-channel MOSFET structure, both device and signal
source protection is provided in the event of an overvoltage or
power loss. The multiplexer can withstand continuous overvolt-
age inputs from −40 V to +55 V. During fault conditions with
power supplies off, the multiplexer input (or output) appears as
an open circuit and only a few nanoamperes of leakage current
will flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG509F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used
to enable or disable the device. When disabled, all channels are
switched off.
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
A0
D
ADG508F
A1 A2 EN
1 OF 8
DECODER
00035-001
Figure 1.
S1A
A0
DA
ADG509F
A1
S4A
S1B
S4B
DB
EN
1 OF 4
DECODER
00035-101
Figure 2.
PRODUCT HIGHLIGHTS
1. Fault protection. The ADG508F/ADG509F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
2. On channel saturates while fault exists.
3. Low RON.
4. Fast switching times.
5. Break-before-make switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
6. Trench isolation eliminates latch-up. A dielectric trench
separates the p and n-channel MOSFETs thereby
preventing latch-up.
ADG508F/ADG509F
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Truth Tables................................................................................... 4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Test Circuits..................................................................................... 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG528F ..............................................................Universal
Changes to Features Section and General Description Section . 1
Changes to Specifications Section.................................................. 3
Deleted Timing Diagrams Section ................................................. 4
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 6
Added Table 6.................................................................................... 7
Replaced Typical Performance Characteristics Section .............. 8
Changes to Terminology Section.................................................. 10
Changes to Figure 27 and Figure 28............................................. 13
Changes to Figure 31...................................................................... 14
Changes to Theory of Operation Section.................................... 11
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 17
7/09—Rev. D: Rev. E
Updated Format..................................................................Universal
Added TSSOP .....................................................................Universal
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
ADG508F/ADG509F
Rev. F | Page 3 of 20
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS + 1.4 V typ Output open circuit
V
DD − 1.4 V typ
V
SS + 2.2 V typ Output loaded, 1 mA
V
DD – 2.2 V typ
RON 270 350 Ω typ −10 V ≤ VS ≤ +10 V, IS = 1 mA;
390 Ω max
VDD = +15 V ± 10%, VSS = −15 V ± 10%
See Figure 21
RON Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA
On-Resistance Match Between
Channels, RON 3 % max VS = ±10 V, IS = −1 mA
LEAKAGE CURRENTS
Source Off Leakage IS (Off) ±0.02 nA typ VD = ±10 V, VS = +10 V;
±1 ±50 nA max See Figure 22
Drain Off Leakage ID (Off) ±0.04 nA typ VD = ±10 V, VS = +10 V;
ADG508F ±1 ±60 nA max See Figure 23
ADG509F ±1 ±30 nA max
Channel On Leakage ID, IS (On) ±0.04 nA typ VS = VD = ± 10 V;
ADG508F ±1 ±60 nA max See Figure 24
ADG509F ±1 ±30 nA max
FAULT
Source Leakage Current IS (Fault) ±0.02 nA typ VS = +55 V or −40 V, VD = 0 V, see Figure 25
(With Overvoltage) ±2 ±2 A max
Drain Leakage Current ID (Fault) ±5 nA typ
VS = ±25 V, VD = +10 V, see Figure 23
(With Overvoltage) ±2 A max
Source Leakage Current IS (Fault)
(Power Supplies Off) ±1 nA typ VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
±2 A max See Figure 26
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±1 A max VIN = 0 or VDD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS1
tTRANSITION 175 ns typ RL = 1 MΩ, CL = 35 pF;
220 300 ns max VS1 = ±10 V, VS8 = +10 V; see Figure 27
tOPEN 90 ns typ RL = 1 kΩ, CL = 35 pF;
60 40 ns min VS = 5 V; see Figure 28
tON (EN) 180 ns typ RL = 1 kΩ, CL = 35 pF;
230 300 ns max VS = 5 V; see Figure 29
tOFF (EN) 100 ns typ RL = 1 kΩ, CL = 35 pF
130 150
tSETT, Settling Time ns max VS = 5 V; see Figure 29
0.1% 1 s typ RL = 1 kΩ, CL = 35 pF;
0.01% 2.5 s typ VS = 5 V
ADG508F/ADG509F
Rev. F | Page 4 of 20
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
Charge Injection 15 pC typ VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 30
Off Isolation 93 dB typ RL = 1 kΩ, CL = 15 pF, f = 100 kHz; VS = 7 V rms;
see Figure 31
CS (Off) 3 pF typ
CD (Off)
ADG508F 22 pF typ
ADG509F 12 pF typ
POWER REQUIREMENTS
IDD 0.05 0.2 mA max VIN = 0 V or 5 V
ISS 0.1 1 µA max
1 Guaranteed by design, not subject to production test.
TRUTH TABLES
Table 2. ADG508F Truth Table1
A2 A1 A0 EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
1 X = don’t care.
Table 3. ADG509F Truth Table1
A1 A0 EN On Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
1 X = don’t care.
ADG508F/ADG509F
Rev. F | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 4.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Digital Input, EN, Ax −0.3 V to VDD + 0.3 V or
20 mA, whichever occurs first
VS, Analog Input Overvoltage with
Power On (VDD = +15 V, VSS = −15 V)
VSS − 25 V to VDD + 40 V
VS, Analog Input Overvoltage with
Power Off (VDD = 0 V, VSS = 0 V)
−40 V to +55 V
Continuous Current, S or D 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP
θJA, Thermal Impedance 112°C/W
Plastic DIP Package
θJA, Thermal Impedance
16-Lead 117°C/W
SOIC Package
θJA, Thermal Impedance
Narrow Body 77°C/W
Wide Body 75°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG508F/ADG509F
Rev. F | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0 1
EN 2
VSS 3
S1 4
A116
A215
GND14
VDD
13
S2 5
S3 6
S4 7
S5
12
S6
11
S710
D8S89
ADG508F
TOP VIEW
(Not to Scale)
00035-004
Figure 3. ADG508F Pin Configuration
Table 5. ADG508F Pin Function Descriptions
Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4 S1 Source Terminal 1. This pin can be an input or an output.
5 S2 Source Terminal 2. This pin can be an input or an output.
6 S3 Source Terminal 3. This pin can be an input or an output.
7 S4 Source Terminal 4. This pin can be an input or an output.
8 D Drain Terminal. This pin can be an input or an output.
9 S8 Source Terminal 8. This pin can be an input or an output.
10 S7 Source Terminal 7. This pin can be an input or an output.
11 S6 Source Terminal 6. This pin can be an input or an output.
12 S5 Source Terminal 5. This pin can be an input or an output.
13 VDD Most Positive Power Supply Potential.
14 GND Ground (0 V) Reference.
15 A2 Logic Control Input.
16 A1 Logic Control Input.
ADG508F/ADG509F
Rev. F | Page 7 of 20
A0
1
EN
2
V
SS 3
S1A
4
A1
16
GND
15
V
DD
14
S1B
13
S2A
5
S3A
6
S4A
7
S2B
12
S3B
11
S4B
10
DA
8
DB
9
ADG509F
TOP VIEW
(Not to Scale)
00035-005
Figure 4. ADG509F Pin Configuration
Table 6. ADG509F Pin Function Descriptions
Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4 S1A Source Terminal 1A. This pin can be an input or an output.
5 S2A Source Terminal 2A. This pin can be an input or an output.
6 S3A Source Terminal 3A. This pin can be an input or an output.
7 S4A Source Terminal 4A. This pin can be an input or an output.
8 DA Drain Terminal A. This pin can be an input or an output.
9 DB Drain Terminal B. This pin can be an input or an output.
10 S4B Source Terminal 4B. This pin can be an input or an output.
11 S3B Source Terminal 3B. This pin can be an input or an output.
12 S2B Source Terminal 2B. This pin can be an input or an output.
13 S1B Source Terminal 1B. This pin can be an input or an output.
14 VDD Most Positive Power Supply Potential.
15 GND Ground (0 V) Reference.
16 A1 Logic Control Input.
ADG508F/ADG509F
Rev. F | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
V
DD
= +15V
V
SS
= –15V
00035-011
T
A
= 125°C
T
A
= 105°C
T
A
= 85°C
T
A
= 25°C
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
T
A
= 25°C
V
DD
= +5V
V
SS
= –5V
V
DD
= +10V
V
SS
= –10V
V
DD
= +15V
V
SS
= –15V
00035-008
Figure 5. On Resistance as a Function of VD (VS) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
VS SOURCE VOLTAGE (V)
ISINPUT LEAKAGE (A)
OPERATING RANGE
VDD = 0V
VSS = 0V
VD = 0V
00035-009
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
V
S
SOURCE VOLTAGE (V)
I
S
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
00035-012
Figure 6. Source Input Leakage Current as a Function of VS (Power Supplies
Off) During Overvoltage Conditions
Figure 9. Source Input Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
0.3
0.2
–0.3
–14 –10 –6 –2 2 6 10 14
0.1
0.0
–0.2
–0.1
V
S
,V
D
(V)
LEAKAGE CURRENTS (nA)
I
D
(OFF)
I
S
(OFF)
I
D
, I
S
(ON)
V
DD
= +15V
V
SS
= –15V
V
S
(V
D
) = ±10V
T
A
= 25°C
00035-013
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
V
S
SOURCE VOLTAGE (V)
I
D
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
00035-010
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 7. Drain Output Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
ADG508F/ADG509F
Rev. F | Page 9 of 20
100
10
0.01
45 5525 65 75 85 95 10535
1
115 125
0.1
TEMPERATURE (°C)
LEAKAGE CURRENTS (nA)
V
DD
= +15V
V
SS
= –15V
V
D
= +10V
V
S
= –10V
I
S
(OFF)
I
D
(ON)
I
D
(OFF)
00035-014
Figure 11. Leakage Currents as a Function of Temperature
260
240
100
10 11 12 13 14 15
120
t
ON
(EN)
220
200
180
160
140
SWITCHING TIME (ns)
POWER SUPPLY (V)
t
TRANSITION
t
OFF
(EN)
00035-015
Figure 12. Switching Time vs. Dual Power Supply
300
0
–40 –20 0 20 40 60 80 100 120
50
250
200
150
100
TEMPERATURE (°C)
SWITCHING TIME (ns)
00035-016
t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
V
DD
= +15V
V
SS
= –15V
Figure 13. Switching Time vs. Temperature
–120
–100
–80
–60
–40
–20
0
OFF ISOL
A
TION (dB)
FREQUENCY (Hz)
10k 100k 1M 10M 100M 1G1k
000354-113
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
Figure 14. Off Isolation vs. Frequency, ±15 V Dual Supply
0
5
10
15
20
25
30
35
40
–15 –10 –5 0 5 10 15
PIN CAPACITANCE (pF)
V
S
(V)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
DRAIN OFF
SOURCE OFF
00035-114
Figure 15. Capacitance vs. Source Voltage
–30
–20
–10
0
10
20
30
–15 –10 –5 0 5 10 15
Q
INJ
(pC)
V
S
(V)
00035-115
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
Figure 16. Charge Injection vs. Source Voltage
ADG508F/ADG509F
Rev. F | Page 10 of 20
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential.
GND
Ground (0 V) reference.
RON
Ohmic resistance between D and S.
RON Drift
Percentage change in RON when temperature changes by one
degree Celsius.
ΔRON
ΔRON represents the difference between the RON of any two
channels as a percentage of the maximum RON of those two
channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
IS (Fault—Power Supplies On)
Source leakage current when exposed to an overvoltage
condition.
ID (Fault—Power Supplies On)
Drain leakage current when exposed to an overvoltage
condition.
IS (Fault—Power Supplies Off)
Source leakage current with power supplies off.
VD (VS)
Analog Voltage on Terminals D, S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IDD
Positive supply current.
ISS
Negative supply current.
ADG508F/ADG509F
Rev. F | Page 11 of 20
THEORY OF OPERATION
The ADG508F/ADG509F multiplexers are capable of withstand-
ing overvoltages from −40 V to +55 V, irrespective of whether the
power supplies are present or not. Each channel of the multiplexer
consists of an n-channel MOSFET, a p-channel MOSFET, and an
n-channel MOSFET, connected in series. When the analog input
exceeds the power supplies, one of the MOSFETs will saturate
limiting the current. The current during a fault condition is
determined by the load on the output. Figure 17 illustrates
the channel architecture that enables these multiplexers to
withstand continuous overvoltages.
When an analog input of VSS + 2.2 V to VDD − 2.2 V (output
loaded, 1 mA) is applied to the ADG508F/ADG509F, the
multiplexer behaves as a standard multiplexer, with spec-
ifications similar to a standard multiplexer, for example,
the on-resistance is 390 Ω maximum. However, when an
overvoltage is applied to the device, one of the three
MOSFETs saturate.
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET saturates because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega-
tive than VSS is applied to the multiplexer, the p-channel
MOSFET will saturate because the analog input is more
negative than the difference between VSS and the p-channel
threshold voltage (VTP). Because VTN is nominally 1.4 V and
VTP −1.4 V, the analog input range to the multiplexer is limited
to VSS + 1.4 V to VDD – 1.4 V (output open circuit) when a
±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
During fault conditions (power supplies off), the leakage
current into and out of the ADG508F/ADG509F is limited to
a few microamps. This protects the multiplexer and succeeding
circuitry from over stresses as well as protecting the signal
sources which drive the multiplexer. Also, the other channels
of the multiplexer will be undisturbed by the overvoltage and
will continue to operate normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET
SATURATES
VDD VSS
00035-017
Figure 17. +55 V Overvoltage Input to the On Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET
IS ON p-CHANNEL
MOSFET
SATURATES
VSS VDD
00035-018
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
00035-019
Figure 19. +55 V Overvoltage with Power Off
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
00035-020
Figure 20. −40 V Overvoltage with Power Off
ADG508F/ADG509F
Rev. F | Page 12 of 20
TEST CIRCUITS
IDS
S
RON = V1/IDS
V1
V
S
D
0
0035-021
Figure 21. On Resistance
S1
S2
S8
V
D
I
S
(OFF)
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-022
Figure 22. IS (Off)
S1
S2
S8
V
S
I
D
(OFF)
V
D
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-023
Figure 23. ID (Off)
0
0035-025
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
Figure 24. ID (On)
S1
S2
S8
VSVD
VDD VSS
V
DD
V
SS
D
0.8VEN
A
00035-026
Figure 25. Input Leakage Current (with Overvoltage)
A2
0V
0
V
V
DD
V
SS
V
S
D
0
V
A1
A0
EN
GND
ADG508F
S1
S8
A
00035-027
Figure 26. Input Leakage Current (with Power Supplies Off)
ADG508F/ADG509F
Rev. F | Page 13 of 20
A2
V
SS
V
DD
D
V
S1
V
IN
V
S8
V
OUT
A1
A0
EN
GND
ADG508F*
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1MΩ
C
L
35pF
V
SS
V
DD
*SIMILAR CONNECTION FOR ADG509F.
3V
50%
V
OUT
t
TRANSITION
90%
90%
t
TRANSITION
ADDRESS
DRIVE (V
IN
)50%
00035-024
Figure 27. Switching Time of Multiplexer, tTRANSITION
A2
V
SS
V
DD
D
V
S
V
IN
V
OUT
A1
A0
EN
GND
ADG508F*
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1kΩ
C
L
35pF
V
SS
V
DD
ADDRESS
DRIVE (V
IN
)
3V
V
OUT
t
OPEN
80% 80%
*SIMILAR CONNECTION FOR ADG509F.
00035-029
Figure 28. Break-Before-Make Delay, tOPEN
A2
V
SS
V
DD
D
V
S
V
OUT
A1
A0
EN
GND
ADG508F*
S1
S2 TO S8
R
L
1kΩ
50ΩC
L
35pF
V
SS
V
DD
ENABLE
DRIVE (V
IN
)
3V
0V
0V
V
OUT
OUTPUT
t
ON
(EN)
t
OFF
(EN)
50%50%
0.9V
OUT
0.1V
OUT
*SIMILAR CONNECTION FOR ADG509F.
00035-030
V
IN
Figure 29. Enable Delay, tON (EN), tOFF (EN)
ADG508F/ADG509F
Rev. F | Page 14 of 20
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= C
L
× ∆V
OUT
0V
A2
V
OUT
D
*SIMILAR CONNECTION FOR ADG509F.
A1
A0
EN
GND
ADG508F*
S
C
L
1nF
V
S
V
SS
V
SS
V
DD
V
DD
V
IN
R
S
∆V
OUT
00035-033
Figure 30. Charge Injection
00035-034
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
IN
V
IN
SA
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
NC
SB
OFF ISOLATION = 20 log V
OUT
V
S
Figure 31. Off Isolation
ADG508F/ADG509F
Rev. F | Page 15 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 32. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 33. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ADG508F/ADG509F
Rev. F | Page 16 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ADG508F/ADG509F
Rev. F | Page 17 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG508FBNZ −40°C to +85°C 16-Lead PDIP N-16
ADG508FBRN −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRNZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRNZ–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRWZ −40°C to +85°C 16-Lead SOIC_W RW-16
ADG508FBRWZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
ADG508FBRUZ −40°C to +85°C 16-Lead TSSOP RU-16
ADG508FBRUZ-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16
ADG509FBNZ −40°C to +85°C 16-Lead PDIP N-16
ADG509FBRN −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRNZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRNZ–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRWZ −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRWZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRUZ −40°C to +85°C 16-Lead TSSOP RU-16
ADG509FBRUZ-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16
1 Z = RoHS Compliant Part.
ADG508F/ADG509F
Rev. F | Page 18 of 20
NOTES
ADG508F/ADG509F
Rev. F | Page 19 of 20
NOTES
ADG508F/ADG509F
Rev. F | Page 20 of 20
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00035-0-7/11(F)