COLDFIRE2UM - Motorola / Freescale Semiconductor

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ColdFire 2/2M

Integrated Microprocessor

User’s Manual

MOTOROLA

ColdFire2/2M User’s Manual

iii

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MOTOROLA

ColdFire2/2M User’s Manual

PREFACE

The

ColdFire2/2M Integrated Microprocessor User’s Manual

describes the programming,

capabilities, and operation of the ColdFire2/2M device. Refer to the

MCF5200 ColdFire

Family Programmer’s Reference Manual Rev. 1.0

for information on the ColdFire Family of

microprocessors.

Throughout this document, the ColdFire2/2M integrated microprocessor is referred to as

“the ColdFire2/2M.”

CONTENTS

This user manual is organized as follows:

Section 1: Overview

Section 2: Signal Summary

Section 3: Master Bus Operations

Section 4: Exception Processing

Section 5: Integrated Memories

Section 6: Multiply-Accumulate Unit

Section 7: Debug Support

Section 8: Test Operation

Section 9: Instruction Execution Timing

Section 10: Electrical Characteristics

Appendix A: Register Summary

Appendix B: New MAC Instructions

Index

MOTOROLA

ColdFire2/2M User’s Manual

vii

TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Overview

1.1 FlexCore Integrated Processors..................................................................1-2

1.1.1 FlexCore Advantages.............................................................................1-4

1.1.2 FlexCore Module Types .........................................................................1-4

1.2 Development Cycle......................................................................................1-5

1.3 System Architecture.....................................................................................1-8

1.3.1 Internal Bus Structure.............................................................................1-8

1.3.1.1 Master Bus.........................................................................................1-8

1.3.1.2 Slave Bus...........................................................................................1-9

1.3.1.3 External Bus ......................................................................................1-9

1.3.1.4 Test Bus.............................................................................................1-9

1.3.2 System Functional Blocks ......................................................................1-9

1.3.2.1 Alternate Master ................................................................................1-9

1.3.2.2 ColdFire2/2M.....................................................................................1-9

1.3.2.3 I-Cache Data Array..........................................................................1-10

1.3.2.4 I-Cache Tag Array ...........................................................................1-10

1.3.2.5 Master Bus Arbiter (MARB).............................................................1-10

1.3.2.6 ROM Array.......................................................................................1-11

1.3.2.7 Slave Modules.................................................................................1-11

1.3.2.8 SRAM Array.....................................................................................1-11

1.3.2.9 System Bus Controller (SBC)..........................................................1-11

1.4 Programming Model ..................................................................................1-11

1.4.1 Integer Unit User Programming Model.................................................1-11

1.4.1.1 Data Registers (D0 – D7) ................................................................1-12

1.4.1.2 Address Registers (A0 – A6)...........................................................1-12

1.4.1.3 Stack Pointer (A7,SP)......................................................................1-12

1.4.1.4 Program Counter (PC).....................................................................1-12

1.4.1.5 Condition Code Register (CCR) ......................................................1-12

1.4.2 MAC Unit User Programming Model....................................................1-13

1.4.2.1 Accumulator (ACC)..........................................................................1-14

1.4.2.2 Mask Register (MASK)....................................................................1-14

1.4.2.3 MAC Status Register (MACSR).......................................................1-14

1.4.3 Supervisor Programming Model...........................................................1-14

TABLE OF CONTENTS (Continued)

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Number Title Number

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MOTOROLA

1.4.3.1 Status Register (SR)........................................................................1-14

1.4.3.2 Cache Control Register (CACR)......................................................1-15

1.4.3.3 Access Control Registers (ACR0, ACR1)........................................1-15

1.4.3.4 Vector Base Register (VBR)............................................................1-15

1.4.3.5 ROM Base Address Register (ROMBAR0).....................................1-15

1.4.3.6 SRAM Base Address Register (RAMBAR0)....................................1-15

1.5 Integer Data Formats.................................................................................1-16

1.6 Organization of Data in Registers..............................................................1-16

1.6.1 Organization of Integer Data Formats in Registers..............................1-16

1.6.2 Organization of Integer Data Formats in Memory................................1-17

1.7 Addressing Mode Summary......................................................................1-18

1.8 Instruction Set Summary...........................................................................1-19

Section 2

Signal Summary

2.1 Introduction..................................................................................................2-1

2.2 Master Bus Signals......................................................................................2-3

2.2.1 68K Interrupt Acknowledge Mode Enable (IACK_68K)..........................2-3

2.2.2 Master Address Bus (MADDR[31:0]) .....................................................2-3

2.2.3 Master Arbiter Control (MARBC[1:0]).....................................................2-3

2.2.4 Master Freeze (MFRZB) ........................................................................2-4

2.2.5 Master Kill (MKILLB) ..............................................................................2-4

2.2.6 Master Read Data Bus (MRDATA[31:0]) ...............................................2-4

2.2.7 Master Read Data Input Enable (MIE)...................................................2-4

2.2.8 Master Read/Write (MRWB)...................................................................2-4

2.2.9 Master Reset (MRSTB)..........................................................................2-4

2.2.10 Master Size (MSIZ[1:0]) .........................................................................2-4

2.2.11 Master Transfer Acknowledge (MTAB)..................................................2-5

2.2.12 Master Transfer Error Acknowledge (MTEAB).......................................2-5

2.2.13 Master Transfer Modifier (MTM[2:0])......................................................2-5

2.2.14 Master Transfer Start (MTSB)................................................................2-6

2.2.15 Master Transfer Type (MTT[1:0])...........................................................2-6

2.2.16 Master Write Data Bus (MWDATA[31:0])...............................................2-6

2.2.17 Master Write Data Output Enable (MWDATAOE)..................................2-6

2.3 General Control Signals ..............................................................................2-6

2.3.1 Clock (CLK)............................................................................................2-6

2.3.2 Interrupt Priority Level (IPLB[2:0])..........................................................2-6

2.4 Integrated Memory Signals..........................................................................2-7

2.4.1 Instruction Cache Signals.......................................................................2-7

TABLE OF CONTENTS (Continued)

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Number Title Number

MOTOROLA

ColdFire2/2M User’s Manual

2.4.1.1 Instruction Cache Address Bus (ICH_ADDR[14:2])...........................2-7

2.4.1.2 Instruction Cache Data Chip-Select (ICHD_CSB).............................2-7

2.4.1.3 Instruction Cache Data Input Bus (ICHD_DI[31:0])...........................2-7

2.4.1.4 Instruction Cache Data Output Bus (ICHD_DO[31:0]).......................2-7

2.4.1.5 Instruction Cache Data Strobe (ICHD_ST)........................................2-7

2.4.1.6 Instruction Cache Data Read/Write (ICHD_RWB).............................2-7

2.4.1.7 Instruction Cache Size (ICH_SZ[2:0])................................................2-8

2.4.1.8 Instruction Cache Tag Chip-Select (ICHT_CSB)...............................2-8

2.4.1.9 Instruction Cache Tag Input Bus (ICHT_DI[31:8]).............................2-8

2.4.1.10 Instruction Cache Tag Output Bus (ICHT_DO[31:8]) ........................2-8

2.4.1.11 Instruction Cache Tag Strobe (ICHT_ST)..........................................2-9

2.4.1.12 Instruction Cache Tag Read/Write (ICHT_RWB) ..............................2-9

2.4.2 Integrated ROM Signals.........................................................................2-9

2.4.2.1 ROM Address Bus (ROM_ADDR[14:2])............................................2-9

2.4.2.2 ROM Data Output Bus (ROM_DO[31:0])...........................................2-9

2.4.2.3 ROM Enable (ROM_ENB[1:0])..........................................................2-9

2.4.2.4 ROM Size (ROM_SZ[2:0]).................................................................2-9

2.4.2.5 ROM Valid (ROM_VLD)...................................................................2-10

2.4.3 Integrated SRAM Signals.....................................................................2-10

2.4.3.1 SRAM Address Bus (SRAM_ADDR[14:2])......................................2-10

2.4.3.2 SRAM Chip-Select (SRAM_CSB)....................................................2-10

2.4.3.3 SRAM Data Input Bus (SRAM_DI[31:0]).........................................2-11

2.4.3.4 SRAM Data Output Bus (SRAM_DO[31:0]).....................................2-11

2.4.3.5 SRAM Size (SRAM_SZ[2:0])...........................................................2-11

2.4.3.6 SRAM Strobe (SRAM_ST[3:0]) .......................................................2-11

2.4.3.7 SRAM Read/Write (SRAM_RWB[3:0])............................................2-11

2.5 Debug Signals ...........................................................................................2-11

2.5.1 Break Point (BKPTB)............................................................................2-11

2.5.2 Debug Data (DDATA[3:0])....................................................................2-12

2.5.3 Development Serial Clock (DSCLK).....................................................2-12

2.5.4 Development Serial Input (DSI)............................................................2-12

2.5.5 Development Serial Output (DSO).......................................................2-12

2.5.6 Processor Status (PST[3:0]).................................................................2-12

2.6 Test Signals...............................................................................................2-12

2.6.1 Integrated Memory Test Signals...........................................................2-12

TABLE OF CONTENTS (Continued)

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Number Title Number

ColdFire2/2M User’s Manual

MOTOROLA

2.6.1.1 Test Address Bus (TEST_ADDR[14:2]) ..........................................2-13

2.6.1.2 Test Control (TEST_CTRL).............................................................2-13

2.6.1.3 Test IDATA Read (TEST_IDATA_RD)............................................2-13

2.6.1.4 Test IDATA Write (TEST_IDATA_WRT).........................................2-13

2.6.1.5 Test Instruction Cache Read Hit (TEST_RHIT)...............................2-13

2.6.1.6 Test Invalidate Inhibit (TEST_IVLD_INH)........................................2-13

2.6.1.7 Test ITAG Write (TEST_ITAG_WRT)..............................................2-13

2.6.1.8 Test KTA Mode Enable (TEST_KTA)..............................................2-13

2.6.1.9 Test Mode Enable (TEST_MODE)..................................................2-13

2.6.1.10 Test SRAM Read (TEST_SRAM_RD) ............................................2-13

2.6.1.11 Test SRAM Write (TEST_SRAM_WRT)..........................................2-13

2.6.1.12 Test Read (TEST_RD)....................................................................2-13

2.6.1.13 Test ROM Read (TEST_ROM_RD) ................................................2-13

2.6.1.14 Test Write Inhibit (TEST_WR_INH).................................................2-13

2.6.2 Scan Signal Description.......................................................................2-13

2.6.2.1 Scan Enable (SCAN_ENABLE).......................................................2-14

2.6.2.2 Scan Exercise Array (SCAN_XARRAY)..........................................2-14

2.6.2.3 Scan Input (SCAN_IN[15:0]) ...........................................................2-14

2.6.2.4 Scan Mode (SCAN_MODE)............................................................2-14

2.6.2.5 Scan Output (SCAN_OUT[15:0]).....................................................2-14

2.6.2.6 Scan Test Ring Clock (TR_CLK).....................................................2-14

2.6.2.7 Scan Test Ring Core Mode Enable (TR_CORE_EN) .....................2-14

2.6.2.8 Scan Test Ring Data Input 0 (TR_DI0)............................................2-14

2.6.2.9 Scan Test Ring Data Input 1 (TR_DI1)............................................2-14

2.6.2.10 Scan Test Ring Data Output 0 (TR_DO0).......................................2-14

2.6.2.11 Scan Test Ring Data Output 1 (TR_DO1).......................................2-14

2.6.2.12 Scan Test Ring Enable (TR_EN).....................................................2-14

2.6.2.13 Scan Test Ring Mode (TR_MODE).................................................2-14

Section 3

Master Bus Operation

3.1 Signal Description........................................................................................3-1

3.1.1 68K Interrupt Acknowledge Mode Enable (IACK_68K)..........................3-1

3.1.2 Master Address Bus (MADDR[31:0]) .....................................................3-1

3.1.3 Master Arbiter Control (MARBC[1:0]).....................................................3-1

3.1.4 Master Freeze (MFRZB) ........................................................................3-2

3.1.5 Master Kill (MKILLB) ..............................................................................3-2

3.1.6 Master Read Data Bus (MRDATA[31:0]) ...............................................3-2

3.1.7 Master Read Data Input Enable (MIE)...................................................3-2

3.1.8 Master Read/Write (MRWB)...................................................................3-2

3.1.9 Master Reset (MRSTB)..........................................................................3-2

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

MOTOROLA

ColdFire2/2M User’s Manual

3.1.10 Master Size (MSIZ[1:0])..........................................................................3-2

3.1.11 Master Transfer Acknowledge (MTAB) ..................................................3-2

3.1.12 Master Transfer Error Acknowledge (MTEAB).......................................3-3

3.1.13 Master Transfer Modifier (MTM[2:0])......................................................3-3

3.1.14 Master Transfer Start (MTSB)................................................................3-3

3.1.15 Master Transfer Type (MTT[1:0]) ...........................................................3-3

3.1.16 Master Write Data Bus (MWDATA[31:0])...............................................3-4

3.1.17 Master Write Data Output Enable (MWDATAOE)..................................3-4

3.2 Data Transfer Mechanism ...........................................................................3-4

3.2.1 Transfer Type Control Signals................................................................3-4

3.2.1.1 ColdFire2/2M Access.........................................................................3-4

3.2.1.2 Alternate Master Access....................................................................3-5

3.2.1.3 Emulator Mode Access......................................................................3-5

3.2.1.4 Interrupt Acknowledge Access ..........................................................3-5

3.2.1.5 CPU Space Access ...........................................................................3-5

3.2.2 Data Bus Requirements .........................................................................3-5

3.3 Data Transfers.............................................................................................3-6

3.3.1 Byte, Word, and Longword Read Transfers...........................................3-6

3.3.2 Byte, Word, and Longword Write Transfers ...........................................3-9

3.3.3 Line Read Transfer...............................................................................3-11

3.3.4 Line Write Transfers.............................................................................3-14

3.4 Misaligned Operands.................................................................................3-18

3.5 Invalid Master Bus Cycles .........................................................................3-20

3.6 Pipeline Stalls............................................................................................3-20

3.7 Interrupt Acknowledge Bus Cycles............................................................3-21

3.7.1 Interrupt Acknowledge Bus Cycle (Terminated normally) ....................3-22

3.7.2 Spurious Interrupt Acknowledge Bus Cycle .........................................3-27

3.8 Master Bus Exception Control Cycles .......................................................3-27

3.8.1 Bus Errors.............................................................................................3-28

3.8.2 Fault-on-Fault Halt................................................................................3-29

3.9 Reset Operation.........................................................................................3-29

3.10 Master Bus Arbitration...............................................................................3-30

3.10.1 Master Bus Arbitration Algorithm..........................................................3-30

3.10.1.1 Park on ColdFire2/2M......................................................................3-30

3.10.1.2 Park on Alternate Master.................................................................3-30

3.10.1.3 Park on Current Master ...................................................................3-31

3.10.2 Bus Arbitration Programming Model.....................................................3-31

Section 4

Exception Processing

4.1 Exception Processing Overview..................................................................4-1

TABLE OF CONTENTS (Continued)

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MOTOROLA

4.1.1 Exception Stack Frame Definition..........................................................4-3

4.1.1.1 Self-Aligning Stack ............................................................................4-4

4.1.2 Exception Vectors ..................................................................................4-5

4.1.3 Multiple Exceptions ................................................................................4-6

4.1.4 Fault-on-Fault Halt..................................................................................4-6

4.2 Exceptions...................................................................................................4-7

4.2.1 Reset Exception.....................................................................................4-7

4.2.2 Access Error Exception..........................................................................4-7

4.2.3 Address Error Exception ........................................................................4-8

4.2.4 Illegal Instruction Exception....................................................................4-9

4.2.5 Privilege Violation Exception..................................................................4-9

4.2.6 Trace Exception .....................................................................................4-9

4.2.7 Unimplemented Opcode Exception........................................................4-9

4.2.8 Debug Interrupt ....................................................................................4-10

4.2.9 Format Error Exceptions ......................................................................4-10

4.2.10 TRAP Instruction Exceptions................................................................4-10

4.2.11 Interrupt Exception...............................................................................4-10

4.2.11.1 Level Seven Interrupts.....................................................................4-11

4.2.11.2 Spurious, Autovectored, and Uninitialized Interrupts.......................4-12

Section 5

Integrated Memories

5.1 Instruction Cache.........................................................................................5-1

5.1.1 Instruction Cache Signal Description .....................................................5-1

5.1.1.1 Instruction Cache Address Bus (ICH_ADDR[14:2]) ..........................5-2

5.1.1.2 Instruction Cache Data Chip-Select (ICHD_CSB).............................5-2

5.1.1.3 Instruction Cache Data Input Bus (ICHD_DI[31:0])...........................5-2

5.1.1.4 Instruction Cache Data Output Bus (ICHD_DO[31:0]) ......................5-2

5.1.1.5 Instruction Cache Data Strobe (ICHD_ST)........................................5-2

5.1.1.6 Instruction Cache Data Read/Write (ICHD_RWB) ............................5-3

5.1.1.7 Instruction Cache Size (ICH_SZ[2:0]) ...............................................5-3

5.1.1.8 Instruction Cache Tag Chip-Select (ICHT_CSB)...............................5-3

5.1.1.9 Instruction Cache Tag Input Bus (ICHT_DI[31:8]).............................5-3

5.1.1.10 Instruction Cache Tag Output Bus (ICHT_DO[31:8])........................5-3

5.1.1.11 Instruction Cache Tag Strobe (ICHT_ST) .........................................5-4

5.1.1.12 Instruction Cache Tag Read/Write (ICHT_RWB)..............................5-4

5.1.2 Instruction Cache Physical Organization................................................5-4

5.1.3 Interaction With Other Modules..............................................................5-4

5.1.4 Cache Miss Fetch Algorithm/Line Fills...................................................5-4

5.1.5 Cacheability............................................................................................5-5

5.1.6 Invalidating Cache Entries......................................................................5-5

TABLE OF CONTENTS (Continued)

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5.1.7 Cache Coherency...................................................................................5-6

5.1.8 Reset......................................................................................................5-6

5.1.9 Instruction Cache Programming Model..................................................5-6

5.2 Access Control Registers ............................................................................5-8

5.2.1 ACR Programming Model.......................................................................5-8

5.3 ROM Module..............................................................................................5-10

5.3.1 ROM Signal Description.......................................................................5-10

5.3.1.1 ROM Address Bus (ROM_ADDR[14:2])..........................................5-11

5.3.1.2 ROM Data Output Bus (ROM_DO[31:0]).........................................5-11

5.3.1.3 ROM Enable (ROM_ENB[1:0])........................................................5-11

5.3.1.4 ROM Size (ROM_SZ[2:0])...............................................................5-12

5.3.1.5 ROM Valid (ROM_VLD)...................................................................5-12

5.3.2 ROM Programming Model....................................................................5-12

5.4 SRAM Module............................................................................................5-14

5.4.1 SRAM Signal Description.....................................................................5-14

5.4.1.1 SRAM Address Bus (SRAM_ADDR[14:2])......................................5-15

5.4.1.2 SRAM Chip-Select (SRAM_CSB)....................................................5-16

5.4.1.3 SRAM Data Input Bus (SRAM_DI[31:0]).........................................5-16

5.4.1.4 SRAM Data Output Bus (SRAM_DO[31:0]).....................................5-16

5.4.1.5 SRAM Size (SRAM_SZ[2:0])...........................................................5-16

5.4.1.6 SRAM Strobe (SRAM_ST[3:0]) .......................................................5-16

5.4.1.7 SRAM Read/Write (SRAM_RWB[3:0])............................................5-16

5.4.2 SRAM Programming Model..................................................................5-16

Section 6

Multiply-Accumulate Unit

6.1 Introduction..................................................................................................6-1

6.2 MAC Programming Model ...........................................................................6-2

6.2.1 Accumulator (ACC).................................................................................6-2

6.2.2 MAC Status Register (MACSR)..............................................................6-2

6.2.3 Mask Register (MASK)...........................................................................6-3

6.3 Shifting Operations......................................................................................6-4

6.4 Overflow Mode.............................................................................................6-4

6.5 MAC Instruction Set Summary ....................................................................6-5

Section 7

Debug Support

7.1 Signal Description........................................................................................7-1

7.1.1 Break Point (BKPTB)..............................................................................7-1

7.1.2 Debug Data (DDATA[3:0])......................................................................7-2

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7.1.3 Development Serial Clock (DSCLK).......................................................7-2

7.1.4 Development Serial Input (DSI)..............................................................7-2

7.1.5 Development Serial Output (DSO).........................................................7-2

7.1.6 Processor Status (PST[3:0])...................................................................7-2

7.2 Real-Time Trace..........................................................................................7-2

7.2.1 Processor Status Signal Encoding.........................................................7-3

7.2.1.1 Continue Execution (PST = $0).........................................................7-3

7.2.1.2 Begin Execution of an Instruction (PST = $1)....................................7-3

7.2.1.3 Entry into User Mode (PST = $3) ......................................................7-3

7.2.1.4 Begin Execution of PULSE or WDDATA instructions (PST = $4) .....7-3

7.2.1.5 Begin Execution of Taken Branch (PST = $5)...................................7-4

7.2.1.6 Begin Execution of RTE Instruction (PST = $7) ................................7-5

7.2.1.7 Begin Data Transfer (PST = $8 - $A) ................................................7-5

7.2.1.8 Exception Processing (PST = $C).....................................................7-5

7.2.1.9 Emulator-Mode Exception Processing (PST = $D) ...........................7-5

7.2.1.10 Processor Stopped (PST = $E).........................................................7-5

7.2.1.11 Processor Halted (PST = $F) ............................................................7-5

7.3 Background Debug Mode (BDM) ................................................................7-5

7.3.1 CPU Halt ................................................................................................7-6

7.3.2 BDM Serial Interface..............................................................................7-7

7.3.2.1 Receive Packet Format.....................................................................7-8

7.3.2.2 Transmit Packet Format....................................................................7-9

7.3.3 BDM Command Set ...............................................................................7-9

7.3.3.1 BDM Command Set Summary..........................................................7-9

7.3.3.2 ColdFire BDM Commands...............................................................7-10

7.3.3.3 Command Sequence Diagram........................................................7-11

7.3.3.4 Command Set Descriptions.............................................................7-12

7.3.3.4.1 Read A/D Register (RAREG/RDREG).......................................7-13

7.3.3.4.2 Write A/D Register (WAREG/WDREG)......................................7-13

7.3.3.4.3 Read Memory Location (READ).................................................7-14

7.3.3.4.4 Write Memory Location (WRITE)...............................................7-16

7.3.3.4.5 Dump Memory Block (DUMP)....................................................7-17

7.3.3.4.6 Fill Memory Block (FILL)............................................................7-19

7.3.3.4.7 Resume Execution (GO)............................................................7-21

7.3.3.4.8 No Operation (NOP)...................................................................7-21

7.3.3.4.9 Read Control Register (RCREG)...............................................7-22

7.3.3.4.10 Write Control Register (WCREG)...............................................7-23

7.3.3.4.11 Read Debug Module Register (RDMREG) ................................7-24

7.3.3.4.12 Write Debug Module Register (WDMREG)................................7-25

7.3.3.4.13 Unassigned Opcodes.................................................................7-25

7.4 Real-Time Debug Support.........................................................................7-26

7.4.1 Theory of Operation .............................................................................7-26

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7.4.1.1 Emulator Mode ................................................................................7-27

7.4.1.2 Reuse of Debug Module Hardware .................................................7-28

7.4.2 Programming Model.............................................................................7-28

7.4.2.1 Address Breakpoint Registers (ABLR, ABHR) ................................7-29

7.4.2.2 Address Attribute Register (AATR)..................................................7-30

7.4.2.3 Program Counter Breakpoint Register (PBR, PBMR) .....................7-32

7.4.2.4 Data Breakpoint Register (DBR, DBMR).........................................7-33

7.4.2.5 Trigger Definition Register (TDR)....................................................7-34

7.4.2.6 Configuration/Status Register (CSR)...............................................7-36

7.4.3 Concurrent BDM and Processor Operation..........................................7-39

7.4.4 Motorola Recommended BDM Pinout..................................................7-39

7.4.5 Differences Between the ColdFire2/2M BDM and CPU32 BDM..........7-40

Section 8

Test Operation

8.1 Integrated Memory Testing..........................................................................8-1

8.1.1 Test Bus Signal Description ...................................................................8-1

8.1.1.1 Test Address Bus (TEST_ADDR[14:2]).............................................8-1

8.1.1.2 Test Control (TEST_CTRL)...............................................................8-1

8.1.1.3 Test IDATA Read (TEST_IDATA_RD)..............................................8-1

8.1.1.4 Test IDATA Write (TEST_IDATA_WRT) ...........................................8-2

8.1.1.5 Test Instruction Cache Read Hit (TEST_RHIT).................................8-2

8.1.1.6 Test Invalidate Inhibit (TEST_IVLD_INH)..........................................8-2

8.1.1.7 Test ITAG Write (TEST_ITAG_WRT)................................................8-2

8.1.1.8 Test KTA Mode Enable (TEST_KTA)................................................8-2

8.1.1.9 Test Mode Enable (TEST_MODE)....................................................8-2

8.1.1.10 Test SRAM Read (TEST_SRAM_RD)...............................................8-2

8.1.1.11 Test SRAM Write (TEST_SRAM_WRT)............................................8-2

8.1.1.12 Test Read (TEST_RD) ......................................................................8-2

8.1.1.13 Test ROM Read (TEST_ROM_RD)...................................................8-2

8.1.1.14 Test Write Inhibit (TEST_WR_INH)...................................................8-2

8.1.2 Theory of Operation................................................................................8-2

8.1.3 Test Mode...............................................................................................8-3

8.1.4 Instruction Cache Tag RAM Testing.......................................................8-3

8.1.4.1 Instruction Cache Tag RAM Write Function ......................................8-3

8.1.4.2 Instruction Cache Tag RAM Read Function......................................8-5

8.1.5 Instruction Cache Data RAM Testing.....................................................8-6

8.1.5.1 Instruction Cache Data RAM Write Function.....................................8-6

8.1.5.2 Instruction Cache Data RAM Read Function.....................................8-8

8.1.6 Instruction Cache KTA Mode Testing.....................................................8-9

8.1.7 ROM Testing ........................................................................................8-11

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8.1.7.1 ROM Read Function........................................................................8-11

8.1.8 SRAM Testing......................................................................................8-13

8.1.8.1 SRAM Write Function......................................................................8-13

8.1.8.2 SRAM Read Function......................................................................8-15

8.2 Scan Testing..............................................................................................8-16

8.2.1 Scan Signal Description.......................................................................8-16

8.2.1.1 Scan Enable (SCAN_ENABLE).......................................................8-16

8.2.1.2 Scan Exercise Array (SCAN_XARRAY)..........................................8-16

8.2.1.3 Scan Input (SCAN_IN[15:0]) ...........................................................8-16

8.2.1.4 Scan Mode (SCAN_MODE)............................................................8-17

8.2.1.5 Scan Output (SCAN_OUT[15:0]).....................................................8-17

8.2.1.6 Scan Test Ring Clock (TR_CLK).....................................................8-17

8.2.1.7 Scan Test Ring Core Mode Enable (TR_CORE_EN) .....................8-17

8.2.1.8 Scan Test Ring Data Input 0 (TR_DI0)............................................8-17

8.2.1.9 Scan Test Ring Data Input 1 (TR_DI1)............................................8-17

8.2.1.10 Scan Test Ring Data Output 0 (TR_DO0).......................................8-17

8.2.1.11 Scan Test Ring Data Output 1 (TR_DO1).......................................8-17

8.2.1.12 Scan Test Ring Enable (TR_EN).....................................................8-17

8.2.1.13 Scan Test Ring Mode (TR_MODE).................................................8-17

8.2.2 Test Ring..............................................................................................8-17

8.3 Burn-In Testing..........................................................................................8-18

8.4 Data Retention Testing..............................................................................8-18

Section 9

Instruction Execution Timing

9.1 Timing Assumptions....................................................................................9-1

9.2 MOVE Instruction Execution Times.............................................................9-2

9.3 Standard One-Operand Instruction Execution Times..................................9-4

9.4 Standard Two-Operand Instruction Execution Times..................................9-5

9.5 Miscellaneous Instruction Execution Times.................................................9-7

9.6 MAC Instruction Execution Timing ..............................................................9-8

9.7 Branch Instruction Execution Times............................................................9-8

Section 10

Electrical Chacteristics

10.1 Definitions of Specifications.......................................................................10-1

10.1.1 Current .................................................................................................10-1

10.1.2 Voltage.................................................................................................10-1

10.1.3 Capacitance .........................................................................................10-2

10.1.4 AC Switching Parameters and Waveforms..........................................10-2

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10.2 ColdFire2 Data Sheet................................................................................10-6

Appendix A

A.1 Register Access Methods........................................................................... A-1

A.2 Register Formats........................................................................................ A-2

Appendix B

New MAC Instructions

B.1 Enhanced Integer Multiply Instructions....................................................... B-1

B.2 New MAC Instructions................................................................................ B-1

B.3 New Register Instructions......................................................................... B-12

B.4 Operation Code Map ................................................................................ B-22

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LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

1-1 FlexCore Integrated Processor Typical Die Layout...........................................1-3

1-2 Design System Overview..................................................................................1-7

1-3 ColdFire2/2M System Diagram.........................................................................1-8

1-4 ColdFire2/2M Block Diagram..........................................................................1-10

1-5 Integer Unit User Programming Model............................................................1-12

1-6 Condition Code Register (CCR)......................................................................1-13

1-7 MAC Unit User Programming Model...............................................................1-13

1-8 Supervisor Programming Model......................................................................1-14

1-9 Status Register (SR).......................................................................................1-15

1-10 Organization of Integer Data Formats in Data Registers................................1-16

1-11 Organization of Integer Data Formats in Address Registers...........................1-17

1-12 Memory Operand Addressing.........................................................................1-18

2-1 ColdFire2/2M Detailed Block Diagram..............................................................2-1

3-1 Byte, Word, and Longword Read Transfer Flowchart.......................................3-7

3-2 Normal Transfer (without Wait States)..............................................................3-8

3-3 Byte, Word, and Longword Write Transfer Flowchart.......................................3-9

3-4 Normal Write Transfer (with wait states).........................................................3-10

3-5 Line Read Transfer Flowchart.........................................................................3-12

3-6 Line Read Transfer (without wait states).........................................................3-13

3-7 Line Write Transfer Flowchart.........................................................................3-15

3-8 Line Write Transfer (without wait states).........................................................3-16

3-9 Line Write Transfer (with wait states)..............................................................3-17

3-10 Example of a Misaligned

Longword

Transfer................................................3-18

3-11 Example of a Misaligned Word Transfer.........................................................3-18

3-12 Misaligned Word Read Transfer .....................................................................3-19

3-13 Example Master Bus Wait State .....................................................................3-21

3-14 Interrupt Acknowledge Bus Cycle Flowchart...................................................3-23

3-15 ColdFire Mode Interrupt Acknowledge Bus Cycle...........................................3-24

3-16 68K Mode Interrupt Acknowledge Bus Cycle..................................................3-26

3-17 Bus Exception Cycle.......................................................................................3-29

3-18 Initial Power-On Reset....................................................................................3-30

4-1 Exception Processing Flowchart.......................................................................4-2

4-2 Exception Stack Frame Form............................................................................4-3

5-1 Example 8 Kbyte Instruction Cache Interface Diagram ....................................5-2

5-2 Cache Control Register (CACR).......................................................................5-6

5-3 Access Control Register (ACR0, ACR1)...........................................................5-9

5-4 Example 8 Kbyte ROM Interface Diagram......................................................5-11

5-5 ROM Base Address Register (ROMBAR0).....................................................5-12

LIST OF ILLUSTRATIONS (Continued)

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5-6 Example 8 Kbyte SRAM Interface Diagram....................................................5-15

5-7 SRAM Base Address Register (RAMBAR0)...................................................5-17

6-1 MAC Flow Diagram...........................................................................................6-2

6-2 MAC Status Register (MACSR)........................................................................6-3

6-3 MAC Mask Register (MASK) ............................................................................6-4

7-1 Processor/Debug Module Interface ..................................................................7-1

7-2 Example PST Diagram .....................................................................................7-4

7-3 BDM Serial Transfer .........................................................................................7-8

7-4 BDM Signal Sampling.......................................................................................7-8

7-5 Receive BDM Packet........................................................................................7-8

7-6 Transmit BDM Packet.......................................................................................7-9

7-7 Command Sequence Diagram........................................................................7-12

7-8 Debug Programming Model............................................................................7-29

7-9 Address Breakpoint Low Register (ABLR)......................................................7-29

7-10 Address Breakpoint High Register (ABHR) ....................................................7-30

7-11 Address Attribute Register (AATR).................................................................7-30

7-12 Program Counter Breakpoint Register (PBR).................................................7-32

7-13 Program Counter Breakpoint Mask Register (PBMR) ....................................7-33

7-14 Data Breakpoint Register (DBR).....................................................................7-33

7-15 Data Breakpoint Mask Register (DBMR)........................................................7-33

7-16 Trigger Definition Register (TDR) ...................................................................7-34

7-17 Configuration/Status Register (CSR)..............................................................7-37

7-18 Recommended BDM Connector.....................................................................7-40

8-1 Test Instruction Cache Tag Write Cycles..........................................................8-4

8-2 Test Instruction Cache Tag Read Cycles .........................................................8-5

8-3 Test Instruction Cache Data Write Cycles........................................................8-7

8-4 Test Instruction Cache Data Read Cycles........................................................8-8

8-5 KTA Mode Cycles...........................................................................................8-10

8-6 Test ROM Read Cycles..................................................................................8-12

8-7 Test SRAM Write Cycles ................................................................................8-14

8-8 Test SRAM Read Cycles................................................................................8-15

10-1 t

PLH

and t

PHL

Measurements..........................................................................10-2

10-2 t

and t

Measurements ...................................................................................10-2

10-3 Internal Cell Three-State Measurements and Example Circuits.....................10-3

10-4 t

rec

Recovery Time..........................................................................................10-4

10-5 t

and t

Measurements Between Data and a Control Signal.......................10-4

10-6 t

and t

Measurements Between Data and Clock Signals...........................10-4

10-7 Switching Waveforms Showing t

w(L)

and t

w(H)

Measurements.......................10-5

A-1 Address Attribute Register (AATR)...................................................................A-2

A-2 Address Breakpoint High Register (ABHR) ......................................................A-2

A-3 Address Breakpoint Low Register (ABLR)........................................................A-2

A-4 Access Control Register (ACR0, ACR1)...........................................................A-3

LIST OF ILLUSTRATIONS (Continued)

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A-5 Cache Control Register (CACR)...................................................................... A-3

A-6 Condition Code Register (CCR)....................................................................... A-3

A-7 Configuration/Status Register (CSR)............................................................... A-4

1-8 Data Breakpoint Mask Register (DBMR) ......................................................... A-4

1-9 Data Breakpoint Register (DBR)...................................................................... A-4

1-10 MAC Status Register (MACSR)....................................................................... A-4

1-11 MAC Mask Register (MASK)............................................................................ A-5

1-12 Program Counter Breakpoint Mask Register (PBMR)...................................... A-5

1-13 Program Counter Breakpoint Register (PBR).................................................. A-5

A-14 SRAM Base Address Register (RAMBAR0).................................................... A-5

A-15 ROM Base Address Register (ROMBAR0)...................................................... A-6

A-16 Status Register (SR)........................................................................................ A-6

A-17 Trigger Definition Register (TDR)..................................................................... A-6

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LIST OF TABLES

Table Page

Number Title Number

1-1 MOVEC Register Map.....................................................................................1-14

1-2 Integer Data Formats......................................................................................1-16

1-3 Effective Addressing Modes and Categories..................................................1-19

1-4 Notational Conventions...................................................................................1-19

1-5 Instruction Set Summary.................................................................................1-21

2-1 Signal Summary................................................................................................2-2

2-2 Master Arbiter Control Encoding.......................................................................2-4

2-3 Master Bus Transfer Size Encoding..................................................................2-5

2-4 Master Bus Transfer Modifier Encoding............................................................2-5

2-5 Master Bus Transfer Type Encoding.................................................................2-6

2-6 Interrupt Levels and Mask Values.....................................................................2-7

2-7 Cache Configuration Encoding .........................................................................2-8

2-8 Valid Tag RAM Data Signals.............................................................................2-8

2-9 Valid ROM Address Bits....................................................................................2-9

2-10 ROM Configuration Encoding .........................................................................2-10

2-11 Valid SRAM Address Bits................................................................................2-10

2-12 SRAM Configuration Encoding .......................................................................2-11

2-13 Processor Status Encoding.............................................................................2-12

3-1 Master Arbiter Control Encoding.......................................................................3-1

3-2 Master Bus Transfer Size Encoding..................................................................3-2

3-3 Master Bus Transfer Modifier Encoding............................................................3-3

3-4 Master Bus Transfer Type Encoding.................................................................3-4

3-5 MRDATA Requirements for Read Transfers.....................................................3-5

3-6 MWDATA Bus Requirements for Write Transfers.............................................3-6

3-7 Allowable Line Access Patterns......................................................................3-11

3-8 Memory Alignment Cycles ..............................................................................3-19

3-9 MTAB and MTEAB Assertion Results.............................................................3-27

4-1 Stack Pointer Alignment....................................................................................4-5

4-2 Exception Vector Assignments .........................................................................4-5

4-3 Exception Priority Groups .................................................................................4-6

4-4 Interrupt Levels and Mask Values...................................................................4-11

5-1 Cache Configuration Encoding .........................................................................5-3

5-2 Valid Tag RAM Data Signals.............................................................................5-3

5-3 Initial Fetch Offset and CLNF Bits.....................................................................5-5

5-4 Cache Line Fill Encoding ..................................................................................5-8

5-5 Valid ROM Address Bits..................................................................................5-11

5-6 ROM Configuration Encoding .........................................................................5-12

5-7 Valid ROM Base Address Bits ........................................................................5-13

LIST OF TABLES (Continued)

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5-8 Valid SRAM Address Bits ...............................................................................5-15

5-9 SRAM Configuration Encoding.......................................................................5-16

5-10 Valid SRAM Base Address Bits......................................................................5-17

6-1 Mask Addressing Mode ....................................................................................6-4

6-2 Accumulator Result in Saturation Mode............................................................6-5

6-3 MAC Instruction Set Summary..........................................................................6-6

7-1 Processor Status Encoding ..............................................................................7-2

7-2 CPU-Generated Message Encoding ................................................................7-9

7-3 BDM Command Summary..............................................................................7-10

7-4 BDM Size Field Encoding...............................................................................7-11

7-5 Control Register Map......................................................................................7-22

7-6 Definition of DRc Encoding - Read.................................................................7-24

7-7 Definition of DRc Encoding - Write .................................................................7-25

7-8 DDATA, CSR[31:28] Breakpoint Response....................................................7-26

7-9 Shared BDM/Breakpoint Hardware.................................................................7-28

7-10 Misaligned Data Operand References............................................................7-34

7-11 BDM Connector Correlation............................................................................7-40

9-1 Misaligned Operand References ......................................................................9-2

9-2 Move Byte and Word Execution Times.............................................................9-3

9-3 Move Long Execution Times ............................................................................9-3

9-4 One Operand Instruction Execution Times.......................................................9-4

9-5 Two Operand Instruction Execution Times.......................................................9-5

9-6 Miscellaneous Instruction Execution Times......................................................9-7

9-7 MAC Instruction Execution Times.....................................................................9-8

9-8 General Branch Instruction Execution Times....................................................9-8

9-9 BRA,

BCC

Instruction Execution Times............................................................9-8

A-1 Register Summary............................................................................................A-1

PRELIMINARY

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LIST OF ACRONYMS

Acronym Definition

BCD........................................................binary coded decimal

BDM........................................................background debug mode

CAD........................................................computer-aided design

CPU........................................................central processing unit

DSP ........................................................digital signal processing

ET...........................................................execution time

IACK .......................................................interrupt acknowledge

IFP..........................................................instruction fetch pipeline

LRU.........................................................least recently used

LSB.........................................................least significant

bit

LSW........................................................least significant word

MAC........................................................multiply-accumulate

MARB .....................................................master bus arbiter

MSB........................................................most significant bit

MSW.......................................................most significant word

OEP........................................................operand execution pipeline

RISC.......................................................reduced instruction set computer

ROM .......................................................read-only memory

SBC ........................................................system bus controller

SRAM .....................................................static random access memory

TA...........................................................transfer acknowledge

TS...........................................................transfer start

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SECTION 1

OVERVIEW

This is a summary of the use and operation of the FlexCore ColdFire® microprocessor core

(referred to as the ColdFire2) and FlexCore ColdFire microprocessor core with the Multiply-

Accumulate unit (MAC), referred to as the ColdFire2M. It also contains a detailed set of

timing and electrical specifications. All references to ColdFire2/2M will apply to both the

ColdFire2 and the ColdFire2M devices. Refer to the

ColdFire Programmer’s Reference

Manual Rev 1.0

(MCF5200PRM/AD) for detailed information on the operation of the

instruction set and addressing modes.

The ColdFire2/2M is part of the FlexCore Program, a semicustom, standard-cell based

design program. Based on the concept of variable-length Reduced Instruction Set Computer

(RISC) technology, ColdFire combines the architectural simplicity of conventional 32-bit

RISC with a memory-saving, variable-length instruction set. In the FlexCore program, high-

volume manufacturers can create their own integrated microprocessor containing a core

processor (such as the ColdFire2/2M) and their own proprietary technology. A FlexCore

integrated processor allows significant reductions in component count, power consumption,

board space, and cost—resulting in higher system reliability and performance.

The main features of the ColdFire2/2M processor include:

• 32-bit address bus which can directly address up to 4 Gbytes

• 32-bit data bus

• Variable-length RISC

• Optimized instruction set for high-level language constructs

• Sixteen general-purpose 32-bit data- and address- registers

• Multiply Accumulate (MAC) unit for DSP applications (ColdFire2M only)

• Supervisor/user modes for system protection

• Vector-base register to relocate exception-vector table

• Special core interfacing signals for integrated memories

• Full debug support

The ColdFire2/2M has 32-bit address and data busses. The 32-bit address bus allows direct

addressing of up to 4 Gbytes. A misalignment unit provides support for misaligned data

accesses, and an optional bus arbitration unit provides support for additional bus masters.

The ColdFire2/2M also supports an integrated instruction cache, SRAM, and ROM

(maximum of 32 Kbyte each.)

Overview

1-2

ColdFire2/2M User’s Manual

MOTOROLA

The ColdFire2/2M supports a subset of the 68000 instruction set, and the ColdFire2M has

the added functionality of a Multiply Accumulate (MAC) unit for DSP applications. The

removed instructions include binary coded decimal, bit field, logical rotate, decrement and

branch, integer division, and integer multiply with a 64-bit result. In addition, only the twelve

addressing modes supported by the 68000 are supported. User-mode code developed for

the ColdFire2 processor will run unchanged on 68020, 68030, 68040, and 68060

processors. The new MAC instructions on the ColdFire2M processor will not run on other

processors.

A complete debug module is integrated into the ColdFire2/2M. This unit provides real-time

trace, background debug mode, and real-time debug support. This includes a parallel

processor status port, a subset of the background debug mode (BDM) functionality found on

Motorola’s 683xx family of parts, and real-time breakpoint capability. This built-in debug

support results in a standard debug interface to established tools for all ColdFire

based

processors.

1.1 FLEXCORE INTEGRATED PROCESSORS

The FlexCore design methodology allows designers of high-volume digital systems and

third-party technology providers to place their proprietary circuitry on-chip with a Motorola

microprocessor core. By using FlexCore, a designer can reduce the total system cost,

component count, and power consumption while providing higher performance and greater

reliability. Custom logic, memory, and peripheral modules can be added to a core processor

to produce the most cost-effective solution for a designer's system. Core processors provide

special power-management features such as 5 V, 3.3 V, and static operation. The 68000

family of processors have a proven architecture with a broad base of application and system

software support, including real-time kernels, operating systems, and compilers, in addition

to a wide range of tools to support software development. In the future, additional processing

architectures will be included in the FlexCore program, including PowerPC



and Digital

Signal Processing (DSP). Figure 1-1 shows a typical die layout of a FlexCore integrated

processor.

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Complete product lines can be created using FlexCore by implementing one base design

using a variety of core processors. Designers already familiar with 680x0 Family design can

easily migrate to FlexCore processors as the core processors use similar interfaces.

Additionally, many peripheral modules and memory elements are available for integration.

Motorola has developed a complete design system for the customer that includes both a

broad cell-based library and effective Computer-Aided Design (CAD) tools. By building on

Motorola's proven 680x0 microprocessor architecture and superior manufacturing

capabilities, FlexCore offers designers the best path to higher system integration.

FlexCore custom processors are ideal for:

• High-volume users of 8-, 16-, and 32-bit integrated solutions requiring higher system

performance whose needs are not met by standard 68300 Family devices.

• Designers of high-volume applications who need to reduce cost, space, and/or power

consumption.

• Third-party technology providers who want to deliver their proprietary application-

specific technology to a worldwide marketplace.

To develop a solution that best suits system requirements in the shortest time frame,

integrated processor design is performed by the designer using a methodology created,

tested, and documented by Motorola. The resulting netlist is then laid out by Motorola,

verified, and fabricated in silicon. This enables FlexCore integrated processors to be

produced quickly and cost-effectively, with the resulting device integrating many of the

discrete functions needed in the final system.

To implement the application-specific logic, the designer uses Motorola's standard-cell

library. This library offers an extensive range of design elements, memory configurations,

and an expanding array of peripheral modules. Each cell in the library has been designed

Figure 1-1. FlexCore Integrated Processor Typical Die Layout

CUSTOMER-DESIGNED

LOGIC SPECIAL-FUNCTION

OR MEMORY BLOCK

SPECIAL FUNCTION

OR MEMORY BLOCK

FLEXCORE FAMILY

PROCESSOR CORE

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for optimum size, power, and performance. The added flexibility of high-speed, high-density

cells allows the designer to achieve the most cost-effective solution while satisfying critical

timing requirements. The standard cell library has been thoroughly characterized and

maintained to ensure a smooth transition from a simulated design to working silicon. If both

Motorola and the customer have the desire, a custom part may also become a standard

product. Standard products are sold on the open market, allowing costs to be spread over

additional units, resulting in lower component prices for high-volume users.

Third-party technology providers can use the same methodology to combine their

application-specific systems expertise with a core processor. The resulting device is

manufactured by Motorola and can be delivered to the marketplace through either the

technologist’s or Motorola’s marketing and sales channels.

Refer to the

Design System User’s Guide for Semicustom & FlexCore

for more information

on the FlexCore design methodology.

1.1.1 FlexCore Advantages

Developers face challenges in reducing product cost. By incorporating user-designed logic

and Motorola-supplied functions into a single FlexCore processor, a system designer can

realize significant savings in cost, power consumption, board space, and pin count. The

equivalent functionality can easily require 20 separate components. Each component might

have 16–64 pins, totaling over 350 connections. Each connection is a candidate for a bad

solder joint or misrouted trace. Each component is another part to qualify, purchase,

inventory, and maintain. Each component requires a share of the printed circuit board. Each

component draws power—often to drive large buffers and circuit board traces to get signals

to another chip. Each component must be individually placed and attached to a printed

circuit board. The signals between the core processor unit and a peripheral might not be

compatible nor run from the same clock, requiring time delays or other special design

considerations.

In a FlexCore integrated processor, the major functions and glue logic are all properly

connected internally, timed with the same clock, and fully tested. Only essential signals are

brought out to pins. The processor is then assembled and tested in a surface-mount

package for the smallest possible footprint.

1.1.2 FlexCore Module Types

The three types of FlexCore modules are:

• Hard Module

— Not alterable

— Laid out

— Has a technology file containing timing data

— Has a defined test scheme

• Soft Module

— Netlist

— Not alterable other than by clock tree insertion

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— Not laid out

— Has a defined test scheme

— Simulation test fixture is provided

• Parameterizable Module

— Alterable via insertion of predefined parameters

— Behavioral model

— Definition of parameters defines test scheme

— Customer selects parameter values and Motorola synthesizes the design

The ColdFire2/2M is available as a hard module only.

1.2 DEVELOPMENT CYCLE

There are several steps that must be followed in order to create a FlexCore integrated mi-

croprocessor with a ColdFire2/2M. Figure 1-2 illustrates the standard cell design flow. These

steps include:

• Schematic capture on workstation—Use the engineering workstation to implement the

required system functions with a ColdFire2/2M, memory blocks, peripherals, and cells

from the Motorola standard cell library.

• Verilog modules—Optionally use Verilog to implement complex user modules or

system interconnect of standard cells.

• Generate test patterns—Generate the stimulus and test patterns for the design to be

used during functional simulation.

• Module compilation—Use Motorola software to generate compiled modules (SRAM,

ROM, etc.)

• Functional simulation—Ensure that the logic of the system is functionally sound by

simulating the design. (No timing information is yet associated with the simulations, and

all propagation delays are preset to a unit delay.)

• Logic synthesis—The behavioral and structural level description of the design is

mapped to a more efficient structural description using Synopsys. This final description

is a netlist of standard cell components.

• Electrical rule check—Motorola software verifies the electrical integrity of the design.

This includes checking connectivity, fan-out, edge rates, and other electrical rules.

• Calculate node delays— Motorola software calculates the estimated propagation

delays of each node in the circuit. The design software estimates delays based on the

fanout, input rise/fall times, drive characteristics, and estimated interconnect

capacitances of the netlist.

• Path delay analysis—With path delay information, the delays between the clocked

elements of the circuit can be determined, and the critical paths that limit the clock rate

can be identified. Checking for setup, hold, and pulse-width violations can also be

accomplished.

• Perform real-time simulation—The real-time simulation is run to verify full functionality

using the estimated propagation delays calculated by the design tools.

• Package and pinout definition—Develop the package and pin definition file.

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• Extract test vectors—The simulator records the input/output patterns generated during

the real-time simulation. The test vectors that Motorola will use to test the prototypes

are derived from these patterns.

• Post testkit verification—Simulate the design using the extracted test vectors to ensure

proper operation.

• Perform fault grading—Determine the fault coverage of the extracted test vectors.

• Timing constraints—Chip-level timing constraints are created to be used during

floorplanning, clock tree synthesis, placement, and routing.

• Floor planning/Clock tree synthesis—Floor planning and clock tree synthesis are

performed by Motorola using the design timing constraints provided by the designer.

• Automatic place & route—The circuit’s physical layout is created by Motorola from the

netlist using automatic place and route software.

• Post-layout delay calculation—After the cells are placed and routed, the interconnect

resistances and capacitances are extracted by Motorola. Extracted elements replace

those estimated earlier during the pre-layout calculation of the node delays.

• Re-simulate—The circuit is re-simulated with Verilog to ensure no problems have

arisen due to a change in load conditions.

• In-place optimization—If the new delay information causes the simulation to fail,

Synopsys is used to further optimize the layout. Placement and routing is then

repeated. This cycle continues until the final layout, with post-layout delay, satisfies the

design goals.

• Post testkit simulation—Simulate the design using the extracted test vectors to ensure

proper operation.

• Re-extract test vectors—Extract the test vectors again in order to account for timing

changes due to more accurate delay analysis after layout and routing.

• Power simulation—A power simulation is performed to determine if the design meets

the necessary design goals. Power simulation should also be run early in the design

cycle to ensure design goals are met.

• Netlist comparison—The netlist after place and route is compared by Motorola to the

original netlist to check for connectivity errors.

• Pattern, mask, and wafer generation—Motorola generates the patterns, masks, and

wafers.

• Assembly/test—Parts are assembled by Motorola and tested using the test vectors.

• Ship tested prototypes—Tested prototypes are shipped from Motorola to the customer.

• Final test program—The final test is performed by Motorola.

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Figure 1-2. Design System Overview

AUTOMATIC PLACE & ROUTE

POST-LAYOUT DELAY

CALCULATION

NETLIST COMPARISON

PATTERN, MASK AND

WAFER GENERATION

ASSEMBLY / TEST

SHIP TESTED PROTOTYPES

MOTOROLA CUSTOMER

LOGIC SYNTHESIS

GENERATE TEST PATTERNS

CALCULATE NODE DELAYS

ELECTRICAL RULE CHECK

PERFORM FAULT GRADING

PERFORM REAL-TIME

SIMULATION

PATH DELAY ANALYSIS

EXTRACT TEST VECTORS

RE-SIMULATE

FINAL TEST PROGRAM

SCHEMATIC CAPTURE

ON WORKSTATION

FUNCTIONAL SIMULATION

POST TESTKIT VERIFICATION

PACKAGE AND PINOUT

DEFINITION

EXTRACT TEST VECTORS

POST TESTKIT SIMULATION

VERILOG MODULES

POWER SIMULATION

FLOOR PLANNING /

CLOCK TREE SYNTHESIS

TIMING CONSTRAINTS

STEPS TO BE DONE

IN PARALLEL

MODULE COMPILATION

IN-PLACE OPTIMIZATION

OPTIONAL STEPS TO

BE DONE IN PARALLEL

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1.3 SYSTEM ARCHITECTURE

Most FlexCore custom processors will be designed according to a standard system

architecture. A block diagram of this architecture is shown in Figure 1-3. This architecture

contains the standardized busses and modules discussed below.

For more information on ColdFire system configurations refer to the

MCF5204 User’s

Manual

(MCF5204UM/AD) and the

MCF5206 User’s Manual

(MCF5206UM/AD.)

1.3.1 Internal Bus Structure

1.3.1.1 MASTER BUS.

The master bus is the primary data interface for the ColdFire2/2M.

It is a basic two-cycle unidirectional bus. Devices on the master bus are capable of initiating

bus transactions. This bus includes a 32-bit address bus, 32-bit read data bus, 32-bit write

data bus, and various control signals. None of the signals can be tri-stated. As a result, an

optional master bus arbiter is required if multiple masters are present in the system. Refer

Section 3 Master Bus Operation

for more information.

Figure 1-3. ColdFire2/2M System Diagram

I-CACHE

DATA

ARRAY

I-CACHE

TAG

ARRAY

SRAM

ARRAY ROM

ARRAY

SYSTEM

BUS

CONTROLLER

COLDFIRE2/2M

SLAVE

MODULE

SLAVE

MODULE

SLAVE

MODULE

ALTERNATE

MASTER

BUS

ARBITER

(OPTIONAL)

MASTER

BUS MASTER

BUS

MASTER

BUS

SLAVE

BUS

EXTERNAL

BUS

TEST

BUS

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1.3.1.2 SLAVE BUS.

The slave bus is a simplified bus that provides the interface between

the internal master bus and the on-chip peripheral modules. The system bus controller

(SBC) transfers information between the master bus and the slave bus and is the slave bus

master. Only the SBC can initiate slave bus transactions. The slave bus includes device

select lines, interrupt lines, output enables, write enables, interrupt vector enables, and

other control signals to interface to slave modules. All signals are unidirectional and can not

be tri-stated.

1.3.1.3 EXTERNAL BUS.

The external bus provides the interface between the internal

master bus and external resources. This bus has no predefined requirements. It can be

asynchronous or synchronous. The address and data bus widths may be different than the

internal master bus. The SBC provides the necessary translation between the master and

external busses.

1.3.1.4 TEST BUS.

The test bus provides an interface for performing extensive tests of the

integrated memories. Signals are provided to control reading and writing of the integrated

SRAMs, SROMs, instruction cache tag RAM, and the instruction cache data RAM.

1.3.2 System Functional Blocks

1.3.2.1 ALTERNATE MASTER.

Any device that is required to initiate bus transactions is

required to be on the master bus. All master bus devices except the ColdFire2/2M that

initiate bus transactions are considered to be alternate masters. Use of alternate masters

requires a master bus arbiter module. Examples of alternate masters include DMA

controllers and coprocessors.

1.3.2.2 COLDFIRE2/2M.

The ColdFire2/2M is the primary CPU for any ColdFire custom

processor. It has dedicated busses for instruction cache and integrated memories. The

master bus is the data interface bus used for all data movement to and from the CPU and

is usually connected to the system bus controller. Clock and debug signals are connected

directly to I/O pins. See

Section 2 Signal Summary

for more information on all of the

ColdFire2/2M interface signals. A block diagram of the CPU is shown in Figure 1-4.

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1.3.2.3 I-CACHE DATA ARRAY.

The optional instruction cache data array is a compiled

RAM used to hold cache data. It is connected directly to the ColdFire2/2M via a dedicated

bus. Refer to

Section 5.1 Instruction Cache

for more information on the cache

configuration and interface signals.

1.3.2.4 I-CACHE TAG ARRAY.

The optional instruction cache tag array is a compiled

RAM used to hold tag information for the cache. It is connected directly to the ColdFire2/2M

via a dedicated bus. Refer to

Section 5.1 Instruction Cache

for more information on the

cache configuration and the interface signals.

1.3.2.5 MASTER BUS ARBITER (MARB).

The optional master bus arbiter is required to

support multiple masters on the master bus. It performs bus control and multiplexing for the

unidirectional signals

the master bus. Refer to

Section 3.10 Master Bus Arbitration

for

more information.

Figure 1-4. ColdFire2/2M Block Diagram

COLDFIRE

CORE

DEBUG MODULE

MULTIPLY

ACCUMULATE

UNIT

MISALIGNMENT UNIT

MASTER

BUS

CONTROLLER

INSTRUCTION

CACHE

CONTROLLER

ROM

CONTROLLER

SRAM

CONTROLLER

SRAM ROM INSTRUCTION CACHE

INTERFACEINTERFACE

INTERFACE

MASTER

BUS

DEBUG

INTERFACE

INTERNAL

BUS

TEST BUS

INTERFACE

(COLDFIRE2M ONLY)

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1.3.2.6 ROM ARRAY.

The optional ROM array is a compiled ROM used to hold boot code,

critical code, and monitor code. It is connected directly to the ColdFire2/2M via a dedicated

bus. Refer to

Section 5.3 ROM Module

for more information on the ROM configuration and

the interface signals.

1.3.2.7 SLAVE MODULES.

The slave modules are on-chip peripherals. They

communicate with the ColdFire2/2M via the slave bus and SBC. Slave modules are always

bus slaves and cannot initiate bus transactions except via interrupts. Examples of slave

modules include serial ports, parallel ports, and timers.

1.3.2.8 SRAM ARRAY.

The optional SRAM array is a compiled RAM used to hold critical

variables and the stack. It is connected directly to the ColdFire2/2M processor via a

dedicated bus. Refer to

Section 5.4 SRAM Module

for more information on the SRAM

configuration and the interface signals.

1.3.2.9 SYSTEM BUS CONTROLLER (SBC).

The system bus controller is responsible for

providing overall control of the slave and external busses. The system bus controller is the

single slave-bus master and interrupt controller, a possible external bus master, bus arbiter

and interrupt controller, and a master-bus slave and interrupt controller. The SBC provides

programmable registers to configure the memory map and interrupt control. The SBC

provides master bus cycle termination for accesses to slave modules on the slave bus. It

also generates interrupts on the master bus when requested by slaves on the slave bus, and

it responds to interrupt acknowledge cycles on the master bus.

1.4 PROGRAMMING MODEL

The ColdFire2/2M programming model consists of three register groups: integer unit user,

MAC unit user, and supervisor. Programs executing in the user mode use only the registers

in the integer and MAC groups. System software executing in the supervisor mode can

access all registers and use the control registers in the supervisor group to perform

supervisor functions. The following paragraphs provide a brief description of the registers in

the user and supervisor models. Refer to

Appendix A Register Summary

1.4.1 Integer Unit User Programming Model

Figure 1-5 illustrates the integer portion of the user programming model. It consists of the

following registers:

• 16 general-purpose 32-bit registers (D0 – D7, A0 – A7)

• 32-bit Program Counter (PC)

• 8-bit Condition Code Register (CCR)

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1.4.1.1 DATA REGISTERS (D0 – D7) .

Registers D0–D7 are used as data registers for bit

(1 bit), byte (8 bits), word (16 bits), and long word (32 bits) operations and may also be used

as index registers.

1.4.1.2 ADDRESS REGISTERS (A0 – A6) .

These registers can be used as software

stack pointers, index registers, or base address registers and may be used for word and long

word operations.

1.4.1.3 STACK POINTER (A7,SP) .

ColdFire2/2M supports a single hardware stack

pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The

initial value of A7 is loaded from the reset exception vector, address $0. The same register

is used for user mode and supervisor mode, and may be used for word and long word

operations.

A subroutine call saves the PC on the stack, and the return restores the PC from the stack.

Both the PC and the Status Register (SR) are saved on the stack during the processing of

exceptions and interrupts. The return from exception instruction restores the SR and PC

values from the stack.

1.4.1.4 PROGRAM COUNTER (PC).

The PC contains the address of the currently

executing instruction. During instruction execution and exception processing, the processor

automatically increments the contents of the PC or places a new value in the PC, as

appropriate. For some addressing modes, the PC can be used as a pointer for PC-relative

operand addressing.

1.4.1.5 CONDITION CODE REGISTER (CCR).

The CCR is the least significant byte of the

processor Status Register (SR), as shown in Figure 1-6. Bits 4–0 represent indicator flags

31 16 15 8 7 0

Data Register 0 (D0)

Data Register 1 (D1)

Data Register 2 (D2)

Data Register 3 (D3)

Data Register 4 (D4)

Data Register 5 (D5)

Data Register 6 (D6)

Data Register 7 (D7)

Address Register 0 (A0)

Address Register 1 (A1)

Address Register 2 (A2)

Address Register 3 (A3)

Address Register 4 (A4)

Address Register 5 (A5)

Address Register 6 (A6)

Stack Pointer (SP,A7)

Program Counter (PC)

Condition Code Register (CCR)

Figure 1-5. Integer Unit User Programming Model

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1-13

based on results generated by processor operations. Bit 4, the extend bit (X bit), is also used

as an input operand during multiprecision arithmetic computations.

Field Definitions:

X[4]—Extend Condition Code

Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to

a specified result.

N[3]—Negative Condition Code

Set if the most significant bit of the result is set; otherwise cleared.

Z[2]—Zero Condition Code

Set if the result equals zero; otherwise cleared.

V[1]—Overflow Condition Code

Set if an arithmetic overflow occurs implying that the result cannot be represented in the

operand size; otherwise cleared.

C[0]—Carry Condition Code

Set if a carryout of the most significant bit of the operand occurs for an addition, or if a borrow

occurs in a subtraction; otherwise cleared.

1.4.2 MAC Unit User Programming Model

Figure 1-7 illustrates the MAC portion of the user programming model available on the

ColdFire2M only. It consists of the following registers:

• 32-bit accumulator (ACC)

• 16-bit mask register (MASK)

• 8-bit MAC status register (MACSR)

BITS 76543210

FIELD

---XNZVC

RESET

--------

R/W

R R R R/W R/W R/W R/W R/W

Figure 1-6. Condition Code Register (CCR)

31 16 15 8 7 0

Accumulator (ACC)

Mask Register (MASK)

MAC Status Register (MACSR)

Figure 1-7. MAC Unit User Programming Model

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See

Section 6.2 MAC Programming Model

for more details.

1.4.2.1 ACCUMULATOR (ACC).

This is a 32-bit special purpose register used to

accumulate the results of MAC operations.

1.4.2.2 MASK REGISTER (MASK).

This is a 16-bit special purpose register used to hold

the address mask for MAC load operations.

1.4.2.3 MAC STATUS REGISTER (MACSR).

This is an 8-bit special purpose register

used to hold the status of MAC operations.

1.4.3 Supervisor Programming Model

System programers use the supervisor programming model to implement sensitive

operating system functions. The following paragraphs briefly describe the registers in the

supervisor programming model. All accesses that affect the control features of the

ColdFire2/2M are in the supervisor programming model, which consist of the registers

available to users as well as the registers listed in Figure 1-8.

Most of the control registers are accessed via the MOVEC instruction using the control

ColdFire Programmer’s Reference Manual Rev. 1.0

(MCF5200PRM/AD).

Refer to

Appendix A Register Summary

for a description of the access methods for all of

the register in the ColdFire2/2M.

1.4.3.1 STATUS REGISTER (SR).

Figure 1-9 illustrates the SR, which stores the

processor status and contains the condition codes that reflect the results of a previous

operation. The low-order byte of the SR is the condition code register (CCR.)

31 16 15 0 Cache Control Register (CACR)

Access Control Register 0 (ACR0)

Access Control Register 1 (ACR1)

Vector Base Register (VBR)

ROM Base Address Register (ROMBAR0)

SRAM Base Address Register (RAMBAR0)

Status Register (SR)

Figure 1-8. Supervisor Programming Model

Table 1-1. MOVEC Register Map

RC[11:0] REGISTER DEFINITION

$002 Cache Control Register (CACR)

$004 Access Control Register 0 (ACR0)

$005 Access Control Register 1 (ACR1)

$801 Vector Base Register (VBR)

$C00 ROM Base Address Register (ROMBAR0)

$C04 RAM Base Address Register 0 (RAMBAR0)

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Field Definitions:

T[15]—Trace Enable

When set, the processor will perform a trace exception after every instruction; otherwise no

trace exception is performed.

S[13]—Supervisor / User State

Denotes the processor privilege mode: supervisor mode (S set) or user mode (S cleared).

M[12]—Master / Interrupt State

This bit is cleared by an interrupt exception, and can be set by software during execution of

the RTE or move to SR instructions.

I[10:8]—Interrupt Priority Mask

Defines the current interrupt priority. Interrupt requests are inhibited for all priority levels less

than or equal to the current priority, except the level seven request, which cannot be

masked.

1.4.3.2 CACHE CONTROL REGISTER (CACR).

The CACR controls the cache operation.

This includes cache enable, cache freeze, cache invalidate, cache mode, and default write

protect. See

Section 5.1.11 Cache Control Register (CACR)

for more information.

1.4.3.3 ACCESS CONTROL REGISTERS (ACR0, ACR1).

The ACRs allow definition of

access attributes for two definable memory regions. These attributes include burst control,

instruction caching, and write protection. These attributes override the defaults in the CACR.

See

Section 5.2.1 ACR Programming Model

for more information.

1.4.3.4 VECTOR BASE REGISTER (VBR).

The VBR contains the base address of the

exception vector table in memory. The displacement of an exception vector is added to the

value in this register to access the vector table. Only the upper 12 bits of the VBR are used

and the lower 20 bits are filled with zeros. This forces the exception vector table to be aligned

on a 1 MByte boundary. This register is reset to zero.

1.4.3.5 ROM BASE ADDRESS REGISTER (ROMBAR0).

The ROMBAR0 register

configures the internal ROM module. This includes the base address, code space masks,

and enable. See

Section 5.3.2 ROM Programming Model

for more information.

1.4.3.6 SRAM BASE ADDRESS REGISTER (RAMBAR0).

The RAMBAR0 register

configures the internal SRAM module. This includes the base address, write protect, code

BITS 15 14 13 12 11 10 8 7 5 4 3 2 1 0

FIELD

T-SM- I - XNZVC

RESET

00110 7 0 00000

R/W

R/W R R/W R/W R R/W R R/W R/W R/W R/W R/W

Figure 1-9. Status Register (SR)

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space masks, and enable. See

Section 5.4.3 RAM Programming Model

for more

information.

1.5 INTEGER DATA FORMATS

Table 1-2 lists the operand data formats that are supported by the integer unit. Integer unit

operands can reside in registers, memory, or instructions. The operand size for each

instruction is either explicitly encoded in the instruction or implicitly defined by the instruction

operation.

1.6 ORGANIZATION OF DATA IN REGISTERS

The following paragraphs describe data organization within the data, address, and control

registers.

1.6.1 Organization of Integer Data Formats in Registers

Figure 1-10 shows the integer format for data registers. Each integer data register is 32 bits

wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data

registers, respectively. Long-word operands occupy the entire 32 bits of integer data

registers. A data register that is either a source or destination operand only uses or changes

the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining

high-order portion does not change. The least significant bit (LSB) of all integer sizes is zero,

the most significant bit (MSB) of a longword integer is 31, the MSB of a word integer is 15,

and the MSB of a byte integer is 7.

Because address registers and stack pointers are 32-bits wide, address registers cannot be

used for byte-size operands. When an address register is a source operand, either the low-

Table 1-2. Integer Data Formats

OPERAND DATA FORMAT SIZE

Bit 1 Bit

Byte Integer 8 Bits

Word Integer 16 Bits

Long-Word Integer 32 Bits

Figure 1-10. Organization of Integer Data Formats in Data Registers

LSB

MSB

1031 30 BIT (0 MODULO (OFFSET)

< 31,OFFSET OF 0 = MSB)

0731

BYTE

031

16-BIT WORD

031

LONG WORD

LOW-ORDER WORD

LONG WORD LSB

LSB

MSB

LSBMSBNOT USED

NOT USED

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order word or the entire longword operand is used, depending on the operation size. When

an address register is the destination operand, the entire register becomes affected, despite

the operation size. If the source operand is a word size, it is sign-extended to 32 bits and

then used in the operation to an address register destination. Address registers are primarily

for addresses and address computation support. The instruction set (See

Section 1.8

Instruction Set Summary

) explains how to add, compare, and move the contents of

address registers. Figure 1-11 illustrates the integer format for address registers.

Control registers vary in size according to function. Some control registers have undefined

bits reserved for future definition by Motorola. Those particular bits read as zeros and must

be written as zeros for future compatibility.

All operations to the SR and CCR are word-size operations. For all CCR operations, the

upper byte is read as all zeros and is ignored when written, despite privilege mode.

1.6.2 Organization of Integer Data Formats in Memory

The ColdFire2/2M uses a big-endian addressing scheme. The byte-addressable

organization of memory allows lower addresses to correspond to higher order bytes. The

address N of a long-word data item corresponds to the address of the high order word. The

lower order word is located at address N + 2. The address N of a word data item

corresponds to the address of the high order byte. The lower order byte is located at address

N + 1. This organization is shown in Figure 1-12.

31 16 15 0

SIGN-EXTENDED 16-BIT ADDRESS OPERAND

31 0

FULL 32-BIT ADDRESS OPERAND

Figure 1-11. Organization of Integer Data Formats in Address Registers

Overview

1-18

ColdFire2/2M User’s Manual

MOTOROLA

1.7 ADDRESSING MODE SUMMARY

The addressing modes are grouped into categories according to the mode of use. Data

addressing modes refer to data operands. Memory addressing modes refer to memory

operands. Alterable addressing modes refer to alterable (writable) operands. Control

addressing modes refer to memory operands without an associated size.

These categories sometimes combine to form new categories that are more restrictive. Two

combined classifications are alterable memory (both alterable and memory) and data

alterable (both alterable and data). Table 1-3 lists a summary of effective addressing modes

and their categories. Only the twelve addressing modes supported by the 68000 are

available on the ColdFire2/2M.

Figure 1-12. Memory Operand Addressing

31 23 15 7 0

BYTE $00000000

WORD $00000000

LONG WORD $00000000

BYTE $00000001 BYTE $00000002 BYTE $00000003

WORD $00000002

BYTE $00000004

WORD $00000004

LONG WORD $00000004

BYTE $00000005 BYTE $00000006 BYTE $00000007

WORD $00000006

BYTE $FFFFFFFC

WORD $FFFFFFFC

LONG WORD $FFFFFFFC

BYTE $FFFFFFFD BYTE $FFFFFFFE BYTE $FFFFFFFF

WORD $FFFFFFFE

Overview

MOTOROLA ColdFire2/2M User’s Manual 1-19

1.8 INSTRUCTION SET SUMMARY

Table 1-4 lists the notational conventions used throughout this manual unless otherwise

specified. Table 1-5 lists the ColdFire2/2M instruction set by opcode. This instruction set is

a reduced version of the 68000 instruction set. The removed instructions include BCD, bit

field, logical rotate, decrement and branch, integer division, and integer multiply with a 64-

bit result. Nine new MAC instructions have been added.

Table 1-3. Effective Addressing Modes and Categories

ADDRESSING MODES SYNTAX MODE

FIELD REG.

FIELD CATEGORY

DATA MEMORY CONTROL ALTERABLE

Data

Address Dn

An 000

001 reg. no.

reg. no. X

——

—X

Address

Address with Postincrement

Address with Predecrement

Address with Displacement

(An)

(An)+

–(An)

, An)

010

011

100

101

reg. no.

—

Address Register Indirect with Index

8-Bit Displacement (d

, An, Xn) 110 reg. no. X X X X

Program Counter Indirect

with Displacement (d

, PC) 111 010 X X X —

Program Counter Indirect with Index

8-Bit Displacement (d

, PC, Xn) 111 011 X X X —

Absolute Data Addressing

Short

Long (xxx).W

(xxx).L 111

111 000

001 X

X—

—

Immediate #<xxx> 111 100 X X — —

Table 1-4. Notational Conventions

OPCODE WILDCARDS

cc Logical Condition (example: NE for not equal)

An Any Address Register n (example: A3 is address register 3)

Ay,Ax Source and destination address registers, respectively

Dn Any Data Register n (example: D5 is data register 5)

Dy,Dx Source and destination data registers, respectively

Rn Any Address or Data Register

Ry,Rx Any source and destination registers, respectively

Rw Any second source register

Rc Any Control Register (example VBR is the vector base register)

ACC MAC Accumulator

DDATA Debug Data Port

CCR Condition Code Register (lower byte of status register)

MACSR MAC Status Register

MASK Mask Register

PC Program Counter

PST Processor Status Port

SR Status Register

Overview

1-20 ColdFire2/2M User’s Manual MOTOROLA

MISCELLANEOUS OPERANDS

#<data> Immediate data following the instruction word(s).

<ea> Effective Address

<label> Assemble Program Label

<list> List of registers (example: D3–D0)

<shift> Shift operation: Shift left (<<), Shift Right (>>)

<size> Operand data size: Byte (B), Word (W), Longword (L)

OPERATIONS

+ Arithmetic addition or postincrement indicator

– Arithmetic subtraction or predecrement indicator

¥ Arithmetic multiplication

~ Invert; operand is logically complemented

L Logical AND

V Logical OR

⊕

Logical exclusive OR

<< Shift left (example: D0 << 3 is shift D0 left 3 bits)

>> Shift right (example: D0 >> 3 is shift D0 right 3 bits)

→

Source operand is moved to destination operand

←→

Two operands are exchanged

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion

If <condition>

then <operations>

else <operations>

Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the optional ‘else’ clause

is present, the operations after ‘else’ are performed. If the condition is false and else is omitted, the instruction performs no

operation. Refer to the Bcc instruction description as an example.

& and

|or

SUBFIELDS AND QUALIFIERS

{} Optional Operation

() Identifies an indirect address

Displacement Value, n-Bits Wide (example: d

is a 16-bit displacement)

Address Calculated Effective Address (pointer)

Bit Bit Selection (example: Bit 3 of D0)

LSB Least Significant Bit (example: MSB of D0)

LSW Least Significant Word

MSB Most Significant Bit

MSW Most Significant Word

CONDITION CODE REGISTER BIT NAMES

C Carry Bit in CCR

N Negative Bit in CCR

V Overflow Bit in CCR

X Extend Bit in CCR

Z Zero Bit in CCR

Table 1-4. Notational Conventions (Continued)

Overview

MOTOROLA ColdFire2/2M User’s Manual 1-21

Table 1-5. Instruction Set Summary

INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION

ADD Dy,<ea>,x

<ea>y,Dx 32

32 Source + Destination

→ Destination

ADDA <ea>y,Ax 32 Source + Destination

→ Destination

ADDI #<data>,Dx 32 Immediate Data + Destination

→ Destination

ADDQ #<data>,<ea>x 32 Immediate Data + Destination

→ Destination

ADDX Dy,Dx 32 Source + Destination + X

→ Destination

AND Dy,<ea>x

<ea>y,Dx 32

32 Source L Destination

→ Destination

ANDI #<data>,Dx 32 Immediate Data L Destination

→ Destination

ASL Dx,Dy

#<data>,Dn 32

32 X/C

←

(Dy << Dx)

←

X/C

←

(Dy << #<data>)

←

ASR Dx,Dy

<data>,Dx 32

32 MSB

→

(Dy >> Dx)

→

X/C

MSB

→

(Dy >> #<data>)

→

X/C

Bcc <label> 8,16 If Condition True, Then PC + d

→

BCHG Dy,<ea>x

#<data>,<ea>x 8,32

8,32 ~(<Bit Number> of Destination)

→

Z, Bit of Destination

BCLR Dy,<ea>x

#<data>,<ea>x 8,32

8,32 ~(<Bit Number> of Destination)

→

Z, 0

→

Bit of Destination

BRA <label> 8,16 PC + d

→

BSET Dy,<ea>x

#<data>,<ea>x 8,32

8,32 ~(<Bit Number> of Destination)

→

Z, 1

→

Bit of Destination

BSR <label> 8,16 SP – 4

→

SP; PC

→

(SP); PC + d

→

BTST Dy,<ea>x

#<data>,<ea>x 8,32

8,32 ~(<Bit Number> of Destination)

→

CLR <ea>x 8,16,32 0

→

Destination

CMPI #<data>,Dx 8,16,32 Destination – Immediate Data

CMP <ea>y,Dx 32 Destination - Source

CMPA <ea>y,Ax 32 Destination - Source

CPUSH (An) 32 Push and Invalidate Cache Line

EOR Dy,<ea>x 32 Source

⊕

Destination

→ Destination

EORI #<data>,Dx 32 Immediate Data

⊕

Destination

→

Destination

EXT Dx

Dx 8

→

32 Sign-Extended Destination

→

Destination

EXTB Dx 8

→

32 Sign-Extended Destination

→

Destination

HALT none none Enter Halted State

JMP <ea>y none <ea>y

→

JSR <ea>y none SP – 4

→

SP; Next PC

→

(SP); <ea>y

→

LEA <ea>y,Ax 32 Address of <ea>

→

LINK Ax,#<data> 32 SP – 4

→

SP; Ax

→

(SP); SP

→

Ax; SP + d16

→

LSL Dx,Dy

#<data>,Dx 32

32 X/C

←

(Dy << Dx)

←

X/C

←

(Dx << #<data>)

←

LSR Dx,Dy

#<data>,Dx 32

32 0

→

(Dy >> Dx)

→

X/C

→

(Dx >> #<data>)

→

X/C

MAC

†

Rw,Rx ,<shift> 16

+ 32 →

32 ACC + (Rw

Rx){ << 1 | >> 1}

→

ACC

MACL

†

Rw,Rx,<shift>,<ea>,Ry 16

+ 32 →

32 ACC + (Rw

Rx){ << 1 | >> 1}

→

ACC; (<ea>{& MASK})

→

MOVE <ea>y,<ea>x 8,16,32 Source

→

Destination

MOVE from ACC

†

ACC,Rx 32 ACC

→

MOVE from CCR Dx 16 CCR

→

Destination

NOTE:

†

Available on the ColdFire2M only.

Overview

1-22 ColdFire2/2M User’s Manual MOTOROLA

MOVE from MACSR

†

MACSR,Rx

MACSR,CCR 32

8MACSR

→

MACSR

→

CCR

MOVE from MASK

†

MASK,Rx 32 MASK

→

MOVE from SR Dx 16 SR

→

Destination

MOVE to ACC

†

Rx,ACC

#<data>,ACC 32

32 Rx

→

ACC

#<data>

→

ACC

MOVE to CCR Dy,CCR,

#<data>,CCR 16 Source

→

CCR

#<data>

→

CCR

MOVE to MACSR

†

Rn,MACSR

#<data>,MACSR 32 Rn

→

MACSR

#<data>

→

MACSR

MOVE to MASK

†

Rn,MASK

#<data>,MASK 32

32 Rn

→

MASK

#<data>

→

MASK

MOVE to SR Dy,SR

#<data>,SR 16 Source

→

#<data>

→

MOVEA <ea>y,Ax 16,32

→

32 Source

→

Destination

MOVEC Rn,Rc 32 Rn

→

MOVEM list,<ea>x

<ea>y,list 32

32 Listed Registers

→

Destination

Source

→

Listed Registers

MOVEQ #<data>,Dx 8

→

32 Sign-extended Immediate Data

→

Destination

MSAC

†

Rw,Rx,<shift> 32 - 16

→

32 - 32

→

32 ACC - (Rw

Rx){ << 1 | >> 1} SF

→

ACC

MSACL

†

Rw,Rx,<shift>,<ea>,Ry 32 - 16

→

32 - 32

→

32 ACC - (Rw

Rx){ << 1 | >> 1} SF

→

ACC; (<ea>{& MASK})

→

MULS <ea>y,Dx

<ea>y, DI 16 x 16

→

32 x 32

→

32 Source

Destination

→

Destination

(Signed or unsigned)

MULU <ea>y,Dx

<ea>y, DI 16 x 16

→

32 x 32

→

32 Source x Destination

→

Destination

(Signed or unsigned)

NEG <ea>x 32 0 – Destination

→

Destination

NEGX <ea>x 32 0 – Destination – X

→

Destination

NOP none none PC + 2

→

PC; Pipeline synchronized

NOT <ea>x 32 ~ Destination

→

Destination

OR Dy,<ea>x

<ea>y,Dx 32 Source

Destination

→

Destination

ORI #<data>,Dx 32 Immediate Data

Destination

→

Destination

PEA <ea>y 32 SP – 4

→

SP; <ea>y

→

(SP)

PULSE none none Generate unique PST value

RTE none none (SP+2)

→

SR; (SP+4)

→

PC; SP+ 8

→

RTS none none (SP)

→

PC; SP + 4

→

Scc Dx 8 If condition true, then 1's

→

Destination;

Else 0's

→

Destination

STOP #<data> 16 Immediate data

→

SR; Enter Stopped State

SUB Dy,<ea>x

<ea>y,Dx 32

32 Destination - Source

→

Destination

SUBA <ea>,Ax 32 Destination - Source

→

Destination

SUBI #<data>,Dx 32 Destination – Immediate data

→

Destination

SUBQ #<data>,<ea>x 32 Destination – Immediate data

→

Destination

SUBX Dy,Dx 32 Destination – Source – X

→

Destination

SWAP Dx 16 MSW of Dx

←→

LSW of Dx

TRAP none none SP – 4

→

SP; PC

→

(SP);

SP – 2

→

SP; SR

→

(SP);

SP – 2

→

SP; Format

→

(SP);

Vector Address

→

Table 1-5. Instruction Set Summary (Continued)

INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION

NOTE:

†

Available on the ColdFire2M only.

Overview

MOTOROLA ColdFire2/2M User’s Manual 1-23

TRAPF none

#<data> none

PC + 2

→

PC;

PC + 4

→

PC;

PC + 6

→

TST <ea>y 8,16,32 Set Integer Condition Codes

UNLK Ax 32 Ax

→

SP; (SP)

→

Ax; SP + 4

→

WDDATA <ea>y 8,16,32 (<ea>y)

→

DDATA port

WDEBUG <ea>y 64 <ea>y

→

DEBUG; <ea>y + 4

→

DEBUG

Table 1-5. Instruction Set Summary (Continued)

INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION

NOTE:

†

Available on the ColdFire2M only.

MOTOROLA

ColdFire2/2M User’s Manual

2-1

SECTION 2

SIGNAL SUMMARY

2.1 INTRODUCTION

This section describes the ColdFire2/2M input and output signals. Figure 2-1 shows the

ColdFire2/2M along with the signal interface. The signals are listed alphabetically in Table

2-1. All ColdFire2/2M signals are unidirectional and synchronous.

Figure 2-1. ColdFire2/2M Detailed Block Diagram

MADDR[31:0]

MRDATA[31:0]

MWDATA[31:0]

MSIZ[1:0]

MTT[1:0]

MTM[2:0]

MIE

MRWB

MTSB

MTAB

MTEAB

MRSTB

ICH_SZ

ROM_SZ

SRAM_SZ

ICH_ADDR[14:

ICHD_CSB

ICHD_DI[31:0]

ICHD_DO[31:0

]

ICHD_ST

ICHD_RWB

ICHT_CSB

ICHT_DI[31:8]

ICHT_DO[31:8]

ICHT_ST

ICHT_RWB

BKPTB

DDATA[3:0]

DSCLK

DSI

DSO

PST[3:0]

ROM_ADDR

ROM_DO

ROM_ENB

ROM_VLD

SRAM_ADDR

SRAM_CSB

SRAM_DI

SRAM_DO

SRAM_ST

SRAM_RWB

CLK

IPLB[2:0]

TEST_ADDR[14:2]

TEST_IDATA_RD

TEST_IVLD_INH

TEST_KTA

TEST_MODE

TEST_SRAM_RD

TEST_RD

TEST_CTRL

BUS CONTROLLER

MISC

I-CACHE

UNIT

SRAM

UNIT

ROM

UNIT

DEBUG

CPU

CORE

MAC UNIT

UNIT

SCAN_XARRAY

TEST_ITAG_WRT

TEST_IDATA_WR

TEST_SRAM_WR

TEST_ROM_RD

TEST_WR_INH

MFRZB

MKILLB

MARBC[1:0]

MWDATAOE

TEST_RHIT

CAN_ENABLE

SCAN_MODE

MEM

CONFIG

IACK_68K

(COLDFIRE2M)

SI[15:0]

SO[15:0]

TR_MODE

TR_SE

TR_SDI[1:0]

CORE_TEST

TRCLK

TEST

PORT

TR_SD0[1:0]

Signal Summary

2-2

ColdFire2/2M User’s Manual

MOTOROLA

Table 2-1. Signal Summary

SIGNAL MNEMONIC INPUT/OUTPUT ACTIVE STATE

68K Interrupt Acknowledge Mode IACK_68K Input High

Break Point BKPTB Input Low

Clock CLK Input High

Debug Data DDATA[3:0] Output High

Development Serial Clock DSCLK Input High

Development Serial Data Input DSI Input High

Development Serial Data Output DSO Output High

Instruction Cache Address Bus ICH_ADDR[14:2] Output High

Instruction Cache Data Chip-Select ICHD_CSB Output Low

Instruction Cache Data Input Bus ICHD_DI[31:0] Output High

Instruction Cache Data Output Bus ICHD_DO[31:0] Input High

Instruction Cache Data Strobe ICHD_ST Output High

Instruction Cache Data Write Enable ICHD_RWB Output Low

Instruction Cache Size ICH_SZ[2:0] Input High

Instruction Cache Tag Chip-Select ICHT_CSB Output Low

Instruction Cache Tag Input Bus ICHT_DI[31:8] Output High

Instruction Cache Tag Output Bus ICHT_DO[31:8] Input High

Instruction Cache Tag Strobe ICHT_ST Output High

Instruction Cache Tag Write Enable ICHT_RWB Output Low

Interrupt Priority Level IPLB[2:0] Input Low

Master Address Bus MADDR[31:0] Output High

Master Arbiter Control MARBC[1:0] Output High

Master Freeze MFRZB Output Low

Master Kill MKILLB Output Low

Master Read Data Bus MRDATA[31:0] Input High

Master Read Data Input Enable MIE Input High

Master Read/Write MRWB Output Low

Master Reset MRSTB Input Low

Master Size MSIZ[1:0] Output High

Master Transfer Acknowledge MTAB Input Low

Master Transfer Error Acknowledge MTEAB Input Low

Master Transfer Modifier MTM[2:0] Output High

Master Transfer Start MTSB Output Low

Master Transfer Type MTT[1:0] Output High

Master Write Data Bus MWDATA[31:0] Output High

Master Write Data Output Enable MWDATAOE Output High

Processor Status PST[3:0] Output High

ROM Address Bus ROM_ADDR[14:2] Output High

ROM Data Output Bus ROM_DO[31:0] Input High

ROM Enable ROM_ENB[1:0] Output Low

ROM Size ROM_SZ[2:0] Input High

ROM Valid ROM_VLD Input High

Scan Enable SCAN_ENABLE Input High

Scan Exercise Array SCAN_XARRAY Input High

Scan Input SI[15:0] Input High

Scan Mode SCAN_MODE Input High

Scan Output SO[15:0] Input High

Scan Test Ring Clock TR_CLK Input High

Signal Summary

MOTOROLA

ColdFire2/2M User’s Manual

2-3

2.2 MASTER BUS SIGNALS

2.2.1 68K Interrupt Acknowledge Mode Enable (IACK_68K)

This active-high input signal enables the 68K interrupt acknowledge mode. In this mode, the

Master Address Bus, MADDR[31:0], MTT[1:0], and MTM[2:0] signals mimic the 68K

address bus and function codes during interrupt acknowledge and CPU space bus cycles.

This is a static input. Refer to

Section 3.7.1 Interrupt Acknowledge Bus Cycle

for more

information.

2.2.2 Master Address Bus (MADDR[31:0])

During a normal bus cycle, this 32-bit output bus provides the address of the first item of a

bus transfer. It is capable of addressing 4 Gbytes of address space.

2.2.3 Master Arbiter Control (MARBC[1:0])

These output signals can be used to specify the mode of operation for an optional arbitration

module. They reflect the bit positions [17:16] in the CACR. If an optional arbitration module

is not used, these signals can be used as general purpose output signals. The CACR is

accessible in supervisor mode as control register $002 using the MOVEC instruction.

Scan Test Ring Core Mode Enable CORE_TEST Input High

Scan Test Ring Data Input TR_SDI[1:0] Input High

Scan Test Ring Data Output TR_SDO[1:0] Output High

Scan Test Ring Enable TR_SE Input High

Scan Test Ring Mode TR_MODE Input High

SRAM Address Bus SRAM_ADDR[14:2] Output High

SRAM Chip-Select SRAM_CSB Output Low

SRAM Data Input Bus SRAM_DI[31:0] Output High

SRAM Data Output Bus SRAM_DO[31:0] Input High

SRAM Size SRAM_SZ[2::0] Input High

SRAM Strobe SRAM_ST[3::0] Output High

SRAM Read/Write SRAM_RWB[3:0] Output Low

Test Address Bus TEST_ADDR[14:2] Input High

Test Control TEST_CTRL Input High

Test Invalidate Inhibit TEST_IVLD_INH Input High

Test ITAG Write TEST_ITAG_WRT Input High

Test Instruction Cache Read Hit TEST_RHIT Output High

Test IDATA Read TEST_IDATA_RD Input High

Test IDATA Write TEST_IDATA_WRT Input High

Test KTA Mode Enable TEST_KTA Input High

Test Mode Enable TEST_MODE Input High

Test SRAM Read TEST_SRAM_RD Input High

Test SRAM Write TEST_SRAM_WRT Input High

Test Read TEST_RD Input High

Test ROM Read TEST_ROM_RD Input High

Test Write Inhibit TEST_WR_INH Input High

Table 2-1. Signal Summary (Continued)

SIGNAL MNEMONIC INPUT/OUTPUT ACTIVE STATE

Signal Summary

2-4

ColdFire2/2M User’s Manual

MOTOROLA

2.2.4 Master Freeze (MFRZB)

This active-low output signal indicates that the core has been halted. MFRZB is not part of

the M-Bus protocol. It is simply a signal that can be used to alert timers or other peripheral

modules that the core has been halted.

2.2.5 Master Kill (MKILLB)

This active-low output signal qualifies MTSB (i.e. it can assert in other cycles but is only

significant in a cycle where MSTB is asserted). When MKILLB is asserted simultaneously

with MTSB assertion, this indicates a hit in a K-Bus memory and that the external cycle must

be inhibited. This means the current master bus transaction is no longer required and should

be ignored (MTAB should not be asserted). MKILLB is asserted late in the MTSB cycle. Note

that if there is no K-Bus resident memory (ICACHE, SRAM, or ROM), MKILLB never

asserts. See Table 2-2 for MTSB/MKILLB interaction in table format.

2.2.6 Master Read Data Bus (MRDATA[31:0])

These input signals provide the read data path between the system and the ColdFire2/2M.

The read data bus is 32-bits wide and can transfer 8, 16 or 32 bits of data per bus transfer.

During a line transfer, the data bus is time-multiplexed across multiple clock cycles to

transfer 128 bits.

2.2.7 Master Read Data Input Enable (MIE)

This active-high input signal enables the capturing of MRDATA[31:0]. Power consumption

can be reduced by minimizing signal switching in the ColdFire2/2M by negating MIE when

MRDATA[31:0] is invalid. MIE must be asserted during all functional operation with one

master and during K-Bus memory testing.

2.2.8 Master Read/Write (MRWB)

This output signal indicates the direction of the data transfer for the current bus cycle. A high

level indicates a read cycle and a low level indicates a write cycle.

2.2.9 Master Reset (MRSTB)

This active-low input signal instructs all master bus modules, including the ColdFire2/2M, to

enter reset mode. The ColdFire2/2M will then initiate a reset exception.

2.2.10 Master Size (MSIZ[1:0])

These output signals indicate the data size for the bus transfer. Refer to Table 2-3 for the

bus size encoding.

Table 2-2. M-Bus Protocol with respect to MTSB and MKILLB

MTSB MKILLB M-BUS PROTOCOL

0 1 Initiate M-Bus transfer

0 0 Nop

1 X Nop

Signal Summary

MOTOROLA

ColdFire2/2M User’s Manual

2-5

2.2.11 Master Transfer Acknowledge (MTAB)

This active-low input signal is asserted by master bus slaves to indicate the successful

completion of a requested bus transfer.

2.2.12 Master Transfer Error Acknowledge (MTEAB)

This active-low input signal is asserted by master bus slaves to indicate an error condition

for the current bus transfer. If MTAB and MTEAB are both asserted, the cycle is terminated

with an error because MTEAB always has precedence over MTAB.

2.2.13 Master Transfer Modifier (MTM[2:0])

These output signals provide supplemental information for each transfer type. The exact

meaning depends on the MTT[1:0], and IACK_68K signals as shown in Table 2-4.

Table 2-3. Master Bus Transfer Size Encoding

MSIZ[1:0] TRANSFER SIZE

00 Longword (4 bytes)

01 Byte (1 byte)

10 Word (2 bytes)

11 Line (16 bytes)

Table 2-4. Master Bus Transfer Modifier Encoding

MTM[2:0] MTT[1:0] COLDFIRE IACK MODE

68K IACK MODE

000 0x Reserved Reserved

001 0x User Data Access User Data Access

010 0x User Code Access User Code Access

011 - 100 0x Reserved Reserved

101 0x Supervisor Data Access Supervisor Data Access

110 0x Supervisor Code Access Supervisor Code Access

111 0x Reserved Interrupt Acknowledge/CPU Space Access

000 - 100 10 Reserved Reserved

101 10 Emulator Mode Data Access Emulator Mode Data Access

110 10 Emulator Mode Code Access Emulator Mode Code Access

111 10 Reserved Reserved

000 11 CPU Space Access Reserved

001 11 Interrupt Acknowledge Level 1 Reserved

010 11 Interrupt Acknowledge Level 2 Reserved

011 11 Interrupt Acknowledge Level 3 Reserved

100 11 Interrupt Acknowledge Level 4 Reserved

101 11 Interrupt Acknowledge Level 5 Reserved

110 11 Interrupt Acknowledge Level 6 Reserved

111 11 Interrupt Acknowledge Level 7 Reserved

NOTES: 1. 68K interrupt acknowledge mode signal negated (IACK_68K = 0)

2. 68K interrupt acknowledge mode signal asserted (IACK_68K = 1)

Signal Summary

2-6

ColdFire2/2M User’s Manual

MOTOROLA

2.2.14 Master Transfer Start (MTSB)

This active-low output signal indicates the start of each bus transfer.

2.2.15 Master Transfer Type (MTT[1:0])

These output signals indicate the type of access of the current bus cycle. The exact meaning

depends on the IACK_68K signal as shown in Table 2-5.

2.2.16 Master Write Data Bus (MWDATA[31:0])

These output signals provide the write data path between the ColdFire2/2M and the system.

The write data bus is 32-bits wide and can transfer 8, 16 or 32 bits of data per bus transfer.

During a line transfer, the data bus is time-multiplexed across multiple clock cycles to carry

128 bits.

2.2.17 Master Write Data Output Enable (MWDATAOE)

This active-high output signal indicates that the ColdFire2/2M is driving the master write data

bus. This is used to control optional bidirectional data bus three-state drivers.

2.3 GENERAL CONTROL SIGNALS

2.3.1 Clock (CLK)

This input signal is the synchronous clock for the ColdFire2/2M. CLK is used to clock or

sequence the ColdFire2/2M internal logic.

2.3.2 Interrupt Priority Level (IPLB[2:0])

These active-low input signals indicate the encoded priority level of the requested interrupt.

Level seven, which cannot be masked, has the highest priority. Level zero indicates no

interrupt has been requested. These signals must maintain the interrupt request until the

ColdFire2/2M acknowledges the interrupt to guarantee that the interrupt is recognized.

Table 2-6 lists the interrupt levels, the IPLB[2:0] states, and the mask value that allows an

interrupt at each level.

Table 2-5. Master Bus Transfer Type Encoding

MTT[1:0] COLDFIRE IACK MODE

68K IACK MODE

00 ColdFire2/2M Access Acknowledge/CPU Space/ColdFire2/2M Access

01 Alternate Master Access Alternate Master Access

10 Emulator Mode Access Emulator Mode Access

11 Acknowledge/CPU Space Access Reserved

NOTES: 1. 68K interrupt acknowledge mode signal negated (IACK_68K = 0)

2. 68K interrupt acknowledge mode signal asserted (IACK_68K = 1)

Signal Summary

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2.4 INTEGRATED MEMORY SIGNALS

These signals interface the ColdFire2/2M to an integrated instruction cache, ROMs and

SRAMs.

2.4.1 Instruction Cache Signals

The signals interface the ColdFire2/2M to an optional integrated instruction cache.

2.4.1.1 INSTRUCTION CACHE ADDRESS BUS (ICH_ADDR[14:2]).

These registered

output signals provide the address of the current bus cycle (i.e. fetch cycle) to the integrated

cache RAMs. ICH_ADDR is only updated on fetch cycles (i.e. ICH_ADDR does not get

updated on SRAM or ROM hits). This bus should be connected to the address bus (A) of

the two compiled cache RAMs.

2.4.1.2 INSTRUCTION CACHE DATA CHIP-SELECT (ICHD_CSB).

This active-low,

output signal indicates the cache data RAM is currently selected to perform a data transfer

with the ColdFire2/2M. This bus should be connected to the chip-select (CSB) signal of the

compiled cache data RAM.

2.4.1.3 INSTRUCTION CACHE DATA INPUT BUS (ICHD_DI[31:0]).

These output

signals provide the write data path between the ColdFire2/2M and the cache data RAM. The

data bus is 32-bits wide and should be connected to the data inputs (DBI) of the compiled

cache data RAM.

2.4.1.4 INSTRUCTION CACHE DATA OUTPUT BUS (ICHD_DO[31:0]).

These input

signals provide the read data path between the cache data RAM and the ColdFire2/2M. The

data bus is 32-bits wide and should be connected to the data outputs (DBO) of the compiled

cache data RAM.

2.4.1.5 INSTRUCTION CACHE DATA STROBE (ICHD_ST).

This output signal initiates a

read or write cycle to the cache data RAM on a low-to-high transition. This signal should be

connected to the strobe input (ST) signal of the compiled cache data RAM.

2.4.1.6 INSTRUCTION CACHE DATA READ/WRITE (ICHD_RWB).

This output signal

indicates the direction of the data transfer to the cache data RAM. A high level indicates a

Table 2-6. Interrupt Levels and Mask Values

REQUESTED

INTERRUPT LEVEL CONTROL LINE STATUS INTERRUPT MASK LEVEL

REQUIRED FOR RECOGNITION

IPLB[2] IPLB[1] IPLB[0]

0 High High High No Request

1 High High Low 0

2 High Low High 0-1

3 High Low Low 0-2

4 Low High High 0-3

5 Low High Low 0-4

6 Low Low High 0-5

7 Low Low Low 0-7

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read cycle and a low level indicates a write cycle. It should be connected to the read/write

(RWB) signal of the compiled cache data RAM.

2.4.1.7 INSTRUCTION CACHE SIZE (ICH_SZ[2:0]).

These static inputs specify the size

of the compiled cache RAMs connected to the ColdFire2/2M processor. Table 2-7 lists the

possible cache configurations. ICH_SZ[2:0] does not affect the CACR in any way; thus a

MOVEC instruction will write the CACR regardless of the ICH_SZ specification (which is

contrary to the SRAM_SZ and ROM_SZ effect during RAMBAR and ROMBAR loading).

2.4.1.8 INSTRUCTION CACHE TAG CHIP-SELECT (ICHT_CSB).

This active-low output

signal indicates the cache tag RAM is currently selected to perform a data transfer with the

ColdFire2/2M. This signal should be connected to the chip-select (CSB) signal of the

compiled cache tag RAM.

2.4.1.9 INSTRUCTION CACHE TAG INPUT BUS (ICHT_DI[31:8]).

These output signals

provide the write data path between the ColdFire2/2M and the cache tag RAM. The data bus

is 24-bits wide. Bit eight is always the valid bit and is always used as seen in the cache

configuration shown in Table 2-8. This bus should be connected to the data inputs (DBI) of

the compiled cache tag RAM. Functionally, ICH_ADDR[31:9] is what gets written onto

ICHT_DI[31:9] and ICHT_DI[8] is written with the valid state of the entry.

Table 2-7. Cache Configuration Encoding

CACHE SIZE

(BYTES) ICH_SZ[2:0] TAG RAM (BITS) DATA RAM (BITS)

ADDRESS DATA ADDRESS DATA

None 000 - - - -

512 001 5 24 7 32

1 K 010 6 23 8 32

2 K 011 7 22 9 32

4 K 100 8 21 10 32

8 K 101 9 20 11 32

16K† 110 10 19 12 32

32K† 111 11 18 13 32

NOTE: †16K and 32K RAMS may require a reduced operating frequency in HPF65

ColdFire2 Hard Macro.

Table 2-8. Valid Tag RAM Data Signals

CACHE SIZE

(BYTES) VALID DATA BITS

512 ICHT_Dx[31:8]

1 K ICHT_Dx[31:10,8]

2 K ICHT_Dx[31:11,8]

4 K ICHT_Dx[31:12,8]

8 K ICHT_Dx[31:13,8]

16K ICHT_Dx[31:14,8]

32K ICHT_Dx[31:15,8]

Signal Summary

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2.4.1.10 INSTRUCTION CACHE TAG OUTPUT BUS (ICHT_DO[31:8]).

These input

signals provide the read data path between the cache tag RAM and the ColdFire2/2M. The

data bus is 24-bits wide. Bit eight is always the valid bit and is always used regardless of the

cache configuration as shown in Table 2-8. This bus should be connected to the data

outputs (DBO) of the compiled cache tag RAM. Unused signals must be tied low.

2.4.1.11 INSTRUCTION CACHE TAG STROBE (ICHT_ST).

This output signal initiates a

read or write cycle to the cache tag RAM on a low-to-high transition. This signal should be

connected to the strobe input (ST) signal of the compiled cache tag RAM.

2.4.1.12 INSTRUCTION CACHE TAG READ/WRITE (ICHT_RWB).

This output signal

indicates the direction of the data transfer to the cache tag RAM. A high level indicates a

read cycle and a low level indicates a write cycle. It should be connected to the read/write

(RWB) signal of the compiled cache tag RAM.

2.4.2 Integrated ROM Signals

These signals interface the ColdFire2/2M to the optional integrated ROMs.

2.4.2.1 ROM ADDRESS BUS (ROM_ADDR[14:2]).

These output signals provide the

address of the current bus cycle to the integrated ROMs. This bus should be connected to

the address bus (A) of the compiled ROMs. The number of valid address signals depends

on the total ROM size as shown in Table 2-9.

2.4.2.2 ROM DATA OUTPUT BUS (ROM_DO[31:0]).

These input signals provide the

read data path from the integrated ROMs to the ColdFire2/2M. The data bus is 32-bits wide

and can transfer 8, 16, or 32 bits of data per bus transfer. During a line transfer, the data

lines are time-multiplexed across multiple cycles to carry 128 bits. This bus should be

connected to the data outputs (DO) of the compiled ROMs.

2.4.2.3 ROM ENABLE (ROM_ENB[1:0]).

These active-low, output signals indicate the

ROMs are currently selected to drive the ROM_DO[31:0] bus. These signals should be

connected individually to the enable signal (ROMENB) signal of the compiled ROMs. Both

are asserted for 32-bit accesses. ROM_ENB[0] connects to the MSW while ROM_ENB[1]

connects to the LSW.

Table 2-9. Valid ROM Address Bits

TOTAL ROM SIZE VALID ROM_ADDR BITS

0 None

512 ROM_ADDR[8:2]

1 K ROM_ADDR[9:2]

2 K ROM_ADDR[10:2]

4 K ROM_ADDR[11:2]

8 K ROM_ADDR[12:2]

16K ROM_ADDR[13:2]

32K ROM_ADDR[14:2]

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2.4.2.4 ROM SIZE (ROM_SZ[2:0]).

These static inputs specify the size of the compiled

ROMs connected to the ColdFire2/2M. These pins need to stay valid during all operation.

Table 2-10 lists the possible ROM configurations. If the ROM_SZ pins are zero, the ROM

cannot be enabled via a CPU space write to ROMBAR. Therefore if the ROM is enabled

while the ROM_SZ pins are at zero, the processor behaves as if no ROM module existed.

2.4.2.5 ROM VALID (ROM_VLD).

This active-high input signal determines if the ROM

module should be active immediately after a hard reset. Thus, if asserted, the first fetches

($0, $4) go to ROM instead of external memory. ROM_VLD controls the reset value of the

ROM base address register (i.e. the ROM must be based at $0000 if ROM_VLD is

asserted).

2.4.3 Integrated SRAM Signals

These signals interface the ColdFire2/2M to the optional integrated SRAMs.

2.4.3.1 SRAM ADDRESS BUS (SRAM_ADDR[14:2]).

These registered output signals provide the address of the current bus cycle to the

integrated SRAMs. This bus should be connected to the address bus (A) of the four

compiled SRAMs. The number of valid address signals depends on the total SRAM size as

shown in Table 2-11.

Table 2-10. ROM Configuration Encoding

TOTAL ROM SIZE

(BYTES) ROM_SZ[2:0] ADDRESS

(BITS) DATA

(BITS)

None 000 - -

512 001 7 2 @ 16

1 K 010 8 2 @ 16

2 K 011 9 2 @ 16

4 K 100 10 2 @ 16

8 K 101 11 2 @ 16

16K

110 12 2 @ 16

32K

111 13 2 @ 16

NOTES: 1. 2 ROMs, each 16-bits wide

2. 16K and 32K ROMs may require a reduced operating frequency.

Table 2-11. Valid SRAM Address Bits

TOTAL SRAM SIZE VALID SRAM_ADDR BITS

0 None

512 SRAM_ADDR[8:2]

1 K SRAM_ADDR[9:2]

2 K SRAM_ADDR[10:2]

4 K SRAM_ADDR[11:2]

8 K SRAM_ADDR[12:2]

16K SRAM_ADDR[13:2]

32K SRAM_ADDR[14:2]

Signal Summary

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2.4.3.2 SRAM CHIP-SELECT (SRAM_CSB).

This active-low output signal indicates the

SRAMs are currently selected to perform a data transfer with the ColdFire2/2M. This signal

should be connected to the chip-select (CSB) signal of the four compiled SRAMs.

2.4.3.3 SRAM DATA INPUT BUS (SRAM_DI[31:0]).

These output signals provide the

write data path between the ColdFire2/2M and the integrated SRAM. The data bus is 32-bits

wide and can transfer 8, 16, or 32 bits of data per bus transfer. During a line transfer, the

data lines are time-multiplexed across multiple cycles to carry 128 bits. This bus should be

connected to the data inputs (DBI) of the four compiled SRAMs. If only one byte is being

written, the byte will be replicated on all 4 lines likewise a word will be replicated in both word

positions.

2.4.3.4 SRAM DATA OUTPUT BUS (SRAM_DO[31:0]).

These input signals provide the

read data path between the integrated RAM and the ColdFire2/2M. The data bus is 32-bits

wide and can transfer 8, 16 or 32 bits of data per bus transfer. During a line transfer, the data

lines are time-multiplexed across multiple cycles to carry 128 bits. This bus should be

connected to the data outputs (DBO) of the four compiled SRAMs.

2.4.3.5 SRAM SIZE (SRAM_SZ[2:0]).

These static inputs specify the size of the compiled

SRAMs connected to the ColdFire2/2M. These pins need to stay valid during all operation.

If the SRAM_SZ pins are zero, the SRAM cannot be enabled via a CPU space write to

RAMBAR. Therefore if the RAM is enabled while the SRAM_SZ pins are at zero, the

processor behaves as if no SRAM module existed.

Table 2-12 lists the possible SRAM configurations.

2.4.3.6 SRAM STROBE (SRAM_ST[3:0]).

These output signals initiate a read or write

cycle to the integrated SRAMs on a low-to-high transition. These signals should be

connected individually to the strobe input (ST) signals of the four compiled SRAMs. The

ST[0] signal connects to the high-order byte and ST[3] connects to the low-order byte.

Table 2-12. SRAM Configuration Encoding

TOTAL SRAM SIZE

(BYTES) RAM_SZ[2:0] ADDRESS

(BITS) DATA

(BITS)

None 000 - -

512 001 7 4@8

1 K 010 8 4@8

2 K 011 9 4@8

4 K 100 10 4@8

8 K 101 11 4@8

16K

110 12 4@8

32K

111 13 4@8

NOTES: 1. 4 RAMs, each 8-bits wide

2. 16K and 32K RAMs may require a reduced operating

frequency.

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2.4.3.7 SRAM READ/WRITE (SRAM_RWB[3:0]).

These output signals indicate the

direction of the data transfer to the to the integrated SRAMs. A high level indicates a read

cycle and a low level indicates a write cycle. They should be connected individually to the

read/write (RWB) signal of the four compiled SRAMs. Like SRAM_ST[3:0], the

SRAM_RWB[3] signal connects to the high-order byte and SRAM_ST[0] connects to the

low-order byte.

2.5 DEBUG SIGNALS

2.5.1 Break Point (BKPTB)

This active-low, unidirectional input signal is used to request a manual break point. It will

cause the processor to enter a halted state after the completion of the current instruction.

This status will be reflected on the processor status (PST) outputs.

2.5.2 Debug Data (DDATA[3:0])

These output signals display the captured processor status and break point status.

2.5.3 Development Serial Clock (DSCLK)

This input signal is used as the development serial clock f or the serial interf ace to the Debug

Module.The maximum frequency is 1/2 the clock (CLK) frequency.

2.5.4 Development Serial Input (DSI)

This input signal provides the single-bit communication for the Debug Module commands.

2.5.5 Development Serial Output (DSO)

This output signal provides single-bit communication for the Debug Module responses.

2.5.6 Processor Status (PST[3:0])

These output signals report the processor status. Table 2-13 shows the encoding of these

signals. These signals indicate the current status of the processor pipeline and, as a result,

are not related to the current bus transfer.

Signal Summary

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2.6 TEST SIGNALS

2.6.1 SIGNALS REQUIRED TO PERFORM SCAN TEST

This section describes the ColdFire2/2M signals dedicated to the scan testing of the

ColdFire2/2M. All ColdFire2/2M signals are unidirectional and synchronous.

2.6.1.1 SCAN ENABLE (SCAN_ENABLE).

This active-high input signal enables scan

testing of the ColdFire2/2M. It forces all internal flip-flops to be linked together into sixteen

parallel scan chains. This signal must be negated for functional operation.

2.6.1.2 SCAN EXERCISE ARRAY (SCAN_XARRAY).

This active-high input signal is

used to exercise the integrated memory arrays during scan testing. This signal causes

random writes to the internal RAMs by strobing the write strobes while scanning.

2.6.1.3 SCAN INPUT (SI[15:0]).

These input signals are connected to the16 internal

ColdFire2/2M scan chain inputs.

2.6.1.4 SCAN MODE (SCAN_MODE).

This active-high, unidirection input signal gates off

all memory array outputs during scan testing.SCAN_MODE should be held asserted for the

duration of scan testing.

2.6.1.5 SCAN OUTPUT (SO[15:0]).

These output signals are connected to the 16 internal

ColdFire2/2M scan chain outputs.

Table 2-13. Processor Status Encoding

PST[3:0] DEFINITION

(HEX) (BINARY)

$0 0000 Continue execution

$1 0001 Begin execution of an instruction

$2 0010 Reserved

$3 0011 Entry into user-mode

$4 0100 Begin execution of

PULSE

and

WDDATA

instructions

$5 0101 Begin execution of taken branch

$6 0110 Reserved

$7 0111 Begin execution of

RTE

instruction

$8 1000 Begin 1-byte transfer on DDATA

$9 1001 Begin 2-byte transfer on DDATA

$A 1010 Begin 3-byte transfer on DDATA

$B 1011 Begin 4-byte transfer on DDATA

$C 1100 Exception processing†

$D 1101 Emulator-mode entry exception processing†

$E 1110 Processor is stopped, waiting for interrupt†

$F 1111 Processor is halted †

NOTE: †These encodings are asserted for multiple cycles.

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2.6.1.6 IO TEST RING CLOCK (TRCLK).

This input signal is the synchronous clock used

to transition the test ring during scan testing. TR_CLK is connected to the clock input of all

IO test ring registers.

2.6.1.7 IO TEST RING CORE MODE ENABLE (CORE_TEST).

This active-high input

signal enables the core mode of the test ring during scan testing. The test ring is in scan

core mode if CORE_TEST is asserted and in scan ASIC mode if CORE_TEST is negated.

2.6.1.8 IO TEST RING DATA INPUT (TR_SDI[1:0]).

These input signals are the serial

data inputs for test ring chain one and zero.

2.6.1.9 IO TEST RING DATA OUTPUT (TR_SDO[1:0]).

These output signals are the

serial output data from test ring chain one and zero.

2.6.1.10 IO TEST RING ENABLE (TR_SE).

This active-high input signal enables the test

ring. TR_SE is connected to the scan enable input of all IO test ring scannable registers.

2.6.1.11 IO TEST RING MODE (TR_MODE). This active-high input signal enables the

scan test mode of the test ring. The test ring is in scan test mode if TR_MODE is asserted

and in normal functional mode if negated. TR_MODE should be asserted for the duration of

scan testing, and be held negated for the duration of memory testing and during functional

operation of the device.

2.6.2 Integrated Memory Test Signals

This section describes the ColdFire2/2M signals dedicated to testing the integrated

memories. Other signals are required to be either controlled or brought out (muxed) to

package pins as well (See Section 8 Test Operation).

2.6.2.1 TEST ADDRESS BUS (TEST_ADDR[14:2]). These input signals specify an

address when testing the integrated memories.

2.6.2.2 TEST CONTROL (TEST_CTRL). This active-high input signal indicates the test

address bus (TEST_ADDR[14:2]) will be latched on the next positive clock edge.

2.6.2.3 TEST IDATA READ (TEST_IDATA_RD). This active-high input signal tests the

instruction cache data memory read operation.

2.6.2.4 TEST IDATA WRITE (TEST_IDATA_WRT). This active-high input signal tests the

instruction cache data memory write operation.

2.6.2.5 TEST INSTRUCTION CACHE READ HIT (TEST_RHIT). This active-high output

signal indicates a hit has occurred when accessing the instruction cache during memory

array testing.

2.6.2.6 TEST INVALIDATE INHIBIT (TEST_IVLD_INH). This active-high input signal

inhibits the invalidate operation when testing the instruction cache.

2.6.2.7 TEST ITAG WRITE (TEST_ITAG_WRT). This active-high input signal tests the

instruction cache tag memory write operation.

Signal Summary

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2.6.2.8 TEST KTA MODE ENABLE (TEST_KTA). This active-high input signal allows the

instruction cache tag and data arrays to be read in parallel, mimicking the functional

operation. This allows testing of the speed path from the tag and data arrays to the core.

2.6.2.9 TEST MODE ENABLE (TEST_MODE). This active-high input signal enables all of

the integrated memory test signals. TEST_MODE should be asserted for the duration of

memory testing.

2.6.2.10 TEST SRAM READ (TEST_SRAM_RD). This active-high input signal tests the

integrated SRAM memory read operation.

2.6.2.11 TEST SRAM WRITE (TEST_SRAM_WRT). This active-high input signal tests the

integrated SRAM memory write operation.

2.6.2.12 TEST READ (TEST_RD). This active-high input signal tests read operations on all

of the integrated memories.

2.6.2.13 TEST ROM READ (TEST_ROM_RD). This active-high input signal tests the

integrated ROM memory read operation.

2.6.2.14 TEST WRITE INHIBIT (TEST_WR_INH). This active-high input signal disables

the write strobes to the SRAM and instruction cache compiled RAMS. TEST_WR_INH

should be negated for the duration of memory test.

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SECTION 3

MASTER BUS OPERATION

The master bus provides a basic two cycle bus protocol, similar to that used by previous

generations of M68000 microprocessors. Basic cycles are defined as the transfer start (TS)

cycle and the transfer acknowledge (TA) cycle. The address and control information is

driven onto the bus during the TS cycle, and the data is valid during the subsequent TA

cycle. By delaying the assertion of the transfer acknowledge signal, the bus automatically

inserts wait states to easily accommodate any slave response speed. The following sections

detail the signal descriptions, data transfer mechanism, and bus transfer protocols.

3.1 SIGNAL DESCRIPTION

This section describes the ColdFire2/2M signals associated with the master bus. All

ColdFire2/2M signals are unidirectional and synchronous.

3.1.1 68K Interrupt Acknowledge Mode Enable (IACK_68K)

This active-high input signal enables the 68K interrupt acknowledge mode. In this mode, the

MADDR[31:0], MTT[1:0], and MTM[2:0] signals mimic the 68K address bus and function

codes during interrupt acknowledge and CPU space bus cycles. This is a static input. Refer

Section 3.7.1 Interrupt Acknowledge Bus Cycle

for more information.

3.1.2 Master Address Bus (MADDR[31:0])

During a normal bus cycle, this 32-bit output bus provides the address of the first item of a

bus transfer. It is capable of addressing four Gbytes of address space.

3.1.3 Master Arbiter Control (MARBC[1:0])

These output signals can be used to specify the mode of operation for an optional arbitration

module. They reflect the bit positions [17:16] in the CACR. If an optional arbitration module

is not used, these signals can be used as general purpose output signals.

3.1.4 Master Freeze (MFRZB)

This active-low output signal indicates that the core has been halted. MFRZB is not part of

the M-Bus protocol. It is simply a signal that can be used to alert timers or other peripheral

modules that the core has been halted.

3.1.5 Master Kill (MKILLB)

This active-low output signal qualifies MTSB (i.e. it can assert in other cycles but is only

significant in a cycle where MSTB is asserted). When MKILLB is asserted simultaneously

with MTSB assertion, this indicates a hit in a K-Bus memory and that the external cycle must

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be inhibited. This means the current master bus transaction is no longer required and should

be ignored (MTAB should not be asserted). MKILLB is asserted late in the MTSB cycle. Note

that if there is no K-Bus resident memory (ICACHE, SRAM, or ROM), MKILLB never

asserts. See Table 3-1 for MTSB/MKILLB interaction in table format.

3.1.6 Master Read Data Bus (MRDATA[31:0])

These input signals provide the read data path between the system and the ColdFire2/2M

device. The read data bus is 32-bits wide and can transfer 8, 16 or 32 bits of data per bus

transfer. During a line transfer, the data bus is time-multiplexed across multiple clock cycles

to transfer 128 bits.

3.1.7 Master Read Data Input Enable (MIE)

This active-high input signal enables the capturing of MRDATA[31:0]. Power consumption

can be reduced by minimizing signal switching in the ColdFire2/2M by negating MIE when

MRDATA[31:0] is invalid. MIE must be asserted during all one-master functional operation

and during K-Bus memory testing.

3.1.8 Master Read/Write (MRWB)

This output signal indicates the direction of the data transfer for the current bus cycle. A high

level indicates a read cycle and a low level indicates a write cycle.

3.1.9 Master Reset (MRSTB)

This active-low input signal instructs all master bus modules, including the ColdFire2/2M

device, to enter reset mode. The ColdFire2/2M processor will then initiate a reset exception.

3.1.10 Master Size (MSIZ[1:0])

These output signals indicate the data size for the bus transfer. Refer to Table 3-2 for the

bus size encoding.

Table 3-1. M-Bus Protocol with respect to MTSB and MKILLB

MTSB MKILLB M-BUS PROTOCOL

0 1 Initiate M-Bus transfer

0 0 Nop

1 X Nop

Table 3-2. Master Bus Transfer Size Encoding

MSIZ[1:0] TRANSFER SIZE

00 Longword (4 bytes)

01 Byte (1 byte)

10 Word (2 bytes)

11 Line (16 bytes)

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3.1.11 Master Transfer Acknowledge (MTAB)

This active low input signal is asserted by master bus slaves to indicate the successful

completion of a requested bus transfer.

3.1.12 Master Transfer Error Acknowledge (MTEAB)

This active low input signal is asserted by master bus slaves to indicate an error condition

for the current bus transfer. If MTAB and MTEAB are both asserted, the cycle is terminated

with an error because MTEAB always has precedence over MTAB.

3.1.13 Master Transfer Modifier (MTM[2:0])

These output signals provide supplemental information for each transfer type. The exact

meaning depends on the MTT[1:0], and IACK_68K signals as shown in Table 3-3.

3.1.14 Master Transfer Start (MTSB)

This active low output signal indicates the start of each bus transfer.

3.1.15 Master Transfer Type (MTT[1:0])

These output signals indicate the type of access of the current bus cycle. The exact meaning

depends on the IACK_68K signal as shown in Table 3-4.

Table 3-3. Master Bus Transfer Modifier Encoding

MTM[2:0] MTT[1:0] COLDFIRE IACK MODE

68K IACK MODE

000 0x Reserved Reserved

001 0x User Data Access User Data Access

010 0x User Code Access User Code Access

011 - 100 0x Reserved Reserved

101 0x Supervisor Data Access Supervisor Data Access

110 0x Supervisor Code Access Supervisor Code Access

111 0x Reserved Interrupt Acknowledge/CPU Space Access

000 - 100 10 Reserved Reserved

101 10 Emulator Mode Data Access Emulator Mode Data Access

110 10 Emulator Mode Code Access Emulator Mode Code Access

111 10 Reserved Reserved

000 11 CPU Space Access Reserved

001 11 Interrupt Acknowledge Level 1 Reserved

010 11 Interrupt Acknowledge Level 2 Reserved

011 11 Interrupt Acknowledge Level 3 Reserved

100 11 Interrupt Acknowledge Level 4 Reserved

101 11 Interrupt Acknowledge Level 5 Reserved

110 11 Interrupt Acknowledge Level 6 Reserved

111 11 Interrupt Acknowledge Level 7 Reserved

NOTES: 1. 68K interrupt acknowledge mode signal negated (IACK_68K = 0)

2. 68K interrupt acknowledge mode signal asserted (IACK_68K = 1)

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3.1.16 Master Write Data Bus (MWDATA[31:0])

These output signals provide the write data path between the ColdFire2/2M and the system.

The write data bus is 32-bits wide and can transfer 8, 16 or 32 bits of data per bus transfer.

During a line transfer, the data bus is time-multiplexed across multiple clock cycles to carry

128 bits.

3.1.17 Master Write Data Output Enable (MWDATAOE)

This active high output signal indicates that the ColdFire2/2M is driving the master write data

bus. This is used to control optional bidirectional data bus three-state drivers.

3.2 DATA TRANSFER MECHANISM

3.2.1 Transfer Type Control Signals

The transfer type control signals indicate the type of bus transaction occurring on the master

bus. This includes the master transfer type (MTT[1:0]) and master transfer modifier

(MTM[2:0]) signals. The MTT[1:0] signals indicates the type of transfer and the MTM[2:0]

signals provide supplemental information. The encodings for MTT[1:0] and MTM[2:0] are

shown in Table 3-3 and Table 3-4. The transfer type attributes for accesses made through

the debug module are determined by the programming of the debug module (see

Section

7.4.2.2 Address Attribute Register (AATR)

3.2.1.1 COLDFIRE2/2M ACCESS.

If the ColdFire2/2M requests a master bus transfer, it

drives the MTT[1:0] signals with a ColdFire2/2M access encoding. The MTM[2:0] encoding

will depend on the privilege mode and address space of the transfer:

Privilege Mode—Supervisor/User Mode Access

When the supervisor (S) bit in the status register (SR) is set, the ColdFire2/2M will drive

MTM[2:0] with one of the supervisor mode encodings during a master bus transfer. When

the S bit in the SR is clear, the ColdFire2/2M will drive MTM[2:0] with one of the user mode

access encodings.

Address Space—Code/Data Access

If the ColdFire2/2M accesses the code space, it will drive MTM[2:0] with one of the code

access encodings during a master bus transfer. Code space accesses are opcode fetches

or operand fetches in one of the PC relative addressing modes. If the ColdFire2/2M

accesses the data space, it will drive MTM[2:0] with one of the data access encodings. Data

Table 3-4. Master Bus Transfer Type Encoding

MTT[1:0] COLDFIRE IACK MODE

68K IACK MODE

00 ColdFire2/2M Access Acknowledge/CPU Space/ColdFire2/2M Access

01 Alternate Master Access Alternate Master Access

10 Emulator Mode Access Emulator Mode Access

11 Acknowledge/CPU Space Access Reserved

NOTES: 1. 68K interrupt acknowledge mode signal negated (IACK_68K = 0)

2. 68K interrupt acknowledge mode signal asserted (IACK_68K = 1)

Master Bus Operation

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space accesses are operand fetches that are not in one of the PC relative addressing

modes.

3.2.1.2 ALTERNATE MASTER ACCESS.

When an alternate master requests a master

bus transfer, the MTT[1:0] signals should be driven with the alternate master access

encoding by the alternate master. The MTM[2:0] encoding is the same as that for the

ColdFire2/2M access.

3.2.1.3 EMULATOR MODE ACCESS.

Accesses made while in emulator mode generate

emulator mode accesses on the master bus. This is controlled by the configuration/status

Section 7.4.1.1 Emulator Mode

Emulator mode accesses result in he MTT[1:0] signals being driven with the emulator mode

access encoding. The encoding of the MTM[2:0] signals will be one of the emulator mode

encodings depending on the address space as defined for the ColdFire2/2M access.

3.2.1.4 INTERRUPT ACKNOWLEDGE ACCESS.

Interrupt acknowledge bus cycles are

indicated as an acknowledge/CPU space access on the MTT[1:0] signals (the encoding

depends on the interrupt acknowledge mode). If the ColdFire2/2M is in the ColdFire interrupt

acknowledge mode, the MTM[2:0] signals are driven with the pending interrupt level

number. In the 68K interrupt acknowledge mode, the MTM[2:0] signals will be driven high.

Refer to

Section 3.7 Interrupt Acknowledge Bus Cycles

3.2.1.5 CPU SPACE ACCESS.

CPU space accesses are indicated as a acknowledge/

CPU space access on the MTT[1:0] signals. The MTM[2:0] signals are driven with a CPU

space encoding. The specific encoding depends on the interrupt acknowledge mode. Many

debug commands and MOVEC instructions result in CPU space accesses.

3.2.2 Data Bus Requirements

The ColdFire2/2M designates all operands for transfers on a byte-boundary system. A line-

sized operand (16 bytes) is four longwords. For all data transfers, MADDR[31:2] indicates

the longword base address of the first byte of the reference item. MADDR[1:0] indicates the

byte offset from this base address. The MSIZ[1:0] signals along with the low-order two

address signals are used to determine how the data bus is used. Table 3-5 indicates the

MRDATA[31:0] requirements for slave devices when responding to read transfers. A “-”

indicates a “don’t care”, i.e. the value is ignored.

Table 3-5. MRDATA Requirements for Read Transfers

TRANSFER SIZE MSIZ[1:0] MADDR[1:0] MRDATA[31:24] MRDATA[23:16] MRDATA[15:8] MRDATA[7:0]

Byte 01 00 Byte Data - - -

01 01 - Byte Data - -

01 10 - - Byte Data -

01 11 - - - Byte Data

Word 10 00 Word Data -

10 10 - Word Data

Long 00 00 Longword Data

Line 11 00 First Longword Data

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Some of the system bus controllers (SBC) within the ColdFire architecture support

dynamically-sized external data transfers, i.e., the slave indicates the width of the data port

at the time of the transfer. To support this bus sizing feature, there are certain data

replication functions which must be performed by all master devices, including the

ColdFire2/2M, during write cycles. Table 3-6 indicates the MWDATA[31:0] requirements for

master devices when initiating write transfers.

Note that the ColdFire2/2M device, as well as all masters, places the byte operand on all

byte lanes for a byte write cycle, and the word operand on both word lanes for a word write

cycle.

3.3 DATA TRANSFERS

3.3.1 Byte, Word, and Longword Read Transfers

For byte, word, and longword read accesses, the ColdFire2/2M requests data from a slave

device. The bus operations are similar for the different sized accesses, with the MSIZ[1:0]

signals defining the access size. Based on the transfer size, the data is placed on the

appropriate byte lanes of the read data bus (MRDATA[31:0]). This read transfer is defined

in Figure 3-1.

Table 3-6. MWDATA Bus Requirements for Write Transfers

TRANSFER SIZE MSIZ[1:0] MADDR[1:0] MWDATA[31:24] MWDATA[23:16] MWDATA[15:8] MWDATA[7:0]

Byte 01 -- Byte Data Byte Data Byte Data Byte Data

Word 10 -0 Word Data Word Data

Long 00 00 Longword Data

Line 11 00 First Longword Data

Master Bus Operation

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See Figure 3-2 for an example of normal read and write master bus transfers without wait

states.

Figure 3-1. Byte, Word, and Longword Read Transfer Flowchart

1) DRIVE ADDRESS ON MADDR[31:0]

2) SET MRWB TO READ (MRWB = 1)

3) SET MSIZ[1:0] TO BYTE, WORD, OR LONG

4) SET MTT[1:0], MTM[2:0] T O SIGNAL THE

APPROPRIATE ACCESS TYPE

5) ASSERT MTSB FOR ONE CLK CYCLE

1) REGISTER THE MRDATA[31:0] BUS

2) RECOGNIZE THE TRANSFER IS DONE

1) DECODE THE ADDRESS AND SELECT

THE APPROPRIATE SLAVE DEVICE.

INSERT NECESSARY WAIT-STATES.

1) DRIVE THE DATA ON THE APPROPRIATE

BYTE LANES OF THE MRDATA[31:0] BUS,

BASED ON MSIZ[1:0], MADDR1:0].

2) ASSERT MIE FOR ONE CLK CYCLE.

2) ASSERT MTAB FOR ONE CLK CYCLE.

MASTER SLAVE

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Clock 1 (C1)

The read cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid values

on the master address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and

MTM[2:0] signals identify the specific access type. The master read/write (MRWB) signal is

driven high for a read cycle, and the master size signals (MSIZ[1:0]) indicate transfer size.

The ColdFire2/2M asserts the master transfer start (MTSB) signal during C1 to indicate the

beginning of a bus cycle.

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB. The selected device uses the

MRWB and MSIZ signals to place the data on the master read data bus (MRDATA[31:0])

and assert the master input enable (MIE) signal. Concurrently, the selected device asserts

the master transfer acknowledge (MTAB) signal. At the end of C2, the ColdFire2/2M

samples the level of MTAB and latches the current value on MRDATA[31:0]. If MTAB is

Figure 3-2. Normal Transfer (without Wait States)

C1 C2 C1 C2

CLK

A1 A2MADDR

MRWB

MSIZ

MTT

MTM

MTSB

D2MWDATA

MWDATAOE

D1MRDATA

MIE

MTAB

MTEAB

READ WRITE

Master Bus Operation

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asserted, the transfer terminates. If MTAB is not asserted, the ColdFire2/2M processor

ignores the data and inserts wait states instead of terminating the transfer. The ColdFire2/

2M continues to sample MTAB on successive rising edges of CLK until it is asserted. The

selected device negates the MIE and MTAB signals in the first half of the next CLK cycle.

3.3.2 Normal Tranfers with MKILLB

Figure3-3 illustrates normal tranfers (no wait states) with MKILLB asserted and negated:

Figure 3-3. Normal Transfer with MKILLB Timing Diagram (without wait states)

Clock 1 (C1)

The read cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid values

on the master address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and

MTM[2:0] signals identify the specific access type. The master read/write (MRWB) signal is

C6C5

C4C3

CLK

MADDR

MRWB

MSIZ

MTT

MTM

MTSB

MKILLB

MWDATA

WDATA

MRDATA

MIE

MTAB

External

Read Internal

Integ.

Memory

Read

External

Write Internal

Integ.

Memory

Write

Access

MTEAB

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driven high for a read cycle, and the master size signals (MSIZ[1:0]) indicate transfer size.

The ColdFire2/2M asserts the master transfer start (MTSB) signal during C1 to indicate the

beginning of a bus cycle. MKILLB does not assert during this cycle so the access will go

external via M-Bus.

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M processor negates MTSB. The selected device

uses the MRWB and MSIZ signals to place the data on the master read data bus

(MRDATA[31:0]) and assert the master input enable (MIE) signal. Concurrently, the

selected device asserts the master transfer acknowledge (MTAB) signal. At the end of C2,

the ColdFire2/2M processor samples the level of MTAB and latches the current value on

MRDATA[31:0]. If MTAB is asserted, the transfer terminates. If MTAB is not asserted, the

ColdFire2/2M ignores the data and inserts wait states instead of terminating the transfer.

The ColdFire2/2M continues to sample MTAB on successive rising edges of CLK until it is

asserted. The selected device negates the MIE and MTAB signals in the first half of the next

CLK cycle.

Clock 3 (C3)

Another read cycle begins in C3; however this read cycle will be to internal integrated

memory. During the first half of C3, the ColdFire2/2M places valid values on the master

address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and MTM[2:0]

signals identify the specific access type. The master read/write (MRWB) signal is driven high

for a read cycle, and the master size signals (MSIZ[1:0]) indicate transfer size. The

ColdFire2/2M asserts the master transfer start (MTSB) signal during C3 to indicate the

beginning of a bus cycle. MKILLB asserts late in the cycle. The combination of the assertion

of both (MTSB and MKILLB signifies that the access will occur internally in integrated

memory and the M-Bus transaction is not needed. The internal access will complete in one

cycle; therefore another access can begin immediately on the following cycle.

Clock 4 (C4)

A write cycle starts in C4. During the first half of C4, the ColdFire2/2M places valid values

on the master address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and

MTM[2:0] signals identify the specific access type. The master read/write (MRWB) signal is

driven low for a write cycle, and the master size signals (MSIZ[1:0]) indicate transfer size.

The ColdFire2/2M asserts the master transfer start (MTSB) signal during C4 to indicate the

beginning of a bus cycle. MKILLB does not assert during this cycle so the access will go

external via M-Bus.

Cycle 5 (C5)

During the first half of C5, the ColdFire2/2M negates MTSB. The selected device uses the

MRWB and MSIZ signals to take the data off the master write data bus (MWDATA[31:0].

Concurrently, the selected device asserts the master transfer acknowledge (MTAB signal.

At the end of C5, if MTAB is asserted, the transfer terminates. If MTAB is not asserted, the

ColdFire2/2M inserts wait states instead of terminating the transfer. The ColdFire2/2M

Master Bus Operation

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continues to sample MTAB on successive rising edges of CLK until it is asserted. The

selected device negates the (MTAB signal in the first half of the next CLK cycle.

Cycle 6 (C6)

Another write cycle begins in C6; however this write cycle will be to internal integrated

memory. During the first half of C6, the ColdFire2/2M places valid values on the master

address bus (MADDR[31:0]) and transfer control signals. The MTT[1:0] and MTM[2:0]

signals identify the specific access type. The master read/write (MRWB) signal is driven low

for a write cycle, and the master size signals (MSIZ[1:0]) indicate transfer size. The

ColdFire2/2M asserts the master transfer start (MTSB) signal during C6 to indicate the

beginning of a bus cycle. MKILLB asserts late in the cycle. The combination of the assertion

of both (MTSB and MKILLB signifies that the access will occur internally in integrated

memory and the M-Bus transaction is not needed. The internal access will complete in one

cycle; therefore another access can begin immediately on the following cycle.

Cycle 7 (C7)

Another access can begin in this cycle ((MTSB can assert).

3.3.3 Byte, Word, and Longword Write Transfers

For byte, word, and longword write accesses, the ColdFire2/2M transfers data to a slave

device. The bus operations are similar for the different sized accesses, with the MSIZ[1:0]

signals defining the access size. Based on the transfer size, the data is placed on the

appropriate byte lanes of the write data bus (MWDATA[31:0]). This write transfer is defined

in Figure 3-4.

Master Bus Operation

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See Figure 3-2 for an example of a normal write transfer without wait states. Figure 3-5

shows an example of a normal write master bus transfer with wait states. Note the Cxw

nomenclature is used to define a wait state during the bus cycle—e.g., C2w.

Figure 3-4. Byte, Word, and Longword Write Transfer Flowchart

MASTER

1) DRIVE ADDRESS ON MADDR[31:0]

2) SET MRWB TO WRITE (MRWB = 0)

3) SET MSIZ[1:0] TO BYTE, WORD, OR LONG

4) SET MTT[1:0], MTM2:0] T O SIGNAL THE

APPROPRIATE ACCESS TYPE

5) ASSERT MTSB FOR ONE CLK CYCLE

1) DRIVE DATA ONTO MWDATA[31:0]

2) ASSERT MWDATAOE

1) RECOGNIZE THE TRANSFER IS DONE

2) NEGATE MWDATAOE

1) DECODE THE ADDRESS AND SELECT

THE APPROPRIATE SLAVE DEVICE.

INSERT NECESSARY WAIT-STATES.

1) CAPTURE THE DATA FROM THE

APPROPRIATE BYTE LANES OF THE

MWDATA[31:0] BUS, BASED ON

MSIZ[1:0], MADDR[1:0]

2) ASSERT MTAB FOR ONE CLK CYCLE

SLAVE

Master Bus Operation

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Clock 1 (C1)

The write cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid values

on the master address bus (MADDR[31:0]) and transfer control signals. The master transfer

type (MTT[1:0]) and master transfer modifier (MTM[2:0]) signals identify the specific access

type. The master read/write (MRWB) signal is driven low for a write cycle, and the master

size signals (MSIZ[1:0]) indicate transfer size. The ColdFire2/2M asserts the master transfer

start (MTSB) signal during C1 to indicate the beginning of a bus cycle.

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB, places the data on the master

write data bus (MWDATA[31:0]), and asserts the master write data output enable

(MWDATAOE) signal. Concurrently, the selected device asserts the master transfer

acknowledge (MTAB) signal if it is ready to latch the data. At the end of C2, the selected

device latches the current value on MWDATA[31:0], and the ColdFire2/2M samples the

level of MTAB. If MTAB is asserted, the bus cycle is terminated and the ColdFire2/2M

negates MWDATAOE in the first half on the next CLK cycle. If MTAB is not asserted, the

ColdFire2/2M inserts wait states instead of terminating the transfer. The ColdFire2/2M

continues to sample MTAB on successive rising edges of CLK until it is asserted.

Figure 3-5. Normal Write Transfer (with Wait States)

C1 C2W C2W C2

CLK

A1MADDR

MRWB

MSIZ

MTT

MTM

MTSB

D1MWDATA

MWDATAOE

MTAB

MTEAB

WRITE

Master Bus Operation

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3.3.4 Line Read Transfer

The ColdFire2/2M uses a line read access to fetch a four-longword operand using a burst

transfer. A line read accesses a block of four longwords, aligned to a 16-byte memory

boundary, by supplying a starting address that points to the critical longword in the four-

longword block. The address and attributes driven by the ColdFire2/2M remain stable

throughout the entire transfer. As a result, the slave device must increment MADDR[3:2]

internally to sequence for each transfer with the address wrapping around at the end of the

block. The allowable longword fetch patterns during a line access are shown in Table 3-7.

The responding slave device terminates each longword transfer on the MRDATA[31:0] bus

by asserting the transfer acknowledge control signal, MTAB. All devices on the master bus

must support burst accesses. The assertion of MTEAB aborts the line read access. See

Section 3.8.1 Access Errors

for more information on MTEAB.

A line read burst is defined in Figure 3-6.

Table 3-7. Allowable Line Access Patterns

MADDR[3:2] LONGWORD ACCESS ORDER

00 0 - 4 - 8 - C

01 4 - 8 - C - 0

10 8 - C - 0 - 4

11 C - 0 - 4 - 8

Master Bus Operation

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See Figure 3-7 for an example of a line read burst master bus transfer without wait states.

Figure 3-6. Line Read Transfer Flowchart

MASTER

1) DRIVE ADDRESS ON MADDR[31:0]

2) SET MRWB TO READ (MRWB = 1)

3) SET MSIZ[1:0] T O LINE

4) SET MTT[1:0] AND MTM[2:0] T O SIGNAL THE

APPROPRIATE ACCESS TYPE

5) ASSERT MTSB FOR ONE CLK CYCLE

1) REGISTER THE MRDATA[31:0] BUS

2) RECOGNIZE THE 1ST TRANSFER IS DONE

1) REGISTER THE MRDATA[31:0] BUS

2) RECOGNIZE THE 2ND TRANSFER IS DONE

1) REGISTER THE MRDATA[31:0] BUS

2) RECOGNIZE THE 3RD TRANSFER IS DONE

1) REGISTER THE MRDATA[31:0] BUS

2) RECOGNIZE THE 4TH TRANSFER IS DONE

1) DECODE THE ADDRESS AND SELECT

THE APPROPRIATE SLAVE DEVICE.

INSERT NECESSARY WAIT-STATES.

1) DRIVE THE DATA ON MRDATA[31:0].

2) ASSERT MIE FOR ONE CLK CYCLE.

3) ASSERT MTAB FOR ONE CLK CYCLE.

1) DRIVE THE DATA ON MRDATA[31:0].

2) ASSERT MIE FOR ONE CLK CYCLE.

3) ASSERT MTAB FOR ONE CLK CYCLE.

1) DRIVE THE DATA ON MRDATA[31:0].

2) ASSERT MIE FOR ONE CLK CYCLE.

3) ASSERT MTAB FOR ONE CLK CYCLE.

1) DRIVE THE DATA ON MRDATA[31:0].

2) ASSERT MIE FOR ONE CLK CYCLE.

3) ASSERT MTAB FOR ONE CLK CYCLE.

SLAVE

Master Bus Operation

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Clock 1 (C1)

The line read cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid

values on the master address bus (MADDR[31:0]) and transfer control signals. The master

transfer type (MTT[1:0]) and master transfer modifier (MTM[2:0]) signals identify the specific

access type. The master read/write (MRWB) signal is driven high for a read cycle, and the

master size signals (MSIZ[1:0]) indicate transfer size (Line = $3). The ColdFire2/2M asserts

the master transfer start (MTSB) signal during C1 to indicate the beginning of a bus cycle.

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB. The selected device uses the

MRWB and MSIZ signals to place the data on the master read data bus (MRDATA[31:0])

and assert the master input enable (MIE) signal. The first transfer must supply the longword

at the corresponding long-word boundary. Concurrently, the selected device asserts master

transfer acknowledge (MTAB) signal. At the end of C2, the ColdFire2/2M samples the level

of MTAB and latches the current value on MRDATA[31:0]. If MTAB is asserted, the transfer

of the first longword terminates. If MTAB is not asserted, the ColdFire2/2M ignores the data

and inserts wait states instead of terminating the transfer. The ColdFire2/2M continues to

sample MTAB on successive rising edges of CLK until it is asserted.

Figure 3-7. Line Read Transfer (without Wait States)

C1 C2 C3 C4 C5

CLK

A1MADDR

MRWB

$3MSIZ

MTT

MTM

MTSB

D1 D2 D3 D4MRDATA

MIE

MTAB

MTEAB

Master Bus Operation

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Clock 3 (C3)

The ColdFire2/2M holds the address and transfer control signals constant during C3. The

selected device must increment the MADDR[3:2] signals to reference the next longword to

transfer, place the data on MRDATA[31:0], assert MIE, and assert MTAB. At the end of C3,

the ColdFire2/2M samples the level of MTAB and latches the current value on the

MRDATA[31:0] signals. If MTAB is asserted, the transfer terminates. If MTAB is not asserted

at the end of C3, the ColdFire2/2M ignores the latched data and inserts wait states instead

of terminating the transfer. The ColdFire2/2M continues to sample MTAB on successive

rising edges of CLK until it is asserted.

Clock 4 (C4)

This clock is identical to C3 except that once MTAB is recognized as being asserted, the

latched value corresponds to the third longword of data for the burst.

Clock 5 (C5)

This clock is identical to C3 except that once MTAB is recognized, the latched value

corresponds to the fourth longword of data for the burst. This is the last clock cycle of the

line read transaction. The selected device negates the MIE and MTAB signals in the first half

of the next CLK cycle.

3.3.5 Line Write Transfers

The line write transfer is similar to the line read transfer. This 16-byte burst write transfer is

defined in Figure 3-8.

Master Bus Operation

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MOTOROLA

The assertion of MTEAB will abort a line write transfer. See

Section 3.8.1 Access Errors

for more information on MTEAB. It is the slave’s responsibility to increment and wrap the

MADDR[3:2] signals internally.

Figure 3-8. Line Write Transfer Flowchart

MASTER

1) DRIVE ADDRESS ON MADDR[31:0]

2) SET MRWB TO WRITE (MRWB = 0)

3) SET MSIZ[1:0] T O LINE

4) SET MTT[1:0] AND MTM[2:0] T O SIGNAL THE

APPROPRIATE ACCESS TYPE

5) ASSERT MTSB FOR ONE CLK CYCLE

1) DRIVE DATA ONTO MWDATA[31:0]

2) ASSERT MWDATAOE

1) RECOGNIZE THE 1ST TRANSFER IS DONE

1) DRIVE DATA ONTO MWDATA[31:0]

1) RECOGNIZE THE 2ND TRANSFER IS DONE

1) DRIVE DATA ONTO MWDATA[31:0]

2) RECOGNIZE THE 3RD TRANSFER IS DONE

1) DRIVE DATA ONTO MWDATA[31:0]

1) RECOGNIZE THE 4TH TRANSFER IS DONE

2) NEGATE MWDATAOE

1) DECODE THE ADDRESS AND SELECT

THE APPROPRIATE SLAVE DEVICE

2) INSERT NECESSARY WAIT-STATES

1) CAPTURE THE DATA FROM

MWDATA[31:0]

2) ASSERT MTAB FOR ONE CLK CYCLE

1) CAPTURE THE DATA FROM

MWDATA[31:0]

2) ASSERT MTAB FOR ONE CLK CYCLE

1) CAPTURE THE DATA FROM

MWDATA[31:0]

2) ASSERT MTAB FOR ONE CLK CYCLE

1) CAPTURE THE DATA FROM

MWDATA[31:0]

2) ASSERT MTAB FOR ONE CLK CYCLE

SLAVE

Master Bus Operation

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See Figure 3-9 for an example of a line write master bus transfer without wait states.

Clock 1 (C1)

The line write cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid

values on the master address bus (MADDR[31:0]) and transfer control signals. The master

transfer type (MTT[1:0]) and master transfer modifier (MTM[2:0]) signals identify the specific

access type. The master read/write (MRWB) signal is driven low for a write cycle, and the

master size signals (MSIZ[1:0]) indicate line size ($3). The ColdFire2/2M asserts the master

transfer start (MTSB) signal during C1 to indicate the beginning of a bus cycle.

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB, places the first longword of data

on the master write data bus (MWDATA[31:0]), and asserts the master write data output

enable (MWDATAOE) signal. Concurrently, the selected device asserts the master transfer

acknowledge (MTAB) signal if it is ready to latch the data. At the end of C2, the ColdFire2/

2M samples the level of MTAB, and the selected device latches MWDATA[31:0]. If MTAB is

asserted, the transfer of the first longword terminates. If MTAB is not asserted, the

ColdFire2/2M inserts wait states instead of terminating the transfer. The ColdFire2/2M

continues to sample MTAB on successive rising edges of CLK until it is recognized asserted.

Figure 3-9. Line Write Transfer (without Wait States)

C1 C2 C3 C4 C5

CLK

A1MADDR

MRWB

$3MSIZ

MTT

MTM

MTSB

D1 D2 D3 D4MWDATA

MWDATAOE

MTAB

MTEAB

Master Bus Operation

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Clock 3 (C3)

The ColdFire2/2M holds the address and transfer control signals constant during C3, but

drives MWDATA[31:0] with the second longword of data. The selected device must

increment MADDR[3:2] to reference the second longword address, and assert MTAB. At the

end of C3, the ColdFire2/2M samples the level of MTAB, and the selected device latches

MWDATA[31:0]. If MTAB is asserted, the transfer terminates. If MTAB is not recognized

asserted at the end of C3, the ColdFire2/2M inserts wait states instead of terminating the

transfer. The ColdFire2/2M continues to sample MTAB on successive rising edges of CLK

until it is recognized.

Clock 4 (C4)

This clock is identical to C3 except that once MTAB is asserted, the value corresponds to

the third longword of data for the burst.

Clock 5 (C5)

This clock is identical to C3 except that once MTAB is asserted, the data value corresponds

to the fourth longword of data for the burst. This is the last clock cycle of the line write

transaction and the ColdFire2/2M negates MWDATAOE in the first half of the next CLK

cycle.

See Figure 3-10 for an example of a line write master bus transfer with wait states. Note the

Cxw nomenclature that is used to define a wait state during the bus cycle, e.g., C2w.

Master Bus Operation

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3-21

3.4 MISALIGNED OPERANDS

All ColdFire2/2M data formats can be located in memory on any byte boundary. A byte

operand is properly aligned at any address, a word operand is misaligned at an odd address,

and a longword is misaligned at an address that is not evenly divisible by four. However,

since operands can reside at any byte boundary, they can be misaligned. Although the

ColdFire2/2M does not enforce any alignment restrictions for data operands, including PC

relative data addressing, some performance degradation occurs when additional bus cycles

are required for longword or word operands that are misaligned. For maximum performance,

data items should be aligned on their natural boundaries. All instruction words and extension

words must reside on word boundaries. Attempting to prefetch an instruction word at an odd

address causes an address error exception. See

Section 4.2.3 Address Error Exception

for more information.

The ColdFire2/2M misalignment unit converts misaligned operand accesses that are

noncachable to a sequence of aligned accesses. Figure 3-11 illustrates the transfer of a

longword operand from an odd address requiring more than one bus cycle. In this example,

the MSIZ[1:0] signals specify a byte transfer, and the byte offset is $1. The slave device

supplies the byte and acknowledges the data transfer. When the ColdFire2/2M starts the

second cycle, the MSIZ[1:0] signals specify a word transfer with a byte offset of $2. The next

two bytes are transferred during this cycle. The ColdFire2/2M then initiates the third cycle,

Figure 3-10. Line Write Transfer (with Wait States)

C1 C2W C2 C3W C3 C4W C4 C5W C5

CLK

A1MADDR

MRWB

$3MSIZ

MTT

MTM

MTSB

D1 D2 D3 D4MWDATA

MWDATAOE

MTAB

MTEAB

Master Bus Operation

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MOTOROLA

with the MSIZ[1:0] signals indicating a byte transfer. The byte offset is now $0; the port

supplies the final byte and the operation is complete. This example is similar to the one

illustrated in Figure 3-12 except that the operand is word sized and the transfer requires only

two bus cycles. Figure 3-13 illustrates a functional timing diagram for a misaligned word read

transfer.

31 24 23 16 15 8 7 0

Transfer 1 - Byte 3 - -

Transfer 2 - - Byte 2 Byte 1

Transfer 3 Byte 0 - - -

Figure 3-11. Example of a Misaligned Longword Transfer

31 24 23 16 15 8 7 0

Transfer 1 - - - Byte1

Transfer 2 Byte 0 - - -

Figure 3-12. Example of a Misaligned Word Transfer

Figure 3-13. Misaligned Word Read Transfer

C1 C2 C1 C2

CLK

A1 A2MADDR

MRWB

$1 $1MSIZ

MTT

MTM

MTSB

D1 D2MRDATA

MIE

MTAB

MTEAB

READ 1 READ 2

Master Bus Operation

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ColdFire2/2M User’s Manual

3-23

The combination of operand size and alignment determines the number of bus cycles

required to perform a particular memory access. Table 3-8 lists the number of bus cycles

required for different operand sizes with all possible alignment conditions for read and write

cycles. The table confirms that alignment significantly affects bus cycle throughput for

noncachable accesses. For example, in Figure 3-11 the misaligned longword operand took

three bus cycles because the first byte offset = $1. If the byte offset = $0, then it would have

taken one bus cycle. The ColdFire2/2M system designer and programmer should account

for these effects, particularly in time-critical applications.

3.5 INVALID MASTER BUS CYCLES

The ColdFire2/2M starts a master bus transaction before it determines if the address hits in

the cache or is mapped to the internal memories. As a result, the ColdFire2/2M will assert

the MKILLB signal (late in that MTSB cycle) to indicate the current bus transaction resulted

in a hit in the cache or internal memories. When this signal is asserted, master bus slaves

must stop driving the master bus and must not return a MTAB or MTEAB. The current

master bus cycle must be inhibited.

The general priority scheme is as follows:

if (SRAM “hits”)

SRAM supplies data to the processor

else if (ROM “hits”)

ROM supplies data to the processor

else if (line fill buffer “hits”)

line fill buffer supplies data to the processor

else if (icache “hits”)

icache supplies data to the processor

else master bus cycle accesses to reference data from non-local memory

Clock 1 (C1)

The read cycle starts in C1. During the first half of C1, the ColdFire2/2M places valid values

on the master address bus (MADDR[31:0]) and transfer control signals. The ColdFire2/2M

asserts the master transfer start (MTSB) signal during C1 to indicate the beginning of a bus

cycle.

Table 3-8. Memory Alignment Cycles

TRANSFER SIZE $0

†

Instruction 1 - - -

Byte Operand 1111

Word Operand 1212

Longword Operand 1323

NOTE: †Where the byte offset (MADDR[1:0]) equals this encoding.

Master Bus Operation

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Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB. Because the MKILLB signal

was not asserted during the rising clock edge of C2, the selected device uses the MRWB

and MSIZ signals to place the data on the master read data bus (MRDATA[31:0]) and assert

the master input enable (MIE) signal. Concurrently, the selected device asserts the master

transfer acknowledge (MTAB) signal. At the end of C2, the ColdFire2/2M samples the level

of MTAB and captures the current value on MRDATA[31:0]. If MTAB is asserted, the transfer

terminates. If MTAB is not asserted, the ColdFire2/2M ignores the data and inserts wait

states instead of terminating the transfer. The ColdFire2/2M continues to sample MTAB on

successive rising edges of CLK until it is asserted. The selected device negates the MIE and

MTAB signals in the first half of the next CLK cycle.

Clock 3 (C3)

The read cycle starts in C3. The ColdFire2/2M asserts the MTSB signal, and then the

MKILLB signal. This signifies that the M-Bus cycle must be inhibited; i.e. the access has “hit”

in an internal-bus memory.

Clock 4 (C4)

Nop.

Clock 5 (C5)

The read cycle starts in C5. The ColdFire2/2M asserts the MTSB signal, and then the

MKILLB signal. This signifies that the M-Bus cycle must be inhibited; i.e. the access has “hit”

in an internal K-Bus memory.

Clock 6 (C6)

Another read cycle starts in C6. The C1 description applies here.

Clock 7 (C7)

During the first half of C7, the ColdFire2/2M negates MTSB. Because the MKILLB signal

was not asserted during the rising clock edge of C7, the selected device uses the MRWB

and MSIZ signals to place the data on the master read data bus (MRDATA[31:0]). The rest

of the C2 description applies here.

3.6 PIPELINE STALLS

In an idealized environment for maximum performance, all ColdFire2/2M references are

mapped to integrated memory resources and complete in a single clock cycle. Any memory

reference that generates a master bus access stalls the processor pipeline since the internal

transfer cannot be completed in a single clock cycle. This performance degradation factor

can be expressed as:

Pipeline Stall = Master Bus Clock Cycles - 1

Master Bus Operation

MOTOROLA ColdFire2/2M User’s Manual 3-25

where the stall is measured in clock cycles, and Master Bus Clock Cycles represents the

entire master bus transfer time in clock cycles. In the examples shown in Figure 3-14, the

read cycle with one wait state stalls the ColdFire2/2M for two clock cycles, and the zero wait

state write transfer produces a stall of one clock cycle.

3.7 INTERRUPT ACKNOWLEDGE BUS CYCLES

When a peripheral device requires the services of the ColdFire2/2M or is ready to send

information that the ColdFire2/2M requires, it can signal the ColdFire2/2M to take an

interrupt exception. The interrupt exception transfers control to a routine that responds

appropriately. The peripheral device uses the active-low interrupt priority level signals

(IPLB[2:0]) to signal an interrupt condition to the ColdFire2/2M and to specify the priority

level for the condition. Refer to Section 4 Exception Processing for a discussion on the

IPLB[2:0] levels.

Figure 3-14. Example Master Bus Wait State

C1 C2W C2 C1 C2

CLK

A1 A2MADDR

MRWB

MSIZ

MTT

MTM

MTSB

D2MWDATA

MWDATAOE

D1MRDATA

MIE

MTAB

MTEAB

READ WRITE

Master Bus Operation

3-26 ColdFire2/2M User’s Manual MOTOROLA

The status register of the ColdFire2/2M, described in Section 1.4.3.1 Status Register (SR),

contains an interrupt priority mask (IPLB[2:o]). The value in the interrupt mask is the highest

priority level that the ColdFire2/2M ignores. When an interrupt request has a priority higher

than the value in the mask, the ColdFire2/2M makes the request a pending interrupt.

IPLB[2:0] must maintain the interrupt request level until the ColdFire2/2M acknowledges the

interrupt to guarantee that the interrupt is recognized. The ColdFire2/2M continuously

samples IPLB[2:0] on consecutive rising edges of CLK. As a result, the IPLB[2:0] signals are

synchronous and must meet setup and hold times to CLK. If the external IPLB[2:0] signals

are asynchronous, flip-flops should be used to synchronize them before they drive the

IPLB[2:0] signals on the ColdFire2/2M.

The ColdFire2/2M takes an interrupt exception for a pending interrupt within one instruction

boundary after processing any other pending exception with a higher priority. Thus, the

ColdFire2/2M executes at least one instruction in an interrupt exception handler before

recognizing another interrupt request. The following paragraphs describe the two kinds of

interrupt acknowledge bus cycles that can be executed as part of interrupt exception

processing.

3.7.1 Interrupt Acknowledge Bus Cycle (Terminated Normally)

When the ColdFire2/2M processes an interrupt exception, it performs an interrupt

acknowledge bus cycle to obtain the vector number that contains the starting location of the

interrupt exception handler. Most interrupting devices have programmable vector registers

that contain the interrupt vectors for the exception handlers they use. Others may have fixed

vector numbers. The values driven on MADDR[31:0], MTT[1:0], and MTM[2:0] are

dependent on the interrupt acknowledge mode. The interrupt acknowledge mode is

statically determined by the connection of the 68K interrupt acknowledge mode enable

(IACK_68K) signal.

The interrupt acknowledge bus cycle is a read transfer. If the ColdFire2/2M is in the ColdFire

interrupt acknowledge mode (IACK_68K negated), it differs from a normal read cycle in the

following respects:

1. MTT[1:0]= $3 to indicate a acknowledge/CPU space bus cycle.

2. Address signals MADDR[31:5] are set to all ones ($3FFFFFF). The MADDR[4:2]

signals are set to the pending interrupt number, and the MADDR[1:0] signals are

driven low.

3. MTM[2:0] are set to the interrupt request level, the inverted values of IPLB[2:0]. This

will be nonzero for all interrupt acknowledge cycles.

If the ColdFire2/2M is in the 68K interrupt acknowledge mode (IACK_68K asserted), it differs

in the following respects:

1. MTT[1:0] = $0 to indicate a Acknowledge/CPU space bus cycle.

2. Address signals MADDR[31:4] are set to all ones ($7FFFFFF). The MADDR[3:1]

signals are set to the pending interrupt number, and the MADDR[0] signal is driven

high.

Master Bus Operation

MOTOROLA ColdFire2/2M User’s Manual 3-27

3. MTM[2:0] = $7 to indicate an interrupt acknowledge cycle.

The responding device places the vector number on MRDATA[31:24] during the interrupt

acknowledge bus cycle, and the cycle is terminated normally with MTAB. Figure 3-15

illustrates a flowchart diagram for an interrupt acknowledge cycle terminated with MTAB.

See Figure 3-16 for an example of a ColdFire mode (IACK_68K negated) interrupt

acknowledge cycle. The interrupt shown occurs during a normal master bus read cycle with

no lower-order interrupts pending.

Figure 3-15. Interrupt Acknowledge Bus Cycle Flowchart

1) RECOGNIZE PENDING INTERRUPT

2) WAIT FOR INSTRUCTION BOUNDARY

1) DRIVE APPROPRIATE VALUE ON

MADDR[31:0]

2) SET MRWB TO READ ($1)

3) SET MSIZ[1:0] TO BYTE ($1)

4) SET MTT[1:0] TO ACKNOWLEDGE

5) DRIVE V ALUE ON MTM[2:0]

6) ASSERT MTSB FOR ONE CLK CYCLE

1) LATCH VECTOR NUMBER

2) RECOGNIZE THE TRANSFER IS DONE

REQUEST INTERRUPT ON IPLB[2:0]

1) DECODE THE ADDRESS AND SELECT

THE INTERRUPTING SLAVE DEVICE.

2) INSERT NECESSARY WAIT-STATES.

3) REMOVE INTERRUPT ON IPLB[2:0]

1) DRIVE THE VECT OR NUMBER ON

MRDATA[31:24]

2) ASSERT MTAB FOR ONE CLK CYCLE.

3) ASSERT MIE FOR ONE CLK CYCLE.

MASTER SLAVE

Master Bus Operation

3-28 ColdFire2/2M User’s Manual MOTOROLA

Clock 1 (C1)

The interrupt acknowledge cycle starts in C1. During the first half of C1, the ColdFire2/2M

drives the master address bus (MADDR[31:5]) high, MADDR[1:0] low, the MTT[1:0] signals

to $3, and the MADDR[4:2] and MTM[2:0] signals to the interrupt level. The master read/

write (MRWB) signal is driven high for a read cycle, and the master size signals (MSIZ[1:0])

indicate transfer size (Byte = $1). The ColdFire2/2M asserts the master transfer start

(MTSB) signal during C1 to indicate the beginning of a bus cycle.

Figure 3-16. ColdFire Mode Interrupt Acknowledge Bus Cycle

C1 C2

CLK

IPLB

STACKMADDR[31:5]

INT LEVEL STACKMADDR[4:2]

STACKMADDR[1:0]

MRWB

$1MSIZ

$0MTT

INT LEVEL $5MTM

MTSB

MWDATA

MWDATAOE

VECMRDATA[31:24]

MRDATA[23:0]

MIE

MTAB

MTEAB

INT ACK STACK

Master Bus Operation

MOTOROLA ColdFire2/2M User’s Manual 3-29

Clock 2 (C2)

During the first half of C2, the ColdFire2/2M negates MTSB. The interrupting device uses

the MRWB and MSIZ signals to place the vector number on the high-order byte of the

master read data bus (MRDATA[31:24]) and assert the master input enable (MIE) signal.

Concurrently, the interrupting device asserts the master transfer acknowledge (MTAB)

signal. At the end of C2, the ColdFire2/2M samples the level of MTAB and latches the

current value on MRDATA[31:24]. If MTAB is asserted, the transfer terminates. If MTAB is

not asserted, the ColdFire2/2M ignores the data and inserts wait states instead of

terminating the transfer. The ColdFire2/2M continues to sample MTAB on successive rising

edges of CLK until it is asserted. The interrupting device negates the MIE and MTAB signals

in the first half of the next CLK cycle.

See Figure 3-17 for an example of a 68K mode (IACK_68K asserted) interrupt acknowledge

cycle. The interrupt is shown occurring during a normal master bus read cycle with no lower-

order interrupts pending.

Master Bus Operation

3-30 ColdFire2/2M User’s Manual MOTOROLA

Clock 1 (C1)

The interrupt acknowledge cycle starts in C1. During the first half of C1, the ColdFire2/2M

drives the master address bus (MADDR[31:4]), MADDR[0], and the MTM[2:0] signals high,

the MTT[1:0] signals low, and MADDR[3:1] to the interrupt level. The master read/write

(MRWB) signal is driven high for a read cycle, and the master size signals (MSIZ[1:0])

indicate transfer size (Byte = $1). The ColdFire2/2M asserts the master transfer start

(MTSB) signal during C1 to indicate the beginning of a bus cycle.

Figure 3-17. 68K Mode Interrupt Acknowledge Bus Cycle

C1 C2

CLK

IPLB

STACKMADDR[31:4]

INT LEVEL STACKMADDR[3:1]

STACKMADDR[0]

MRWB

$1MSIZ

$0MTT

INT LEVEL $5MTM

MTSB

MWDATA

MWDATAOE

VECMRDATA[31:24]

MRDATA[23:0]

MIE

MTAB

MTEAB

INT ACK STACK

Master Bus Operation

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