EDE5104ABSE-5C-E - Elpida Memory, Inc.

Document No. E0323E81 (Ver. 8.1)

Date Published September 2004 (K) Japan

URL: http://www.elpida.com

Elpida Mem o r y, Inc . 2002 -2 00 4

DATA SHEET

512M bits DDR2 SDRAM

EDE5104ABSE (128M words ×

××

× 4 bits)

EDE5108ABSE (64M words ×

××

× 8 bits)

EDE5116ABSE (32M words ×

××

× 16 bits)

Description

The EDE5104AB is a 512M bits DDR2 SDRAM

organized as 33,554,432 words × 4 bits × 4 banks.

The EDE5108AB is a 512M bits DDR2 SDRAM

organized as 16,777,216 words × 8 bits × 4 banks.

They are packaged in 64-ball FBGA (µBGA) package.

The EDE5116AB is a 512M bits DDR2 SDRAM

organized as 8,388,608 words × 16 bits × 4 banks.

It is packaged in 84-ball FBGA (µBGA) package.

Features

• 1.8V power supply

• Double-data-rate architecture: two data transfers per

clock cy cle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operatio n for each burs t acce ss

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• FBGA (µBGA) package with lead free solder

(Sn-Ag-Cu)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Ordering Information

Part number Mask

version Organization

(words × bits) Internal

Banks Speed bin

(CL-tRCD-tRP)

Package

EDE5104ABSE-5C-E

EDE5104ABSE-4A-E B 128M × 4 4 DDR2-533 (4-4-4)

DDR2-400 (3-3-3) 64-ball FBGA (µBGA)

EDE5108ABSE-5C-E

EDE5108ABSE-4A-E 64M × 8 DDR2-533 (4-4-4)

DDR2-400 (3-3-3)

EDE5116ABSE-5C-E

EDE5116ABSE-4A-E 32M × 16 DDR2-533 (4-4-4)

DDR2-400 (3-3-3) 84-ball FBGA (µBGA)

Part Number

Elpida Memory

Density / Bank

51: 512M /4 banks

Bit Organization

04: x4

08: x8

16: x16

Voltage, Interface

A: 1.8V, SSTL_18 Die Rev.

Package

SE: FBGA (µBGA with back cover)

Speed

5C: DDR2-533 (4-4-4)

4A: DDR2-400 (3-3-3)

Product Code

E: DDR2

Type

D: Monolithic Device

E D E 51 04 A B SE - 5C - E

Environment code

E: Lead Free

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Pin Configurations

/xxx indicates active low signal.

VDD

DQ6

(NC)*

VDDQ

DQ4

(NC)*

VDDL

VSS

VDD

NU/ /RDQS

(NC)*

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

DM/RDQS

(DM)*

VDDQ

DQ3

VSS

/WE

BA1

VSSQ

DQS

VDDQ

DQ2

VSSDL

/RAS

/CAS

A11

/DQS

VSSQ

DQ0

VSSQ

/CK

/CS

A13

VDDQ

DQ7

(NC)*

VDDQ

DQ5

(NC)*

VDD

VSS

(Top view)

64-ball FBGA (µBGA)

Note: ( )* marked pins are for ×4 organization.

ODT

(×8, ×4 organization)

VDD

VDDQ

VDD

VDDL

VSSQ UDMDQ14

DQ9

VSSQDQ12

VREF

VSSNC

VDDQ

DQ11

VSS

CKE /WE

VSS

VSSQ

UDQS

VDDQ

DQ10

VSSQ

/RAS

/UDQS

VSSQ DQ15

DQ8

VSSQ DQ13

/LDQS

/CK

RVDD A12 NC NC NC

VDDQ

DQ6

DQ4

VSSQ

DQ1VDDQ

VSSQ

LDM

VDDQ

DQ3

LDQS

VDDQ

VSSQ

DQ0 VDDQ

DQ2 VSSQ DQ5

DQ7

VDDQ

VSSDL CK VDD

VSS

A10

A11

VDD

VSS

(Top view)

84-ball FBGA (µBGA)

BA0 BA1 /CAS /CSNC

ODT

(×16 organization)

NC NC

NCNC

Pin name Function Pin name Function

A0 to A13 Address inputs ODT ODT control

BA0, BA1 Bank select VDD Supply vol tage for internal circuit

DQ0 to DQ15 Data input/output VSS Ground for internal ci rcuit

DQS, /DQS

UDQS, /UDQS

LDQS, /L D Q S Differential data strobe VDDQ Supply volt age for DQ circuit

RDQS, /RDQS Different i a l data strobe f or read VSSQ Ground for DQ circuit

/CS Chip select VREF Input reference vol tage

/RAS, /CAS, /WE Command input VDDL Supply voltage for DLL circuit

CKE Clock enable VSSDL Ground for DLL circuit

CK, /CK Differential clock input NC*1 No connection

DM, UDM, LDM W rite data mask NU*2 Not usable

Notes: 1. Not internally connected with die.

2. Don’t use other than reserved functions.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electric al Specificatio ns.................................................................................................................................5

Block Diagram .............................................................................................................................................15

Pin Function.................................................................................................................................................16

Command Operation ...................................................................................................................................18

Simplif ied Sta te D iagr am.............................................................................................................................25

Operation of DDR2 SDRAM........................................................................................................................26

Package Drawing ........................................................................................................................................62

Recommended Soldering Conditions..........................................................................................................64

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Rating Unit Note

Power supply volt age VDD −1.0 to +2.3 V 1

Power supply voltage for output VDDQ −0.5 to +2 .3 V 1

Input volt age VIN −0.5 to +2 .3 V 1

Output voltage VOUT −0.5 to +2 .3 V 1

Storage temperature Tstg −55 to +100 °C 1, 2

Power dissipation PD 1.0 W 1

Short circuit output current IOUT 50 mA 1

Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage temperature is the case surface temperature on the center/top side of the DRAM.

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Operating Temperature Condition

Parameter Symbol Rating Unit Note

Operating case temperat ure TC 0 to +85 °C 1, 2

Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.

2. The operation temperature range is the temperature where all DRAM specification will be supported. Out

side of this temperature range, even it is still within the limit of stress condition, some deviation on portion

of operation specification may be required.

During operation, the DRAM case temperature must be maintained between 0 to +85°C under all other

specificat ion para met ers.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Recommended DC Operating Conditions (SSTL_18)

Parameter Symbol min. typ. max. Unit Notes

Supply volt age VDD 1.7 1.8 1.9 V 4

Supply voltage for out put VDDQ 1.7 1.8 1.9 V 4

Input reference vol t age VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V 1, 2

Termination voltage VTT V RE F − 0.04 VREF VREF + 0.04 V 3

DC input logic high VIH (DC) VREF + 0.125  VDDQ + 0.3V V

DC input low VIL (DC) −0.3  VREF – 0.125 V

AC input logic high VIH (AC) VREF + 0.250   V

AC input low VIL (AC)   VREF − 0.250 V

Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected

to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and

VDDL tied together.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

DC Characteristics 1 (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

max.

Parameter Symbol Grade × 4 × 8 × 16 Unit Test c onditi on

Operating current

(ACT-PRE) IDD0 -5C

-4A 105

90 110

95 155

140 mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD ) ;

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE) IDD1 -5C

-4A 120

105 125

110 170

155 mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-

down standby current IDD2P -5C

-4A 10

8 10

8 mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus in puts are STABLE;

Data bus inputs are FLOATING

Precharge quiet

standby current IDD2Q -5C

-4A 25

20 25

20 mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus in puts are STABLE;

Data bus inputs are FLOATING

Idle standby current IDD2N -5C

-4A 30

25 30

25 mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus i nputs are SW ITCHING;

Data bus inputs are SWITCHING

IDD3P-F -5C

-4A 40

35 40

35 mA Fast PDN Exit

MRS(12) = 0

Active power-down

standby current IDD3P-S -5C

-4A 25

20 25

20 mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address bus

inputs are STABLE;

Data bus inputs are FLOATING Slow PDN Exit

MRS(12) = 1

Active standby

current IDD3N -5C

-4A 65

60 65

60 85

75 mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus i nputs are SW ITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operati ng) IDD4R -5C

-4A 170

140 190

150 240

200 mA

all banks open, conti nuous burst reads, IOUT = 0m A;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write

operating) IDD4W -5C

-4A 170

140 190

150 240

200 mA

all banks open, conti nuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

max.

Parameter Symbol Grade × 4 × 8 × 16 Unit Test c onditi on

Auto-refresh current IDD5 -5C

-4A 250

230 250

230 mA

tCK = tCK (IDD);

Refresh comm and at every tRFC (IDD) int erval ;

CKE is H, /CS is H between valid commands;

Other control and address bus i nputs are SW ITCHING;

Data bus inputs are SWITCHING

Self-refresh current IDD6 6 6 6 mA

Self Refresh Mode;

CK and /CK at 0V;

CKE ≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving) IDD7 -5C

-4A 300

280 320

300 500

480 mA

all bank interl eavi ng reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),

tRCD = 1 × tCK (IDD);

CKE is H, CS is H between valid commands;

Address bus inputs are STAB LE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD

values must be met with all combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN ≤ VIL (AC) (max.)

H is de fined as VIN ≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-533 DDR2-400

Parameter 4-4-4 3-3-3 Unit

CL(IDD) 4 3 tCK

tRCD(IDD) 15 15 ns

tRC(IDD) 55 55 ns

tRRD(IDD)-×4/×8 7.5 7.5 ns

tRRD(IDD)- ×16 10 10 ns

tCK(IDD) 3.75 5 ns

tRAS(min.)(IDD) 40 40 ns

tRAS(max.)(IDD) 70000 70000 ns

tRP(IDD) 15 15 ns

tRFC(IDD) 105 105 ns

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

DC Characteristics 2 (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

Parameter Symbol Value Unit Notes

Input leakage current ILI 2 µA VDD ≥ VIN ≥ VSS

Output leakage current ILO 5 µA VDDQ ≥ VOUT ≥ VSS

Minimum required out put pull -up under AC

test load VOH VTT + 0.603 V 5

Maximum required output pull-down under

AC test load VOL VTT − 0.603 V 5

Output timing measurement reference level VOTR 0.5 × VDDQ V 1

Output minimu m sink DC current IOL +13.4 mA 3, 4, 5

Output minimu m source DC current IOH −13.4 mA 2, 4, 5

Notes: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.7V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

5. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V.

DC Characteristics 3 (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

Parameter Symbol min. max. Unit Note

AC differenti al input voltage VID (AC) 0.5 VDDQ + 0.6 V 1, 2

AC differenti al c ross poi nt voltage VIX (AC) 0.5 × VDDQ − 0.175 0.5 × VDDQ + 0.175 V 2

AC differenti al c ross poi nt voltage VOX (AC) 0.5 × VDDQ − 0.125 0.5 × VDDQ + 0.125 V 3

Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true

input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as

/CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) − VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX(AC)

is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals

must cross.

3. The typical value of VOX(AC) is expected to be about 0.5 × VDDQ of the transmitting device and

VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential

output signals must cross.

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

VDDQ

Differential Signal Levels*1, 2

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

ODT DC Electrical Characteristics (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

Parameter Symbol min. typ. max. Unit Note

Rtt effective impedance value for EMRS (A6 , A2) = 0, 1; 75 Ω Rtt1(eff) 60 75 90 Ω 1

Rtt effective impedance value for EMRS (A6 , A2) = 1, 0; 150 Ω Rtt2(eff) 120 150 180 Ω 1

Deviation of VM with respect to VDDQ/2 ∆VM −3.75  +3.75 % 1

Note: 1. Test condition for Rtt measurements.

Measurement Definition for Rtt(eff)

Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.

VIH(AC), and VDDQ values defined in SSTL_18.

VIH(AC) − VIL(A C)

I(VIH(AC)) − I(VIL(AC))

Rtt(eff) =

Measurement Definition for ∆

∆∆

∆VM

Measure voltage (VM) at test pin (midpoint) with no load.

2 × VM

VDDQ

∆VM = × 100%

− 1

OCD Default Characteristics (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

Parameter min. typ. max. Unit Notes

Output impedance 12.6 18 23.4 Ω 1

Pull-up and pull -down mismatch 0  4 Ω 1, 2

Output slew rate 1.5  4.5 V/ns 3, 4

Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.

Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;

VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.

2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and

voltage.

3. Slew rate measured from VIL(AC) to VIH(AC).

4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate

as measured from AC to AC. This is guaranteed by design and characterization.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Pin Capacitance (TA = 25°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V)

Parameter Symbol Pins min. max. Unit Notes

CLK input pin capacitance CCK CK , /CK 1.0 2.0 pF 1

Input pin capacitanc e CIN

/RAS, /C AS,

/WE, /CS,

CKE, ODT,

Address

1.0 2.0 pF 1

Input/output pi n capacitanc e CI/O

DQ, DQS, /DQS,

UDQS, /UDQS,

LDQS, /LDQS,

RDQS, /RDQS,

DM, UDM, LDM

3.0 4.0 pF 2

Notes: 1. M atching within 0.25pF.

2. Matching within 0.50pF.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

AC Characteristics (TC = 0 to +85°

°°

°C, VDD, VDDQ = 1.8V ±

±±

± 0.1V, VSS, VSSQ = 0V)

-5C -4A

Frequency (Mbps) 533 400

Parameter Symbol min. max. min. max. Unit Notes

/CAS late ncy CL 4 5 3 5 tCK

Active t o read or write command delay tRCD 15  15  ns

Precharge command period tRP 15  15  ns

Active t o active/auto refresh command

time tRC 55  55  ns

DQ output access t ime from CK, /CK tAC −500 +500 −600 +600 ps

DQS output access time from CK, /CK tDQSCK −450 +450 −500 +500 ps

CK high-level width tCH 0. 45 0.55 0.45 0.55 tCK

CK low-level width t CL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min.

(tCL, tCH)  min.

(tCL, tCH)  ps

Clock cycle time tCK 3750 8000 5000 8000 ps

DQ and DM input hold time tDH 225  275  ps 5

DQ and DM input setup time tDS 100  150  ps 4

Control and Address input pulse widt h

for each input tIPW 0.6  0.6  tCK

DQ and DM input pulse width for each

input tDIPW 0.35  0.35  tCK

Data-out high-impedance time from

CK,/C K tHZ  tAC ma x.  tAC ma x. ps

Data-out low-im pedance tim e from

CK,/C K tLZ tAC min. tAC max. tAC min. tAC max. ps

DQS-DQ skew for DQS and associated

DQ signals tDQSQ  300  350 ps

DQ hold skew factor tQHS  400  450 ps

DQ/DQS output hold time from DQS tQH tHP – tQHS  tHP – tQHS  ps

Write command to first DQS latching

transition tDQSS WL − 0.25 WL + 0.25 WL − 0.25 WL + 0.25 tCK

DQS input high pulse width tDQSH 0.35  0.35  tCK

DQS input low pulse width tDQSL 0.35  0.35  tCK

DQS falling edge to CK setup time tDS S 0.2  0.2  tCK

DQS falling edge hold time from CK tDSH 0.2  0.2  tCK

Mode register set command cycle time tMRD 2  2  tCK

Write preamble setup time tWPRES 0  0  tCK

Write postambl e tWPST 0.4 0.6 0. 4 0.6 tCK

Write preamble tWPRE 0.25  0.25  tCK

Address and control input hold time t IH 375  475  ps 5

Address and control input setup time tIS 250  350  ps 4

Read preamble tRPRE 0.9 1.1 0. 9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Active to precharge command tRAS 40 70000 40 70000 ns

Active t o auto-prec harge del ay tRAP tRCD min.  tRCD min .  ns

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

-5C -4A

Frequency (Mbps) 533 400

Parameter Symbol min. max. min. max. Unit Notes

Active bank A t o active bank B

command period

(EDE5104AB, EDE5108AB) t RRD 7.5  7.5  ns

(EDE5116AB) tRRD 10  10  ns

W rite recovery t ime tWR 15  15  ns

Auto precharge write recovery +

precharge tim e tDAL (tWR/tCK)+

(tRP/tCK)  (tWR/tCK)+

(tRP/tCK)  tCK 1

Internal write t o read command delay tWTR 7. 5  10  ns

Internal read to prec harge command

delay tRTP 7.5  7.5  ns

Exit self refresh to a non-read command tXS NR tRFC + 10  tRFC + 10  ns

Exit self refresh to a read command tXSRD 200  200  tCK

Exit precharge power down to any non-

read command tXP 2  2  tCK

Exit active power down to read

command tXARD 2  2  tCK 3

Exit active power down to read

command

(slow exit/low power mode) tXARDS 6 − AL  6 − AL  tCK 2, 3

CKE minimum pulse width (high and

low pulse width) tCKE 3  3  tCK

Output impedance test driver delay tOI T 0 12 0 12 ns

Auto refresh to acti ve/auto refresh

command time tRFC 105  105  ns

Average periodic refresh interval tREFI  7.8  7.8 µs

Minimum time clocks remains ON after

CKE asynchronously drops low tDELAY tIS + tCK + tIH  tIS + tCK + tIH  ns

Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.

2. AL: Additive Latency.

3. MRS A12 bit defines which active power down exit timing to be applied.

4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the

VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.

5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the

VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.

DQS

/DQS

tDS tDH tDS tDH VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

/CK

tIS tIH tIS tIH VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

Input Waveform Timing 1 (tDS, tDH) Input Waveform Timing 2 (tIS, tIH)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

ODT AC Electrical Characteristics

Parameter Symbol min. max. Unit Notes

ODT turn-on delay tAOND 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max) + 1000 ps 1

ODT turn-on (power down mode) t A ONPD tA C(m i n) + 2000 2tCK + tAC(max) + 1000 ps

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max) + 600 ps 2

ODT turn-off (power down mode) t AOFPD tA C(m in) + 2000 2.5t CK + tAC(max) + 1000 ps

ODT to power down entry latency tANP D 3 3 t CK

ODT power down exit latency tAXPD 8 8 tCK

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

AC Input Test Conditions

Parameter Symbol Value Unit Notes

Input reference vol tage VREF 0.5 × VDDQ V 1

Input signal maximum peak to peak swing VSWING(max.) 1.0 V 1

Input signal maximum slew rate SLE W 1.0 V/ns 2, 3

Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the

device under test.

2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)

(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in

the below figure.

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive

transitions and VIH(AC) to VIL(AC) on the negative transitions.

VSWING(max.)

∆TR

∆TF

Start of falling edge input timing Start of rising edge input timing

VIH (DC)(min.)

−

VIL (AC)(max.)

∆TF

Falling slew =

VDDQ

VIH (AC)(min.)

VIH (DC)(min.)

VIL (DC)(max.)

VIL (AC)(max.)

VSS

VREF

VIH (AC) min.

−

VIL (DC)(max.)

∆TR

Rising slew =

AC Input Test Signal Wave forms

VTT

Measurement point

DQ RT =25 Ω

Output Load

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Block Diagram

A0 to A13, BA0, BA1

/CS

/RAS

/CAS

/WE

Command decoder

Input & Output buffer

Latch circuit

Data control circuit

Column decoder

Row decoder

Memory cell array

Bank 0

Sense amp.

Bank 1

Bank 2

Bank 3

Control logic

Column

address

buffer

and

burst

counter

Row

address

buffer

and

refresh

counter

Mode

Clock

generator

/CK

CKE

DQS, /DQS

DLLCK, /CK RDQS, /RDQS

ODT

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Pin Function

CK, /CK (input pins)

CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of cros sin g).

/CS (input pin)

All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with

multiple ranks. /CS is considered part of the command code.

/RAS, /CAS, /WE (input pins)

/RAS, /CAS and /WE (along with /CS) define the command being entered.

A0 to A13 (input pins)

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the respective bank. The address inputs also provide

the op-code during mode register set commands.

[Address Pins Table]

Address (A0 to A13)

Part number Row address Column address Note

EDE5104AB AX0 to AX 13 AY0 to AY9, AY11

EDE5108AB AX0 to AX 13 AY0 to AY9

EDE5116AB AX0 to AX 12 AY0 to AY9 1

Note: 1. A13 pin is NC for ×16 organization.

A10 (AP) (input pin)

A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)

or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1.

BA0, BA1 (input pins)

BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also

determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-

refresh.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

DM, UDM and LDM (input pins)

DM is an input mask signal for write data. In 32M × 16 products, UDM and LDM control upper byte (DQ8 to DQ15)

and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled high coincident with that input data during

a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches

the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by

EMRS.

DQ (input/output pins)

Bi-directional data bus.

DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins)

Output with read data, input with write data for source synchronous operation. In 32M × 16 products, UDQS, /UDQS

and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data,

centered in write data. Used to capture write data. /DQS can be disabled by EMRS.

RDQS, /RDQS (output pins)

Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins

exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS.

ODT (input pins)

ODT ( On Die Termination control) is a registered high signal that enables termination resistance internal to the DDR

II SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, R DQS, /RDQS, and DM signal for × 4, × 8

configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM

signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.

VDD, VSS, VDDQ, VSSQ (power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

VDDL and VSSDL (power supply)

VDDL and VSSDL are power supply pins for DLL circuits.

VREF (Power supply)

SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Command Operation

Command Truth Table

The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Function

Symbol Previous

cycle Current

cycle

/CS

/RAS

/CAS

/WE BA1,

BA0 A13 to

A11

A10 A0 to

Notes

Mode register set MRS H H L L L L BA 0 = 0 and MRS OP Code 1

Extended mode regist er set EMRS H H L L L L B A 0 = 1 and EMRS OP Code 1

Auto refresh REF H H L L L H × × × × 1

Self refres h entry SE LF H L L L L H × × × × 1

Self refresh exit SELFX L H H × × × × × × × 1, 6

L H L H H H × × × ×

Single bank precharge P RE H H L L H L BA × L × 1, 2

Precharge all banks PALL H H L L H L × × H × 1

Bank activate ACT H H L L H H BA Row Address 1, 2

Write WRIT H H L H L L BA Column L Column 1, 2, 3

Write with auto precharge WRITA H H L H L L BA Column H Column 1, 2, 3

Read READ H H L H L H BA Column L Column 1, 2, 3

Read with auto precharge RE A DA H H L H L H BA Column H Column 1, 2, 3

No operation NOP H × L H H H × × × × 1

Device des el ect DESL H × H × × × × × × × 1

Power down mode entry PDEN H L H × × × × × × × 1, 4

H L L H H H × × × ×

Power down mode exit P DE X L H H × × × × × × × 1, 4

L H L H H H × × × ×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the

clock.

2. Bank select (BA0, BA1), determine which bank is to be operated upon.

3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in

burst read command [R EAD] or ″Writes interrupted by a Write″ in burst write command [WRIT].

4. The power down mode does not perform any refresh operations. The duration of power down is therefore

limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.

5. The state of ODT does not affect the states described in this table. The ODT function is not available

during self-refresh.

6. Self refresh exit is asynchronous.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

CKE Truth Table

CKE

Current st ate*2 Previous

cycle (n-1)*1 Current

cycle (n)*1 Command(n)*3

/CS, /R AS, /CAS, / WE Opera tio n (n ) *3

Notes

Power down L L × Maintain power down 11, 13, 15

L H DESL or NOP Power down exit 4, 8, 11, 13

Self refresh L L × Maintain s elf refresh 11, 15

L H DESL or NOP Self refresh exit 4, 5, 9

Bank Acti ve H L DESL or NOP Acti ve power down entry 4, 8, 10, 11, 13

All banks idle H L DESL or NOP Precharge power down entry 4, 8, 10, 11, 13

H L SELF Self refresh entry 6, 9, 11, 13

Any stat e other than

listed above H H Refer to the Command Truth Table 7

Remark: H = VIH. L = VIL. × = Don’t care

Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) was the state of CKE at the previous clock

edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n).

4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this

document.

5. On self refresh exit, [DESL] or [NOP] commands must be issued on every clock edge occurring during the

tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6. Self refresh mode can only be entered from the all banks idle state.

7. Must be a legal command as defined in the command truth table.

8. Valid commands for power down entry and exit are [NOP] and [DESL] only.

9. Valid commands for self refresh exit are [NOP] and [DESL] only.

10. Power down and self-refresh can not be entered while read or write operations, (extended) mode register

set operations or precharge operations are in progress. See section Power Down and Self Refresh

Command for a detailed list of restrictions.

11. Minimum CKE high time is 3 clocks; minimum CKE low time is 3 clocks.

12. The state of ODT does not affect the states described in this table. The ODT function is not available

during self-refresh. See section ODT (On Die Termination).

13. The power down does not perform any refresh operations. The duration of power down mode is therefore

limited by the refresh requirements outlined in section automatic refresh command.

14. CKE must be maintained high while the SDRAM is in OCD calibration mode.

15. “×” means “don’t care” (including floating around VREF) in self refresh and power down. However ODT

must be driven high or low in power down if the ODT function is enabled (bit A2 or A6 set to “1” in

EMRS(1) ).

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current st ate / CS /RAS /CAS /WE Address Command Operation Not e s

Idle H × × × × DESL Nop or Power down

L H H H × NOP Nop or Power down

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT Row activating

L L H L BA, A10 (AP) PRE Precharge

L L H L A10 (AP) PALL Precharge all banks

L L L H × REF Auto refresh 2

L L L H × SELF Self refresh 2

L L L L BA, MRS-OPCOD E MRS Mode register accessing 2

L L L L BA, EMRS-OPCODE EMRS Extended mode register access i ng 2

Bank(s) active H × × × × DESL Nop

L H H H × NOP Nop

L H L H BA, CA, A10 (AP) READ Begin Read

L H L H BA, CA, A10 (AP) READA Begin Read

L H L L BA, CA, A10 (AP) WRIT Begin Write

L H L L BA, CA, A10 (AP) WRITA Begin Write

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE Precharge

L L H L A10 (AP) PALL Precharge all banks

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Read H × × × × DESL Continue burst to end -> Row active

L H H H × NOP Continue burst to end -> Row active

L H L H BA, CA, A10 (AP) READ Burst interrupt 1, 4

L H L H BA, CA, A10 (AP) READA Burst interrupt 1, 4

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Current st ate /CS /RAS /CAS /WE Address Command Operat i on Note

Write H × × × × DESL Continue burst to end

-> Write recovering

L H H H × NOP Continue burst to end

-> Write recovering

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT Burst interrupt 1, 4

L H L L BA, CA, A10 (AP) WRITA Burst interrupt 1, 4

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Read with H × × × × DESL Continue burst to end -> Precharging

auto precharge L H H H × NOP Continue burst to end -> Precharging

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Write with auto

Precharge H × × × × DESL Continue burst to end

->Writ e recoveri ng with auto precharge

L H H H × NOP Continue burst to end

->Writ e recoveri ng with auto precharge

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Current st ate /CS /RAS /CAS /WE Address Command Operation Note

Precharging H × × × × DESL Nop -> Enter idle after tRP

L H H H × NOP Nop -> Enter idle after tRP

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE Nop -> Enter idle after tRP

L L H L A10 (AP) PALL Nop -> Enter idle after tRP

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Row activating H × × × × DE S L Nop -> Enter bank active afte r t RCD

L H H H × NOP Nop -> Enter bank active after t RCD

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Write recoveri ng H × × × × DESL Nop -> Enter bank active aft er tWR

L H H H × NOP Nop -> Enter bank active after tWR

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT New write

L H L L BA, CA, A10 (AP) WRITA New write

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Current st ate / CS /RAS /CAS /WE Address Command Operation Note

Write recoveri ng

with H × × × × DES L Nop -> Enter bank active after tWR

auto precharge L H H H × NOP Nop -> Enter bank active after tWR

L H L H BA, CA, A10 (AP) READ ILLEGAL 1

L H L H BA, CA, A10 (AP) READA ILLEGAL 1

L H L L BA, CA, A10 (AP) WRIT ILLEGAL 1

L H L L BA, CA, A10 (AP) WRITA ILLEGAL 1

L L H H BA, RA ACT ILLEGAL 1

L L H L BA, A10 (AP) PRE ILLEGAL 1

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Refresh H × × × × DESL Nop -> Enter idle after tRFC

L H H H × NOP Nop -> Enter idle after tRFC

L H L H BA, CA, A10 (AP) READ ILLEGAL

L H L H BA, CA, A10 (AP) READA ILLEGAL

L H L L BA, CA, A10 (AP) WRIT ILLEGAL

L H L L BA, CA, A10 (AP) WRITA ILLEGAL

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10 (AP) PRE ILLEGAL

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Mode register

accessing H × × × × DESL Nop -> Enter idle after tMRD

L H H H × NOP Nop -> Enter idle after tMRD

L H L H BA, CA, A10 (AP) READ ILLEGAL

L H L H BA, CA, A10 (AP) READA ILLEGAL

L H L L BA, CA, A10 (AP) WRIT ILLEGAL

L H L L BA, CA, A10 (AP) WRITA ILLEGAL

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10 (AP) PRE ILLEGAL

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Current st ate / CS /RAS /CAS /WE Address Command Operation Note

Extended Mode H × × × × DESL Nop -> Enter idle after tMRD

L H L H BA, CA, A10 (AP) READ ILLEGAL

L H L H BA, CA, A10 (AP) READA ILLEGAL

L H L L BA, CA, A10 (AP) WRIT ILLEGAL

L H L L BA, CA, A10 (AP) WRITA ILLEGAL

L L H H BA, RA ACT ILLEGAL

L L H L BA, A10 (AP) PRE ILLEGAL

L L H L A10 (AP) PALL ILLEGAL

L L L H × REF ILLEGAL

L L L H × SELF ILLEGAL

L L L L BA, MRS-OPCOD E MRS ILLEGAL

L L L L BA, EMRS-OPCODE EMRS ILLEGAL

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. This command may be issued for other banks, depending on the state of the banks.

2. All banks must be in "IDLE".

3. All AC timing specs must be met.

4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Simplified Stat e Diagr am

INITALIZATION AUTO REFRESH SELF REFRESH

MRS

EMRS

tRFC

tRCD

tMRD

tRP

MRS

PRE

REF

ACT

IDLE

ACTIVATING

PRECHARGE

BANK ACTIVE

WL + BL/2 + tWR

WRITA

RL + tRTP

READA

WRITE

WRITA

READA

WRIT

READ

CKEH

CKEL

CKEH

PDEN

CKEL

PDEN

PRECHARGE

POWER

DOWN

CKEL

SELFX

SELF

PRE

READA

ACTIVE

POWER

DOWN Automatic sequence

Command sequence

READ

Simplified State Diagram

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Operation of DDR2 SDRAM

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue

for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of an

active command, which is then followed by a read or write command. The address bits registered coincident with

the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A13 select

the row). The address bits registered coincident with the read or write command are used to select the starting

column location for the burst access and to determine if the auto precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sec tions provide detailed information

covering device initialization; register definition, command descriptions and device operation.

Power On and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation.

Power-Up and Initialization Sequence

The following sequence is required for power up and initialization.

1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT *1 at a low state (all other inputs may be

undefined.)

 VDD, VDDL and VDDQ are driven from a single power converter output, AND

 VTT is limited to 0.95V max, AND

 VREF tracks VDDQ/2.

 Apply VDD before or at the same time as VDDL.

 Apply VDDL before or at the same time as VDDQ.

 Apply VDDQ before or at the same time as VTT and VREF.

at least one of these two sets of conditions must be met.

2. Start clock and maintain stable condition.

3. For the minimum of 200µs after stable power and clock(CK, /CK), then apply [NOP] or [DESL] and take CKE

high.

4. W ait minimum of 400ns then issue precharge all command. [NOP] or [DESL] applied during 400ns period.

5. Issue EMRS(2) command. (To issue EMRS(2) command, provide low to BA0, high to BA1.)

6. Issue EMRS(3) command. (To issue EMRS(3) command, high to BA0 and BA1.)

7. Issue EMRS to enable DLL. (To issue DLL enable command, provide low to A0, high to BA0 and low to BA1 and

A13.)

8. Issue a mode register set command for DLL reset.

(To issue DLL reset command, provide high to A8 and low to BA0, BA1, and A13 to A15.)

9. Issue precharge all command.

10. Issue 2 or more auto-refresh commands.

11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating

parameters without resetting the DLL.)

12. At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment). If OCD

calibration is not used, EMRS OCD default command (A9 = A8 = A7 = 1) followed by EMRS OCD calibration

mode exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS.

13. The DDR2 SDRAM is now ready for normal operation.

Note: 1. To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

Command EMRS

PALL MRS

tRP

400ns tMRD

200 cycles (min)

tMRD

tMRD tRP tRFC tRFC

PALL MRS

REF REF EMRS

DLL enable DLL reset

Follow OCD

Flowchart

Any

command

/CK

CKE

EMRS

OCD calibration mode

exit

tOIT

OCD default

NOP

tCH tCL

tIS

Power up and Initialization Sequence

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Programming the Mode Register and Extended Mode Registers

For application flexibility, burst length, burst type, /CAS latency, DLL reset function, write recovery time(tWR)

are user defined variables and must be programmed with a mode register set command [MRS]. Additionally, DLL

disable function, driver impedance, additive /CAS latency, ODT(On Die Termination), single-ended strobe, and OCD

(Off-Chip Driver Impedance Adjustment) are also user defined variables and must be programmed with an extended

mode register set command [EMRS]. Contents of the Mode Register (MR) or Extended Mode Registers (EMR(#))

can be altered by reexecuting the MRS and EMRS commands. If the user chooses to modify only a subset of the

MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be

executed any time after power-up without affecting array contents.

DDR2 SDRAM Mode Register Set [MRS]

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls /CAS

latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2

SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode

/RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins A0 to A13.

The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register.

The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register.

The mode register contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in the precharge state. The mode register is divided into various fields depending

on functionality. Burst length is defined by A0 to A2 with options of 4 and 8 bit burst lengths. The burst length

dec odes are co mpatibl e with DDR SDRAM. B urst add ress se quence typ e is define d by A3, /C AS latenc y is defined

by A4 to A6. The DDR2 doesn’t support half clock latency mode. A7 is use d for test mode. A8 is used for DLL reset.

A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 to A11. Refer to the

table for specific codes.

Notes: 1. BA1 and A13 are reserved for future use and must be programmed to 0 when setting the mode register.

2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.).

WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR [cycles] = tWR (ns) / tCK (ns)).

The mode register must be programmed to this value. This is also used with tRP to determine tDAL.

0PD

BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field

BA1

DLL reset

Yes

DLL TM /CAS latency BT Burst length Mode register

Mode

Normal

Test

/CAS latency

Latency

Reserved

Burst type

Sequential

Interleave

A12

Active power down exit timing

Fast exit (use tXARD timing)

Slow exit (use tXARDS timing)

Burst length

A11

Write recovery for autoprecharge

A10

Reserved

BA1

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

BA0

DDR400

DDR533

Mode Register Set (MRS)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

DDR2 SDRAM Extended Mode Registers Set [EMRS]

EMRS(1) Programming

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive

latency, ODT, /DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is

not defined, therefore the extended mode register(1) must be written after power-up for proper operation. The

extended mode register(1) is written by asserting low on /CS, /RAS, /CAS, /W E, high on BA0 and low on BA1, while

controlling the states of address pins A0 to A13. The DDR2 SDRAM should be in all bank precharge with CKE

already high prior to writing into the extended mode register(1). The mode register set command cycle time (tMRD)

must be satisfied to complete the write operation to the extended mode register(1). Mode register contents can be

changed using the same command and clock cycle requirements during normal operation as long as all banks are in

the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3

to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for /DQS disable and A11 is

used for RDQS enable. A2 and A6 are used for ODT setting.

Notes: 1. A13 are reserved for future use, and must be programmed to 0 when setting the extended mode register.

2 When adjust mode is issued, AL from previously set value must be applied.

3. After setting to default, OCD mode needs to be exited by setting A9 to A7 to 000.

Refer to the chapter Off-Chip Driver (OCD)Impedance Adjustment for detailed information.

A13BA0BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field

A11

RDQS enable

Disable

Enable

10 0*

/DQS

OCD program Rtt Additive latency Rtt D.I.C DLL Extended mode register

A10

/DQS enable

Enable

Disable

Additive latency

Latency

Reserved

DLL enable

Enable

Disable

BA1

MRS mode

MRS

EMRS(1)

EMRS(2): Reserved

EMRS(3): Reserved

Rtt (nominal )

ODT Disabled

150

Reserved

Driver impedance adjustment

OCD calibration mode exit

Drive(1)

Drive(0)

Adjust mode*

OCD Calibration default*

Driver strength control

Output driver

impedance control

Normal

Weak

Driver

size

100%

60%

A11

(RDQS enable)

A10

(/DQS enable)

0 (Enable)

1 (Disable)

0 (Enable)

1 (Disable)

RDQS/DM

RDQS

/RDQS

High-Z

/RDQS

High-Z

DQS

/DQS

High-Z

/DQS

High-Z

Operation

RDQS

Qoff

BA0

A12

Qoff

Output buffers enabled

Output buffers disabled

Strobe function matrix

EMRS(1)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self-

refresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

EMRS(2) Programming: Reserved*1

Note : 1. EMRS(2) is reserved for future use and all bits except BA0 and BA1 must be programmed

to 0 when setting the mode register during initialization.

Address field

Extended mode register (2)

A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

BA1 BA0 A12

EMRS(2)

EMRS(3) Programming: Reserved*1

Extended Mode Register(3)

Address Field

A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1 BA0 A12

Note : 1. EMRS (3) is reserved for future use and all bits except BA0 and BA1 must be programmed

to 0 when setting the mode register during initialization.

EMRS(3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Off-Chip Driver (OCD) Impedance Adjustment

DDR2 SDRAM supports driver calibration feature and the OCD Flow Chart is an example of sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be

carefully controlled depending on system environment.

Test Test

ALL OK ALL OK

Need calibration Need calibration

EMRS: OCD calibration mode exit

MRS should be set before entering OCD impedance adjustment and ODT should

be carefully controlled depending on system environment

EMRS: Drive(0)

DQ & DQS low ; /DQS high

EMRS: Drive(1)

DQ & DQS high ; /DQS low

EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

Start

End

OCD Flow Chart

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Extended Mode Register Set for OCD Impedance Adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out

by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive(1) mode, all

DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive(0) mode, all DQ, DQS

(and RDQS) signals are driven low and all /DQS signals are driven high.

In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver

characteristics follow approximate nominal V/I curve for 18Ω output drivers, but are not guaranteed. If tighter control

is required, which is controlled within 18Ω ± 3Ω driver impedance range, OCD must be used.

[OCD Mode Set Program]

A9 A8 A7 Operation

0 0 0 OCD calibration mode exit

0 0 1 Drive (1) DQ, DQS, (RDQS) high and /DQS low

0 1 0 Drive (0) DQ, DQS, (RDQS) low and /DQS high

1 0 0 Adjust mode

1 1 1 OCD calibration default

OCD Impedance Adjustment

To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code

to DDR2 SDRAM as in OCD Adjustm ent Program table. For this operation, burst length has to be set to BL = 4 via

MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in

OCD Adjustment Program table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output

impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given

DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16

and when the limit is reached, further increment or decrement code has no effect. The default setting may be any

step within the 16-step range.

[OCD Adjustment Program]

4bits burst data inputs to all DQs Operation

DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strengt h

0 0 0 0 NOP NOP

0 0 0 1 Increase by 1 step NOP

0 0 1 0 Decrease by 1 step NOP

0 1 0 0 NOP Increase by 1 step

1 0 0 0 NOP Decrease by 1 step

0 1 0 1 Increas e by 1 step Increas e by 1 step

0 1 1 0 Decrease by 1 step Increase by 1 step

1 0 0 1 Increas e by 1 step Decreas e by 1 step

1 0 1 0 Decrease by 1 step Dec rease by 1 step

Other combinati ons Reserved

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

For proper operation of adjust mode, W L = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the Output

Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not

affected by MRS addressing mode (i.e. sequential or interleave).

Command EMRS

OCD adjust mode OCD calibration mode exit

NOP

DT0

tDS tDH

DT1 DT2 DT3

NOPEMRS

/CK

WL tWR

DQS, /DQS

DQ_in

Output Impedance Control Register Set Cycle

Drive Mode

Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver i mpedance before

OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all

output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance

Measurement/Verify Cycle”.

Command

Enter drivemode OCD Calibration mode exit

NOP

/CK

DQS, /DQS High-Z High-Z

DQs high for drive (1)

DQs low for drive (0)

tOIT

EMRS EMRS

tOIT

DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0)

Output Impedance Measurement/Verify Cycle

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

ODT(On Die Termination)

On Die Termination (ODT), is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS,

/DQS, RDQS, /RDQS, and DM signal for × 4 × 8 configurations via the ODT control pin. For × 16 configuration ODT

is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal via the ODT control pin. The ODT

feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to

independently turn on/off termination resistance for any or all DRAM devices.

The ODT function is turned off and not supported in self-refresh mode.

Switch sw1 or sw2 is enabled by ODT pin.

Selection between sw1 or sw2 is determined by Rtt (nominal) in EMRS

Termination included on all DQs, DM, DQS, /DQS, RDQS and /RDQS pins.

Target Rtt (

) = (Rval1) / 2 or (Rval2) / 2

DRAM

input

buffer

VDDQ

VSSQ

sw1

sw1 sw2

Rval1

Input

VDDQ

VSSQ

sw2

Rval2

Functional Representation of ODT

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

/CK T0 T1 T2 T3 T4 T5 T6

ODT

CKE

Internal

Term Res. Rtt

tIS tIS

tAOND tAOFD

tAON max.

tAON min. tAOF min. tAOF max.

tAXPD ≤ 6tCK

ODT Timing for Active and Standby Mode

/CK T0 T1 T2 T3 T4 T5 T6

ODT

CKE

Internal

Term Res.

Rtt

tIS tIS

tAONPD min.

tAONPD max.

tAOFPD min.

tAOFPD max.

tAXPD ≤ 6tCK

ODT Timing for Power down Mode

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

T-5 T-4 T-3 T-2 T-1 T0 T1 T2 T3 T4

/CK

CKE

ODT

Internal

Term Res.

Internal

Term Res.

Internal

Term Res.

Internal

Term Res.

tIS

ODT

tIS

ODT

tIS

Active and standby

mode timings to

be applied.

Active and standby

mode timings to

be applied.

Power down

mode timings to

be applied.

Power down

mode timings to

be applied.

Rtt

tAOFPD(max.)

tAOFD

tAOND

tAONPD(max.)

tANPD

Entering slow exit active power down mode

or precharge power down mode.

ODT Timing Mode Switch at Entering Power Down Mode

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

T0 T1 T4 T5 T6 T7

/CK

CKE

ODT

Internal

Term Res.

Internal

Term Res.

Internal

Term Res.

Internal

Term Res.

tIS

T9 T10 T11

ODT

tIS

ODT

Active and standby

mode timings to

be applied.

Active and standby

mode timings to

be applied.

ODT

tIS

Power down

mode timings to

be applied.

Power down

mode timings to

be applied.

Exiting from slow active power down mode

or precharge power down mode.

Rtt

tAXPD

tAOFPD (max.)

tAONPD(max.)

tAOFD

tAOND

ODT Timing Mode Switch at Exiting Power Down Mode

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Bank Activate Command [ACT]

The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the

clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A13 is

used to determine which row to activate in the selected bank. The Bank activate command must be applied before

any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can

accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not

satisfied the tRCD (min.) sp ecification, then additive latency m ust be programmed into the devic e to delay when the

R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.)

is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be

precharged before another bank activate command can be applied to the same bank. The bank active and

precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank

activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to

tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is

determined by (tRRD).

/CK

Address

Command

T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3

tRCD(min.)

tRAS tRP

tRC

ROW: 0

ACT

Bank0

Active Bank1

Active Bank0

Active

Bank0

Precharge Bank1

Precharge

Posted

READ Posted

READ

ACT PRE PRE ACT

COL: 0 ROW: 0ROW: 1 COL: 1

tRCD =1

tCCD

Additive latency (AL)

tRRD

Bank0 Read begins

Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high,

/CS and /CAS low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access

cycle is a read operation (/WE high) or a write operation (/WE low).

The DDR2 SDRAM provides a fast column access operation. A single read or write command will initiate a serial

read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific

segments of the page length. For example, the 32M bits × 4 I/O × 4 banks chip has a page length of 2048 bits

(defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary

segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the

column address supplied to the device during the read or write command (CA0 to CA9, CA11). The second, third

and fourth access will also occur within this group segment, however, the burst order is a function of the starting

address, and the burst sequence.

A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is

defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Posted /CAS

Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a /CAS read or write command to be issued immediately after

the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is

held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is

controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before

the tRCD (min), then AL (greater than 0) must be written into the EMRS. The W rite Latency (W L) is al ways defined

as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency (RL = AL

+ CL).

-1

/CK

DQS, /DQS AL = 2

> tRCD

> tRAC

CL = 3

Command

0123456789101112

ACT READ NOP NOP

WRIT

out0 out1 out2 out3 in0 in1 in2 in3

WL = RL n–1 = 4

RL = AL + CL = 5

Read Followed by a Writ e to the Same Bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

-10123456789101112

/CK

DQS, /DQS

AL = 0

> tRCD

> tRAC

CL = 3

Command

ACT READ WRIT

out0 out1 out2 out3 in0 in1 in2 in3

RL = AL + CL = 3

WL = RL n–1 = 2

NOP NOP NOP

Read Followed by a Writ e to the Same Bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. DDR2 SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave

address ordering is supported, however, sequential address ordering is nibble based for ease of implementation.

The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS,

which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported.

Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or W rite by W rite at

the boundary of Burst 4. Therefore the burst stop command is not supported on DDR2 SDRAM devices.

[Burst Length and Sequence]

Burst lengt h Start i ng address (A 2, A1, A0) Sequential addressing (decimal) Interleave addressing (decim al )

000 0, 1, 2, 3 0, 1, 2, 3

001 1, 2, 3, 0 1, 0, 3, 2

010 2, 3, 0, 1 2, 3, 0, 1

011 3, 0, 1, 2 3, 2, 1, 0

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5

011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1

111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0

Note: Page length is a function of I/O organization and column addressing

32M bits × 4 organization (CA0 to CA9, CA11); Page Length = 2048 bits

16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits

8M bits × 16 organization (CA0 to CA9); Page Length = 1024 bits

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Burst Read Command [READ]

The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start

of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency

(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.

The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out

appears on the DQ pin in phase with the DQS signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set

(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set

(EMRS).

READ NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

DQ out0 out1 out2 out3

<tDQSCK

CL = 3

RL = 3

Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))

READ NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

DQ out0 out1 out2 out3 out4 out5 out6 out7

<tDQSCK

CL = 3

RL = 3

Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Posted

READ NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

AL = 2 CL = 3

RL = 5

out0 out1 out2 out3

<tDQSCK

Burst Read Operation (RL = 5, BL = 4 (AL = 2, CL = 3))

Posted

READ NOP

/CK T0 T1 T3 T4 T5 T6 T7 T8 T9

Command

DQS, /DQS

NOP Posted

WRIT

RL = 5

out0 out1 out2 out3 in0 in2

NOP

in3in1

tRTW (Read to Write = 4 clocks)

WL = RL - 1 = 4

Burst Read Followed by Burst Write (RL = 5, WL = RL-1 = 4, BL = 4)

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-

around-time, which is 4 clocks.

Posted

READ NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

Posted

READ NOP

out

AL = 2

CL = 3

RL = 5 out

A1 out

A2 out

A3 out

B0 out

B1 out

Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Enabling a read command at every other clock supports the seamless burst read operation. This operation is

allowed regardless of same or different banks as long as the banks are activated.

READ NOP READ

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

RL = 4

Burst interrupt is only

allowed at this timing.

out

A0 out

A1 out

A2 out

A3 out

B0 out

B1 out

B2 out

B3 out

B4 out

B5 out

B6 out

A B

Burst Read Interrupt b y Read

Notes :1. Read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited.

2. Read burst of 8 can only be interrupted by another read command. Read burst interruption by write

command or precharge command is prohibited.

3. Read burst interrupt must occur exactly two clocks after previous read command. any other read burst

interrupt timings are prohibited.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with auto precharge enabled is not allowed to interrupt.

6. Read burst interruption is allowed by another read with auto precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, minimum read to precharge timing is AL + BL/2 where BL is the burst length

set in the mode register and not the actual burst (which is shorter because of interrupt).

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Burst Write Command [WRIT]

The Burst W rite command is initiated by having /CS, /CAS and /W E low while holding /RAS high at the rising edge of

the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read

latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble)

one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge

of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent

burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. W hen the burst

has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst

write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery

time (tWR).

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

>tRP

>tWR

in2

PRE NOP

ACT

in1 in3in0

=Completion of

the Burst Write

<tDQSS

WL = RL –1 = 2

Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

>tRP

>tWR

in2in1 in3in0 in6in5 in7in4

=Completion of

the Burst Write

<tDQSS

WL = RL –1 = 2

T9 T11

NOP ACT

PRE

Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Posted

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

WL = RL −1 = 4 >tWR

in0 in1 in2 in3

PRE

<tDQSS Completion of

the Burst Write

Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

CL = 3

RL = 5

AL = 2

>tWTR

in0 in2

NOP

in1 in3

Posted

READ

WL = RL –1 = 4

Write to Read = CL - 1 + BL/2 + tWTR (2) = 6

out0 out1

Burst Write Followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3))

The minimum number of clock from the burst write command to the burst read command is CL - 1 + BL/2 + a write

to-read-turn-around-time (tW TR). This tWTR is not a write recovery time (tW R) but the time required to transfer the

4bit write data from the input buffer into sense amplifiers in the array.

NOP

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

DQ in

A0 in

NOP

A1 in

A3 in

B0 in

B1 in

Posted

WRIT Posted

WRIT

WL = RL − 1 = 4

Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4)

Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed

regardless of same or different banks as long as the banks are activated.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

WRIT NOP WRIT

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

WL = 3

Burst interrupt is only

allowed at this timing.

A0 in

A1 in

A2 in

A3 in

B0 in

B1 in

B2 in

B3 in

B4 in

B5 in

B6 in

A B

Write Interrupt by Write (WL = 3, BL = 8)

Notes :1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

2. Write burst of 8 can only be interrupted by another write command. Write burst interruption by read

command or precharge command is prohibited.

3. Write burst interrupt must occur exactly two clocks after previous write command. Any other write burst

interrupt timings are prohibited.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with auto precharge enabled is not allowed to interrupt.

6. Write burst interruption is allowed by another write with auto precharge command.

7. All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, minimum write to precharge timing is WL+BL/2+tWR where tWR starts with

the rising clock after the un-interrupted burst end and not from the end of actual burst end.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Write Data Mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the

implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in

a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used

during read cycles.

DQS

/DQS

T1 T2 T3 T4 T5 T6

Write mask latency = 0

in in in in in in in in

Data Mask Timing

/CK

DQS, /DQS

Command

[tDQSS(min.)]

tWR

tDQSS

[tDQSS(max.)]

WRIT NOP

in0 in2 in3

Data Mask Function, WL = 3, AL = 0 shown

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Precharge Command [PRE]

The precharge command is used to precharge or close a bank that has been activated. The precharge command is

triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge

command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,

BA0 and BA1 are used to define which bank to precharge when the command is issued.

[Bank Selection for Precharge by Address Bits]

A10 BA0 BA1 Precharged Bank(s)

L L L Bank 0 only

L H L Bank 1 only

L L H Bank 2 only

L H H Bank 3 only

H × × All banks 0 to 3

Remark: H: VIH, L: VIL, ×: VIH or VIL

Burst Read Operation Followed by Precharge

Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks

For the earliest possible precharge, the precharge command may be issued on the rising edge that is

“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the

same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

AL + 2 clocks

RL = 4

AL = 1

CL = 3

out0 out2

PRE NOP

out1 out3

Posted

READ ACT NOP

> tRP

> tRAS

Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

> tRAS CL = 3

CL = 3

out0 out2

NOPPRE

out1 out3

Posted

READ ACT NOP

> tRP

AL + 2 clocks

Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

AL = 2 CL = 4

out0 out2

NOPPRE

out1 out3 out4 out6out5 out7

Posted

READ ACT NOP

> tRP

RL = 6

AL + BL/2 Clocks

> tRAS(min.)

Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4, BL=8))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Burst Write followed by Precharge

Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge

command can be issued. This delay is known as a write recovery time (tW R) referenced from the completion of the

burst write to the precharge command. No precharge command should be issued prior to the tW R delay, as DDR2

SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.

in3in1

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

> tWR

Completion of

the Burst Write

WL = 3

in0 in2

Posted

WRIT PRE

Burst Write Followed by Precharge (WL = (RL-1) =3)

Posted

WRIT

/CK T0 T1 T2 T3 T4 T5 T6 T7 T9

Command

DQS, /DQS

WL = 4

in0 in1 in2 in3

PRE

> tWR

Completion of

the Burst Write

NOP

Burst Write Followed by Precharge (WL = (RL-1) = 4)

Posted

WRIT NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T11

Command

DQS, /DQS

WL = 4

in0 in1 in2 in3 in4 in5 in6 in7

> tWR

Completion of

the Burst Write

PRE

Burst Write Followed by Precharge (WL = (RL-1) = 4,BL= 8)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge

command or the auto-precharge function. When a re ad or a write command is given to the DDR2 SDRAM, the /CAS

timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at

the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is

issued, then normal read or write burst operation is executed and the bank remains active at the completion of the

burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is

engaged. During auto-precharge, a read Command will execute as normal with the exception that the active bank

will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst.

Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally

delays the Precharge operation until the array restore operation has been completed so that the auto precharge

command may be issued with any read or write command.

Burst Read with Auto Precharge [READA]

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2

SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with

AP command when the condition that. W hen tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the

start point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command)

may be issued to the same bank if the following two conditions are satisfied simultaneously.

(1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

> tRC CL = 3

Auto precharge begins

CL = 3

out0 out2out1 out3

Posted

READ ACT

> tRP

> tRAS(min.)

A10 = 1

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

NOP

/CK T0T-1 T1T2T3T4T5T6T7T8

Command

DQS, /DQS

RL = 5

AL = 2

> tRC CL = 3

Auto precharge begins

CL = 3

out0 out2out1 out3

Posted

READ ACT

> tRP

> tRAS(min.)

A10 = 1

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRAS lockout case)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))

NOP

/CK T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DQS, /DQS

RL = 5

AL = 2

A10 = 1

> tRC CL = 3

CL = 3

Auto precharge begins

out0 out2out1 out3

Posted

READ ACT NOP

> tRP

> tRAS(min.)

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit)

(RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3)

READ ACT

/CK T0 T2 T4 T6 T8 T10T1 T3 T5 T7 T9 T11

Command

DQS, /DQS

NOP

RL = 5

AL = 2

A10 = 1

CL = 3 ≥tRP

Auto Precharge begins

out0 out1 out2 out3 out4 out5 out6 out7

≥tRC

≥tRAS (min.)

Burst Read with Auto Precharge Followed by an Activation to the Same Bank

(RL = 5, BL = 8 (AL = 2, CL = 3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Burst Write with Auto-Precharge [WRITA]

If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR2

SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time

(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following tw o conditions are satisfied.

(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

in1 in3

/CK

T0 T1 T2 T3 T4 T5 T6 T7 T12

Command

DQS, /DQS

> tWR

> tRC

Auto Precharge Begins

Completion of the Burst Write

in0 in2

Posted

WRIT ACT

NOP

> tRP

WL = RL –1 = 2

A10 = 1

Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)

NOP

/CK T0 T3 T4 T5 T6 T7 T8 T9 T10

Command

DQS, /DQS

> tWR

> tRC

Auto Precharge Begins

Completion of the Burst Write

in0 in2

NOP

in1 in3

Posted

WRIT ACT

> tRP

WL = RL –1 = 4

A10 = 1

Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

WRIT ACT

/CK T0 T2 T4 T6 T8 T10T3 T5 T7 T9 T11 T12 T13

Command

DQS, /DQS

NOP

WL = RL − 1 = 4

A10 = 1

≥tWR ≥tRP

Auto Precharge begins.

in0 in1 in2 in3 in4 in5 in6 in7

≥tRC

Burst Write with Auto Precharge Followed by an Activation to the Same Bank

(WL = 4, BL = 8, tWR = 2, tRP = 3)

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Refresh Requirements

DDR2 SDRAM requires a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two

ways: by an explicit automatic refresh command, or by an internally timed event in self-refresh mode. Dividing the

number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline

to controllers for distributed refresh timing.

Automatic Refresh Command [REF]

When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic

refresh mode (REF). All banks of the DDR2 SDRAM must be p recha rged and idle fo r a minim um of the precharge

time (tRP) before the auto refresh command (REF) can be applied. An address counter, internal to the device,

supplies the bank address during the refresh cycle. No control of the external address bus is required once this

cycle has started.

When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay

between the auto refresh command (REF) and the next activate command or subsequent auto refresh command

must be greater than or equal to the auto refresh cycle time (tRFC).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of 8 refresh commands can be posted to any given DDR2 SDRAM, meaning that

the maximum absolute interval between any refresh command and the next Refresh command is 9 × tREFI.

NOPPRE

/CK T0 T1 T2 T3 T15 T7 T8

CKE

Command

≥ tRP

VIH

≥ tRFC ≥ tRFC

REFREF NOP Any

Command

Automatic Refresh Command

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Self Refresh Command [SELF]

The DDR2 SDRAM device has a built-in tim er to acc ommodate self-refresh operation. The se lf-refresh command is

defined by having /CS, /RAS, /CAS and CKE held low with /W E high at the rising edge of the clock.

ODT must be turned off before issuing self refresh command, by either driving ODT pin low or using EMRS

command. Once the command is registered, CKE must be held low to keep the device in self-refresh mode.

When the DDR2 SDRAM has entered self refresh mode all of the external signals except CKE, are “don’t care”.

The clock is internally disabled during self-refresh operation to save power. The user may change the external clock

frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be

restarted and stable before the device can exit self refresh operation. Once self-refresh exit command is registered,

a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the

device. CKE must remain high for the entire self-refresh exit period tXSRD for proper operation. NOP or deselect

commands must be registered on each positive clock edge during the self-refresh exit interval. ODT should also be

turned off during tXSRD.

Notes: 1. Device must be in the “All banks idle” state prior to entering self refresh mode.

2. ODT must be turned off tAOFD before entering self refresh mode, and can be turned on again

when tXSRD timing is satisfied.

3. tXSRD is applied for a read or a read with autoprecharge command.

4. tXSNR is applied for any command except a read or a read with autoprecharge command.

Comand

T0 T2T1 Tm Tn

CKE

T3 T4 T5

ODT

tAOFD

/CK

≥ tXSNR

≥ tXSRD

tRP*

tCK

tCH tCL

tIStIS

tIS

tIS tIH

Valid

NOP

SELF NOP

Self Refresh Command

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Power-Down [PDEN]

Power-down is synchronously entered when CKE is registered low (along with NOP or deselect command). CKE is

not allowed to go low while mode register or extended mode register command time, or read or write operation is in

progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-

precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those

operations. Timing diagrams are shown in the following pages with details for entry into power down.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting

power-down mode for proper read operation.

If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down

occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down

deactivates the input and output buffers, excluding CK, /CK, ODT and CKE. Also the DLL is disabled upon entering

precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-

down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2

SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must be

maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.

The power-down state is synchronously exited when CKE is registered high (along with a NOP or deselect

command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be

applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is

defined at AC Characteristics table of this data sheet.

/CK

CKE

Command

VIH or VIL

tXP, tXARD,

tXARDS

Enter power-down mode

tCKE tCKE

Exit power-down mode

tCKE

tIHtIS tIHtIS tIH tIS tIH tIHtIS

VALID

NOP

VALID

Power Down

Read to Power-Down Entry

Command

CKE

DQS

Command

CKE

DQS

/CK

AL + CL

BL=4

BL=8

T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6T1 T2 Tx+1 Tx+7 Tx+8 Tx+9

/DQS

READ

out

0out

1out

2out

out

0out

1out

2out

3out

4out

5out

6out

VIH

CKE should be kept high until the end of burst operation.

Read operation starts with a read command and

T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6T1 T2 Tx+1 Tx+7 Tx+8 Tx+9

READ

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Read with Auto Precharge to Power-Down Entr y

Command

CKE

DQS

Command

CKE

DQS

AL + BL/2

with tRTP = 7.5ns

and tRAS min. satisfied

/CK

Start internal precharge

AL + CL

CKE should be kept high

until the end of burst operation.

CKE should be kept high

until the end of burst operation.

AL + CL

BL=4

BL=8

T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6T1 T2 Tx+1 Tx+7 Tx+8 Tx+9

/DQS

READ PRE

READ

out

0out

1out

2out

out

0out

1out

2out

out

4out

5out

6out

AL + BL/2

with tRTP = 7.5ns

and tRAS min. satisfied

PRE

T0 Tx Tx+2 Tx+3 Tx+4 Tx+5 Tx+6T1 T2 Tx+1 Tx+7 Tx+8 Tx+9

Write to Power-Down Entry

Command

CKE

DQS

Command

CKE

DQS

/CK

BL=4

BL=8

/DQS

tWTR

0in

1in

2in

T0 Tm+1 Tm+3 Tx Tx+1 Tx+2 TyT1 Tm Tm+2 Ty+1 Ty+2 Ty+3

WRIT

0in

1in

2in

3in

4in

5in

6in

T0 Tm+1 Tm+3 Tm+4 Tm+5 Tx Tx+1T1 Tm Tm+2 Tx+2 Tx+3 Tx+4

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Write with Auto Precharge to Power-Down Entry

/CK

WR*1

Command

CKE

DQS

Command

CKE

DQS

/CK

BL=4

BL=8

/DQS

WRITA PRE

WRITA

0in

1in

2in

PRE

T0 Tm+1 Tm+3 Tx Tx+1 Tx+2 Tx+3T1 Tm Tm+2 Tx+4 Tx+5 Tx+6

Note: 1. WR is programmed through MRS

T0 Tm+1 Tm+3 Tm+4 Tm+5 Tx Tx+1T1 Tm Tm+2 Tx+2 Tx+3 Tx+4

0in

1in

2in

3in

4in

5in

6in

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Refresh command to Power-Down Entry

Command

CKE

T0 T3 T5 T6 T7 T8 T9T1 T2 T4 T10

/CK

CKE can go to low one clock after an auto-refresh command

T11

REF

Active command to power down ent ry

Command

CKE

CKE can go to low one clock after an active command

ACT

Precharge/Precharge all command to power down entry

Command

CKE CKE can go to low one clock after a precharge or precharge all command

PRE or

PALL

MRS/EMRS command to power down entry

Command

CKE

MRS or

EMRS

tMRD

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Asynchronous CKE Low Event

DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet. If CKE

asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array. If

this event occurs, memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks.

Stable clocks must exist at the input of DRAM before CKE is raised high again. DRAM must be fully re-initialized

(steps 4 through 13) as described in initialization sequence. DRAM is ready for normal operation after the

initialization sequence. See AC Characteristics table for tDELAY specification

tCK

/CK

tDELAY

CKE

CKE asynchronously

drops low Clocks can be

turned off after

this point

Stable clocks

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Input Clock Frequency Change during Precharge Pow e r Down

DDR2 SDRAM input clock frequency can be changed under following condition:

DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic low level.

A minimum of 2 clocks must be waited after CKE goes low before clock frequency may change. SDRAM input clock

frequency is allowed to change only within minimum and maximum operating frequency specified for the particular

speed grade. During input clock frequency change, ODT and CKE must be held at stable low levels.

Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down

may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new clock

frequency an additional MRS command may need to be issued to appropriately set the WR, CL and soon. During

DLL relock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock

frequency.

Clock Frequency Change in Precharge Power Down Mode

CKE

T0 T4 Tx+1 Ty Ty+1 Ty+2T1 T2 Tx

/CK Ty+3 Tz

tRP tXP

tAOFD

Stable new clock

before power down exit

ODT is off during

DLL RESET

Minmum 2 clocks

required before

changing frequency

ODT

Command

Ty+4

NOP NOP NOP NOP DLL

RESET NOP Valid

200 clocks

Frequency change

occurs here

Burst Interruption

Interruption of a burst read or write cycle is prohibited.

No Operation Command [NOP]

The no operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The

purpose of the no operation command is to prevent the DDR2 SDRAM from registering any unwanted commands

between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /W E held high at

the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

Deselect Command [DESL]

The deselect command performs the same function as a no operation command. Deselect Command occurs when

/CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares.

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Package Drawing

64-ball FBGA (µ

µµ

µBGA)

Solder ball: Lead free (Sn-Ag-Cu)

64-φ0.45 ± 0.05

11.3 ± 0.1

INDEX MARK

1.6

13.8 ± 0.1

0.1

0.2

S1.12 max.

0.35 ± 0.05

INDEX MARK

0.8

1.3

2.45

0.8

Unit: mm

0.2

φ0.08

MSAB

ECA-TS2-0091-01

0.2

3.2

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

84-ball FBGA (µ

µµ

µBGA)

Solder ball: Lead free (Sn-Ag-Cu)

84-φ0.45 ± 0.05

11.3 ± 0.1

INDEX MARK

13.8 ± 0.1

0.1

0.2

S1.12 max.

0.35 ± 0.05

INDEX MARK 0.8

1.3

2.45

Unit: mm

0.2

φ0.08

MSAB

ECA-TS2-0092-01

0.2

0.81.6

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDE51XXABSE.

Type of Surface Mount Device

EDE5104ABSE, EDE5108ABSE: 64-ball FBGA (µBGA) < Lead free (Sn-Ag-Cu) >

EDE5116ABSE: 84-ball FBGA (µBGA) < Lead free (Sn-Ag-Cu) >

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E81 (Ver. 8.1)

µBGA is a registered trademark of Tessera, Inc.

All other trademarks are the intellectual property of their respective owners.

M01E0107

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.