ATA6560-GAQW-N - MICROCHIP TECHNOLOGY

 2018 Microchip Technology Inc. DS20005991A-page 1

ATA6560/1

Features

• Fully ISO 11898-2, ISO 11898-5, and SAE J2284

Compliant

• CAN FD Ready

• Communication Speed up to 5 Mbps

• Low Electromagnetic Emission (EME) and High

Electromagnetic Immunity (EMI)

• Differential Receiver with Wide Common-Mode

Range

• ATA6560: Silent Mode (Receive Only)

• Remote Wake-Up Capability via CAN Bus

• Functional Behavior Predictable under All Supply

Conditions

• Transceiver Disengages from the Bus when Not

Powered Up

• RXD Recessive Clamping Detection

• High Electrostatic Discharge (ESD) Handling

Capability on the Bus Pins

• Bus Pins Protected Against Transients in

Automotive Environments

• Transmit Data (TXD) Dominant Time-Out

Function

• Undervoltage Detection on VCC and VIO Pins

• CANH/CANL Short-Circuit and Overtemperature

Protected

• Qualified According to AEC-Q100: Only

ATA6560-GAQW, ATA6560-GBQW,

ATA6561-GAQW, and ATA6561-GBQW

• Packages: SOIC8, VDFN8 with Wettable Flanks

(Moisture Sensitivity Level 1)

Applications

Classical CAN and CAN FD networks in the following

applications:

• Automotive

• Industrial

• Aerospace

• Medical

•Consumer

General Description

The ATA6560/1 is a high-speed CAN transceiver that

provides an interface between a Controller Area Net-

work (CAN) protocol controller and the physical

two-wire CAN bus. The transceiver is designed for

high-speed (up to 5 Mbps) CAN applications in the

automotive industry, providing differential transmit and

receive capability to (a microcontroller with) a CAN

protocol controller.

It offers improved Electromagnetic Compatibility (EMC)

and ESD performance, as well as features such as:

• Ideal passive behavior to the CAN bus when the

supply voltage is off

• Direct interfacing to microcontrollers with supply

voltages from 3V to 5V (ATA6561)

Three operating modes, together with the dedicated

fail-safe features, make the ATA6560/1 an excellent

choice for all types of high-speed CAN networks,

especially in nodes requiring a Low-Power mode with

wake-up capability via the CAN bus.

Package Types

ATA6561

3 x 3 VDFN* with

wettable flanks

ATA6560

SOIC

VCC

GND

RXD

CANH

CANL

5NSIL

STBYTXD

ATA6561

SOIC

VCC

GND

RXD

CANH

CANL

5VIO

STBYTXD

ATA6560

3 x 3 VDFN* with

wettable flanks

VCC

GND

RXD

CANH

CANL

NSIL

STBY

TXD 1

*Includes Exposed Thermal Pad (EP); see Table 1-2.

VCC

GND

RXD

CANH

CANL

VIO

STBY

TXD 1

High-Speed CAN Transceiver with Standby Mode

CAN FD Ready

ATA6560/1

DS20005991A-page 2  2018 Microchip Technology Inc.

ATA6560/1 FAMILY MEMBERS

Device VIO Pin NSIL Pin VDFN8 SOIC8 AEC-Q100

Qualified Description

ATA6560-GAQW X X X Standby mode and Silent mode

ATA6560-GBQW X X X Standby mode and Silent mode

ATA6561-GAQW X X X Standby mode, VIO - pin for

compatibility with 3.3V and 5V

microcontroller

ATA6561-GBQW X X X Standby mode, VIO - pin for

compatibility with 3.3V and 5V

microcontroller

ATA6560-GAQW-N X X Standby mode and Silent mode

ATA6560-GBQW-N X X Standby mode and Silent mode

ATA6561-GAQW-N X X Standby mode, VIO - pin for

compatibility with 3.3V and 5V

microcontroller

ATA6561-GBQW-N X X Standby mode, VIO - pin for

compatibility with 3.3V and 5V

microcontroller

Note: For ordering information, see the Product Identification System section.

 2018 Microchip Technology Inc. DS20005991A-page 3

ATA6560/1

Functional Block Diagram

Temperature

Protection

Control

Unit

Wake-Up

Filter

Slope

Control

and

Driver

TXD

Time-Out

Timer

VIO

VIO(1)

VCC

9&&

MUX

TXD

STBY

CANH

ATA6560/1

RXD

NSIL

5(1) 3

CANL

GND

5(1)

VIO(1)

WUC(3)

HSC(2)

Note 1: Pin 5: ATA6561: VIO

ATA6560: NSIL (the VIO line and the VCC line are internally connected)

2: HSC: High-Speed Comparator

3: Wake-Up Comparator

ATA6560/1

DS20005991A-page 4  2018 Microchip Technology Inc.

1.0 FUNCTIONAL DESCRIPTION

The ATA6560/1 is a stand-alone, high-speed CAN

transceiver, compliant with the ISO 11898-2 and

ISO 11898-5 standards. It provides a very low current

consumption in Standby mode and wake-up capability

via the CAN bus. There are two versions available, only

differing in the function of pin 5:

• ATA6560: Pin 5 is the control input for Silent mode

NSIL, allowing the ATA6560 to only receive data

and not send data via the bus. The output driver

stage is disabled. The VIO line and the VCC line

are internally connected; this sets the signal levels

of the TXD, RXD, STBY, and NSIL pins to levels

compatible with 5V microcontrollers.

• ATA6561: Pin 5 is the VIO pin and should be

connected to the microcontroller supply voltage.

This allows direct interfacing to microcontrollers

with supply voltages down to 3V and adjusts the

signal levels of the TXD, RXD, and STBY pins to

the I/O levels of the microcontroller. The I/O ports

are supplied by the VIO pin.

1.1 Operating Modes

The ATA6561 supports three operating modes: Unpow-

ered, Standby, and Normal. The ATA6560 has an addi-

tional Silent mode. These modes can be selected via

the STBY and NSIL pin. See Figure 1-1 and Table 1-1

for a description of the operating modes.

FIGURE 1-1: Operating Modes.

TABLE 1-1: OPERATING MODES

Mode

Inputs Outputs

STBY NSIL TXD CAN Driver RXD

Unpowered X(3) X(3) X(3) Recessive Recessive

Standby HIGH X(3) X(3) Recessive Active(4)

Silent (only for ATA6560) LOW LOW X(3) Recessive Active(1)

Normal LOW HIGH(2) LOW Dominant LOW

LOW HIGH(2) HIGH Recessive HIGH

Note 1: LOW if the CAN bus is dominant, and HIGH if the CAN bus is recessive.

2: Internally pulled up if not bonded out.

3: Irrelevant.

4: Reflects the bus only for wake-up.

VCC < V

uvd(VCC)

VCC < V

uvd(VCC)

STBY = 1 STBY = 1

STBY = 0 and

NSIL = 1 and

STBY = 0 and

(NSIL = 0 or

TXD = 0)

STBY = 0 and

TXD = 0

NSIL = 1 and

TXD = 1 and

Error = 0

NSIL = 0 or

Error = 1

TXD = 1 and

Error = 0

VCC > V

uvd(VCC)

VCC < V

uvd(VCC)

Unpowered

Mode

Standby

Mode

Silent

Mode

Normal

Mode

VCC < V

uvd(VCC)

STBY = 1

STBY = 0 and

TXD = 1 and

Error = 0 and

TXD = 1



Error = 1

Error = 0

VCC < V

uvd(VCC)

VIO < V

uvd(VIO)

VIO < V

uvd(VIO)

VCC < V

uvd(VCC)

or VCC > V

uvd(VCC)

and

VIO < V

uvd(VIO)

VIO > V

uvd(VIO)

Unpowered

Mode

Standby

Mode

Silent

Mode

Normal

Mode

ATA6560 ATA6561

STBY = 1

Note 1: The Silent mode is externally not accessible.

2: For the ATA6561, NSIL is internally set to “1”.

 2018 Microchip Technology Inc. DS20005991A-page 5

ATA6560/1

1.1.1 NORMAL MODE

A low level on the STBY pin, together with a high level on

pins TXD and NSIL, selects the Normal mode. In this

mode, the transceiver can transmit and receive data via

the CANH and CANL bus lines (see the “Functional

Block Diagram”). The output driver stage is active and

drives data from the TXD input to the CAN bus. The

High-Speed Comparator (HSC) converts the analog data

on the bus lines into digital data, which is output to pin

RXD. The bus biasing is set to VVCC/2, and the

undervoltage monitoring of VCC is active.

The slope of the output signals on the bus lines is

controlled and optimized to ensure the lowest possible

EME.

To switch the device to a normal operating mode, set

the STBY pin to low and the TXD and NSIL pins (if

applicable) to high (see Table 1-1, Figure 1-2, and

Figure 1-3). Both the STBY and the NSIL pins provide

a pull-up resistor to VIO, thus ensuring defined levels if

the pins are open.

The device cannot enter the Normal mode as long as

the TXD is at ground level. ATA6560 only switches to

the Normal mode when all inputs are set accordingly.

FIGURE 1-2: Switching from Standby Mode to Normal Mode (NSIL = High).

FIGURE 1-3: Switching from Silent Mode to Normal Mode.

STBY

TXD

Standby Pode

tdel(stby-norm) =

47μs max

Normal Pode

Operation

Pode

STBY

NSIL

TXD

Silent Pode

tdel(sil-norm) =

10μs max

Normal Pode

Operation

Pode

ATA6560/1

DS20005991A-page 6  2018 Microchip Technology Inc.

1.1.2 SILENT MODE (ONLY FOR THE

ATA6560)

A low level on the NSIL pin (available on pin 5) and on

the STBY pin selects the Silent mode. This

receive-only mode can be used to test the connection

of the bus medium. In the Silent mode, the ATA6560

can still receive data from the bus, but the transmitter is

disabled and therefore no data can be sent to the CAN

bus. The bus pins are released to recessive state. All

other IC functions, including the HSC, continue to oper-

ate as they do in the Normal mode. The Silent mode

can be used to prevent a faulty CAN controller from

disrupting all network communications.

1.1.3 STANDBY MODE

A high level on the STBY pin selects the Standby

mode. In this mode, the transceiver cannot transmit or

correctly receive data via the bus lines. The transmitter

and the HSC are switched off to reduce current con-

sumption, and only the low-power Wake-Up Compara-

tor (WUC) monitors the bus lines for a valid wake-up

signal. A signal change on the bus from “Recessive” to

“Dominant,” followed by a dominant state longer than

twake, switches the RXD pin to low to signal a wake-up

request to the microcontroller.

In the Standby mode, the bus lines are biased to

ground to reduce current consumption to a minimum.

The WUC monitors the bus lines for a valid wake-up

signal. When the RXD pin switches to low to signal a

wake-up request, a transition to the Normal mode is not

triggered until the microcontroller forces back the STBY

pin to low. A bus dominant time-out timer prevents the

device from generating a permanent wake-up request

by switching the RXD pin to high.

For ATA6560 only: If the NSIL input pin is set to low in

the Standby mode, the internal pull-up resistor causes

an additional quiescent current from VIO to GND.

Microchip recommends setting the NSIL pin to high in

the Standby mode.

1.2 Fail-Safe Features

1.2.1 TXD DOMINANT TIME-OUT

FUNCTION

A TXD dominant time-out timer is started when the

TXD pin is set to low. If the low state on the TXD pin

persists for longer than tto(dom)TXD, the transmitter is

disabled, releasing the bus lines to a recessive state.

This function prevents a hardware failure, software

application failure, or both from driving the bus lines to

a permanent dominant state (blocking all network

communications). The TXD dominant time-out timer is

reset when the TXD pin is set to high (≥ 4 µs).

1.2.2 INTERNAL PULL-UP STRUCTURE

AT TXD, NSIL, AND STBY INPUT

PINS

The TXD, STBY, and NSIL pins have an internal pull-up

to VIO. This ensures a safe, defined state in case one

or all of these pins are left floating. Pull-up currents flow

in these pins in all states, meaning all pins should be in

a high state during the Standby mode to minimize the

current consumption.

1.2.3 UNDERVOLTAGE DETECTION ON

PINS VCC AND VIO

If VVCC or VVIO drops below their respective undervoltage

detection levels (Vuvd(VCC) and Vuvd(VIO), see Section 2.0

“Electrical Characteristics”), the transceiver switches

off and disengages from the bus until VVCC and VVIO have

recovered. The low-power WUC is only switched off

during a VCC or VIO undervoltage. The logic state of the

STBY pin is ignored until the VCC voltage or the VIO

voltage has recovered.

1.2.4 BUS WAKE-UP TIME-OUT

FUNCTION

In the Standby mode, a bus wake-up time-out timer is

started when the CAN bus changes from recessive to

dominant state. If the dominant state on the bus persists

for longer than tto_bus, the RXD pin is switched to high.

This function prevents a clamped dominant bus (due to a

bus short circuit or a failure in one of the other nodes on

the network) from generating a permanent wake-up

request. The bus wake-up time-out timer is reset when

the CAN bus changes from dominant to recessive state.

1.2.5 OVERTEMPERATURE PROTECTION

The output drivers are protected against overtemperature

conditions. If the junction temperature exceeds the

shutdown junction temperature, TJsd, the output drivers

are disabled until the junction temperature drops below

TJsd and pin TXD is at a high level again. The TXD

condition ensures that output driver oscillations due to

temperature drift are avoided.

 2018 Microchip Technology Inc. DS20005991A-page 7

ATA6560/1

FIGURE 1-4: Release of Transmission After Overtemperature Condition.

1.2.6 SHORT-CIRCUIT PROTECTION OF

THE BUS PINS

The CANH and CANL bus outputs are short-circuit

protected, either against GND or a positive supply

voltage. A current-limiting circuit protects the trans-

ceiver against damage. If the device heats up due to

a continuous short on CANH or CANL, the internal

overtemperature protection switches the bus trans-

mitter off.

1.2.7 RXD RECESSIVE CLAMPING

This fail-safe feature prevents the controller from

sending data on the bus if its RXD line is clamped to

high (for example, recessive). That is, if the RXD pin

cannot signal a dominant bus condition (for example,

because it is shorted to VCC), the transmitter within the

ATA6560/1 is disabled to avoid possible data collisions

on the bus. In Normal and Silent modes (only for the

ATA6560), the device permanently compares the state

of the HSC to the state of the RXD pin.

If the HSC indicates a dominant bus state for more than

tRC_det, without the RXD pin doing the same, a

recessive clamping situation is detected and the device

is forced into the Silent mode. This Fail-Safe mode is

released by entering either the Standby or the Unpow-

ered mode or if the RXD pin is showing a dominant (for

example, low) level again.

Failure

Overtemp

GND

TXD

Overtemperature

RDR

BUS VDIFF

(CANH-CANL)

V9,O

RDD

RXD

V9,O

GND

ATA6560/1

DS20005991A-page 8  2018 Microchip Technology Inc.

FIGURE 1-5: RXD Recessive Clamping Detection.

1.3 Pin Description

The descriptions of the pins are listed in Table 1-2.

CAN

TXD

RXD

Operation

Pode Normal NormalSilent

If the clamping condition is removed and a

dominant bus is detected, the transceiver

goes back to 1ormal mode.

TABLE 1-2: PIN FUNCTION TABLE

ATA6560 ATA6561

Symbol Description

SOIC8 VDFN8 SOIC8 VDFN8

1111 TXD

Transmit Data Input

2222 GNDGround Supply

3333 VCCSupply Voltage

4444 RXDReceive Data Output; reads out data from the bus lines

— — 5 5 VIO Supply Voltage for the I/O Level Adapter; the VIO and VCC lines

are internally connected

5 5 — — NSIL Silent Mode Control Input (low active)

6666CANLLow-Level CAN Bus Line

7777CANHHigh-Level CAN Bus Line

8888STBYStandby Mode Control Input

— 9 — 9 EP Exposed Thermal Pad; heat slug, internally connected to the GND

 2018 Microchip Technology Inc. DS20005991A-page 9

ATA6560/1

1.4 Typical Application

ATA6560 Typical Application

ATA6561 Typical Application

Note 1: The size of this capacitor depends on the external voltage regulator used.

2: For the VDFN package, the heat slug must always be connected to GND.

3CANH

VCC

VDD

Microcontroller

GND

ATA6560

CANH

STBY

NSIL

TXD

RXD CANL

BAT

100nF

6CANL

GND

12V

GND

22μF

(1)

3CANH

100nF 22μF(1)

VIO VCC

VDD

Microcontroller

GND

ATA6561

CANH

STBY

TXD

RXD

CANL

BAT

12V

6CANL

GND GND

3.3V

12V

100nF

Note 1: The size of this capacitor depends on the external voltage regulator used.

2: For the VDFN package, the heat slug must always be connected to GND.

ATA6560/1

DS20005991A-page 10  2018 Microchip Technology Inc.

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

DC Voltage at CANH, CANL (VCANH, VCANL) ................................................................................................–27 to +42V

Transient Voltage at CANH, CANL (according to ISO 7637 part 2) (VCANH, VCANL) .................................–150 to +100V

DC Voltage on all other pins (VX) .................................................................................................................–0.3 to +5.5V

ESD according to IBEE CAN EMC - Test specification following IEC 61000-4-2 — Pin CANH, CANL ..................±8 kV

ESD (HBM following STM5.1 with 1.5 kΩ/100 pF) - Pins CANH, CANL to GND .................................................... ±6 kV

Component-Level ESD (HBM according to ANSI/ESD STM5.1, JESD22-A114, AEC-Q100 (002) ........................±4 kV

CDM ESD STM 5.3.1 ..............................................................................................................................................±750V

ESD Machine Model AEC-Q100-RevF(003) ...........................................................................................................±200V

Virtual Junction Temperature (TvJ) .............................................................................................................–40 to +150°C

Storage Temperature Range (Tstg) ............................................................................................................–55 to +150°C

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

ATA6560/1 ELECTRICAL CHARACTERISTICS

Electrical Specifications: TvJ = –40°C to +150°C; VVCC = 4.5V to 5.5V; VVIO = 2.8V to 5.5V; RL=60, CL= 100 pF,

unless otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions

Supply, Pin VCC

Supply Voltage VVCC 4.5 — 5.5 V

Supply Current in Silent Mode IVCC_sil 1.9 2.5 3.0 mA Silent mode,

VTXD =V

VIO

Supply Current in Normal

Mode

IVCC_rec 2 — 5 mA Recessive,

VTXD =V

VIO

IVCC_dom 20 50 70 mA Dominant, VTXD =0V

Supply Current in Standby

Mode

IVCC_STBY — — 12 µA VVCC =V

VIO,

VTXD =V

NSIL =V

VIO

IVCC_STBY —7—µAT

a=+25°C (Note 3)

Undervoltage Detection

Threshold on Pin VCC

Vuvd(VCC) 2.75 — 4.5 V

I/O Level Adapter Supply, Pin VIO (only for the ATA6561)

Supply Voltage on Pin VIO VVIO 2.8 — 5.5 V

Supply Current on Pin VIO IIO_rec 10 80 250 µA Normal and Silent

modes

Recessive,

VTXD =V

VIO

IIO_rdom 50 350 500 µA Normal and Silent

modes

Dominant, VTXD =0V

IIO_STBY — — 1 µA Standby mode

Undervoltage Detection

Threshold on Pin VIO

Vuvd(VIO) 1.3 — 2.7 V

Note 1: This parameter is 100% correlation tested.

2: This parameter is ensured by characterization on samples.

3: This parameter is ensured by design.

 2018 Microchip Technology Inc. DS20005991A-page 11

ATA6560/1

Mode Control Input, Pin NSIL and STBY

High-Level Input Voltage VIH 0.7 x VVIO —V

VIO +0.3 V

Low-Level Input Voltage VIL –0.3 — 0.3 x VVIO V

Pull-Up Resistor to VIO Rpu 75 125 175 kΩ VSTBY =0V, V

NSIL =0V

High-Level Leakage Current IL–2 — +2 µA VSTBY =V

VIO,

VNSIL =V

VIO

CAN Transmit Data Input, Pin TXD

High-Level Input Voltage VIH 0.7 x VVIO —V

VIO +0.3 V

Low-Level Input Voltage VIL –0.3 — 0.3 x VVIO V

Pull-Up Resistor to VIO RTXD 20 35 50 kΩ VTXD =0V

High-Level Leakage Current ITXD –2 — +2 µA Normal mode,

VTXD =V

VIO

Input Capacitance CTXD — 5 10 pF Note 3

CAN Receive Data Output, Pin RXD

High-Level Output Current IOH –8 — –1 mA Normal mode,

VRXD =V

VIO –0.4V,

VVIO =V

VCC

Low-Level Output Current IOL 2 — 12 mA Normal mode,

VRXD =0.4V,

bus dominant

Bus Lines, Pins CANH and CANL

Dominant Output Voltage IIO 2.75 3.5 4.5 V VTXD =0V,

t<t

to(dom)TXD

pin CANH

0.5 1.5 2.25 V VTXD =0V,

t<t

to(dom)TXD

pin CANL

Transmitter Dominant Voltage

Symmetry

Vdom(TX)sym 0.9 x VVCC —1.1 x VVCC VV

dom(TX)sym =V

CANH +

VCANL (Note 1)

Bus Differential Output Voltage VO(diff)bus 1.5 — 3 V VTXD =0V,

t<t

to(dom)TXD

RL= 45Ω to 65Ω

–50 — +50 mV VVCC = 4.75V to 5.25V

VTXD =V

VIO, receive,

no load

Recessive Output Voltage VO(rec) 20.5x VVCC 3 V Normal and Silent

modes,

VTXD =V

VIO, no load

–0.1 — +0.1 V Standby mode,

VTXD =V

VIO, no load

ATA6560/1 ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: TvJ = –40°C to +150°C; VVCC = 4.5V to 5.5V; VVIO = 2.8V to 5.5V; RL=60, CL= 100 pF,

unless otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: This parameter is 100% correlation tested.

2: This parameter is ensured by characterization on samples.

3: This parameter is ensured by design.

ATA6560/1

DS20005991A-page 12  2018 Microchip Technology Inc.

Differential Receiver Threshold

Voltage

Vth(RX)dif 0.5 0.7 0.9 V Normal and Silent

modes (HSC),

Vcm(CAN) =–27V to

+27V

0.4 0.7 1 V Standby mode (WUC),

Vcm(CAN) =–27V to

+27V (Note 1)

Differential Receiver Hystere-

sis Voltage (HSC)

Vhys(RX)dif 50 120 200 mV Normal and Silent

modes (HSC),

Vcm(CAN) =–27V to

+27V (Note 1)

Dominant Output Current IIO(dom) –100 — –35 mA VTXD =0V,

t<t

to(dom)TXD,

VVCC =5V

pin CANH, VCANH =0V

35 — 100 mA VTXD =0V,

t<t

to(dom)TXD,

VVCC =5V

pin CANL,

VCANL =5V/40V

Recessive Output Current IIO(rec) –5 — +5 mA Normal and Silent

modes,

VTXD =V

VIO, no load,

VCANH =V

CANL = –27V

to +32V

Leakage Current IIO(rec) –5 0 +5 µA VVCC =V

VIO =0V,

VCANH =V

CANL =5V

Input Resistance Ri91528kΩ

Input Resistance Deviation ΔRi–1 0 +1 % Between VCANH and

VCANL

Differential Input Resistance Ri(dif) 19 30 56 kΩ

Ri(dif) 20 30 56 kΩ TvJ < +125°C

Common-Mode Input

Capacitance

Ci(cm) — — 20 pF Note 3

Differential Input Capacitance Ci(dif) — — 10 pF Note 3

Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-2

Delay Time from TXD to Bus

Dominant

td(TXD-busdom) 40 — 130 ns Normal mode (Note 2)

Delay Time from TXD to Bus

Recessive

td(TXD-busrec) 40 — 130 ns Normal mode (Note 2)

Delay Time from Bus Dominant

to RXD

td(busdom-RXD)20 — 100 ns Normal and Silent

modes (Note 2)

Delay Time from Bus Reces-

sive to RXD

td(busrec-RXD) 20 — 100 ns Normal and Silent

modes (Note 2)

ATA6560/1 ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: TvJ = –40°C to +150°C; VVCC = 4.5V to 5.5V; VVIO = 2.8V to 5.5V; RL=60, CL= 100 pF,

unless otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: This parameter is 100% correlation tested.

2: This parameter is ensured by characterization on samples.

3: This parameter is ensured by design.

 2018 Microchip Technology Inc. DS20005991A-page 13

ATA6560/1

Propagation Delay from TXD

to RXD

tPD(TXD-RXD) 40 — 210 ns Normal mode, Rising

edge at pin TXD

40 — 200 ns Normal mode, Falling

edge at pin TXD

tPD(TXD-RXD) — — 300 ns Normal mode, Rising

edge at pin TXD

RL= 120Ω,

CL= 200 pF (Note 3)

— — 300 ns Normal mode, Falling

edge at pin TXD

RL= 120Ω, CL= 200pF

(Note 3)

TXD Dominant Time-Out Time tto(dom)TXD 0.8 — 3 ms VTXD = 0V, Normal

mode

Bus Wake-Up Time-Out Time tto_bus 0.8 — 3 ms Standby mode

Minimum Dominant/Recessive

Bus Wake-Up Time

twake 0.75 3 5 µs Standby mode

Delay Time for Standby Mode

to Normal Mode Transition

tdel(stby-norm) — — 47 µs Falling edge at pin

STBY

NSIL = HIGH

Delay Time for Normal Mode to

Standby Mode Transition

tdel(norm-stby) — — 5 µs Rising edge at pin

STBY

NSIL = HIGH (Note 3)

Delay Time for Normal Mode to

Silent Mode Transition

tdel(norm-sil) — — 10 µs Falling edge at pin

NSIL

STBY = LOW (Note 3)

Delay Time for Silent Mode to

Normal Mode Transition

tdel(sil-norm) — — 10 µs Rising edge at pin NSIL

STBY = LOW (Note 3)

Delay Time for Silent Mode to

Standby Mode Transition

tdel(sil-stby) — — 5 µs Rising edge at pin

STBY

NSIL = LOW (Note 3)

Delay Time for Standby Mode

to Silent Mode Transition

tdel(stby-sil) — — 47 µs Rising edge at pin

STBY

NSIL = LOW (Note 3)

Debouncing Time for Reces-

sive Clamping State Detection

tRC_det —90—nsV

(CANH-CANL) > 900 mV

RXD = HIGH (Note 3)

Transceiver Timing for higher Bit Rates, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3

Recessive Bit Time on Pin

RXD

tBit(RXD) 400 — 550 ns Normal mode,

tBit(TXD) = 500 ns

(Note 3)

120 — 220 ns Normal mode,

tBit(TXD) = 200 ns

ATA6560/1 ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: TvJ = –40°C to +150°C; VVCC = 4.5V to 5.5V; VVIO = 2.8V to 5.5V; RL=60, CL= 100 pF,

unless otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: This parameter is 100% correlation tested.

2: This parameter is ensured by characterization on samples.

3: This parameter is ensured by design.

ATA6560/1

DS20005991A-page 14  2018 Microchip Technology Inc.

FIGURE 2-1: Timing Test Circuit for the ATA6560/1 CAN Transceiver.

Temperature Specifications

Parameters Sym. Min. Typ. Max. Units Conditions

8-Lead SOIC

Thermal Resistance Virtual Junction to Ambient RthvJA —145 — K/W

Thermal Shutdown of Bus Drivers TJsd 150 175 195 °C

8-Lead VDFN

Thermal Resistance Virtual Junction to Heat Slug RthvJC —10 —K/W

Thermal Resistance Virtual Junction to Ambient,

where Heat Slug is Soldered to PCB According to

JEDEC

RthvJA —50 —K/W

Thermal Shutdown of Bus Drivers TJsd 150 175 195 °C

TXD

+5V

22μF 100nF

15pF

RXD

CANH

GND STBY

CANL

VIO/NSIL VCC

RLCL

 2018 Microchip Technology Inc. DS20005991A-page 15

ATA6560/1

FIGURE 2-2: CAN Transceiver Timing Diagram.

FIGURE 2-3: CAN Transceiver Timing Diagram for Loop Delay Symmetry.

TXD

CANH

HIGH

LOW

HIGH

recessive

LOW

dominant

0.9V

0.5V

CANL

RXD

VO(dif) (bus)

td(TXD-busdom) td(TXD-busrec)

td(busdom-RXD)

tPD(TXD-RXD) tPD(TXD-RXD)

td(busrec-RXD)

0.7V9,O

0.3V9,O

30%

70%

30%

70%

5 x tBit(TXD) tBit(TXD)

tBit(RXD)

tLoop

falling edge

tLoop

rising edge

TXD

RXD

Note: The bit time of a recessive bit after five dominant bits is measured on the RXD pin.

ATA6560/1

DS20005991A-page 16  2018 Microchip Technology Inc.

3.0 PACKAGING INFORMATION

3.1 Package Marking Information

810

6561-N

1810256

810

6560-N

1810256

810

ATA6561

1810256

810

ATA6560

1810256

YWW

XXXXXXXX

YYWWNNN

Legend: XX...X

Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

6566

ZZZ

8-Lead SOIC

8-Lead 3 x 3 mm VDFN

Example ATA6560 Example ATA6561

Example ATA6561

6561

256

6566

ZZZ

6560

256

Example ATA6560

Industrial type

Example ATA6561

Industrial type

Example ATA6561

Industrial type

6566

ZZZ

6561-N

256

6566

ZZZ

6560-N

256

Example ATA6560

Industrial type

Example ATA6560

 2018 Microchip Technology Inc. DS20005991A-page 17

ATA6560/1

8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

0.25 CA–B D

SEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10 C

Microchip Technology Drawing No. C04-057-OA Rev D Sheet 1 of 2

NOTE 5

NX b

0.10 CA–B

H0.23

(L1)

R0.13

VIEW C

SEE VIEW C

NOTE 1

ATA6560/1

DS20005991A-page 18  2018 Microchip Technology Inc.

8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

Microchip Technology Drawing No. C04-057-OA Rev D Sheet 2 of 2

Foot Angle 0° - 8°

15°-5°

Mold Draft Angle Bottom

15°-5°

Mold Draft Angle Top

0.51-0.31

Lead Width

0.25-0.17

Lead Thickness

1.27-0.40LFoot Length

0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10

Standoff

--1.25A2Molded Package Thickness

1.75--AOverall Height

1.27 BSC

Pitch

8NNumber of Pins

MAXNOMMINDimension Limits

MILLIMETERSUnits

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

 Pin 1 visual index feature may vary, but must be located within the hatched area.

 Significant Characteristic

 Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.15mm per side.

 Dimensioning and tolerancing per ASME Y14.5M

Notes:

Footprint L1 1.04 REF

5. Datums A & B to be determined at Datum H.

 2018 Microchip Technology Inc. DS20005991A-page 19

ATA6560/1

8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-OA Rev B

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

Dimension Limits

Units

CContact Pad Spacing

Contact Pitch

MILLIMETERS

1.27 BSC

MIN

MAX

5.40

Contact Pad Length (X8)

Contact Pad Width (X8)

1.55

0.60

NOM

SILK SCREEN

ATA6560/1

DS20005991A-page 20  2018 Microchip Technology Inc.

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With

2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

0.10 C

0.10 C A B

0.05 C

(DATUM B)

(DATUM A)

SEATING

PLANE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-21358 Rev B Sheet 1 of 2

NOTE 1

(A3)

AA1

NOTE 1

8X b

 2018 Microchip Technology Inc. DS20005991A-page 21

ATA6560/1

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With

2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

Microchip Technology Drawing C04-21358 Rev B Sheet 2 of 2

Number of Terminals

Overall Height

Terminal Width

Overall Width

Terminal Length

Exposed Pad Width

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

0.65 BSC

0.203 REF

1.50

0.35

0.25

0.80

0.00

0.30

0.40

1.60

0.85

0.03

3.00 BSC

MILLIMETERS

MIN NOM

1.70

0.45

0.35

0.90

0.05

MAX

K-0.20 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

Overall Length

Exposed Pad Length

D2 2.30

3.00 BSC

2.40 2.50

SECTION A–A

PARTIALLY

PLATED

Wettable Flank Step Cut Depth A4 0.10 0.130.15

E3--0.04Wettable Flank Step Cut Width

ATA6560/1

DS20005991A-page 22  2018 Microchip Technology Inc.

8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN] With

2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Optional Center Pad Width

Optional Center Pad Length

Contact Pitch

2.50

1.70

MILLIMETERS

0.65 BSC

MIN

MAX

Contact Pad Length (X8)

Contact Pad Width (X8)

0.80

0.35

Microchip Technology Drawing C04-23358 Rev B

NOM

CContact Pad Spacing 3.00

Contact Pad to Center Pad (X8) G1 0.20

Thermal Via Diameter V

Thermal Via Pitch EV

0.33

1.20

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

ØV

SILK SCREEN

EVX2

Pin 1 Index Chamfer CH 0.20

Contact Pad to Contact Pad (X6) G2 0.20

 2018 Microchip Technology Inc. DS20005991A-page 23

ATA6560/1

APPENDIX A: REVISION HISTORY

Revision A (April 2018)

• Original release of this document.

• This document replaces Atmel -

9288J-AUTO-04/15.

• Added Industrial types.

• Added table ATA6560/1 Family Members.

ATA6560/1

DS20005991A-page 24  2018 Microchip Technology Inc.

NOTES:

 2018 Microchip Technology Inc. DS20005991A-page 25

ATA6560/1

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is available through the web site

at: http://microchip.com/support

ATA6560/1

DS20005991A-page 26  2018 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Examples:

a) ATA6560-GAQW: ATA6560, 8-Lead SOIC,

Qualified according to

AEC-Q100, Tape and Reel,

Package according to RoHS

b) ATA6560-GBQW: ATA6560, 8-Lead VDFN,

Qualified according to

AEC-Q100, Tape and Reel,

Package according to RoHS

c) ATA6561-GAQW: ATA6561, 8-Lead SOIC,

Qualified according to

AEC-Q100, Tape and Reel,

Package according to RoHS

d) ATA6561-GBQW: ATA6561, 8-Lead VDFN,

Qualified according to

AEC-Q100, Tape and Reel,

Package according to RoHS

e) ATA6560-GAQW-N: ATA6560, 8-Lead SOIC,

Tape and Reel, Package

according to RoHS,

Industrial type

f) ATA6560-GBQW-N: ATA6560, 8-Lead VDFN,

Tape and Reel, Package

according to RoHS,

Industrial type

g) ATA6561-GAQW-N: ATA6561, 8-Lead SOIC,

Tape and Reel, Package

according to RoHS,

Industrial type

h) ATA6561-GBQW-N: ATA6561, 8-Lead VDFN,

Tape and Reel, Package

according to RoHS,

Industrial type

PART NO. X

Package DirectivesDevice

Device: ATA6560/1: High-Speed CAN Transceiver with Standby

Mode – CAN FD Ready

Package: GA = 8-Lead SOIC

GB = 8-Lead VDFN

Tape and Reel

Option:

Q = 330 mm diameter Tape and Reel

Package

Directives

Classification:

W = Package according to RoHS(2)

Device Variant N = Device Variant N (Industrial type)

Package

[X]

(1)

Tape and Reel

Option Classification

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identifier is

used for ordering purposes and is not printed on

the device package. Check with your Microchip

Sales Office for package availability with the Tape

and Reel option.

2: RoHS compliant; maximum concentration value

of 0.09% (900 ppm) for Bromine (Br) and

Chlorine (Cl) and less than 0.15% (1500 ppm)

total Bromine (Br) and Chlorine (Cl) in any

homogeneous material. Maximum concentration

value of 0.09% (900 ppm) for Antimony (Sb) in

any homogeneous material.

Device

Variant

–

 2018 Microchip Technology Inc. DS20005991A-page 27

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT

logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,

Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK

MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST

logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32

logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,

SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are

registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,

CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,

ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-

Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,

MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,

PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,

RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial

Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,

Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-2875-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTS

YSTEM

CERTIFIEDBYDNV

== ISO/TS16949==

DS20005991A-page 28  2018 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

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10/25/17