© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 6
1Publication Order Number:
CAT28C256/D
CAT28C256
256 kb Parallel EEPROM
Description
The CAT28C256 is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 32K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bits signal the start and end of the self−timed
write cycle. Additionally, the CAT28C256 features hardware and
software write protection.
The CAT28C256 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP
or 32−pin PLCC packages.
Features
•Fast Read Access Times: 120/150 ns
•Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 150 mA Max.
•Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
•Fast Write Cycle Time:
− 5 ms Max.
•CMOS and TTL Compatible I/O
•Hardware and Software Write Protection
•Automatic Page Write Operation:
− 1 to 64 Bytes in 5 ms
− Page Load Timer
•End of Write Detection:
− Toggle Bit
− DATA Polling
•100,000 Program/Erase Cycles
•100 Year Data Retention
•Commercial, Industrial and Automotive Temperature Ranges
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See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
PLCC−32
N, G SUFFIX
CASE 776AK
Address InputsA0−A14
Data Inputs/OutputsI/O0−I/O7
Chip EnableCE
Output EnableOE
Write EnableWE
5 V SupplyVCC
FunctionPin Name
PIN FUNCTION
GroundVSS
No ConnectNC
PDIP−28
P, L SUFFIX
CASE 646AE
TSOP−28
T13, H13 SUFFIX
CASE 318AE
CAT28C256
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PIN CONFIGURATION
PLCC Package (N, G)DIP Package (P, L) TSOP Package (8 mm X 13.4 mm) (T13, H13)
5
4
7
6
3
2
1
10
9
12
11
8
24
25
22
23
26
27
28
19
20
17
18
21
VCC
WE
A11
A10
CE
I/O7
I/O6
I/O5
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
VSS
5
7
6
10
9
12
11
8
13
14 1516 1718 19 20
4 3 2 1 32 31 30
29
27
28
24
25
22
23
26
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A7
A12
A14
NC
VCC
WE
A13
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VSS
NC
OE
A11
5
4
7
6
3
2
1
10
9
12
11
8
14
13
A9
A8
A13
WE
24
25
22
23
26
27
28
19
20
17
18
21
15
16
A4
A3
A6
A5
A7
A12
A14
VCC
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
(Top Views)
14
13
15
16 I/O4
I/O3
A13
A8
A9
OE
I/O1
I/O2
Figure 1. Block Diagram
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
CONTROL
LOGIC
TIMER
HIGH VOLTAGE
GENERATOR
I/O BUFFERS
32,768 x 8
EEPROM
ARRAY
CE
OE
WE
VCC
A0−A5
A6−A14
WRITE
PROTECTION
COLUMN
DECODER
ROW
DECODER
DATA POLLING
AND
TOGGLE BIT I/O0−I/O7
64 BYTE PAGE
REGISTER
CAT28C256
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Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias –55 to +125 °C
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –2.0 V to +VCC + 2.0 V V
VCC with Respect to Ground −2.0 to +7.0 V
Package Power Dissipation Capability (TA = 25°C) 1.0 W
Lead Soldering Temperature (10 secs) 300 °C
Output Short Circuit Current (Note 2) 100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol Parameter Test Method Min Max Units
NEND Endurance MIL−STD−883, Test Method 1033 100,000 Cycles/Byte
TDR Data Retention MIL−STD−883, Test Method 1008 100 Years
VZAP ESD Susceptibility MIL−STD−883, Test Method 3015 2,000 V
ILTH (Note 4) Latch−Up JEDEC Standard 17 100 mA
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 5 V ±10%, unless otherwise specified.)
Symbol Parameter Test Conditions
Limits
Units
Min Typ Max
ICC VCC Current (Operating, TTL) CE = OE = VIL,
f = 8 MHz, All I/O’s Open
30 mA
ICCC (Note 5) VCC Current (Operating, CMOS) CE = OE = VILC,
f = 8 MHz, All I/O’s Open
25 mA
ISB VCC Current (Standby, TTL) CE = VIH, All I/O’s Open 1 mA
ISBC (Note 6) VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 150 mA
ILI Input Leakage Current VIN = GND to VCC −10 10 mA
ILO Output Leakage Current VOUT = GND to VCC,
CE = VIH
−10 10 mA
VIH (Note 6) High Level Input Voltage 2 VCC + 0.3 V
VIL (Note 5) Low Level Input Voltage −0.3 0.8 V
VOH High Level Output Voltage IOH = −400 mA2.4 V
VOL Low Level Output Voltage IOL = 2.1 mA 0.4 V
VWI Write Inhibit Voltage 3.5 V
5. VILC = −0.3 V to +0.3 V.
6. VIHC = VCC −0.3 V to VCC + 0.3 V.
CAT28C256
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Table 4. MODE SELECTION
Mode CE WE OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE
Byte Write (CE Controlled) L H DIN ACTIVE
Standby and Write Inhibit H X X High−Z STANDBY
Read and Write Inhibit X H H High−Z ACTIVE
Table 5. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V)
Symbol Test Max Conditions Units
CI/O (Note 7) Input/Output Capacitance 10 VI/O = 0 V pF
CIN (Note 7) Input Capacitance 6 VIN = 0 V pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V ±10%, unless otherwise specified.)
Symbol Parameter
28C256−12 28C256−15
Units
Min Max Min Max
tRC Read Cycle Time 120 150 ns
tCE CE Access Time 120 150 ns
tAA Address Access Time 120 150 ns
tOE OE Access Time 50 70 ns
tLZ (Note 8) CE Low to Active Output 0 0 ns
tOLZ (Note 8) OE Low to Active Output 0 0 ns
tHZ (Notes 8, 9) CE High to High−Z Output 50 50 ns
tOHZ (Notes 8, 9) OE High to High−Z Output 50 50 ns
tOH (Note 8) Output Hold from Address Change 0 0 ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28C256
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Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.)
Symbol Parameter
28C256−12 28C256−15
Units
Min Max Min Max
tWC Write Cycle Time 5 5 ms
tAS Address Setup Time 0 0 ns
tAH Address Hold Time 50 50 ns
tCS CE Setup Time 0 0 ns
tCH CE Hold Time 0 0 ns
tCW (Note 10) CE Pulse Time 100 100 ns
tOES OE Setup Time 0 0 ns
tOEH OE Hold Time 0 0 ns
tWP (Note 10) WE Pulse Width 100 100 ns
tDS Data Setup Time 50 50 ns
tDH Data Hold Time 10 10 ns
tINIT (Note 11) Write Inhibit Period After Power−up 5 10 5 10 ms
tBLC (Notes 11, 12) Byte Load Cycle Time 0.1 100 0.1 100 ms
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within tBLC max. stops the timer.
Figure 2. A.C. Testing Input/Output Waveform (Note 13)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
0.0 V
VCC − 0.3 V
13.Input rise and fall times (10% and 90%) < 10 ns.
Figure 3. A.C. Testing Load Circuit (example)
1.3 V
DEVICE
UNDER
TEST
1N914
3.3 K
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
CAT28C256
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DEVICE OPERATION
Read
Data stored in the CAT28C256 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Figure 4. Read Cycle
ADDRESS
DATA OUT DATA VALIDDATA VALID
HIGH−Z
tOHZ
tHZ
tAA
tOH
tOE
tOLZ
tCE
tLZ
tRC
VIH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
ADDRESS
DATA OUT
DATA IN DATA VALID
HIGH−Z
WE
OE
CE
tAH
tAS
tCS tCH
tWP
tOES tOEH
tBLC
tDS tDH
tWC
CAT28C256
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Page Write
The page write mode of the CAT28C256 (essentially an
extended BYTE WRITE mode) allows from 1 to 64 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 64.
Following an initial WRITE operation (WE pulsed low,
for tWP
, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address and
data bytes into a 64 byte temporary buffer. The page address
where data is to be written, specified by bits A6 to A14, is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A0 to A5 (which can be loaded
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within tBLC MAX
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
Figure 6. Byte Write Cycle [CE Controlled]
ADDRESS
DATA OUT
DATA IN DATA VALID
HIGH−Z
WE
OE
CE
tAS tAH
tCS
tOES
tCW
tOEH
tCH
tBLC
tDS tDH
tWC
Figure 7. Page Mode Write Cycle
ADDRESS
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
WE
CE
OE
tWC
tBLC
tWP
CAT28C256
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8
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O6 are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature of the
CAT28C256, the device offers an additional method for
determining the completion of a write cycle. While a write
cycle is in progress, reading data from the device will result
in I/O6 toggling between one and zero. However, once the
write is complete, I/O6 stops toggling and valid data can be
read from the device.
Figure 8. DATA Polling
ADDRESS
I/O7
WE
OE
CE
DIN = X DOUT = X DOUT = X
tOEH tOE
tWC
tOES
Figure 9. Toggle Bit
tOES
tOE
tWC
tOEH
I/O6
OE
CE
WE
(Note 14) (Note 14)
14.Beginning and ending state of I/O6 is indeterminate.
CAT28C256
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9
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28C256.
1. VCC sense provides for write protection when VCC
falls below 3.5 V min.
2. A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 3.5 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Software Data Protection
The CAT28C256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28C256 is in the standard operating mode).
WRITE DATA: XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: A0
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 80
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
20
ADDRESS: 5555
Figure 10. Write Sequence for Activating
Software Data Protection
Figure 11. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
SOFTWARE DATA
PROTECTION ACTIVATED (Note 15)
15.Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max.,
after SDP activation.
CAT28C256
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To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
Figure 12. Software Data Protection Timing
Figure 13. Resetting Software Data Protection Timing
AA
5555
55
2AAA
A0
5555
DATA
ADDRESS
BYTE OR
PAGE
WRITES
ENABLED
AA
5555
55
2AAA
DATA
ADDRESS
80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
DEVICE
UNPROTECTED
CE
WE
tWC
CE
WE
tWP tBLC
tWC
CAT28C256
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PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
E1 E2E
PIN#1 IDENTIFICATION
D
D1
be
b1
D2
A2
A3
SIDE VIEW
TOP VIEW END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
SYMBOL MIN NOM MAX
A2
A3
b
b1
D
D1
D2
E
E1
e
E2
2.54
0.33
0.66
12.32
12.10
11.36
9.56
14.86
0.38
2.80
0.54
0.82
12.57
13.86
11.50
11.32
15.11
1.27 BSC
13.90 14.04
CAT28C256
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PACKAGE DIMENSIONS
TSOP 28, 8x13.4
CASE 318AE−01
ISSUE O
TOP VIEW
D
D1
PIN 1
e
L
L2
c
L1
b
A2
E1
SIDE VIEW
END VIEW
q1
A1
A
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-183.
SYMBOL MIN NOM MAX
q
θ
A
A1
A2
b
c
D
D1
E
e
L1
0° 5°
L2
0.05
0.90
0.17
0.10
0.675
13.20
11.70
7.90
0.55 BSC
0.25 BSC
1.20
0.15
1.05
0.27
0.20
13.60
11.90
8.10
13.40
11.80
8.00
θ1 10° 12° 16°
3°
1.00 1.10
1.00
0.22
0.15
L 0.30 0.700.50
CAT28C256
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13
PACKAGE DIMENSIONS
PDIP−28, 600 mils
CASE 646AE−01
ISSUE A
c
E1
D
ebb1
A2 A
A1 L
eB
SIDE VIEW
TOP VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
E
SYMBOL MIN NOM MAX
A
A1
A2
b
b1
c
D
e
E1
L
0.39
3.18
0.36
12.32
0.77
0.21
35.10
2.54 BSC
6.35
4.95
0.55
14.73
1.77
0.38
39.70
eB 15.24 17.78
E 15.24 15.87
2.93 5.08
CAT28C256
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Example of Ordering Information (Note 16)
Prefix Device # Suffix
Company ID
CAT 28C256 N
Product Number
28C256
I− 15 T
Package
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C) (Note 18)
Temperature Range
P: PDIP (Note 17)
N: PLCC (Note 17)
T13: TSOP (8 mm x 13.4 mm) (Note 17)
L: PDIP (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free) (Note 19)
T: Tape & Reel
Speed
12: 120 ns
15: 150 ns
Tape & Reel (Note 20)
(Optional)
16.The device used in the above example is a CAT28C256NI−15T (PLCC, Industrial Temperature, 150 ns Access Time, Tape & Reel).
17.Solder−plate (tin−lead) packages, contact Factory for availability.
18.−40°C to +125°C is available upon request.
19.For the TSOP package (H13), the orderable part number does not contain a hyphen, example: CAT28C256H13I15T.
20.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
CAT28C256/D
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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