1-/2-/4-Channel
Digital Potentiometers
AD8400/AD8402/AD8403
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.
FEATURES
256-position variable resistance device
Replaces 1, 2, or 4 potentiometers
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Power shutdown—less than 5 μA
3-wire,SPI-compatible serial data input
10 MHz update data loading rate
2.7 V to 5.5 V single-supply operation
Qualified for automotive applications
APPLICATIONS
Mechanical potentiometer replacement
Programmable filters, delays, time constants
Volume control, panning
Line impedance matching
Power supply adjustment
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single-, dual-, or
quad-channel, 256-position, digitally controlled variable resistor
(VR) device.1 These devices perform the same electronic adjust-
ment function as a mechanical potentiometer or variable
resistor. The AD8400 contains a single variable resistor in the
compact SOIC-8 package. The AD8402 contains two independent
variable resistors in space-saving SOIC-14 surface-mount
packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each
part contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by the digital code
loaded into the controlling serial input register. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. Each variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional
switched resistor designs, avoiding any make-before-break
or break-before-make operation.
(continued on Page 3)
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
FUNCTIONAL BLOCK DIAGRAM
8
8-BIT
LATCH
CK RS
8
8-BIT
LATCH
CK RS
8
8-BIT
LATCH
CK RS
8
8-BIT
LATCH
CK RS
DAC
SELECT
A1, A0
1
10-BIT
SERIAL
LATCH
CK RSQ
D
SDO SHDNRS
AD8403
V
DD
DGND
SDI
CLK
CS
8
2
3
2
4
RDAC1
W1
A1
B1
AGND1
RDAC2
W2
A2
B2
AGND2
RDAC3
W3
A3
B3
AGND3
RDAC4
W4
A4
B4
AGND4
SHDN
SHDN
SHDN
SHDN
0
1092-001
Figure 1.
CODE (Decimal)
100
75
50
25
00 64 128 192 255
R
WA
(D),
R
WB
(D) (% of Nominal R
AB
)
R
WA
R
WB
01092-002
Figure 2. RWA and RWB vs. Code
AD8400/AD8402/AD8403
Rev. E | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Electrical Characteristics—10 kΩ Version ................................ 4
Electrical Characteristics—50 kΩ and 100 kΩ Versions ......... 6
Electrical Characteristics—1 kΩ Version .................................. 8
Electrical Characteristics—All Versions ................................. 10
Timing Diagrams ........................................................................ 10
Absolute Maximum Ratings .......................................................... 11
Serial Data-Word Format .......................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 14
Test Circuits ..................................................................................... 19
Theory of Operation ...................................................................... 20
Programming the Variable Resistor ......................................... 20
Programming the Potentiometer Divider ............................... 21
Digital Interfacing ...................................................................... 21
Applications ..................................................................................... 24
Active Filter ................................................................................. 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 30
Automotive Products ................................................................. 31
REVISION HISTORY
7/10—Rev. D to Rev. E
Changes to Features Section ............................................................ 1
Changes to IAB Continuous Current Parameter (Table 5) ......... 11
Updated Outline Dimensions ........................................................ 26
Changes to Ordering Guide ........................................................... 30
Added Automotive Products Section ........................................... 31
10/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features ........................................................................... 1
Changes to Table 1 ............................................................................. 4
Changes to Table 2 ............................................................................. 6
Changes to Table 3 ............................................................................. 8
Changes to Table 5 ........................................................................... 11
Added Figure 36 ............................................................................... 18
Replaced Figure 37 .......................................................................... 19
Changes to Theory of Operation Section ..................................... 20
Changes to Applications Section ................................................... 24
Updated Outline Dimensions ........................................................ 26
Changes to Ordering Guide ........................................................... 28
11/01—Rev. B to Rev. C
Addition of new Figure ..................................................................... 1
Edits to Specifications ....................................................................... 2
Edits to Absolute Maximum Ratings .............................................. 6
Edits to TPCs 1, 8, 12, 16, 20, 24, 35 ............................................... 9
Edits to
the Programming the Variable Resistor Section .......................... 13
AD8400/AD8402/AD8403
Rev. E | Page 3 of 32
GENERAL DESCRIPTION
(continued from Page 1)
Each VR has its own VR latch that holds its programmed
resistance value. These VR latches are updated from an SPI-
compatible, serial-to-parallel shift register that is loaded from
a standard 3-wire, serial-input digital interface. Ten data bits
make up the data-word clocked into the serial input register.
The data-word is decoded where the first two bits determine
the address of the VR latch to be loaded, and the last eight bits
are the data. A serial data output pin at the opposite end of the
serial register allows simple daisy chaining in multiple VR
applications without additional external decoding logic.
The reset (RS) pin forces the wiper to midscale by loading 80H
into the VR latch. The SHDN pin forces the resistor to an end-
to-end open-circuit condition on the A terminal and shorts the
wiper to the B terminal, achieving a microwatt power shutdown
state. When SHDN is returned to logic high, the previous latch
settings put the wiper in the same resistance setting prior to
shutdown. The digital interface is still active in shutdown so
that code changes can be made that will produce new wiper
positions when the device is taken out of shutdown.
The AD8400 is available in the SOIC-8 surface mount. The
AD8402 is available in both surface-mount (SOIC-14) and
14-lead PDIP packages, while the AD8403 is available in a
narrow-body, 24-lead PDIP and a 24-lead, surface-mount
package. The AD8402/AD8403 are also offered in the 1.1 mm
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.
All parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +125°C.
AD8400/AD8402/AD8403
Rev. E | Page 4 of 32
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2 R-DNL RWB, VA = no connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −2 ±1/2 +2 LSB
Nominal Resistance3 R
AB T
A = 25°C, model: AD840XYY10 8 10 12 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 500 ppm/°C
Wiper Resistance RW V
DD = 5V, IW = VDD/RAB 50 100 Ω
R
W V
DD = 3V, IW = VDD/RAB 200 Ω
Nominal Resistance Match ∆R/RAB CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity4 INL −2 ±1/2 +2 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80H 15 ppm/°C
Full-Scale Error VWFSE Code = FFH −4 −2.8 0 LSB
Zero-Scale Error VWZSE Code = 00H 0 1.3 2 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, B, W 0 VDD V
Capacitance6 Ax, Capacitance Bx CA, B f = 1 MHz, measured to GND, code = 80H 75 pF
Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 120 pF
Shutdown Current7 I
A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH V
DD = 5 V 2.4 V
Input Logic Low VIL V
DD = 5 V 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Output Logic High VOH R
L = 2.2 kΩ to VDD V
DD − 0.1 V
Output Logic Low VOL I
OL = 1.6 mA, VDD = 5 V 0.4 V
Input Current IIL V
IN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) IDD V
IH = VDD or VIL = 0 V 0.01 5 µA
Supply Current (TTL)8 I
DD V
IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
Power Dissipation (CMOS)9 P
DISS V
IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
AD8400/AD8402/AD8403
Rev. E | Page 5 of 32
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB BW_10 K R = 10 kΩ 600 kHz
Total Harmonic Distortion THDW V
A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VW Settling Time tS V
A = VDD, VB = 0 V, ±1% error band 2 µs
Resistor Noise Voltage eNWB RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz
Crosstalk11 C
T V
A = VDD, VB = 0 V −65 dB
1 Typical represents average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
IW = 50 µA for VDD = 3 V and IW = 400 µA for VDD = 5 V for the 10 kΩ versions.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
AD8400/AD8402/AD8403
Rev. E | Page 6 of 32
ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2 R-DNL RWB, VA = No Connect −1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA = No Connect −2 ±1/2 +2 LSB
Nominal Resistance3 R
AB T
A = 25°C, Model: AD840XYY50 35 50 65 kΩ
R
AB T
A = 25°C, Model: AD840XYY100 70 100 130 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, Wiper = No Connect 500 ppm/°C
Wiper Resistance RW V
DD = 5V, IW = VDD/RAB 50 100 Ω
R
W V
DD = 3V, IW = VDD/RAB 200 Ω
Nominal Resistance Match ∆R/RAB CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C 0.2 1 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity4 INL −4 ±1 +4 LSB
Differential Nonlinearity4 DNL VDD = 5 V −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = 25°C −1 ±1/4 +1 LSB
DNL VDD = 3 V, TA = −40°C to +85°C −1.5 ±1/2 +1.5 LSB
Voltage Divider Tempco ∆VW/∆T Code = 80H 15 ppm/°C
Full-Scale Error VWFSE Code = FFH −1 −0.25 0 LSB
Zero-Scale Error VWZSE Code = 00H 0 +0.1 +1 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, VB, VW 0 VDD V
Capacitance6 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = 80H 15 pF
Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 80 pF
Shutdown Current7 I
A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH V
DD = 5 V 2.4 V
Input Logic Low VIL V
DD = 5 V 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Output Logic High VOH R
L = 2.2 kΩ to VDD V
DD − 0.1 V
Output Logic Low VOL I
OL = 1.6 mA, VDD = 5 V 0.4 V
Input Current IIL V
IN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) IDD V
IH = VDD or VIL = 0 V 0.01 5 µA
Supply Current (TTL)8 I
DD V
IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
Power Dissipation (CMOS)9 P
DISS V
IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10% 0.0002 0.001 %/%
PSS VDD = 3 V ± 10% 0.006 0.03 %/%
AD8400/AD8402/AD8403
Rev. E | Page 7 of 32
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB BW_50 K R = 50 kΩ 125 kHz
BW_100 K R = 100 kΩ 71 kHz
Total Harmonic Distortion THDW V
A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 %
VW Settling Time tS_50 K VA = VDD, VB = 0 V, ±1% error band 9 µs
t
S_100 K VA = VDD, VB = 0 V, ±1% error band 18 µs
Resistor Noise Voltage eNWB_50 K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz
e
NWB_100 K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz
Crosstalk11 C
T V
A = VDD, VB = 0 V −65 dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
AD8400/AD8402/AD8403
Rev. E | Page 8 of 32
ELECTRICAL CHARACTERISTICS—1 KΩ VERSION
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2 R-DNL RWB, VA = no connect −5 −1 +3 LSB
Resistor Nonlinearity2 R-INL RWB, VA = no connect −4 ±1.5 +4 LSB
Nominal Resistance3 R
AB T
A = 25°C, model: AD840XYY1 0.8 1.2 1.6 kΩ
Resistance Tempco ∆RAB/∆T VAB = VDD, wiper = no connect 700 ppm/°C
Wiper Resistance RW V
DD = 5V, IW = VDD/RAB 53 100 Ω
R
W V
DD = 3V, IW = VDD/RAB 200 Ω
Nominal Resistance Match ∆R/RAB CH 1 to CH 2, VAB = VDD, TA = 25°C 0.75 2 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution N 8 Bits
Integral Nonlinearity4 INL −6 ±2 +6 LSB
Differential Nonlinearity4 DNL VDD = 5 V −4 −1.5 +2 LSB
DNL VDD = 3 V, TA = 25°C −5 −2 +5 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H 25 ppm/°C
Full-Scale Error VWFSE Code = FFH −20 −12 0 LSB
Zero-Scale Error VWZSE Code = 00H 0 6 10 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, VB, VW 0 VDD V
Capacitance6 Ax, Bx CA, CB f = 1 MHz, measured to GND, code = 80H 75 pF
Capacitance6 Wx CW f = 1 MHz, measured to GND, code = 80H 120 pF
Shutdown Supply Current7 I
A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA
Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 50 100 Ω
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH V
DD = 5 V 2.4 V
Input Logic Low VIL V
DD = 5 V 0.8 V
Input Logic High VIH V
DD = 3 V 2.1 V
Input Logic Low VIL V
DD = 3 V 0.6 V
Output Logic High VOH R
L = 2.2 kΩ to VDD V
DD − 0.1 V
Output Logic Low VOL I
OL = 1.6 mA, VDD = 5 V 0.4 V
Input Current IIL V
IN = 0 V or 5 V, VDD = 5 V ±1 µA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD range 2.7 5.5 V
Supply Current (CMOS) IDD V
IH = VDD or VIL = 0 V 0.01 5 µA
Supply Current (TTL)8 I
DD V
IH = 2.4 V or 0.8 V, VDD = 5.5 V 0.9 4 mA
Power Dissipation (CMOS)9 P
DISS V
IH = VDD or VIL = 0 V, VDD = 5.5 V 27.5 µW
Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% 0.0035 0.008 %/%
PSS ∆VDD = 3 V ± 10% 0.05 0.13 %/%
AD8400/AD8402/AD8403
Rev. E | Page 9 of 32
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB BW_1 K R = 1 kΩ 5,000 kHz
Total Harmonic Distortion THDW V
A = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 %
VW Settling Time tS V
A = VDD, VB = 0 V, ±1% error band 0.5 µs
Resistor Noise Voltage eNWB RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz
Crosstalk11 C
T V
A = VDD, VB = 0 V −65 dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 µA for VDD = 3 V and
IW = 2.5 mA for VDD = 5 V for 1 kΩ version.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
AD8400/AD8402/AD8403
Rev. E | Page 10 of 32
ELECTRICAL CHARACTERISTICS—ALL VERSIONS
VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions Min Typ1 Max Unit
SWITCHING CHARACTERISTICS2, 3
Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns
Data Setup Time tDS 5 ns
Data Hold Time tDH 5 ns
CLK to SDO Propagation Delay4 t
PD R
L = 1 kΩ to 5 V, CL ≤ 20 pF 1 25 ns
CS Setup Time tCSS 10 ns
CS High Pulse Width tCSW 10 ns
Reset Pulse Width tRS 50 ns
CLK Fall to CS Rise Hold Time tCSH 0 ns
CS Rise to Clock Rise Setup tCS1 10 ns
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and
timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate
of 1 V/µs should be maintained.
4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section).
TIMING DIAGRAMS
DAC REGISTER LOAD
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
V
DD
0V
SDI
CLK
V
OUT
CS
01092-003
Figure 3. Timing Diagram
±1% ERROR BAND
±1%
t
CSH
t
CSS
t
DH
Ax O R DxAx OR Dx
t
PD_MIN
t
PD_MAX
A'x OR D'x A'x OR D'x
1
0
1
0
1
0
V
DD
0V
SDI
(DATA IN)
CLK
CS
V
OUT
1
0
SDO
(DATA OUT)
t
DS
t
CH
t
CS1
t
CL
t
S
t
CSW
01092-004
Figure 4. Detailed Timing Diagram
±1%
±1% ERROR BAND
1
0
V
DD
V
DD
/2
V
OUT
t
RS
t
S
RS
01092-005
Figure 5. Reset Timing Diagram
AD8400/AD8402/AD8403
Rev. E | Page 11 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V, +8 V
VA, VB, VW to GND 0 V, VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1 ±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA
IAB Continuous (RAB = 1 kΩ/10 kΩ/
50 kΩ/100 kΩ)1
±2.1 mA/±2.1 mA/
±540 A/±540 A
Digital Input and Output Voltage
to GND
0 V, 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature
(TJ Maximum)
150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Package Power Dissipation (TJ max − TA)/θJA
Thermal Resistance (θJA)
SOIC (R-8) 158°C/W
PDIP (N-14) 83°C/W
PDIP (N-24) 63°C/W
SOIC (R-14) 120°C/W
SOIC (R-24) 70°C/W
TSSOP-14 (RU-14) 180°C/W
TSSOP-24 (RU-24) 143°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
SERIAL DATA-WORD FORMAT
Table 6.
ADDR DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
29 2
8 2
7 2
0
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package; VDD = 5 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8400/AD8402/AD8403
Rev. E | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B1
1
GND
2
CS
3
SDI
4
A1
8
W1
7
V
DD
6
CLK
5
AD8400
TOP VIEW
(Not to Scale)
01092-006
Figure 6. AD8400 Pin Configuration
1
2
3
4
5
6
7
AD8402
B2
A2
W2
CS
SHDN
DGND
A
GND
14
13
12
11
10
9
8
A1
W1
V
DD
SDI
CLK
RS
B1
TOP VIEW
(Not to Scale)
01092-007
Figure 7. AD8402 Pin Configuration
A
GND2
1
B2
2
A2
3
W2
4
B1
24
A1
23
W1
22
AGND1
21
A
GND4
5
B4
6
A4
7
B3
20
A3
19
W3
18
W4
8
AGND3
17
DGND
9
V
DD
16
SHDN
10
RS
15
CS
11
CLK
14
SDI
12
SDO
13
AD8403
TOP VIEW
(Not to Scale)
01092-008
Figure 8. AD8403 Pin Configuration
Table 7. AD8400 Pin Function Descriptions
Pin No. Mnemonic Description
1 B1 Terminal B RDAC.
2 GND Ground.
3 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
4 SDI Serial Data Input.
5 CLK Serial Clock Input, Positive Edge Triggered.
6 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V.
7 W1 Wiper RDAC, Addr = 002.
8 A1 Terminal A RDAC.
Table 8. AD8402 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND Analog Ground.1
2 B2 Terminal B RDAC 2.
3 A2 Terminal A RDAC 2.
4 W2 Wiper RDAC 2, Addr = 012.
5 DGND Digital Ground.1
6 SHDN Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.
7 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
8 SDI Serial Data Input.
9 CLK Serial Clock Input, Positive Edge Triggered.
10 RS Active Low Reset to Midscale. Sets RDAC registers to 80H.
11 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V
12 W1 Wiper RDAC 1, Addr = 002.
13 A1 Terminal A RDAC 1.
14 B1 Terminal B RDAC 1.
1 All AGND pins must be connected to DGND.
AD8400/AD8402/AD8403
Rev. E | Page 13 of 32
Table 9. AD8403 Pin Function Descriptions
Pin No. Mnemonic Description
1 AGND2 Analog Ground 2.1
2 B2 Terminal B RDAC 2.
3 A2 Terminal A RDAC 2.
4 W2 Wiper RDAC 2, Addr = 012.
5 AGND4 Analog Ground 4.1
6 B4 Terminal B RDAC 4.
7 A4 Terminal A RDAC 4.
8 W4 Wiper RDAC 4, Addr = 112.
9 DGND Digital Ground.1
10 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4.
11 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded,
based on the address bits, and loaded into the target DAC register.
12 SDI Serial Data Input.
13 SDO Serial Data Output. Open drain transistor requires a pull-up resistor.
14 CLK Serial Clock Input, Positive Edge Triggered.
15 RS Active Low Reset to Midscale. Sets RDAC registers to 80H.
16 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V.
17 AGND3 Analog Ground 3.1
18 W3 Wiper RDAC 3, Addr = 102.
19 A3 Terminal A RDAC 3.
20 B3 Terminal B RDAC 3.
21 AGND1 Analog Ground 1.1
22 W1 Wiper RDAC 1, Addr = 002.
23 A1 Terminal A RDAC 1.
24 B1 Terminal B RDAC 1.
1 All AGND pins must be connected to DGND.
AD8400/AD8402/AD8403
Rev. E | Page 14 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
10
8
00 32 256
64 96 128 160 192 224
6
4
2
RESI S TANCE (kΩ)
R
WB
R
WA
V
DD
=3V OR5V
R
AB
= 10kΩ
01092-009
Figure 9. Wiper to End Terminal Resistance vs. Code
I
WB
CURRENT (mA)
V
WB
VOLTAGE (V)
5
4
0
3
2
1
80
H
40
H
20
H
FF
H
CODE = 10
H
05
H
01234567
T
A
=25°C
V
DD
=5V
01092-010
Figure 10. Resistance Linearity vs. Conduction Current
DIGITAL INPUT CODE (Decimal)
R-IN L E RRO R (LS B)
1.0
0.5
–1.0 0 32 256
64 96 128 160 192 224
0
–0.5
V
DD
=5V
T
A
=–40°CT
A
=+25°C
T
A
=+85°C
01092-011
Figure 11. Resistance Step Position Nonlinearity Error vs. Code
WIPER RESISTANCE (Ω)
FREQUEN
C
Y
60
48
040.0 42.5 65.045.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5
36
24
12
SS = 1205 UNITS
V
DD
=4.5V
T
A
=25°C
01092-012
Figure 12. 10 kΩ Wiper-Contact-Resistance Histogram
DIGITAL INPUT CODE (Decimal)
I NL NONLINEAR IT Y ERROR ( LS B )
1.0
0.5
–1.0 0 32 25664 96 128 160 192 224
0
–0.5
T
A
= –40°C
T
A
=+25°C
T
A
=+85°C
V
DD
=5V
01092-013
Figure 13. Potentiometer Divider Nonlinearity Error vs. Code
WIPER RESISTANCE (Ω)
FREQUEN
C
Y
60
48
035 37 5539 41 43 45 47 49 51 53
36
24
12
SS = 184 UNITS
V
DD
=4.5V
T
A
=25°C
01092-014
Figure 14. 50 kΩ Wiper-Contact-Resistance Histogram
AD8400/AD8402/AD8403
Rev. E | Page 15 of 32
WIPER RESISTANCE (Ω)
FREQUENCY
60
48
040.0 42.5 65.045.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5
36
24
12
SS = 184 UNITS
V
DD
=4.5V
T
A
=25°C
01092-015
Figure 15. 100 kΩ Wiper-Contact-Resistance Histogram
TEMPERATURE (°C)
NOMIN
A
L RESI STANCE (k
Ω
)
10
8
0–75 –50 125
–25 0 25 50 75 100
6
4
2
R
AB
(END-TO-END)
R
WB
(WIPER-TO-END)
CODE = 80
H
R
AB
=10kΩ
0
1092-016
Figure 16. Nominal Resistance vs. Temperature
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/
°
C)
70
60
–10 0 32 16064 96 128
30
20
10
0
50
40
192 224 256
V
DD
=5V
T
A
=–40°C/+85°C
V
A
=2V
V
B
=0V
01092-017
Figure 17. ΔVWB/ΔT Potentiometer Mode Tempco
CODE (Decimal)
RHEOS TAT M ODE TEMPCO (p pm/
°
C)
700
600
–100 0 32 16064 96 128
300
200
100
0
500
400
192 224 256
V
DD
=5V
T
A
= –40°C/+85°C
V
A
= NO CONNECT
R
WB
MEASURED
01092-018
Figure 18. ΔRWB/ΔT Rheostat Mode Tempco
500ns5V
20mV
R
W
(20mV/DIV)
CS
(5V/DIV)
TIME 500ns/DIV
01092-019
Figure 19. One Position Step Change at Half-Scale (Code 7FH to 80H)
FREQUENCY (Hz)
GAIN (dB)
6
0
–5410 1M100 1k 10k 100k
–6
–12
–48
–18
–24
–30
–36
–42
CODE = FF
80
40
20
10
08
04
02
01
TA=25°C
01092-020
Figure 20. 10 kΩ Gain vs. Frequency vs. Code
(See Figure 43)
AD8400/AD8402/AD8403
Rev. E | Page 16 of 32
HOURS OF OPE RATION AT 150 °C
ΔRWB RESI STANCE (%)
0.75
0.50
–0.75 0 600
100 300 400
0.25
–0.25
–0.50
200 500
0
AVERAGE + 2 SIGMA
AVERAGE
AVERAGE – 2 SIGMA
CODE = 80H
VDD =5V
SS = 158 UNITS
01092-021
Figure 21. Long-Term Drift Accelerated by Burn-In
5μs
5V
2V
OUTPUT
INPUT
TIME 500μs/DIV
01092-022
Figure 22. Large Signal Settling Time
FREQUENCY (Hz)
GAIN (dB)
0
–6
–48
1k 10k 1M
–30
–36
–42
–12
–24
–18
–54 100k
6CODE = FF
H
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
01092-023
Figure 23. 50 kΩ Gain vs. Frequency vs. Code
FREQUENCY (Hz)
THD + NOISE (%)
10
0.001 10 100k100 1k 10k
1
0.1
0.01
FILTER = 22kHz
V
DD
=5V
T
A
=25°C
01092-024
Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency
(See Figure 41 and Figure 42)
VOUT
(50mV/DIV)
TIME 200ns/DIV
200ns
50mV
45.25μs
01092-025
Figure 25. Digital Feedthrough vs. Time
FREQUENCY (Hz)
GAIN (dB)
0
–6
–48
1k 10k 1M
–30
–36
–42
–12
–24
–18
–54 100k
CODE = FF
H
6
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
01092-026
Figure 26. 100 kΩ Gain vs. Frequency vs. Code
AD8400/AD8402/AD8403
Rev. E | Page 17 of 32
FREQUENCY (Hz)
X
NORMALIZED GAIN FLAT NESS (0.1dB/DIV)
10 10k 1M100k100 1k
R=10kΩ
R = 100kΩ
R=50kΩ
CODE = 80
H
V
DD
=5V
T
A
=25°C
01092-027
Figure 27. Normalized Gain Flatness vs. Frequency
(See Figure 43)
DIGITAL INPUT VOLTAGE (V)
I
DD
– SUPPLY CURRENT (mA)
10
1
0.01
0.1
T
A
=25°C
V
DD
=5V
V
DD
=3V
01234
01092-028
5
Figure 28. Supply Current vs. Digital Input Voltage
FREQUENCY (Hz)
PSRR (dB)
80
0100 1M1k 10k 100k
60
40
20
V
DD
=+5VDC
±
1V p-p AC
T
A
=25
°
C
CODE = 80
H
C
L
= 10pF
V
A
=4V,V
B
=0V
01092-029
Figure 29. Power Supply Rejection Ratio vs. Frequency
(See Figure 40)
FREQUENCY (Hz)
GAIN (dB)
0
–6
1k 10k 1M
–30
–36
–42
–12
–24
–18
100k
6
12
V
IN
= 100mV rms
V
DD
=5V
R
L
=1M
Ω
f
–3dB
= 700kHz, R = 10k
Ω
f
–3dB
= 71kHz, R = 100k
Ω
f
–3dB
= 125kHz, R = 50k
Ω
01092-030
Figure 30. −3 dB Bandwidths
FREQUENCY (Hz)
I
DD
– SUPPLY CURRENT
(
μ
A)
1k 1M 10M10k 100k
1200
1000
800
600
400
200
0
AB
C
D
A: V
DD
=5.5V
CODE = 55
H
B: V
DD
=3.3V
CODE = 55
H
C: V
DD
=5.5V
CODE = FF
H
D: V
DD
=3.3V
CODE = FF
H
01092-031
TA=25
°
C
Figure 31. Supply Current vs. Clock Frequency
VBIAS (V)
R
ON
(
Ω)
160
0
140
80
60
40
20
120
100
0123456
T
A
=25
°
C
V
DD
=2.7V
V
DD
=5.5V
01092-032
Figure 32. AD8403 Incremental Wiper On Resistance vs. VDD
(See Figure 39)
AD8400/AD8402/AD8403
Rev. E | Page 18 of 32
FREQUENCY (Hz)
PHASE (Degrees)
100k 2M200k 1M
0
–10
–20
0
–45
–90
400k 4M 6M 10M
GAIN (dB)
VDD =5V
TA=25°C
WIPER SET AT
HALF-SCALE 80H
01092-033
Figure 33. 1 kΩ Gain and Phase vs. Frequency
TEMPERATURE (°C)
I
A
SHUTDOWN CURRENT (nA)
100
1
–55 –35
10
V
DD
=5V
–15 5 25 45 65 85 105 125
01092-034
Figure 34. Shutdown Current vs. Temperature
TEMPERATURE (°C)
I
DD
– SUPPLY CURRENT
(
μA)
1
0.1
0.001
–55 –35 –15 5 25 45 65 85 105 125
0.01
V
DD
=5.5V
V
DD
=3.3V
LOGIC INPUT
VOLTAGE = 0, V
DD
01092-035
Figure 35. Supply Current vs. Temperature
CODE (Decimal)
01092-057
0
3
2
1
4
5
6
0 32 64 96 128 160 192 224 256
THEORETICAL IWB_MAX (mA)
RAB = 1kΩ
VA= VB= OPEN
TA=25°C
RAB = 10kΩ
RAB = 50kΩ
RAB = 100kΩ
Figure 36. IWB_MAX vs. Code
AD8400/AD8402/AD8403
Rev. E | Page 19 of 32
TEST CIRCUITS
V+
DUT
V
MS
A
B
W
V+ = V
DD
1LSB = V+/256
01092-036
Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL)
DUT
V
MS
A
B
W
NO CONNECT
I
W
01092-037
Figure 38. Resistor Position Nonlinearity Error
(Rheostat Operations; R-INL, R-DNL)
AW
B
DUT
V
MS1
V
W
I
W
=V
DD
/R
NOMINAL
V
MS2
R
W
=[V
MS1
–V
MS2
]/I
W
01092-038
Figure 39. Wiper Resistance
V+ A
B
W
~
V
A
V
MS
V
DD
V+ = V
DD
±10%
PSRR (dB) = 20LOG ΔV
MS
ΔV
DD
PSS (%/%) = ΔV
MS
%
ΔV
DD
%
()
01092-039
Figure 40. Power Supply Sensitivity (PSS, PSRR)
A
V
IN
2.5V DC
OP279
5V V
OUT
~
DUT
W
OFFSET
GND
B
01092-040
Figure 41. Inverting Programmable Gain
~
A
VIN
2.5V
OP279
5
V
V
OUT
DUT
W
OFFSET
GND B
01092-041
Figure 42. Noninverting Programmable Gain
~
B
A
V
IN
2.5V
+15V
V
OUT
DUT W
–15V
O
FFSET
GND
OP42
01092-042
Figure 43. Gain vs. Frequency
DUT
I
SW
B
W
V
BIAS
R
SW
=0.1
V
I
SW
CODE =
0.1V
A=NC
+
–
01092-043
H
Figure 44. Incremental On Resistance
AD8400/AD8402/AD8403
Rev. E | Page 20 of 32
THEORY OF OPERATION
The AD8400/AD8402/AD8403 provide a single, dual, and quad
channel, 256-position, digitally controlled variable resistor (VR)
device. Changing the programmed VR setting is accomplished
by clocking in a 10-bit serial data-word into the SDI (Serial
Data Input) pin. The format of this data-word is two address
bits, MSB first, followed by eight data bits, also MSB first.
Table 6 provides the serial register data-word format. The
AD8400/AD8402/AD8403 have the following address assign-
ments for the ADDR decoder, which determines the location
of the VR latch receiving the serial register data in Bit B7 to
Bit B0:
VR# = A1 × 2 + A0 + 1 (1)
The single-channel AD8400 requires A1 = A0 = 0. The dual-
channel AD8402 requires A1 = 0. VR settings can be changed
one at a time in random sequence. A serial clock running at
10 MHz makes it possible to load all four VRs under 4 μs
(10 × 4 × 100 ns) for AD8403. The exact timing requirements
are shown in Figure 3, Figure 4, and Figure 5.
The AD8400/AD8402/AD8403 do not have power-on midscale
preset, so the wiper can be at any random position at power-up.
However, the AD8402/AD8403 can be reset to midscale by
asserting the RS pin, simplifying initial conditions at power-up.
Both parts have a power shutdown SHDN pin that places the
VR in a zero-power-consumption state where Terminal Ax is
open-circuited and the Wiper Wx is connected to Terminal Bx,
resulting in the consumption of only the leakage current in the
VR. In shutdown mode, the VR latch settings are maintained
so that upon returning to the operational mode, the VR settings
return to the previous resistance values. The digital interface is
still active in shutdown, except that SDO is deactivated. Code
changes in the registers can be made during shutdown that will
produce new wiper positions when the device is taken out of
shutdown.
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Ax
Wx
Bx
R
S
=R
NOMINAL
/256
R
S
SHDN
R
S
R
S
R
S
01092-044
Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the VR (RDAC) between Terminal A
and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ. The final digits of the part number determine the
nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100.
The nominal resistance (RAB) of the VR has 256 contact points
accessible by the wiper terminal, and the resulting resistance
can be measured either across the wiper and B terminals (RWB)
or across the wiper and A terminals (RWA). The 8-bit data-word
loaded into the RDAC latch is decoded to select one of the
256 possible settings. The wiper’s first connection starts at the
B terminal for data 00H. This B terminal connection has a wiper
contact resistance of 50 Ω. The second connection (for the 10 kΩ
part) is the first tap point located at 89 Ω = [RAB (nominal
resistance) + RW = 39 Ω + 50 Ω] for data 01H. The third
connection is the next tap point representing 78 Ω + 50 Ω =
128 Ω for data 02H. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
10,011 Ω. Note that the wiper does not directly connect to the
B terminal even for data 00H. See Figure 45 for a simplified
diagram of the equivalent RDAC circuit.
The AD8400 contains one RDAC, the AD8402 contains
two independent RDACs, and the AD8403 contains four
independent RDACs. The general transfer equation that
determines the digitally programmed output resistance
between Wx and Bx is
()
WABWB RR
D
DR +×= 256 (2)
where D, in decimal, is the data loaded into the 8-bit RDAC#
latch, and RAB is the nominal end-to-end resistance.
For example, when the A terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following RWB (for the 10 kΩ version):
Table 10.
D (Dec) RWB (Ω) Output State
255 10,011 Full scale
128 5,050
Midscale (RS = 0 condition)
1 89 1 LSB
0 50 Zero-scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
50 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
AD8400/AD8402/AD8403
Rev. E | Page 21 of 32
Like a mechanical potentiometer, RDAC is symmetrical. The
resistance between the Wiper W and Terminal A also produces
a digitally controlled complementary resistance, RWA. When
these terminals are used, the B terminal can be tied to the wiper
or left floating. RWA starts at the maximum and decreases as the
data loaded into the RDAC latch increases. The general transfer
equation for this RWA is
()
WABWA RR
D
DR +×
−
=256
256 (3)
where D is the data loaded into the 8-bit RDAC# latch, and RAB
is the nominal end-to-end resistance.
For example, when the B terminal is either open-circuited or
tied to the Wiper W, the following RDAC latch codes result in
the following RWA (for the 10 kΩ version):
Table 11.
D (Dec) RWA (Ω) Output State
255 89 Full-Scale
128 5,050
Midscale (RS = 0 Condition)
1 10,011 1 LSB
0 10,050 Zero-Scale
The typical distribution of RAB from channel to channel
matches within ±1%. However, device-to-device matching
is process lot dependent and has a ±20% variation. The tem-
perature coefficient, or the change in RAB with temperature,
is 500 ppm/°C.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not con-
tribute any significant temperature related errors. The graph in
Figure 18 shows the performance of RWB tempco vs. code. Using
the potentiometer with codes below 32 results in the larger
temperature coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting the A terminal to 5 V and the B termi-
nal to ground produces an output voltage at the wiper starting
at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage
applied across the A to B terminals divided by the 256-position
resolution of the potentiometer divider. The general equation
defining the output voltage with respect to ground for any given
input voltage applied to the A to B terminals is
BABW VV
D
V+×= 256 (4)
Operation of the digital potentiometer in the voltage divider
mode results in more accurate operation over temperature.
Here the output voltage is dependent on the ratio of the internal
resistors, not the absolute value; therefore, the temperature drift
improves to 15 ppm/°C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases because the contribution of
the CMOS switch wiper resistance becomes an appreciable
portion of the total resistance from the B terminal to the
Wiper W. See Figure 17 for a plot of potentiometer tempco
performance vs. code setting.
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contain a standard SPI-
compatible, 3-wire, serial input control interface. The three
inputs are clock (CLK), chip select (CS), and serial data input
(SDI). The positive-edge sensitive CLK input requires clean
transitions to avoid clocking incorrect data into the serial input
register. For the best result, use logic transitions faster than
1 V/μs. Standard logic families work well. If mechanical switches
are used for product evaluation, they should be debounced by
a flip-flop or other suitable means. The block diagrams in
, , and show the internal digital
circuitry in more detail. When
Figure 46 Figure 47 Figure 48
CS is taken active low, the clock
loads data into the 10-bit serial register on each positive clock
edge (see ). Table 12
RDAC
LATCH
NO. 1
GND
A1
W1
B1
V
DD
AD8400
CS
CLK
8
D7
D0
EN
ADDR
DEC
A1
A0
SDI DI D0
D7
10-BIT
SER
REG
0
1092-045
Figure 46. AD8400 Block Diagram
RDAC
LATCH
NO. 1
R
AGND
RS
A1
W1
B1
VDD
AD8402
CS
CLK D7
D0
RDAC
LATCH
NO. 2
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
SDI DI
10-BIT
SER
REG
D0
S
HDN
DGND
D7
8
01092-046
Figure 47. AD8402 Block Diagram
AD8400/AD8402/AD8403
Rev. E | Page 22 of 32
RDAC
LATCH
NO. 1
R
AGND
RS
A1
W1
B1
V
DD
AD8403
CS
CLK
SDO
D7
D0
RDAC
LATCH
NO. 4
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
D7
SDI
DO
DI
SER
REG
D0
SHDN
DGND
8
01092-047
Figure 48. AD8403 Block Diagram
Table 12. Input Logic Control Truth Table1
CLK CS RS SHDN Register Activity
L L H H No SR effect; enables SDO pin
P L H H Shift one bit in from the SDI pin. The
10th previously entered bit is shifted
out of the SDO pin.
X P H H Load SR data into RDAC latch based
on A1, A0 decode (Table 13).
X H H H No operation
X X L H Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared
X H P H Latches all RDAC latches to 80H
X H H L Open-circuits all Resistor A terminals,
connects W to B, turns off SDO
output transistor.
1 P = positive edge, X = don’t care, SR = shift register
The serial data output (SDO) pin, which exists only on the
AD8403 and not on the AD8400 or AD8402, contains an
open-drain, n-channel FET that requires a pull-up resistor to
transfer data to the SDI pin of the next package. The pull-up
resistor termination voltage may be larger than the VDD supply
(but less than the max VDD of 8 V) of the AD8403 SDO output
device. For example, the AD8403 could operate at VDD = 3.3 V,
and the pull-up for interface to the next device could be set at 5 V.
This allows for daisy-chaining several RDACs from a single proc-
essor serial data line. The clock period needs to be increased
when using a pull-up resistor to the SDI pin of the following
device in the series. Capacitive loading at the daisy-chain node
SDO to SDI between devices must be accounted for in order to
transfer data successfully. When daisy chain is used, CS should
be kept low until all the bits of every package are clocked into
their respective serial registers and the address and data bits are
in the proper decoding location.
If two AD8403 RDACs are daisy-chained, it requires 20 bits
of address and data in the format shown in Table 6. During
shutdown (SHDN = logic low), the SDO output pin is forced
to the off (logic high) state to disable power dissipation in the
pull-up resistor. See for equivalent SDO output circuit
schematic.
Figure 50
The data setup and hold times in the specification table deter-
mine the data valid time requirements. The last 10 bits of the
data-word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four (AD8403)
positive edge-triggered RDAC latches. See and . Figure 49 Table 13
Table 13. Address Decode Table
A1 A0 Latch Decoded
0 0 RDAC#1
0 1 RDAC#2
1 0 RDAC#3 AD8403 Only
1 1 RDAC#4 AD8403 Only
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4
SERIAL
REGISTER
A
D8403
SDI
CLK
CS
0
1092-048
Figure 49. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data-word completing one RDAC update. In the case of
AD8403, four separate 10-bit data-words must be clocked in to
change all four VR settings.
SERIAL
REGISTER
SDI
CK RS
D
SHDN
CS
CLK
RS
SDO
0
1092-049
Q
Figure 50. Detailed SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 51. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, and CLK. The
digital input ESD protection allows for mixed power supply
applications where 5 V CMOS logic can be used to drive an
AD8400, AD8402, or AD8403 operating from a 3 V power
supply. Analog Pin A, Pin B, and Pin W are protected with a
20 Ω series resistor and parallel Zener diode (see ). Figure 52
AD8400/AD8402/AD8403
Rev. E | Page 23 of 32
1kΩ
DIGITAL
PINS LOGIC
01092-050
Figure 51. Equivalent ESD Protection Circuits
20
Ω
A
,B,W
01092-051
Figure 52. Equivalent ESD Protection Circuit (Analog Pins)
A
C
A
C
B
W
RD
A
C
10kΩB
C
W
120pF
C
A
= 90.4pF (DW/256) + 30pF C
B
= 90.4pF [1 – (DW/256)] + 30pF
01092-052
Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ
The AC characteristics of the RDAC are dominated by the
internal parasitic capacitances and the external capacitive loads.
The −3 dB bandwidth of the AD8403AN10 (10 kΩ resistor)
measures 600 kHz at half scale as a potentiometer divider.
Figure 30 provides the large signal Bode plot characteristics
of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ.
The gain flatness vs. frequency graph of the 1 kΩ version predicts
filter applications performance (see Figure 33). A parasitic
simulation model has been developed and is shown in Figure 53.
Listing I provides a macro model net list for the 10 kΩ RDAC.
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD + N), shown in
Figure 41, is measured at 0.003% in an inverting op amp circuit
using an offset ground and a rail-to-rail OP279 amplifier.
Thermal noise is primarily Johnson noise, typically 9 nV/√Hz
for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device,
thermal noise becomes 29 nV/√Hz. Channel-to-channel
crosstalk measures less than −65 dB at f = 100 kHz. To achieve
this isolation, the extra ground pins provided on the package to
segregate the individual RDACs must be connected to circuit
ground. AGND and DGND pins should be at the same voltage
potential. Any unused potentiometers in a package should be
connected to ground. Power supply rejection is typically −35 dB
at 10 kHz. Care is needed to minimize power supply ripple in
high accuracy applications.
AD8400/AD8402/AD8403
Rev. E | Page 24 of 32
APPLICATIONS
INVERTING GAIN (V/V)
256
128
0
0.1 1 10
96
64
32
160
192
224
DIG I TAL CODE (Deci mal)
01092-053
The digital potentiometer (RDAC) allows many of the applica-
tions of a mechanical potentiometer to be replaced by a solid-
state solution offering compact size and freedom from vibration,
shock, and open contact problems encountered in hostile
environments. A major advantage of the digital potentiometer
is its programmability. Any settings can be saved for later recall
in system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and
the rheostat (2-terminal configuration) connections shown
in Figure 37 and Figure 38.
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the GND to VDD range used to operate the
single-supply AD8400/AD8402/AD8403. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with
a suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications,
a virtual ground is generally needed. Whichever method is used
to create the virtual ground, the result must provide the necessary
sink and source current for all connected loads, including
adequate bypass capacitance. Figure 41 shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a ±2.5 V range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80H) toward the A terminal (code FFH), the
voltage gain of the circuit is increased in successively larger
increments. Alternatively, as the wiper is adjusted toward the B
terminal (code 00H), the signal becomes attenuated. The plot in
Figure 54 shows the wiper settings for a 100:1 range of voltage
gain (V/V). Note the ±10 dB of pseudologarithmic gain around
0 dB (1 V/V). This circuit is mainly useful for gain adjustments
in the range of 0.14 V/V to 4 V/V; beyond this range the step
sizes become very large, and the resistance of the driving circuit
can become a significant term in the gain equation.
Figure 54. Inverting Programmable Gain Plot
ACTIVE FILTER
The state variable active filter is one of the standard circuits
used to generate a low-pass, high-pass, or band-pass filter.
The digital potentiometer allows full programmability of the
frequency, gain, and Q of the filter outputs. Figure 55 shows
the filter circuit using a 2.5 V virtual ground, which allows a
±2.5 VP input and output swing. RDAC2 and RDAC3 set the
LP, HP, and BP cutoff and center frequencies, respectively.
These variable resistors should be programmed with the same
data (as with ganged potentiometers) to maintain the best
Circuit Q. Figure 56 shows the measured filter response at the
band-pass output as a function of the RDAC2 and RDAC3
settings that produce a range of center frequencies from 2 kHz
to 20 kHz. The filter gain response at the band-pass output is
shown in Figure 57. At a center frequency of 2 kHz, the gain is
adjusted over a −20 dB to +20 dB range determined by RDAC1.
Circuit Q is adjusted by RDAC4. For more detailed reading on
the state variable active filter, see Analog Devices’ application
note AN-318.
A1
RDAC1
V
IN
BA2 A3 A4
RDAC4
B
10kΩ
10kΩ
OP279 ×2
RDAC2 RDAC3
BB
0.01μF0.01μF
BAND-
PASS
HIGH-
PASS
LOW-
PASS
0
1092-054
Figure 55. Programmable State Variable Active Filter
AD8400/AD8402/AD8403
Rev. E | Page 25 of 32
FREQUENCY (Hz)
40
20
–8020 100k100 1k 10k
0
–20
–40
–60
200k
AMPLIT UDE (d B)
–0.16 20.0000 k
01092-055
Figure 56. Programmed Center Frequency Band-Pass Response
FREQUENCY (Hz)
40
20
–8020 100k100 1k 10k
0
–20
–40
–60
200k
AMPL ITUDE ( dB)
–19.01 2.00000 k
01092-056
Figure 57. Programmed Amplitude Band-Pass Response
AD8400/AD8402/AD8403
Rev. E | Page 26 of 32
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 58. 8-Lead Standard Small outline package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COM PLI ANT TO JE DE C S TANDARDS MS-001
CONT ROLLING DIM E NS IONS ARE IN INCHES; M IL L IMETER DIMENS IONS
(IN PARENTHESES) ARE RO UNDED- OF F INCH EQ UIVALENTS FO R
REFERENCE ONLY AND ARE NOT APPRO PRIATE FOR USE IN DESIGN.
CORNER L E ADS MAY BE CONFI GURED AS WHOLE O R HALF LEADS.
070606-A
0.022 ( 0 .56)
0.018 ( 0 .46)
0.014 ( 0 .36)
0.150 (3.81)
0.130 (3.30)
0.110 (2. 79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 ( 2 .54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 ( 0 .38)
GAUGE
PLANE
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0 .13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2. 92)
Figure 59. 14-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-14)
Dimensions shown in inches and (millimeters)
AD8400/AD8402/AD8403
Rev. E | Page 27 of 32
CONTROL LI NG DIM E NSIO NS ARE IN M ILLI M E TERS; INCH DIM E NSIONS
(I N PARENTHES E S ) ARE ROUNDED-O FF MILLIMETER E QUIVALENTS FOR
REFE RE NCE ONLYAND ARE NOT APPROPRIATE FO R USE I N DESIGN.
COMP LI ANT TO JE DEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 60. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
COMP LI ANT TO JEDE C S TANDARDS MO -153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8400/AD8402/AD8403
Rev. E | Page 28 of 32
CONT ROLLING DIMENSI ONS ARE IN INCHES; MILLIMETER DI M E NS IONS
(IN PARENTHESES) ARE RO UNDE D- OFF INCH E QUI VALENT S FO R
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CO NFIGURED AS WHOLE O R HALF LEADS.
COM PLI ANT TO JE DE C S TANDARDS MS-001
071006-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2. 92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
112
13
0.100 ( 2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0 .13)
MIN
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.060 ( 1 .52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 62. 24-Lead Plastic Dual-In-Line Package [PDIP]
Narrow Body (N-24-1)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24 13
12
1
1.27 (0.0500)
BSC
06-07-2006-A
Figure 63. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-24)
Dimensions shown in millimeters and (inches)
AD8400/AD8402/AD8403
Rev. E | Page 29 of 32
24 13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC 1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
AD8400/AD8402/AD8403
Rev. E | Page 30 of 32
ORDERING GUIDE
Model1, 2, 3
Number of
Channels
End-to-End
RAB (kΩ)
Temperature
Range (°C)
Package
Description
Package
Option Ordering
Quantity Branding Information
AD8400AR10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10
AD8400AR10-REEL 1 10 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A10
AD8400ARZ10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10
AD8400ARZ10-REEL 1 10 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A10
AD8400AR50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50
AD8400AR50-REEL 1 50 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A50
AD8400ARZ50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50
AD8400ARZ50-REEL 1 50 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A50
AD8400AR100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC
AD8400AR100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC
AD8400ARZ100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC
AD8400ARZ100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC
AD8400AR1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1
AD8400AR1-REEL 1 1 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A1
AD8400ARZ1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1
AD8400ARZ1-REEL 1 1 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A1
AD8402AN10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10
AD8402ANZ10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10
AD8402AR10 2 10 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A10
AD8402AR10-REEL 2 10 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A10
AD8402ARU10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10
AD8402ARU10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10
AD8402ARUZ10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10
AD8402ARUZ10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10
AD8402ARZ10 2 10 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A10
AD8402ARZ10-REEL 2 10 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A10
AD8402AR50 2 50 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A50
AD8402AR50-REEL 2 50 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A50
AD8402ARU50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50
AD8402ARU50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50
AD8402ARUZ50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50
AD8402ARUZ50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50
AD8402ARZ50 2 50 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A50
AD8402ARZ50-REEL 2 50 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A50
AD8402AR100 2 100 −40 to +125 14-Lead SOIC_N R-14 56 AD8402AC
AD8402AR100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC
AD8402ARU100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C
AD8402ARU100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C
AD8402ARUZ100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C
AD8402ARUZ100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C
AD8402ARZ100 2 100 −40 to +125 14-Lead SOIC_N R-14 96 AD8402AC
AD8402ARZ100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC
AD8402AR1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1
AD8402AR1-REEL 2 1 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A1
AD8402ARU1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 8402A1
AD8402ARUZ1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 AD8402A1
AD8402ARUZ1-REEL 2 1 −40 to +125 14-Lead TSSOP RU-14 2,500 AD8402A1
AD8402ARZ1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1
AD8402ARZ1-REEL 2 1 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A1
AD8400/AD8402/AD8403
Rev. E | Page 31 of 32
Model1, 2, 3
Number of
Channels
End-to-End
RAB (kΩ)
Temperature
Range (°C)
Package
Description
Package
Option Ordering
Quantity Branding Information
AD8403AN10 4 10 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A10
AD8403AR10 4 10 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A10
AD8403AR10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A10
AD8403ARU10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10
AD8403ARU10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10
AD8403ARUZ10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10
AD8403ARUZ10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10
AD8403ARZ10 4 10 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A10
AD8403ARZ10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A10
AD8403AN50 4 50 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A50
AD8403AR50 4 50 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A50
AD8403AR50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A50
AD8403ARU50 4 50 −40 to +125 24-Lead TSSOP RU-24 63 8403A50
AD8403ARUZ50 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50
AD8403ARUZ50-REEL 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50
AD8403ARZ50 4 50 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A50
AD8403ARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A50
AD8403AR100 4 100 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A100
AD8403AR100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A100
AD8403ARU100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100
AD8403ARU100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100
AD8403ARUZ100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100
AD8403ARUZ100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100
AD8403ARZ100 4 100 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A100
AD8403ARZ100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A100
AD8403AR1 4 1 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A1
AD8403AR1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A1
AD8403ARU1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1
AD8403ARU1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1
AD8403ARUZ1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1
AD8403ARUZ1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1
AD8403ARZ1 4 1 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A1
AD8403ARZ1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A1
AD8403WARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500
EVAL-AD8403SDZ Evaluation Board
1 Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of
production and WW is the work week. For example, a non-lead-free part manufactured in the 30th work week of 2005 has the date code of either 530 or 0530, while a
lead-free part has the date code of #530.
2 Z = RoHS Compliant Part.
3 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8403W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
AD8400/AD8402/AD8403
Rev. E | Page 32 of 32
NOTES
© 2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01092-0-7/10(E)
