3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06056 Rev. *C Revised March 25, 2009
Features
■True dual-ported memory cells that allow simultaneous access
of the same memory location
■Six flow through/pipelined devices:
❐16K x 16/18 organization (CY7C09269V/369V)
❐32K x 16/18 organization (CY7C09279V/379V)
❐64K x 16/18 organization (CY7C09289V/389V)
■Three modes:
❐Flow through
❐Pipelined
❐Burst
■Pipelined output mode on both ports allows fast 100 MHz
operation
■0.35 micron CMOS for optimum speed and power
■High speed clock to data access: 6.5[1, 2], 7.5[2], 9, 12 ns (max)
■3.3V low operating power:
❐Active = 115 mA (typical)
❐Standby = 10 μA (typical)
■Fully synchronous interface for easier operation
■Burst counters increment addresses internally:
❐Shorten cycle times
❐Minimize bus noise
❐Supported in flow through and pipelined modes
■Dual chip enables easy depth expansion
■Upper and lower byte controls for bus matching
■Automatic power down
■Commercial and industrial temperature ranges
■Pb-Free 100-pin TQFP package available
Logic Block Diagram
R/
W
L
1
0
0/1
CE
0L
CE
1L
LB
L
OE
L
UB
L
1b
0/1 0b 1a 0a
ba
FT
/Pipe
L
I/O
8/9L
–I/O
15/17L
I/O
0L
–I/O
7/8L
I/O
Control
Counter/
Address
Register
Decode
A
0L
–A
13/14/15L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True Dual-Ported
RAM Array
R/
W
R
1
0
0/1
CE
0R
CE
1R
LB
R
OE
R
UB
R
1b0/1
0b1a0a ba FT
/Pipe
R
I/O
Control
Counter/
Address
Register
Decode
14/15/16
8/9
8/9 I/O
8/9R
–I/O
15/17R
I/O
0R
–I/O
7/8R
A
0R
–A
13/14/15R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
14/15/16
8/9
8/9
[3]
[4]
[3]
[4]
[5] [5]
Notes
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
4. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
5. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 2 of 19
Pinouts
Figure 1. 100-Pin TQFP (Top View)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
ADSR
A0R
A1R
A0L
A2L
CLKR
CNTENR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C09289V (64K x 16)
[6]
[7]
[8] [8]
[6]
[7]
Notes
6. This pin is NC for CY7C09269V.
7. This pin is NC for CY7C09269V and CY7C09279V.
8. For CY7C09269V and CY7C09279V , pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible
to an IDT 5V x16 flow through device.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 3 of 19
Figure 2. 100-Pin TQFP (Top View)
Selection Guide
Specifications CY7C09269V/79V/89V
CY7C09369V/79V/89V
-6[1, 2]
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-7[2]
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-9
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-12
fMAX2 (MHz) (Pipelined) 100 83 67 50
Max. Access Time (ns)
(Clock to Data, Pipelined) 6.5 7.5 9 12
Typical Operating Current
ICC (mA) 175 155 135 115
Typical Standby Current for
ISB1 (mA)
(Both Ports TTL Leve l)
25 25 20 20
Typical Standby Current for
ISB3 (μA)
(Both Ports CMOS Level)
10 10 10 10
Pinouts (continued)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
A13R
CE0R
A15R
UBR
CNTRSTR
R/WR
FT/PIPER
I/O17R
LBR
A14R
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
A9L
A10L
A11L
A12L
A13L
A14L
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
A15L
VCC
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
CNTRSTL
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
GND
CNTENR
A0R
A0L
A2L
ADSR
CLKR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
I/10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
CY7C09389V (64K x 18)
[9]
[10]
[9]
[10]
Notes
9. This pin is NC for CY7C09369V.
10.This pin is NC for CY7C09369V and CY7C09379V.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 4 of 19
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory[11]. Registers on control, address, and data
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid tCD2 = 6.5 ns[1, 2] (pipeli ned). Flow thro ugh mode can also
be used to bypass the pipelined output register to eliminate
access latency. In flow through mo de, data is available tCD1 =
18 ns after the address is clocked into the device. Pipelined
output or flow through mode is selected through the FT/Pipe pin.
Each port contains a burst counter on the input address register .
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
Counter enable inputs are prov ided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one wo rd from or into
each successive address location, until CNTEN is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST) is used to reset the burst
counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Definitions
Left Port Right Port Description
A0L–A15L A0R–A15R Address Inputs (A0–A14 for 32K, A0–A13 for 16K devices).
ADSLADSRAddress Strobe Inpu t. Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pin s .
CE0L, CE1L CE0R,CE1R Chip Enable Input. To select either the l eft or right port, both CE0 AND CE1 must be asserted to their
active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enabl e Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW .
CNTRSTLCNTRSTRCounter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBLLBRLower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower
byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both the LB and
OE signals must be asserted to drive output data on the lower byte of the data pins.
UBLUBRUpper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OELOEROutput Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WLR/WRRead/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPELFT/PIPERFlow Through/Pipelined Select Input. For flow through mo de operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
Note
11. When writing simultaneo usly to the same location, the final value cannot be guaranteed.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 5 of 19
Maximum Ratings [12]
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State..............................................−0.5V to VCC+0.5V
DC Input Voltage..........................................−0.5V to VCC+0.5V
Output Current into Outputs (LOW).......... ... .............. ..20 mA
Static Discharge Voltage.......................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial –40°C to +85°C 3.3V ± 300 mV
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/79V/89V Unit
-6[1, 2] -7[2] -9 -12
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage
(VCC = Min. lOH = –4.0 mA) 2.4 2.4 2.4 2.4 V
VOL Output LOW V oltage
(VCC = Min. lOH = +4.0 mA) 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 –10 10 –10 10 μA
ICC Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Com’l. 175 320 155 275 135 230 115 180 mA
Indust. 275 390 185 300 mA
ISB1 Standby Current
(Both Ports TTL Level)[13]
CEL & CER ≥ VIH, f = fMAX
Com’l. 25 95 25 85 20 75 20 70 mA
Indust. 85 120 35 85 mA
ISB2 Standby Current
(One Port TTL Level)[13]
CEL | CER ≥ VIH, f = fMAX
Com’l. 115 175 105 165 95 155 85 140 mA
Indust. 165 210 105 165 mA
ISB3 Standby Current
(Both Ports CMOS Level)[13]
CEL & CER ≥ VCC – 0.2V , f = 0
Com’l. 10 250 10 250 10 250 10 250 μA
Indust. 10 250 10 250 μA
ISB4 Standby Current
(One Port CMOS Level)[13]
CEL | CER ≥ VIH, f = fMAX
Com’l. 105 135 95 125 85 115 75 100 mA
Indust. 125 170 95 125 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 10 pF
COUT Output Capacitance 10 pF
Notes
12.The voltage on any i nput or I/O pin can not exceed the power pin during power up.
13.CEL and CER are internal signals. To select either the left or right port, both CE0 and C E1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 6 of 19
Figure 3. AC Test Loads and Waveforms
Figure 4. AC Test Loads (Applicable to -6 and -7 only) [14]
(a) Normal Load (Load 1)
R1= 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c)Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
RTH =250Ω
(Used for tCKLZ, tOLZ, and tOHZ
including scope and jig)
V
TH
=1.4V
OUTPUT
C
(a) Load 1 (-6 and -7 only)
R = 50
Ω
Z
0
= 50
Ω
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
≤≤
0.00
0.1 0
0.20
0.30
0.40
0.50
0.60
530352025101
(b) Load Derating Curve
Capacitance (pF)
'
(ns) for all -7 access times
Note
14.Test Conditions: C = 10 pF.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 7 of 19
Switching Characteristics
Over the Operating Range
Parameter Description
CY7C09269V/79V/89V
CY7C09369V/79V/89V Unit
-6 [1, 2] -7[2] -9 -12
Min Max Min Max Min Max Min Max
fMAX1 fMax Flow Through 53 45 40 33 MHz
fMAX2 fMax Pipelined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow Through 19 22 25 30 ns
tCYC2 Clock Cycle T ime - Pipelined 10 12 15 20 ns
tCH1 Clock HIGH Time - Flow Through 6.5 7.5 12 12 ns
tCL1 Clock LOW T i me - Flow Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns
tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns
tRClock Rise Time 3333ns
tFClock Fall Time 3333ns
tSA Address Set-Up Time 3.5 4 4 4 ns
tHA Address Hold Time 0 0 1 1 ns
tSC Chip Enable Setup Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0 0 1 1 ns
tSW R/W Set-Up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0 0 1 1 ns
tSD Input Data Setup Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0 0 1 1 ns
tSAD ADS Set-Up Time 3.5444ns
tHAD ADS Hold Time 0011ns
tSCN CNTEN Setup Time 3.5 4.5 5 5 ns
tHCN CNTEN Hold Time 0011ns
tSRST CNTRST Setup Time 3.5444ns
tHRST CNTRST Hold Time 0011ns
tOE Output Enable to Data Valid 8 9 10 12 ns
tOLZ[15,16] OE to Low Z 2222ns
tOHZ[15,16] OE to High Z 17171717ns
tCD1 Clock to Data Valid - Flow Through 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns
tDC Data Output Hold After Clock HIGH 2 2 2 2 ns
tCKZ[15,16] Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns
tCKZ[15,16] Clock HIGH to Output Low Z 2 2 2 2 ns
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns
tCCS Clock to Clock Setup Time 9 10 15 15 ns
Notes
15.Test conditions used are Load 2.
16.This parameter is guaranteed by design, but it is not production tested.
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 8 of 19
Switching Waveforms
Figure 5. Read Cycl e for Flow Throug h Output (FT/PIPE = VIL) [17, 18, 19, 20]
Figure 6. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[17, 18, 19, 20]
Notes
17.OE is asynchronously controlled; all other input s are synchronous to the rising clock edge.
18.ADS = VIL, CNTEN and CNTRST = VIH.
19.The output is disabl ed (high impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
20.Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
tCH1 tCL1
tCYC1
tSC tHC
tDC
tOHZ
tOE
tSC tHC
tSW tHW
tSA tHA
tCD1 tCKHZ
tDC
tOLZ
tCKLZ
AnAn+1 An+2 An+3
QnQn+1 Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 9 of 19
Figure 7. Bank Select Pipelined Read[21, 22]
Figure 8. Left Port Write to Flow Through Right Port Read[23, 24, 25, 26]
Notes
21.In this depth expansion example, B1 repre sents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device fr om this datasheet.
ADDRESS(B1) = ADDRESS(B2).
22.UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
23.The same waveforms apply for a right port write to flow through left port read.
24.CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
25.OE = VIL for th e Ri ght Port, which is being read from. OE = VIH for the Left Port, which i s being written to.
26.It tCCS ≤ maximum specified, then data f rom right port READ is not valid un til the maximum specifi ed for tCWDD. If tCCS>maximum specified, then dat a is not valid until
tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
D3
D1
D0
D2
A0A1A2A3A4A5
D4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
t
SA
t
HA
t
SW
t
HW
t
SD
t
HD
MATCH
VALID
t
CCS
t
SW
t
HW
t
DC
t
CWDD
t
CD1
MATCH
t
SA
t
HA
MATCH
NO
MATCH
NO
VALID VALID
t
DC
t
CD1
CLK
L
R/
W
L
ADDRESS
L
DATA
INL
ADDRESS
R
DATA
OUTR
CLK
R
R/
W
R
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 10 of 19
Figure 9. Pipelined Read-to-Write-to-Read (OE = VIL)[20, 27, 28, 29]
Figure 10. Pipelined Read-to-Write-to-Read (OE Contro lle d)[20, 27, 28, 29]
Notes
27.Output state (High, LOW, or high impedance) is determined by the previous cycle control signals.
28.CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
29.During “No Operation”, data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
Switching Waveforms (continued)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
t
SD
t
HD
t
CKLZ
t
CD2
NO OPERATION WRITEREAD READ
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
t
HW
t
SW
t
SD
t
HD
D
n+2
t
CD2
t
OHZ
READ READWRITE
D
n+3
t
CKLZ
t
CD2
Q
n
Q
n+4
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
IN
DATA
OUT
OE
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 11 of 19
Figure 11. Flow Through Read-to-Write-to-Read (OE = VIL)[18, 20, 28, 29]
Figure 12. Flow Throug h Rea d- to-Write-to-Read (OE Controlled)[18, 20, 27, 28, 29]
Switching Waveforms (continued)
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tSW tHW
tSD tHD
AnAn+1 An+2 An+2 An+3 An+4
Dn+2
QnQn+1 Qn+3
tCD1 tCD1
tDC tCKHZ
tCD1 tCD1
tCKLZ tDC
READ NO
OPERATION WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Qn
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tCD1 tDC
tOHZ
READ
AnAn+1 An+2 An+3 An+4 An+5
Dn+2 Dn+3
tSW tHW
tSD tHD
tCD1 tCD1
tCKLZ tDC
Qn+4
tOE
WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 12 of 19
Figure 13. Pipelined Read with Address Counter Advance[30]
Figure 14. Flow Through Read with Address Counter Advan c e[30]
Note
30.CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
tSA tHA
tSAD tHAD
tSCN tHCN
tCH2 tCL2
tCYC2
tSAD tHAD
tSCN tHCN
Qx-1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATAOUT
CNTEN
An
tCH1 tCL1
tCYC1
tSA tHA
tSAD tHAD
tSCN tHCN
QxQnQn+1 Qn+2 Qn+3
An
tSAD tHAD
tSCN tHCN
tDC
tCD1
COUNTER HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
CLK
ADDRESS
ADS
DATAOUT
CNTEN
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 13 of 19
Figure 15. Write with Address Counter Advance (Flo w Through or Pipelined Outputs)[31, 32]
Notes
31.CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
32.The “Internal Address” is equal to the “External Add ress” when ADS = VIL and equals the counter output when ADS = VIH.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRITE EXTERNAL WRITE WITH COUNTER
ADDRESS WRITE WITH
COUNTER WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
tSA tHA
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 14 of 19
Figure 16. Counter Reset (Pipelined Outputs)[20, 27, 33, 34]
Notes
33.CE0, UB, and LB = VIL; CE1 = VIH.
34.No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental wit h the counter reset.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AX01A
nAn+1
tSAD tHAD
tSCN tHCN
tSRST tHRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRESS 1 READ
ADDRESS n
[+] Feedback [+] Feedback
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 15 of 19
Read/Write and Enable Operation[35, 36, 37]
Inputs Outputs Operation
OE CLK CE0CE1R/W I/O0–I/O17
X H X X High-Z Deselected[38]
X X L X High-Z Deselected[38]
X L H L DIN Write
L L H H DOUT Read[35]
H X L H X High-Z Outputs Disabled
Address Counter Control Operation[35, 39, 40, 41]
Address Previous
Address CLK ADS CNTEN CNTRST I/O Mode Operation
X X X X L Dout(0) Reset Counter Reset to Address 0
AnX L X H Dout(n) Load Address Load into Counter
X AnH H H Dout(n) Hold External Address Blocked—Counter
Disabled
X AnH L H Dout(n+1) Increment Counter Enabled—Internal Ad dress
Generation
X AnH L H Dout(n+1) Increment Counter Enabled—Internal Ad dress
Generation
Notes
35.“X” = “Don’t Care”, “H” = VIH, “L” = VIL.
36.ADS, CNTEN, CNTRST = “Don’t Care”.
37.OE is an asynchronous input signal.
38.When CE changes sta te In the pipelined mode, deselection and read happen in the following clock cycle.
39.CE0 and OE = VIL; CE1 and R/W = VIH.
40.Data shown for flow through mode; pipelined mode out put is delayed by one cycle.
41.Counter operation is independent of CE0 and CE1.
[+] Feedback [+] Feedback
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CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 16 of 19
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Range
6.5[1, 2] CY7C09269V-6AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V-6AXC 100-Pin Thin Quad Flat Pack (Pb-Free )
7.5[2] CY7C09269V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V-7AXC 100-Pin Thin Quad Flat Pack (Pb-Free )
9CY7C09269V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V-9AXC 100-Pin Thin Qu ad Flat Pack (Pb-Free)
CY7C09269V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09269V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09269V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
32K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Range
6.5[1, 2] CY7C09279V-6AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09279V-6AXC 100-Pin Thin Quad Flat Pack (Pb - Free)
7.5[2] CY7C09279V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09279V-7AXC 100-Pin Thin Quad Flat Pack (Pb - Free)
9 CY7C09279V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09279V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
12 CY7 C09279V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09279V-12AXC 100-Pin Thin Quad Flat Pack (Pb - Free)
64K x16 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Range
6.5[1, 2] CY7C09289V-6AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09289V-6AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
7.5[2] CY7C09289V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09289V-7AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
9 CY7C09289V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09289V-9AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
CY7C09289V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C09289V-9AXI 100-Pin Thin Quad Flat Pack (Pb-Free)
12 CY7C09289V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09289V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
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CY7C09369V/79V/89V
Document #: 38-06056 Rev. *C Page 17 of 19
Ordering Information (Continued)
16K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Ran ge
6.5[1, 2] CY7C09369V-6AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09369V-6AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
7.5[2] CY7C09369V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09369V-7AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
CY7C09369V-7AI 51-8 5048 100-Pin Thin Quad Flat Pack Industrial
9 CY7C09369V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09369V-9AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
CY7C09369V-9AI 51-8 5048 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09369V-12AC 51-85048 100-Pin Thin Qu ad Flat Pack Commercial
CY7C09369V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
32K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Range
6.5[1, 2] CY7C09379V-6AC 51-85048 100-Pin T hin Quad Flat Pack Commercial
CY7C09379V-6AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
7.5[2] CY7C09379V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09379V-9AC 51-85048 100-Pin T hin Quad Flat Pack Commercial
CY7C09379V-9AI 51-85048 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09379V-12AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09379V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
CY7C09379V-12AXCT 100-Pin Thin Quad Flat Pack (Pb-Free)
64K x18 3.3V Synchronous Dual-Port SRAM
Speed (ns) Ordering Code Package
Diagram Package Type Operating Range
6.5[1, 2] CY7C09389V-6AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C09389V-6AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
7.5[2] CY7C09389V-7AC 51-85048 100-Pin Thin Quad Flat Pack Commercia l
CY7C09389V-7AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
9 CY7C09389V-9AC 51-85048 100-Pin Thin Quad Flat Pack Commercia l
CY7C09389V-9AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
CY7C09389V-9AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C09389V-9AXI 100-Pin Thin Quad Flat Pack (Pb-Free)
12 CY7C09389V-12AC 51-85048 100-Pin Thin Qu ad Flat Pack Commercial
CY7C09389V-12AXC 100-Pin Thin Quad Flat Pack (Pb-Free)
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Document #: 38-06056 Rev. *C Revised March 25, 2009 Page 19 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
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Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
Document Number: 38-06056
Revision ECN Submission
Date Orig. of
Change Description of Cha ng e
** 110215 12/18/01 SZV Change from Spec number: 38-00668 to 38-06056
*A 122306 12/27/02 RBI Power up requirements added to Maximum Ratings Information
*B 344354 See ECN PCX Added Pb-Free Part Ordering Information
*C 2678221 03/25/2009 VKN/AESA Added CY7C09379V-12AXCT part. Updated 51-85048 to *C.
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