©2001 Fairchild Semiconductor Corporation
March 2001
Rev. A, March 2001
FQNL2N50B
QFETTM
FQNL2N50B
500V N-Ch anne l MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high effi ciency switch mode power supply, power
factor correction, electronic lamp ballast based on half
bridge.
Features
0.35A, 500V, RDS(on) = 5.3 @VGS = 10 V
Low gate charge ( typical 6.0 nC)
Low Crss ( typical 4.0 pF)
Fast switching
Improved dv/dt capability
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter FQNL2N50B Units
VDSS Drain-Source Voltage 500 V
IDDrain Current - Continuous (TC = 25°C) 0.35 A
- Continuous (TC = 100°C) 0.22 A
IDM Drain Current - Pulsed (Note 1) 1.4 A
VGSS Gate-Source Voltage ± 30 V
IAR Avalanche Current (Note 1) 0.35 A
EAR Repetitive Avalanche Energy (Note 1) 0.15 mJ
dv/dt Peak Diode Recovery dv/dt (Note 2) 4.5 V/ns
PDPower Dissipation (TC = 25°C) 1.5 W
- Derate above 25°C 0.012 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJA Thermal Resistance, Junction-to-Ambient -- 83 °C/W
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D
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TO-92L
FQNL Series
GS
D
Rev. A, March 2001
FQNL2N50B
©2001 Fairchild Semiconductor Corporation
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. ISD 2.1A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25°C
3. Pulse Test : Pulse width 300µs, Duty cycle 2%
4. Essentially independent of operating temperature
Symbol Parame ter Test Condit i ons Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA500 -- -- V
BVDSS
/ TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.48 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 500 V, VGS = 0 V -- -- 1 µA
VDS = 400 V, TC = 125°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA2.3 3.0 3.7 V
VDS = VGS, ID = 250 mA 3.6 4.3 5.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 0.175 A -- 4.2 5.3
gFS Forward Transconductance VDS = 50 V, ID = 0.175 A -- 0.72 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 180 230 pF
Coss Output Capacitance -- 30 40 pF
Crss Reverse Transfer Capacitance -- 4 6 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 250 V, ID = 2.1 A,
RG = 25
-- 6 20 ns
trTurn-On Rise T ime -- 25 60 ns
td(off) Turn-Off D e l a y Time -- 10 30 ns
tfTurn -Off F a ll Time -- 2 0 50 ns
QgTotal Gate Ch arge VDS = 400 V, ID = 2.1 A,
VGS = 10 V
-- 6.0 8.0 nC
Qgs Gate-Source Charge -- 1.3 -- nC
Qgd Gate-Drain Charge -- 3.0 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 0.35 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 1.4 A
VSD Drain-Source Diode Forward V olt age VGS = 0 V, I S = 0.35 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, I S = 2.1 A,
dIF / dt = 100 A/µs
-- 195 -- ns
Qrr Reverse Recovery Charge -- 0.69 -- µC
(Note 3)
(Note 3, 4)
(Note 3, 4)
(Note 3)
Rev. A, March 2001©2001 Fairchild Semiconductor Corporation
FQNL2N50B
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10-1
100
25
150
N o te :
1. V GS = 0 V
2. 250μs Pu lse Te st
IDR , Re verse Drain Current [A]
VSD , Source-Drain Voltage [V]
246810
10-1
100
No te
1. VDS = 50V
2. 250μs Pulse Test
-55
150
25
ID , Drain Cur re n t [A]
VGS , G ate -Sou rc e Volta g e [V]
10-1 100101
10-2
10-1
100
N o te :
1. 250μs Pulse Test
2. T C = 25
VGS
T op : 1 5 V
10 V
8.0 V
7.0 V
6.5 V
6.0 V
B otto m : 5.5 V
ID , Drain C u rre n t [A ]
VDS , Drain-Source Voltage [V]
01234567
0
2
4
6
8
10
12
VDS = 250V
VDS = 100V
VDS = 400V
Note : ID = 2.1 A
VGS, Gate-Source Voltage [V]
QG, T otal G a t e Cha rg e [n C]
10-1 100101
0
50
100
150
200
250
300
350 Ciss = Cgs + C gd (C ds = shorted)
Coss = C ds + C gd
Crss = C gd
No te :
1. V GS = 0 V
2. f = 1 MH z
Crss
Coss
Ciss
Capacitances [pF]
VDS, Drain-Source Voltage [V]
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
3
6
9
12
15
18
N o te : TJ = 25
VGS = 20V
VGS = 10V
RDS(on) [],
Drain-Source O n-Resistance
ID , Dr ain C u rren t [A ]
Typical Characteristics
Figure 5. C apacitance Cha rac te ri st i cs Figure 6. Ga te Ch arge Cha ra c t eri s ti cs
Figu re 3. On-Resi stance Variation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Charact er i st ics
©2001 Fairchild Semiconductor Corporation Rev. A, March 2001
FQNL2N50B
25 50 75 100 125 150
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
ID, Drain Cur re nt [A]
TC, C ase T emperature [
]
100101102103
10-3
10-2
10-1
100
101
10 s
100 m s
1 s
100 µs
DC
10 m s
1 m s
Operation in This Area
is Limited by R DS(on)
N o te s :
1. T C = 25 oC
2. T J = 150 oC
3. Single Pulse
ID, Drain Current [A]
VDS, Drain-Source Vo ltage [V]
10-4 10-3 10-2 10-1 100101102
100
101
102
No te s :
1 . Z θJC(t) = 83 /W Ma x .
2 . D u ty F a c to r , D= t1/t2
3 . T JM - T C = PDM * Z θJC(t)
single p ulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC
(t), T h ermal R es po n se
t1, S qu a re W a ve P u ls e Du ra tion [s e c]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
No te :
1. VGS = 10 V
2. ID = 1.05 A
RDS(ON) , (N o rmalized )
Drain-Source On-Resistance
TJ, Junc tion Tem p erature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
N o te :
1 . VGS = 0 V
2 . ID = 250 μA
BV DSS , (N ormaliz e d )
Drain-Source Breakdow n Voltage
TJ, Junction Temperature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figu re 7. Brea kdown Voltage Variat i o n
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Res pons e Cur ve
t1
PDM
t2
Rev. A, March 2001©2001 Fairchild Semiconductor Corporation
FQNL2N50B
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
©2001 Fairchild Semiconductor Corporation Rev. A, March 2001
FQNL2N50B
Peak Diode Recover y dv/dt Test Circuit & Waveform s
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
Rev. A, March 2001©2001 Fairchild Semiconductor Corporation
FQNL2N50B
Package Dimensions
4.90 ±0.20
0.50 ±0.10
1.27TYP
[1.27 ±0.20]
0.45 ±0.10
0.45 ±0.10
0.80 ±0.10
0.70MAX.
1.00MAX.
2.54 TYP
8.00 ±0.20
1.70 ±0.20
1.00 ±0.10
13.50 ±0.40
3.90 ±0.20
3.90 ±0.20
1.45 ±0.20
TO-92L
©2001 Fairchild Semiconductor Corporation
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intended to be an exhaustive list of all such trademarks.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devic es or syst em s
which, (a) ar e intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This dat asheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconduct or reserv es the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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