2010 Microchip Technology Inc. DS39951C-page 301
PIC24FJ64GA104 FAMILY
N
Near Data Space ................................................................ 34
O
Oscillator Configuration
Bit Values for Clock Selection................................... 102
Clock Switching......................................................... 106
Sequence.......................................................... 107
Control Registers ...................................................... 103
CPU Clocking Scheme ............................................. 102
Initial Configuration on POR ..................................... 102
Reference Clock Output............................................ 108
Secondary Oscillator (SOSC) ................................... 108
Output Compare
32-Bit Mode............................................................... 155
Operations ................................................................ 157
Subcycle Resolution ................................................. 160
Synchronous and Trigger Modes.............................. 155
Output Compare with Dedicated Timers........................... 155
P
Packaging ......................................................................... 283
Details ....................................................................... 285
Marking ..................................................................... 283
Parallel Master Port. See PMP. ........................................ 191
Peripheral Module Disable Bits......................................... 119
Peripheral Pin Select (PPS).............................................. 123
Available Peripherals and Pins ................................. 123
Configuration Control Changes................................. 126
Considerations for Use ............................................. 127
Function Priority ........................................................ 123
Input Mapping ........................................................... 124
Output Mapping ........................................................ 125
Pinout Descriptions ............................................................. 13
Power-Saving Features .................................................... 111
Clock Frequency and Clock Switching...................... 111
Product Identification System ........................................... 305
Program Memory
Access Using Table Instructions................................. 49
Address Space............................................................ 31
Addressing Space....................................................... 47
Flash Configuration Words ......................................... 32
Memory Maps ............................................................. 31
Organization................................................................ 32
Program Space Visibility ............................................. 50
Program Space Visibility (PSV) .......................................... 50
Program Verification ......................................................... 248
Pulse-Width Modulation (PWM) Mode .............................. 158
Pulse-Width Modulation. See PWM.
PWM
Duty Cycle and Period .............................................. 159
R
Reader Response ............................................................. 304
Register Maps
A/D Converter ............................................................. 43
Comparators ............................................................... 45
CPU Core.................................................................... 35
CRC ............................................................................ 44
CTMU.......................................................................... 43
Deep Sleep ................................................................. 46
I2C............................................................................... 41
ICN.............................................................................. 36
Input Capture .............................................................. 39
Interrupt Controller ...................................................... 37
NVM............................................................................ 46
Output Compare ......................................................... 40
Pad Configuration....................................................... 43
Parallel Master/Slave Port .......................................... 44
Peripheral Pin Select .................................................. 45
PMD............................................................................ 46
PORTA ....................................................................... 42
PORTB ....................................................................... 42
PORTC ....................................................................... 42
RTCC.......................................................................... 44
SPI.............................................................................. 42
System........................................................................ 46
Timers......................................................................... 38
UART.......................................................................... 41
Registers
AD1CHS (A/D Input Select)...................................... 224
AD1CON1 (A/D Control 1)........................................ 221
AD1CON2 (A/D Control 2)........................................ 222
AD1CON3 (A/D Control 3)........................................ 223
AD1CSSL (A/D Input Scan Select)........................... 226
AD1PCFG (A/D Port Configuration) ......................... 225
ALCFGRPT (Alarm Configuration) ........................... 205
ALMINSEC (Alarm Minutes and
Seconds Value) ................................................ 209
ALMTHDY (Alarm Month and Day Value) ................ 208
ALWDHR (Alarm Weekday and Hours Value) ......... 208
CLKDIV (Clock Divider) ............................................ 105
CMSTAT (Comparator Module Status) .................... 232
CMxCON (Comparator x Control) ............................ 231
CORCON (CPU Control) ............................................ 29
CORCON (CPU Core Control) ................................... 69
CRCCON1 (CRC Control 1) ..................................... 216
CRCCON2 (CRC Control 2) ..................................... 217
CRCXORH (CRC XOR Polynomial, High Byte) ....... 218
CRCXORL (CRC XOR Polynomial, Low Byte)......... 217
CTMUCON (CTMU Control)..................................... 237
CTMUICON (CTMU Current Control)....................... 238
CVRCON (Comparator Voltage
Reference Control) ........................................... 234
CW1 (Flash Configuration Word 1) .......................... 240
CW2 (Flash Configuration Word 2) .......................... 242
CW3 (Flash Configuration Word 3) .......................... 243
DEVID (Device ID).................................................... 245
DEVREV (Device Revision)...................................... 245
DSCON (Deep Sleep Control).................................. 117
DSWAKE (Deep Sleep Wake-up Source) ................ 118
I2CxCON (I2Cx Control) ........................................... 178
I2CxMSK (I2Cx Slave Mode Address Mask)............ 182
I2CxSTAT (I2Cx Status) ........................................... 180
ICxCON1 (Input Capture x Control 1)....................... 153
ICxCON2 (Input Capture x Control 2)....................... 154
IEC0 (Interrupt Enable Control 0) ............................... 77
IEC1 (Interrupt Enable Control 1) ............................... 78
IEC2 (Interrupt Enable Control 2) ............................... 79
IEC3 (Interrupt Enable Control 3) ............................... 80
IEC4 (Interrupt Enable Control 4) ............................... 81
IFS0 (Interrupt Flag Status 0) ..................................... 72
IFS1 (Interrupt Flag Status 1) ..................................... 73
IFS2 (Interrupt Flag Status 2) ..................................... 74
IFS3 (Interrupt Flag Status 3) ..................................... 75
IFS4 (Interrupt Flag Status 4) ..................................... 76
INTCON1 (Interrupt Control 1) ................................... 70
INTCON2 (Interrupt Control 2) ................................... 71
INTTREG (Interrupt Control and Status) .................... 98
IPC0 (Interrupt Priority Control 0) ............................... 82