05/18/11
www.irf.com 1
HEXFET® Power MOSFET
IRFI4410ZGPbF
S
D
G
GDS
Gate Drain Source
D
S
D
G
TO-220AB Full-Pak
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
V
DSS
100V
R
DS(on)
typ.
7.9m
:
max.
9.3m
:
I
D
Absolute Maximum Ratings
Symbol
Parameter
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
IDM Pulsed Drain Current
c
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited)
Single Pulse Avalanche Energy
d
mJ
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ. Max. Units
RθJC
Junction-to-Case
f
––– 3.2 °C/W
RθJA
Junction-to-Ambient
f
––– 65
-55 to + 175
0.3
10lb
x
in (1.1N
x
m)
300
±30
310
47
Max.
43
30
170
PD - 96372
IRFI4410ZGPbF
2www.irf.com
S
D
G
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.91mH
RG = 25Ω, IAS = 26A, VGS =10V. Part not recommended for use
above this value.
Pulse width 400μs; duty cycle 2%.
Rθ is measured at TJ approximately 90°C
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Static @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage 100 –– ––– V
V(BR)DSS
/T
J Breakdown Voltage Temp. Coefficient –– 95 –––
RDS(on) Static Drain-to-Source On-Resistance –– 7.9 9.3 m
V
GS(th)
Gate Threshold Voltage 2.0 –– 4.0 V
I
DSS
Drain-to-Source Leakage Current –– –– 20 μA
–– –– 250
IGSS Gate-to-Source Forward Leakage –– –– 100 nA
Gate-to-Source Reverse Leakage –– –– -100
R
G(i nt)
Internal Gate Resistance –– 0.9 ––
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 80 –– ––– S
Q
g
Total Gate Charge –– 81 110 nC
Q
gs
Gate-to-Source Charge –– 18 –––
Q
gd
Gate-to-Drain ("Miller") Charge –– 23 –––
t
d(on)
Turn-On Delay Time –– 15 ––– ns
trRise Time –– 27 –––
t
d(off)
Turn-Off Delay Time –– 43 –––
t
f
Fall Time –– 30 –––
C
iss
Input Capacitance –– 4910 ––– pF
Coss Output Capacitance –– 330 –––
C
rs s
Reverse Transfer Capacitance –– 15 0 –––
C
oss
eff. (ER)
Effective Output Capacitance (Energy Related)
–– 420 –––
C
oss
eff. (TR) Effective Output Capacitance (Time Related) –– 680 ––
Diode Characteristics
Symbol
Parameter
Min.
Typ.
Max.
I
S
Continuous Source Current –– –– 43 A
(Body Diode)
I
SM
Pulsed Source Current –– –– 170 A
(Body Diode)
c
VSD D iode Forw ar d V oltag e –– –– 1.3 V
t
rr
Reverse Recovery Time –– 47 71 ns T
J
= 25°C V
R
= 85V,
––
54
81
T
J
= 125°C
I
F
= 26A
Qrr Reverse Recovery Charge –– 110 160 nC TJ = 25°C
di/dt = 100A/μs
e
––
140
210
T
J
= 125°C
I
RRM
Reverse Recovery Current –– 2.5 ––– A T
J
= 25°C
t
on
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 10V
e
V
GS
= 0V
VDS = 50V
Conditions
VDS = 50V, ID = 26A
I
D
= 26A
VGS = 10V
e
VDD = 65V
ID = 26A
R
G
= 2.7
VDS = VGS
, ID = 150μA
VDS = 100V, VGS = 0V
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
V
DS
= 50V
VGS = 20V
VGS = -20V
Conditions
V
GS
= 0V, I
D
= 250μA
Reference to 25°C, I
D = 5mA
e
VGS = 10V, ID = 26A
e
p-n junction diode.
TJ = 25°C, IS = 26A, VGS
= 0V
e
ƒ = 1.0MHz
VGS = 0V, VDS
= 0V to 80V
h
, See Fig.11
V
GS
= 0V, V
DS
= 0V to 80V
g
Conditions
MOSFET symbol
showing the
integral reverse
IRFI4410ZGPbF
www.irf.com 3
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
60μs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
60μs PULSE WIDTH
Tj = 175°C
4.5V
2 3 4 5 6
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current
(A)
TJ = 25°C
TJ = 175°C
VDS = 50V
60μs PULSE WIDTH
110 100
VDS, Drain-to-Source Voltage (V)
0
2000
4000
6000
8000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 20 40 60 80 100 120
QG Total Gate Charge (nC)
0
4
8
12
16
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
VDS= 20V
ID= 26A
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 26A
VGS = 10V
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4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
25 50 75 100 125 150 175
TC , CaseTemperature (°C)
0
10
20
30
40
50
ID , Drain Current (A)
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
100
105
110
115
120
125
130
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
020 40 60 80 100
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
Energy (μJ)
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
200
400
600
800
1000
1200
1400
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 8.6A
14A
BOTTOM 26A
0.1 1 10 100 1000
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
DC
IRFI4410ZGPbF
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1 110
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
80
160
240
320
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 26A
Ri (°C/W)
τι
(sec)
0.117574 0.000176
1.337531 0.7389
1.260992 0.103059
0.508931 0.008379
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci
i
/
Ri
Ci=
τ
i
/
Ri
τ
τ
C
τ
4
τ
4
R
4
R
4
IRFI4410ZGPbF
6www.irf.com
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250μA
ID = 150μA
100 200 300 400 500 600 700
diF /dt (A/μs)
0
2
4
6
8
10
12
14
16
IRR (A)
IF = 26A
VR = 85V
TJ = 25°C
TJ = 125°C
100 200 300 400 500 600 700
diF /dt (A/μs)
0
2
4
6
8
10
12
14
16
IRR (A)
IF = 17A
VR = 85V
TJ = 25°C
TJ = 125°C
100 200 300 400 500 600 700
diF /dt (A/μs)
0
50
100
150
200
250
300
350
QRR (A)
IF = 17A
VR = 85V
TJ = 25°C
TJ = 125°C
100 200 300 400 500 600 700
diF /dt (A/μs)
0
50
100
150
200
250
300
350
QRR (A)
IF = 26A
VR = 85V
TJ = 25°C
TJ = 125°C
IRFI4410ZGPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Inductor Current
1K
VCC
DUT
0
L
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8www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
TO-220AB Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Full-Pak Part Marking Information
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
IR WORLD HEADQUARTERS: 101N Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.05/2011
LOGO
AS S E MBLED ON WW 31, 2010
EXAMPLE:
LOT CODE 1234
T HIS IS AN IRF I4110G
WI T H AS S E MB L Y
PART NUMBER
INTERNATIONAL
RECTIFIER
P031D
F I4110G
Notes : - "P" in assembly line position
i ndi cates "L ead-F ree"
ASSEMBLY SITE D
WEEK 31
YEAR 0 = 2010
DAT E CODE
LOT CODE
ASSEMBLY
12 34
- "G" s uffix in part number
i ndicates "H al ogen- F ree"