PD - 96372 IRFI4410ZGPbF HEXFET(R) Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free VDSS RDS(on) typ. max. ID 100V 7.9m: 9.3m: 43A D D G G S D S TO-220AB Full-Pak G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units A ID @ TC = 25C Continuous Drain Current, VGS @ 10V 43 ID @ TC = 100C Continuous Drain Current, VGS @ 10V 30 IDM Pulsed Drain Current 170 PD @TC = 25C Maximum Power Dissipation 47 W Linear Derating Factor 0.3 30 W/C V EAS (Thermally limited) Gate-to-Source Voltage Single Pulse Avalanche Energy 310 mJ TJ Operating Junction and -55 to + 175 C TSTG Storage Temperature Range VGS c d 300 Soldering Temperature, for 10 seconds (1.6mm from case) x x 10lb in (1.1N m) Mounting torque, 6-32 or M3 screw Thermal Resistance Parameter f RJC Junction-to-Case RJA Junction-to-Ambient www.irf.com f Typ. --- Max. 3.2 --- 65 Units C/W 1 05/18/11 IRFI4410ZGPbF Static @ T J = 25C (unless otherwise specified) Symbol Param eter Min. Typ. Max. Units Conditions V(BR)DSS V(BR)DSS/ T J RDS(on) VGS(th) Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage 100 --- --- 2.0 --- 95 7.9 --- IDSS Drain-to-Source Leakage Current IG SS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage --- --- --- --- --- --- --- --- --- V V GS = 0V, ID = 250A --- mV/C Reference to 25C, ID = 5mA 9.3 m V GS = 10V, ID = 26A 4.0 V V DS = VGS, ID = 150A 20 A V DS = 100V, V GS = 0V V DS = 100V, V GS = 0V, TJ = 125C 250 100 nA V GS = 20V -100 V GS = -20V RG(int) Internal Gate Resistance --- 0.9 --- e e Dynamic @ T J = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Param eter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capaci tance Reverse Transfer Capaci tance 80 --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related) --- Effective Output Capacitance (Time Related) --- --- 81 18 23 15 27 43 30 4910 330 150 420 680 --- 110 --- --- --- --- --- --- --- --- --- --- --- S nC ns pF Conditions V DS = 50V, ID = 26A ID = 26A V DS = 50V V GS = 10V V DD = 65V ID = 26A RG = 2.7 V GS = 10V V GS = 0V V DS = 50V = 1.0MHz V GS = 0V, VDS = 0V to 80V V GS = 0V, VDS = 0V to 80V e e h, See Fig.11 g Diode Characteristics Symbol IS Parameter VSD tr r Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM c Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.91mH RG = 25, IAS = 26A, VGS =10V. Part not recommended for use above this value. 2 Min. Typ. Max. Units --- --- Conditions MOSFET symbol showing the G --- --- 170 A integral reverse p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 26A, V GS = 0V --- 47 71 ns TJ = 25C V R = 85V, --- 54 81 TJ = 125C IF = 26A di/dt = 100A/s --- 110 160 nC TJ = 25C --- 140 210 TJ = 125C --- 2.5 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 43 A e D S e Pulse width 400s; duty cycle 2%. R is measured at TJ approximately 90C Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS . www.irf.com IRFI4410ZGPbF ID, Drain-to-Source Current (A) TOP BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 1000 60s PULSE WIDTH Tj = 25C 100 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) 1000 BOTTOM 100 4.5V 4.5V 60s PULSE WIDTH Tj = 175C 10 10 0.1 1 10 100 0.1 100 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 3.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current(A) 10 VDS, Drain-to-Source Voltage (V) 1000 100 TJ = 175C 10 TJ = 25C 1 VDS = 50V 60s PULSE WIDTH 0.1 ID = 26A VGS = 10V 2.5 2.0 1.5 1.0 0.5 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics 8000 VGS, Gate-to-Source Voltage (V) Coss = Cds + Cgd Ciss 4000 2000 Coss Crss 0 1 ID= 26A VDS= 80V VDS= 50V 12 VDS= 20V 8 4 0 10 100 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com Fig 4. Normalized On-Resistance vs. Temperature 16 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 6000 C, Capacitance (pF) 1 VDS, Drain-to-Source Voltage (V) 0 20 40 60 80 100 120 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFI4410ZGPbF 1000 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 TJ = 175C 10 TJ = 25C 1 VGS = 0V 0.5 1.0 100 10msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 20 10 0 150 175 V(BR)DSS, Drain-to-Source Breakdown Voltage (V) ID , Drain Current (A) 30 125 1000 Id = 5mA 125 120 115 110 105 100 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage EAS, Single Pulse Avalanche Energy (mJ) 2.0 1.5 Energy (J) 100 130 TC , CaseTemperature (C) 1.0 0.5 0.0 1400 I D 8.6A 14A BOTTOM 26A 1200 TOP 1000 800 600 400 200 0 0 20 40 60 80 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 10 Fig 8. Maximum Safe Operating Area 40 100 1 VDS, Drain-toSource Voltage (V) 50 75 DC 1.5 Fig 7. Typical Source-Drain Diode Forward Voltage 50 1msec 10 VSD, Source-to-Drain Voltage (V) 25 100sec 0.1 0.1 0.0 OPERATION IN THIS AREA LIMITED BY R DS (on) 100 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (C) Fig 12. Maximum Avalanche Energy Vs. DrainCurrent www.irf.com IRFI4410ZGPbF Thermal Response ( ZthJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 R1 R1 J 0.02 0.01 J 1 R2 R2 R3 R3 R4 R4 C 2 1 3 2 4 3 4 Ci= i/Ri Ci i/Ri 0.01 Ri (C/W) (sec) 0.117574 0.000176 1.337531 0.7389 1.260992 0.103059 0.508931 0.008379 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case Avalanche Current (A) 100 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 320 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 10% Duty Cycle ID = 26A 240 160 80 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (C) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFI4410ZGPbF 16 ID = 1.0A ID = 1.0mA ID = 250A ID = 150A 4.0 3.5 14 12 10 3.0 IRR (A) VGS(th) Gate threshold Voltage (V) 4.5 2.5 8 6 2.0 IF = 17A VR = 85V 4 1.5 TJ = 25C TJ = 125C 2 1.0 0 -75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 TJ , Temperature ( C ) 400 500 600 700 diF /dt (A/s) Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage Vs. Temperature 16 350 14 300 12 250 QRR (A) IRR (A) 10 8 6 200 150 4 IF = 26A VR = 85V 100 2 TJ = 25C TJ = 125C 50 0 IF = 17A VR = 85V TJ = 25C TJ = 125C 0 100 200 300 400 500 600 700 100 200 diF /dt (A/s) 300 400 500 600 700 diF /dt (A/s) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 350 300 QRR (A) 250 200 150 100 IF = 26A VR = 85V 50 TJ = 25C TJ = 125C 0 100 200 300 400 500 600 700 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFI4410ZGPbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG + V - DD IAS VGS 20V tp A 0.01 I AS Fig 22a. Unclamped Inductive Test Circuit LD Fig 22b. Unclamped Inductive Waveforms VDS VDS + 90% VDD - 10% D.U.T VGS VGS Pulse Width < 1s Duty Factor < 0.1% td(on) Fig 23a. Switching Time Test Circuit tr td(off) tf Fig 23b. Switching Time Waveforms Id Vds Vgs L DUT 0 1K VCC Vgs(th) Qgs1 Qgs2 Fig 24a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRFI4410ZGPbF TO-220AB Full-Pak Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB Full-Pak Part Marking Information EXAMPLE : T HIS IS AN IRFI4110G WIT H AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 31, 2010 PART NUMBER INT ERNAT IONAL RECT IFIER LOGO Notes : - "P" in ass embly line pos ition indicates "Lead-Free" - "G" s uffix in part number indicates "Halogen-F ree" F I4110G P031D 12 34 AS S EMBLY LOT CODE DAT E CODE YEAR 0 = 2010 WEEK 31 AS S EMBLY S ITE D TO-220AB Full-Pak packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 101N Sepulveda Blvd, El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.05/2011 8 www.irf.com