Data Sheet No.PD60270
Typical Connection
Product Summary
VOFFSET 200 V max.
IO+/- 130 mA/270 mA
VOUT 10 V - 20 V
ton/off (typ.) 680 ns/150 ns
Deadtime (typ.) 520 ns
HALF-BRIDGE DRIVER
Features
•Floating channel designed for bootstrap operation
•Fully operational to +200 V
•Tolerant to negative transient voltage, dV/dt
immune
•Gate drive supply range from 10 V to 20 V
•Undervoltage lockout
•3.3 V, 5 V, and 15 V input logic compatible
•Cross-conduction prevention logic
•Internally set deadtime
•High-side output in phase with input
•Shutdown input turns off both channels
• Matched propagation delay for both channels
Description
The IRS2004 is a high voltage, high speed power
MOS
FET and IGBT dri
ver with dep
endent high- and low-
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. The logic input is compatible
with standard CMOS or LSTTL output, down to 3.3 V
logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates from 10 V to 200 V.
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IRS2004(S)PbF
(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
Packages
8 Lead PDIP
IRS2004
8 Lead SOIC
IRS2004S
•
RoHS compliant
IRS2004(S) PbF
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Symbol Definition Min. Max. Units
VBHigh-side floating absolute voltage-0.3225
VSHigh-side floating supply offset voltageVB - 25VB + 0.3
VHOHigh-side floating output voltageVS - 0.3VB + 0.3
VCCLow-side and logic fixed supply voltage-0.325
VLOLow-side output voltage-0.3VCC + 0.3
VIN Logic input voltage (IN & )-0.3V
CC + 0.3
dVs/dt Allowable offset supply voltage transient — 50 V/ns
PDPackage power dissipation @ TA ≤ +25 °C(8 lead PDIP) — 1.0
(8 lead SOIC) — 0.625
RthJA Thermal resistance, junction to ambient (8 lead PDIP) — 125
(8 lead SOIC) — 200
TJJunction temperature — 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VBHigh-side floating supply absolute voltageVS + 10VS + 20
VSHigh-side floating supply offset voltageNote 2200
VHOHigh-side floating output voltageVSVB
VCCLow-side and logic fixed supply voltage1020
VLOLow-side output voltage0VCC
VIN Logic input voltage (IN & )0V
CC
TAAmbient temperature -40 125
Note 1: Logic operational for VS of -5 V to +200 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
°C
V
V
W
°C/W
°C
IRS2004(S) PbF
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Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “1” (HO) & Logic “0” (LO) input voltage 2.5 — —
VIL Logic “0” (HO) & Logic “1” (LO) input voltage — — 0.8
VSD,TH+ SD input positive going threshold 2.5 — —
VSD,TH- SD input negative going threshold — — 0.8
VOHHigh level output voltage, VBIAS - VO—0.050.2
VOL Low level output voltage, VO— 0.02 0.1
ILK Offset supply leakage current — — 50 VB = VS = 200 V
IQBS Quiescent VBS supply current — 30 55
IQCC Quiescent VCC supply current — 150 270
IIN+ Logic “1” input bias current — 3 10 VIN = 5 V
IIN-Logic “0” input bias current——5VIN = 0 V
VCCUV+
VCC supply undervoltage positive going 8 8.9 9.8
threshold
VCCUV-
VCC supply undervoltage negative going 7.4 8.2 9
threshold
IO+ Output high short circuit pulsed current 130 290 — VO = 0 V
PW ≤ 10 µs
IO- Output low short circuit pulsed current 270 600 — VO = 15 V
PW ≤ 10 µs
Symbol Definition Min. Typ. Max. Units Test Conditions
ton Turn-on propagation delay — 680 820 VS = 0 V
toff Turn-off propagation delay — 150 220 VS = 200 V
tsd Shutdown propagation delay — 160 220
trTurn-on rise time — 70 170
tfTurn-off fall time — 35 90
DT Deadtime, LS turn-off to HS turn-on & 400 520 650
HS turn-on to LS turn-off
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 °C unless otherwise specified.
V
V
mA
MT Delay matching, HS & LS turn-on/off — — 60
ns
µA
VCC = 10 V to 20 V
IO = 2 mA
VIN = 0 V or 5 V
IRS2004(S) PbF
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Functional Block Diagram
Lead Definitions
Symbol Description
INLogic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
Logic input for shutdown
VBHigh-side floating supply
HOHigh-side gate drive output
VSHigh-side floating supply return
VCCLow-side and logic fixed supply
LOLow-side gate drive output
COMLow-side return
Lead Assignments
8 Lead PDIP 8 Lead SOIC
IRS2004PbF IRS2004SPbF
1
2
3
4
8
7
6
5
VCC
IN
SD
COM
VB
HO
VS
LO
1
2
3
4
8
7
6
5
VCC
IN
SD
COM
VB
HO
VS
LO
VB
HO
VS
IN
SD
DEAD TIME &
SHOOT-THROUGH
PREVENTION
PULSE
GEN
PULSE
FILTER
HV
LEVEL
SHIFT R
S
Q
VCC
LO
COM
UV
DETECT
IRS2004(S) PbF
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Figure 5. Delay Matching Waveform Definitions
Figure 4. Deadtime Waveform Definitions
Figure 3. Shutdown Waveform Definitions
Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
IRS2004(S) PbF
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Figure 6A. T urn-On Time vs. Temperature Figure 6B. T urn-On Time vs. Supply V oltage
Figure 7A. T urn-Off Time vs. T emperature
Figure 7B. T urn-Off Time vs. Supply V oltage
Temperature (°C) VBIAS Supply Voltage (V)
Temperature (°C)
VBIAS Supply Voltage (V)
Turn-Off Delay Time (ns)
0
100
200
300
400
500
10 12 14 16 18 20
Max.
Typ.
Turn-Off Delay Time (ns)
0
200
400
600
800
1000
1200
1400
-50 -25 0 25 50 75 100 125
Turn-On Delay Time (ns)
Max
.
Typ
.
Turn-On Delay Time (ns)
0
200
400
600
800
1000
1200
1400
10 12 14 16 18 20
Max.
Typ.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Max.
Typ.
0
200
400
600
800
1000
0 2 4 6 8101214161820
Turn-On Delay Time (ns
)
Max.
Typ.
0
200
400
600
800
1000
0 2 4 6 8 101214161820
Turn-Off Delay Time (ns)
Max.
Typ
Figure 7C. T urn-Off Time vs. Input V oltage
Figure 6C. T urn-On Time vs. Input V oltage
Input Voltage (V)
Input Voltage (V)
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Figure 8A. Shutdown Time vs. T emperature Figure 8B. Shutdown Time vs. V oltage
VBIAS Supply Voltage (V)
Temperature (°C)
Shutdown Delay Time (ns)
0
100
200
300
400
500
10 12 14 16 18 20
Max.
Typ.
Shutdown Delay Time (ns)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Typ.
Max.
Figure 10A. T urn-Off Fall Time
vs. Temperature
Temperature (°C)
Figure 10B. T urn-Off Fall Time
vs. Input V oltage
Turn-Off Fall Time (ns)
Turn-Off Fall Time (ns)
Figure 9A. T urn-On Rise Time
vs. Temperature Figure 9B. T urn-On Rise Time vs. V oltage
Temperature (°C) VBIAS Supply Voltage (V)
Turn-On Rise Time (ns)
Turn-On Rise Time (ns)
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
MAX
Max.
Typ. 0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Suppl y Voltage (V)
(
Max.
Typ.
0
50
100
150
200
-50 -25 0 25 50 75 100 125
Max.
Typ. 0
50
100
150
200
10 12 14 16 18 20
Input Voltage (V)
Max.
Typ.
IRS2004(S) PbF
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0
1
2
3
4
5
6
7
8
10 12 14 16 18 20
VBIAS Supply Voltage (V)
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Figure 13A. Logic "0" (HO) & Logic “1” (LO)
& Active SD Input Voltage vs. Temperature
Temperature (°C)
Vcc Supply Voltage (V)
Figure 13B. Logic "0" (HO) & Logic “1” (LO)
& Active SD Input Voltage vs. Supply Voltage
0
0.8
1.6
2.4
3.2
4
10 12 14 16 18 20
Input Voltage (V)
Max
.
0
0.8
1.6
2.4
3.2
4
-50-250 255075100125
Input Voltage (V)
Max.
Temperature (°C)
VBIAS Supply Voltage (V)
Deadtime (ns)
Figure 1 1A. Deadtime vs. T emperature
Deadtime (ns)
Figure 1 1B. Deadtime vs. Voltage
0
200
400
600
800
1000
1200
1400
-50 -25 0 25 50 75 100 125
Max.
Typ.
Min
.
0
200
400
600
800
1000
1200
1400
10 12 14 16 18 20
M ax.
Typ.
Min.
Temperature (oC)
Input Voltage (V)
Input Voltage (V)
Figure12A. Logic "1" Input Voltage
vs. Temperature Figure 12B. Logic "1" Input Voltage
vs. Supply Voltage
Min.
Min
Min. Min.
IRS2004(S) PbF
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Offset Supply Leakage Current (µA)
Temperature (°C)
Figure 16A. Offset Supply Current
vs. Temperature
Offset Supply Leakage Current (µA)
Figure 16B. Offset Supply Current
vs. V oltage
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Max.
0
100
200
300
400
500
0 100 200 300 400 500 600
Max.
VB Boost Voltage (V)
Figure 14A. High Level Output Voltage
vs. Temperature
Figure 14B. High Level Output Voltage
vs. Supply Voltage
High Level Output Voltage (V)
High Level Output Voltage (V)
VBIAS Supply Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
Figure 15A. Low Level Output Voltage
vs. Temperature
Figure 15B. Low Level Output Voltage
vs. Supply Voltage
Low Level Output Voltage (V)
Low Level Output Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
-50-25 0 25 50 75100125
Temperature (oC)
0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
IRS2004(S) PbF
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Figure 18A. Vcc Supply Current
vs. Temperature
Vcc Supply Current (µA)
Vcc Supply Current (µA)
Figure 18B. Vcc Supply Current vs. Voltage
Vcc Supply Voltage (V)
Figure 19A. Logic"1" Input Current
vs. Temperature
Temperature (°C)
Logic 1” Input Current (µA)
Logic 1” Input Current (µA)
Figure 19B. Logic"1" Input Current
vs. V oltage
0
100
200
300
400
500
600
700
10 12 14 16 18 20
Max.
Typ.
0
5
10
15
20
25
30
-50 -25 0 25 50 75 100 125
Max.
Typ.
0
5
10
15
20
25
30
10 12 14 16 18 20
Max.
Typ.
Vcc Supply Voltage (V)
0
100
200
300
400
500
600
700
-50 -25 0 25 50 75 100 125
Max.
Typ.
Temperature (°C)
Figure 17A. VBS Supply Current
vs. Temperature Figure 17B. VBS Supply Current
vs. V oltage
VBS Floating Supply Voltage (V)
Temperature (°C)
VBS Supply Current (µA)
VBS Supply Current (µA)
0
30
60
90
120
150
10 12 14 16 18 20
Max.
Typ.
0
30
60
90
120
150
-50 -25 0 25 50 75 100 125
Max.
Typ.
IRS2004(S) PbF
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0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Logic “0” Input Bias Current ( µA)
Figure 20A. Logic "0" Input Bias Current
vs. Temperature
Figure 20B. Logic "0" Input Bias Current
vs. Voltage
Vcc UVLO T hreshold +(V)
Figure 21A. Vcc Undervoltage Threshold(+)
vs. Temperature
Temperature (°C)
Figure 21B. Vcc Undervoltage Threshold(-)
vs. Temperature
Vcc UVLO Threshold - (V)
Output Source Current (mA)
Figure 22A. Output Source Current
vs. Temperature
Temperature (°C)
Figure 22B. Output Source Current
vs. Voltage
Output Source Current (mA)
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Max.
Min.
Typ.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Max.
Min.
Typ.
Temperature (°C)
VBIAS Supply Voltage (V)
Typ.
Min.
0
100
200
300
400
500
10 12 14 16 18 20
Typ.
Min.
Max
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Bi as Current (µA )
Max
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Bias Current (µA)
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Output Sink Current (mA)
Temperature (°C)
Figure 23A. Output Sink Current
vs. Temperature Figure 23B. Output Sink Current
vs. Supply V oltage
Output Sink Current (mA)
VBIAS Supply Voltage (V)
Figure 24A. SD Input Positive Going Threshold (+)
vs. Temperature Figure 24B. SD Input Positive Going Threshold (+)
vs. Supply V oltage
Temperature (°C) Vcc Supply Voltage (V)
1
2
3
4
5
6
-50-25 0 25 50 75100125
SD Input Threshold (+) (V)
1
2
3
4
5
6
10 12 14 16 18 20
SD Input Threshold (+) (V)
Max. Max.
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125 0
200
400
600
800
1000
10 12 14 16 18 20
Min.
Typ.
Min.
Typ.
IRS2004(S) PbF
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01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
01-6027
01-0021 11 (MS-012AA)
8 Lead SOIC
87
5
65
D B
E
A
e
6X
H
0. 25 [.010 ] A
6
4312
4 . OUT L INE CONFORMS TO JEDEC OUT L INE MS-012A A .
NOTES:
1. DI MENSI ONI NG & TOLERANCING PER ASME Y14.5M-1994.
2 . CONT R OLLING D IMENSION: MILLIMETER
3 . D IMENSIONS ARE SHOW N IN MILLIMETERS [INCHES] .
7
K x 4 5°
8X L 8X c
y
FOOTPRINT
8X 0.72 [ . 02 8]
6. 46 [ . 2 55]
3X 1.27 [ . 05 0] 8X 1.78 [ . 07 0]
5 D IMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 D IMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 D IMENSION IS T HE LE NGT H OF LEAD FOR SOLD ERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
0. 25 [.010 ] CAB
e1 A
A1
8X b
C
0. 10 [.004 ]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINC HES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
Case Outline
IRS2004(S) PbF
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CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A 7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D 5.45 5.55 0.214 0.218
E 6.30 6.50 0.248 0.255
F 5.10 5.30 0.200 0.208
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062
Metric Imperial
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 18.40 n/a 0.724
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566
Metric Imperial
E
F
A
C
D
G
A
BH
N
OT E : CO NTROLLING
D
IMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
Tape & Reel
8-lead SOIC
IRS2004(S) PbF
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ORDER INFORMATION
8-Lead PDIP IRS2004PbF
8-Lead SOIC IRS2004SPbF
8-Lead SOIC Tape & Reel IRS2004STRPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRSxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
Data and specifications subject to change without notice. 11/27/2006
