intel. 82050 ASYNCHRONOUS COMMUNICATIONS CONTROLLER m Asynchronous Operation @ Seven I/O Pins 5- to 8-Bit Character Format Dedicated Modem 1/0 Odd-, Even-, or No-Parity Generation General Purpose I/O and Detection . Serial Bit Rate: DC to 56 Kb/s Moceeeee ace fo Most Intel m Programmable, 16-Bit Baud Rate @ Internal Diagnostics with Local Generator Loopback @ System Clock On-Chip Crystal Oscillator 7 Reperting Interrupt and Status Externally Generated Clock CHMOS III Techno! Provid . echnology Provides 28-Lead DIP and PLCC Packages Increased Reliability and Reduced g IBM PC (INS 16450/8250A) Software Power Consumption Compatible @ Line Break Generation and Detection The Intel CHMOS 82050 Asynchronous Communications Controller is a low cost, higher performance alterna- tive to the INS 16450it emulates the INS 16450 and provides 100% compatibility with IBM PC software. Its 28-lead package provides all the functionality necessary for an IBM PC environment while substantially de- creasing board space requirements. The 82050s simpler system interface reduces TTL glueespecially for higher frequency PC bus designs. The 82050 provides a low cost, high-performance integrated modem solu- tion when combined with Intels 89024 modem chip set. The compact 28-pin 82050 is fabricated using CHMOS III technology for decreased power consumption and increased reliability. Voc Vss Tx MACHINE TxD A(2=0) (7-0) INT Rx MACHINE BUS INTER= RESET FACE UNIT cs BAUD RATE GENERATOR ouT2 Ri DSR MODEM 1/0 DTR RIS cTs CLKX4 CRYSTAL X2 OSCIL 290137-1 Figure 1. Block Diagram August 1990 2-26 Order Number: 290137-004intel. 82050 WY p4C]1 28) ps ps 2 27 2) 02 pe C3 26 01 INT p74 25) po Txo INTC] 5 24D a2 vss Txo O16 230 a1 0UT2/x2 G vss 7 22/0) ao cik/x1 0UT2/x2 C] 8 82050 21 vec Iq cLK/x1 CJ 9 20RD psRQ Ri} 10 1919 WR DSR} 11 18 Cs OCD Cy 12 17 [EI RESET g n ie EB RxD 4 13 16 ats BE ble a cTsy 14 15/5 OTR a 290137-2 290137-3 Figure 2. PLCC Pinout Figure 3. DIP Pinout 82050 PINOUT DEFINITION Symbol Pin No. Type Name and Description RESET 17 RESET: A high on this input pin resets the 82050. cs 18 CHIP SELECT: A low on this input pin enables the 82050 and allows read or write operations. A2-A0 24-22 ADDRESS PINS: These inputs interface with three bits of the system address bus to select one of the internal registers for read or write. D7-D0 1-4 25-28 1/0 DATA BUS: Bi-directional, three state, 8-Bit Data Bus. These pins allow transfer of bytes between the CPU and the 82050. 20 READ: A low on this input pin allows the CPU to read data or status bytes from the 82050. 19 WRITE: A low on this input allows the CPU to write data or control bytes to the 82050. INT INTERRUPT: A high on this output pin signals an interrupt request to the CPU. The CPU may determine the particular source and cause of the interrupt by reading the 82050 status registers. CLK/X1 MULTIFUNCTION: This input pin serves as a source for the internal system clock. The clock may be asynchronous to the serial clocks and to the processor clock. This pin may be used in one of two modes: CLK-in this mode an externally generated clock should be used to drive this input pin; X1-in this mode the clock is generated by a crystal to be connected between this pin (X1) and the X2 pin. (See system clock generation.) OUT2/X2 MULTIFUNCTION: This is a dual-function pin which may be configured to one of the following functions: OUT2a general purpose output pin controlled by the CPU is only available when the CLK/X1 pin is driven by an externally generated clock; X2this pin serves as an output pin for the crystal oscillator. Note: The configuration of pin is done during hardware reset. For more details refer to the system clock generation. 2-27intel. 82050 82050 PINOUT DEFINITION (Continued) Symbol a Type Name and Description TXD 6 oO TRANSMIT DATA: Serial data is transmitted via this output pin starting at the least significant bit. RXD 13 l RECEIVE DATA: Serial data is received on this input pin starting at the least significant bit. Ri 10 I RING INDICATION: RI - Ring indicatorinput, active low. This is a general purpose input accessible by the CPU. BTR 15 oO DBTRDATA TERMINAL READY: Output, active low. This is a general purpose output pin controlled by the CPU. During hardware reset, this pin is an input used to determine the system clock mode. (See System Clock Generation.) DSR 4 1/0 DSRDATA SET READY: Input, active low. This is a general purpose input pin accessible by the CPU. RTS 16 Oo RTSREQUEST TO SEND: Output, active low. This is a general purpose output pin controlled by the CPU. During hardware reset, this pin is an input used to determine the system clock mode. (See system clock generation) cTs 14 I CLEAR TO SEND: input active low. This is a general purpose input pin accessible by the CPU. : DCD 12 1/0 DCDDATA CARRIER DETECTED: Input, active low. This is a general purpose input pin accessible by the CPU. vec 21 P VCC: Device power supply. VSS 7 P VSS: Ground. SYSTEM INTERFACE The 82050 has a simple demultiplexed bus interface which consists of a bidirectional, three-state, 8-bit data bus and a 3-bit address bus. The Reset, Chip Select, Read, and Write pins, along with the Interrupt pin, provide the remaining signals necessary to inter- face to the CPU. The 82050s system clock can be generated externally and provided through the CLK pin; or its on-chip crystal oscillator can be used by attaching a crystal to the X1 and X2 pins. For com- patibility with IBM PC software, a system clock of 18.432 MHz (with divide by two enabled) is recom- mended. The 82050, along with a transceiver, ad- dress decoder, and a crystal, complete the interface to the IBM PC Bus. SYSTEM CLOCK OPTIONS The 82050 has two modes of system clock opera- tion. It can accept an externally generated clock, or use a crystal to internally generate its system clock by using the on-chip oscillator. , The 82050 has an on-chip oscillator which can be used to generate its system clock. The oscillator will take the input from a crystal attached to the X1 and CRYSTAL OSCILLATOR Hr xt Tut. Parallet Resonant Crystal Freq. Max = 18.432 MHz (Divided by 2) Figure 4. Crystal Oscillator X2 pins. The oscillator frequency is divided by two before being inputted into the chip circuitry. !f an 18.432 MHz crystal is used, then the actual system clock frequency of the 82050 will be 9.216 MHz. This_mode is configured via a strapping option on the RTS pin. It is very important to distinguish between the clock frequency being supplied into the 82050 and the system clock frequency. The term system clock re- fers to the clock frequency being supplied to the 82050 circuitry (divided or undivided). The following examples delineate the three options for clock us- age and their effect on the 82050 system clock as weil as on the BRG source frequency:intel. 82050 1. Crystal Oscillator: (Maximum 18.432 MHz) System Clock Frequency = Crystal Frequency/2 BRG Source Clock Frequency = Crystal Frequency/10 2. External Clock (Divide by Two Enabled): (Maxi- mum 18.432 MHz) System Clock Frequency = External Clock Frequency/2 BRG Source Clock Frequency = External Clock Frequency/10 3. External Clock (Divide by Two Disabied): (Max- imum 9.216 MHz) System Clock Freq. quency BRG Source Clock Freq. = External Clock Frequency/5 External Clock Fre- OPEN COLLECTOR el RTS RESET 290137-5 Figure 5. Strapping During the power up or reset the RTS pin is an input; it is weakly pulled high internally and sampled by the falling edge of reset. If it is driven low externally, then the 82050 is configured for a crystal oscillator; otherwise an externally generated clock is expected. EXTERNALLY GENERATED SYSTEM CLOCK Osc. 290137-6 Figure 7. External Clock This is the default mode of system clock operation. The system clock is divided by two; however, the user may disable the divide by two by a hardware strapping option on the DTR pin. The strapping op- tion is similar to the one used on the RTS pin. 2-29 NOTE: The use of the Divide by Two strapping option in the crsytal oscillator mode is forbidden. BAUD RATE GENERATION The 82050 has a programmable 16-bit Baud Rate Generator (BRG). The 16X baud rate is generated by dividing the source clock with the divisor count from the BRG divisor registers (BAL, BAH). The BRG source clock is the 82050 system clock divided by five. If using an actual 82050 system clock of 9.216 MHz, then the BRG source clock will be 9.216 MHz/5 = 1.8432 MHz, which is compatible with the BRG source clock fed into the IBM PC serial port BRG. This allows the 82050, while using a faster system clock, to maintain full compatibility with soft- ware divisor calculations based on the 1.8432 MHz clock used in the IBM PC. RESET The 82050 can be reset by asserting the RESET pin. The RESET pin must be held high for at least 8 sys- tem clock cycles. If using crystal oscillator, a reset puise at least 1 ms should be used to ensure oscilla- tor start up. Upon reset, all 82050 registers (except TXD and RXD) are returned to their default states. During reset, the 82050s system clock mode of op- eration is also selected by strapping options on the RTS and DTR pins (see system clock generation). INTERRUPTS The INT pin will go high, or active, whenever one of the following conditions occurs provided it is en- abled in the interrupt enable register (IER): a. Receive Machine Error or Break Condition b. Receive Data Available c. Transmit Data Register Empty d. Change in the State of the Modem Input Pins The INT pin will be reset (low) when the interrupt source is serviced. The Interrupt Identification Regis- ter (IIR) along with the Line Status Register (LSR) and the Modem Status Register (MSR) can be used to identify the source requesting service. The IIR register identifies one of the four conditions listed above. The particular event or status, which triggers the interrupt mechanism, can be identified by read- ing either the Line Status Register or the Modem Status register. If multiple interrupt sources become active at any one time, then highest priority interrupt source is reflected in the IIR register when the inter- rupt pin becomes active. Once the highest priority interrupt is serviced, then the next highest priority82050 (HIGHEST PRIORITY) INTERRUPT MODEM (LOWEST PRIORITY) Rx CONDITION Rx DATA AVAILABLE Tx DATA REGISTER STATUS Rx PARITY ERROR OVERRUN ERROR BREAK DETECTED FRAMING ERROR DCD STATE CHANGE RI STATE CHANGE DSR STATE CHANGE CTS STATE CHANGE 290137~7 Figure 8. Interrupt Structure interrupt source is decoded into the IIR register; the whole procedure is repeated until there are no more pending interrupt sources. TRANSMIT The 82050 transmission mechanism involves the TX Machine and the TXD Register. The TX Machine reads characters from the TXD Register, serializes the bits, and transmits them over the TXD pin ac- cording to signals provided for transmission by the Baud Rate Generator. It also generates parity, and break transmissions upon CPU request. RECEIVE The 82050 reception mechanism involves the RX Machine and the RXD Register. The RX Machine assembles the incoming characters, and loads them onto the RXD Register. The RX Machine synchroniz- es the data, passes it through a digital filter to filter out spikes, and then uses three samples to generate the bit polarity. 2-30 The falling edge of the start bit triggers the RX Ma- chine, which then starts sampling the RXD input (3 samples). If the samples do not indicate a start bit, then a false start bit is determined and the RX Ma- chine returns to the start bit search mode. Once a Start bit is detected, the RX Machine starts sampling for data bits. If the RXD input is low for the entire character time, including stop bits, then the RX Machine sets Break Detect and Framing Error bits in the Line Status Register (LSR). It loads a NULL character into the RXD register. The RX Machine then enters the idle state. When it detects a MARK it resumes normal operation. SOFTWARE INTERFACE Like other I/O based peripherals, the 82050 is pro- grammed through its registers to support a variety of functions. The 82050 register set is identical to the 16450 register set to provide compatibility with soft- ware written for the IBM PC. The 82050 register set occupies eight addresses and includes control, status, and data registers. The three address lines and the Divisor Latch Access Bit are used to select the 82050 registers.age, UoNd0seq 40)}s/Bey 6 aun614 82050 HOO Z JaysiBey peg-yoyes0s YOS S19 ul ySC ul I Ul goa u! eBueu9 eBueuD eBueyo eBueup |. pepedu; peyeau| | peyenul peyeau| Hoo 9 ayes ees | 1 < H) eles eyes | indujsio | induj usa | induliy | induj god YS eIqEileAy JOM JOU JOU peyajeq Adwy snyejs Hog S eyeg xy UNJEAD Aued Buiwes4 yeeig OxL WXL 0 yS1 juewajdw0ey | juewedwo5 juewajdwoy | Wg }ojU0D HOO v y1d Sly 0 Z@1NO | yOeqdoo7 0 0 0 HOW vg sseooy eR is) bug oud , ove bva 2g yoye"] uybue7 u)6ue7 uyi6ue7 eapow epoy apow yeaig JOSIAIG Hoo 49}98J8UD JeyoeBseyo ug das Aued Aued Aued 19S avid HO1 oug bug Buipued ydnsejzu| ydnueyy HLO ydnue}u} BANOY eAnoy 0 0 0 0 0 ull eiqeug eiqeuR eqeu5 eyqeug ydnueyuy ydnse8}U| ydnwe}U| ydnweju) HOO L eyeg Xy Byeg XL BUIOBW XY wepow 0 0 0 y3! HOO I (L = avid) jnoo epiniq asW VDYg HVva H2o 0 (L = SV1d) UNOD epiAig gs7 VDE 1a _ 0 ove bug evg eve vig Sug 9g Zug eyeg xy eyeg xy eyeg xy eyeq xy eyeg xy eyeq xy | eleq xy eyeq xy axy oa bug ua eug pug sug 9ug Z4ua _ 0 eyeg XL eyed XL eyeq xX) eyed XL Beg XL eyeq xi | beg x1 eyeg XL OXL ynejeq | ssaippy 0 b @ S 9 Z 49}s/Bay dey 49}s|Bay NOILdIHDS30 YALSIDAY 2-31intel. 82050 TRANSMIT DATA REGISTER (TXD) This register holds the next data byte to be transmit- ted. When the transmit shift register becomes emp- ty, the contents of the Transmit Data Register are loaded into the shift register and the Transmit Data Register Empty condition becomes true. 7/65 ),4 o7< ps < Ds <___ Da 37, 2],1],0 L- po > pi > D2 > 03 290137-8 TXDTransmit Data Register RECEIVE DATA REGISTER (RXD) This register holds the last character received by the RX Machine. The character is right justified and the leading bits are zeroed. Reading the register emp- ties the register and resets the Received Character Available condition. CTsTsl-Tsl2T'[] o7 + Ly bo 06 < L> 01 Ds + > 2 ba > D3 290137-9 RXD-~-Receive Data Register 2-32 BRG DIVISOR LOW BYTE (BAL) This register contains the least significant byte of the Baud Rate Generators 16-bit divisor. This register is accessible only when the DLAB bit is set in the LCR register. MTelsl4lslz11] o7 +t ber do b+ Lane D1 ps <_ Lp 02 D4 4 > DS 290137-10 BALB5RG Divisor Low Byte BRG DIVISOR HIGH BYTE (BAH) This register contains the most significant byte of the Baud Rate Generators 16-bit divisor. This regis- ter is accessible ony when the DLAB bit is set in the LCR register. 7767574 ]3]2 ow bs < 0s <__ D< 140 Li D0 bneremep> ff eeeierermememen> [2 > D3 290137-11 . BAHBRG Divisor High Byteintel. 82050 INTERRUPT ENABLE REGISTER (IER) This register enables four types of interrupts which independently activate the INT pin. Each of the four interrupt types can be disabled by resetting the appropriate bit of the IER register. Similarly by setting the appropriate bits, selected interrupts can be enabled. If all interrupts are disabled, then the interrupt requests are inhibited from the IIR register and the INT pin. All other functions, including Status Register and the Line Status Register bits continue to operate normally. 776; 5t4 73721], 0 e Ly RXDA = RX DATA INTERRUPT ENABLE nme TXDE - TX DATA EMPTY ENABLE mt> RXIE RX INTERRUPT ENABLE > MIE = MODEM INTERRUPT ENABLE RESERVED A 290137-12 IERinterrupt Enable Register MIEMODEM Interrupt Enable RXIERX Machine Interrupt Enable TXDETX Data Register Empty RXDARX Data Available INTERRUPT IDENTIFICATION REGISTER (IIR) This register holds the highest priority enabled and active interrupt request. The source of the interrupt request can be identified by reading bits 2-1. (Telsl-lslz1-1] _ Ly ip INTERRUPT PENDING reserveo| * 80 | ACTIVE Py | INTERRUPT + > RESERVED 290137-13 ItRinterrupt Identification Register B1, BOInterrupt Bits, 2-1. These two bits reflect the highest priority, enabled and pending interrupt request. 11: RX Error Condition (Highest Priority) 10: RX Character Available 01: TXD Register Empty 00: Modem Interrupt (Lowest Priority) {PNInterrupt PendingThis bit is active low, and indicates that there is an interrupt pending. The interrupt logic asserts the INT pin as soon as this bit goes active (NOTE: the IIR register is continuously updated; so while the user is serving one interrupt source, a new interrupt with higher priority may enter IIR and replace the older interrupt vector). 2-33intel. 82050 LINE CONTROL REGISTER (LCR) This is a read/write register which defines the basic configuration of the serial link. 7letsl4]3f2}1]o pias < Ly cio) cuaracter SBK- SET BACK 4 Ls yy | LENGTH PM2 < L___ sBio- sToP BIT LENGTH PARITY { PM1 <___ wm __- LCA-Line Configure Register 290137-14 DLABDivisor Latch Access BitThis bit, when set, allows access to the Divisor Count Registers BAL and BAH. SBKSet BreakThis will force the TXD pin low. The TXD pin will remain low until this bit is reset. PM2PM0Parity Mode BitsThese three bits are used to select the various parity modes of the 82050. PMO PM2 PM1 Function 0 X X No Parity 1 0 0 Odd Parity 1 0 1 Even Parity 1 1 0 High Parity 1 1 1 Low Parity SBLStop Bit LengthThis bit defines the Stop Bit lengths for transmission. The RX Machine can identify 3/4 stop bit or more. SBL Character Length Stop Bit Length 0 Xx 1 1 5-Bit 41/2 1 (6, 7, or 8-Bit) 2 CLOCL1Character LengthThese bits define the character length used on the serial link. cli cLo Character Length 0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits 2-34intel. 82050 LINE STATUS REGISTER (LSR) This register holds the status of the serial link. When read, all bits of the register are reset to zero. (Te[sl-lsl2]:]] RESERVED aa ty RXDA = RX DATA AVAILABLE TXST= TX MACHINE STATUS 4 n> OF - OVERRUN ERROR TXDE = TXD EMPTY + ea> PE = PARITY ERROR BKD = BREAK DETECTED < > FE- FRAMING ERROR LSRLine Status Register 290137-15 RXDARxX Data AvailableThis bit, indicates that the RXD register has data available for the CPU to read. OEOverrun Errorindicates that a received character was lost because the RXD register was not empty. PE Parity ErrorIndicates that a received character had a parity error. FEFraming Errorindicates that a received character had a framing error. BkDBreak DetectedThis bit indicates that a break condition was detected, i.e., RxD input was held low for two character times. TXDETXD EmptyThis indicates that the 82050 is ready to accept a new character for transmission. in addition, this bit causes an interrupt request to be generated if the TXD register Empty interrupt is enabled. TXSTTX Machine StatusWhen set, this bit indicates that the TX Machine is Empty, i.e., both the TXD register and the TX Shift Register are empty. MODEM CONTROL REGISTER (MCR) This register controls the modem output pins. All the outputs invert the data, i.e., their output will be the complement of the data written into this register. 7TEGPS T4737 2717 0 Ly DTR RESERVED { 4=# meet RTS + ree RESERVED ic > OUT2 290137-16 MCRModem Control Register 2-35intel. 82050 LCLoopback ControlThis bit puts the 82050 into a Local Loopback mode. OUT2OUT2 OutputThis bit controls the OUT2 pin. The output signal is the complement of this bit. NOTE: This bit is only effective when the 82050 is being used with an externally generated clock. RTSRTS Output BitThis bit controls the RTS pin. The output signal is the complement of this bit. DTRDTR Output BitThis bit controls the DTR pin. The output signal is the complement of this bit. MODEM STATUS REGISTER (MSR) This register holds the status of the modem input pins (CTS, DGD, DSR, RI). It is the source of Modem interrupts (bits 3-0) when enabled in the IER register. If any of the above input pins change levels, then the appropriate bit in MSR is set. Reading MSR will clear the status bits. Ts[sl4[sl2]: Jo] COMPLEMENT OCD (H==>L) Ri COMPLEMENT CTS > STATE CHANGE DCD MSRMode Status Register 290137-17 DCDCDCD ComplementHolds the complement of the DCD pin. DRICRI ComplementHolds the complement of the RI pin. DSRCDSR ComplementHolds the complement of the DSR pin. CTSCCTS CompiementHolds the complement of the CTS pin. DDCDDelta DCDIndicates that the DCD pin has changed state since this register was last read. DRIDelta RiIndicates that the Ri pin has changed state from high to low since this register was last read. DDSRDelta DSRIndicates that the DSR pin has changed state since this register was last read. DCTSDelta CTSindicates that the CTS pin has changed state since this register was last read. SCRATCHPAD REGISTER (SCR) The 8-bit Read/Write register does not control the ACC. It is intended as a scratch pad register for use by the programmer. 2-36intel. 82050 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias ...... 0C to 70C D.C. SPECIFICATIONS Storage Temperature .......... 65C to + 150C Voltage on any Pin (w.r.t. Vg. 0.5V to Voc + 0.5V Voltage on Vcc Pin (w.r.t. Vgg)...... 0.5V to +7V Power Dissipation. ....................5 300 mw D.C. CHARACTERISTICS (Ta = 0 TO 70C, Voc = 5V +10%) Symbol Parameter Notes Min Max Units Vit input Low Voltage (1) 0.5 0.8 Vv Vin Input High Voltage (1), (7) 2.0 Voc Vv +0.5 VoL Output Low Voltage (2), (9) 0.45 Vv y Vou Output High Voltage (3), (9) 2.4 Vv lu Input Leakage Current (4) +10 pA ILo 3-State Leakage Current (5) +10 pA loHR Input High for DTR, RTS (10) 0.4 mA lotr Input Low for DTR, RTS (10) 14 mA LYTAL X1, X2 Load 10 pF loc Power Supply Current (6) 3.8 mA/MHz 35 mA (max) Cin Input Capacitance (8) 10 pF Cio \/O Capacitance (8) 10 pF CxTAL X41, X2 Load 10 pF NOTES: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2. @ lo = 2 mA. 3. @ lop = 0.4 mA. 4.0 < Vin < Voc. 5. 0.45V < Vout < (Vcc 0.45). 6. Voc = 5.5V; Vi_ 0.5V (max); Vin = Voc 0.5V (min); lo = lon = 0; 9.2 MHz (max). 7. Vin = -2.4V on RD and RXD pins. 8. Freq = 1 MHz. 9. Does not apply OUT2/X2 pin, when configured as crystal oscillator output (X2). 10. Input current for DTR, ATS pins during Reset for Clock Mode Configuration. 2-37intel. 82050 A.C. SPECIFICATIONS Testing Conditions: All AC output parameters are under output load of 20 to 100 pF, unless otherwise specified. AC testing inputs are driven at 2.4 for logic 1, and 0.45V for logic 0. Output timing measure- ments are made at 1.5V for both a logical 0 and 4. In the following tables, the units are ns, unless otherwise specified. System Interface SpecificationSystem Clock Specification: The 82050 system clock is supplied via the CLK pin or generated by on-chip crystal oscillator. The clock is optionally divided by two. The CLK parameters are given separately for internal divide-by-two option ACTIVE and INACTIVE. The system clock (after division by two, if active) must be at feast 16X the Tx or Rx baud rate (the faster of the two). RESET SPECIFICATION SYSTEM CLOCK SPECIFICATIONS Symbol Parameter | Min | Max | Notes DIVIDE BY TWO OPTIONACTIVE Tey/2 CLK Period 54} 250 (2) TCLCH {CLK Low Time 25 TCHCL | CLK High Time 25 TCH1CH2 | CLK Rise Time 10 (1) TCL2CL1 | CLK Fall Time 10 (1) FXTAL External Crystal | 4.0 | 18.432 Frequency Rating MHz DIVIDE BY TWO OPTIONINACTIVE Tcy CLK Period 108 TCLCH | CLK Low Time 54 TCHCL =| CLK High Time 44 {| 250 TCH1CH2 | CLK Rise Time 15 (1) TCL2CL1 | CLK Fall Time 15 (1) NOTES: 1. Rise/fall times are measured between 0.8 and 2.0V. 2. Tcy in ACTIVE divide by two option is TWICE the input clock period. Symbol Parameter Min Max Notes TRSHL Reset WidthCLK/X1 Configured to CLK 8 Tcy (1) TTLRSL RTS/DTR LOW Setup to Reset Inactive 6 Tcy (2) TRSLTX RTS/DTR Low Hold after Reset Inactive 0 Tey 20 (2) TRSHL RESET ne, | DTR/RTS NOTES: yO =e i t 290137-18 1. In case of CLK/X1 configured as X1, additional time is required to guarantee crystal oscillator wake-up. 2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally driven LOW during RESET according to the required configuration of the system clock. These parameters specify the timing requirements on these pins, in case they are externally driven LOW during RESET. The maximum spec on TRSLTX requires that the RTS/DTR pins not be forced later than TRSLTX maximum. 2-38intel. 82050 READ CYCLE SPECIFICATIONS Symbol Parameter Min Max Notes TRLRH RD Active Width 2 Tcy + 65 TAVRL Address/CS Setup Time to RD Active TRHAX Address/CS Hold Time after RD Inactive TRLDV Data Out Valid after RD Active 2Tcy + 65 (1) TCIAD Command Inactive to Active Delay Tey + 15 (2) TRHDZ Data Out Float Delay after RD Inactive 40 NOTES: 1. C1 = 20 pF to 100 pF. 2. Command refers to either Read or Write signals. A2-0 CS D7-0 29013719 WRITE CYCLE SPECIFICATION Symbol Parameter Min Max Notes TWLWH WR Active Width 2Tcy + 15 TAVWL Address CS Setup Time to WR Active TWHAX Address and CS Hold Time after WR TDVWH Data in Setup Time to WR Inactive 90 TWHDX Data in Hold Time after WR Inactive 12 we SCSSN VN _ +TWLWH et+ TCIAD o] TAVWL ~| TWHAX A2~0 CS _ VALID VALID _-_ TDVWH TWHDX D7=0 A_VALID P = i+ TCIAD \- 290137-20 2-39