a in tel M27128A Advanced 128K (16 x 8) UV Erasable PROM Military m Fast Access Times: B inteligent Programming Algorithm M27128A-20 200 ns Fastest EPROM Programming M27128A-30 300 ns a Intgligent Identifier Mode m Low Power Automated Programming Operations 140 mA Maximum Active = Compatible with M2764A and M27256 50 mA Maximum Standby Military T ture R a ul ry temperature Range gm Two Line Control 55C to + 125C (Tc) The Intel M27128A is a 5V only, 131,072-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The M27128A is an advanced version of the M27128 and is fabricated with Intel's HMOSIH-E technology which significantly reduces die size and greatly improves the devices performance, reliability and manufacturability. Several advanced features have been designed into the M27128A that allow fast and reliable programming the intgligent Programming Algorithm and the intgligent identifier Mode. Programming equipment that takes advantage of these innovations will electronically identify the M27128A and then rapidly program it using an efficient programming method. Two-line control and JEDEC-approved, 28 pin packaging are standard features of all Intel higher density EPROMs. This ensures easy microprocessor interfacing and minimum design efforts when upgrading, adding or choosing between non-volatile memory alternatives. *HMOS is a patented | process of intel Corporation , DATA OUTPUTS cc 0 Qp-0; GND o_ , Vip O t I { { { t t { IM27256|M2764A|M2732A|M27 16) M27128A 7 16; M2732A| M2764A| M272: OE | OUTPUT ENABLE v FGM | CHIP ENABLE pp | Vpp Veco | Voc El non atc ourputpurrers | | Aiz | Ar2 PGM | Aig A? Az Az Ar Yoo |Voc NAC. Aig ed 46 Ae Ae | Ae As {Ae Ag Ag =S] pecoven [c.| GATING As | As | As | As Ag |Ao Ag | Ag : _! = As Ag Aq Ay Vpp {A141 Any An apotess 4] re | Ag Ag Ag Ag OE |OE/Vpp| OE OE meuts {"} peconen | 19,072-BIT Ag Ag Ag | Az Ayo |A1o Ato | Ato a : CELL MATRIX Ay Ay A Ay GE ICE Ce CE oI Ao Ao Ao Ao 07 |07 oO; Oo; Oo Og Qo Qo Og |06 O6 O6 210603-1 1 Oy a, | 0; Os |Os5 Og Os Figure 1. Block Diagram 2 om o oy of of of of A a my 3 3 3 3 Pin Names NOTE: Ag-A1g Addresses Intel Universal Site-Compatible EPROM Pin Configurations are Shown in the cE Chip Enable Blocks Adjacent to the M27128A Pins OE Output Enable Figure 2. Pin Configurations Op-O7 Outputs PGM Program December 1989 7-32 Order Number: 210603-003intel M27128A ABSOLUTE MAXIMUM RATINGS NOTICE: This is a production data sheet. The specifi- Case T Under Bi C to + 125C cations are subject to change without notice. ase Temperature Under Bias... . 5 to 125" * WARNING: Stressing the device beyond the Absolute Storage Temperature .......... 65C to + 150C Maximum Ratings may cause permanent damage. All Input or Output Voltages with These are stress ratings only. Operation beyond the Respect to Ground........... +6.25V to 0.6V Operating Conditions is not recommended and ex- . . tended exposure beyond the Operating Conditions Voltage on Pin 24 with may affect device reliability. Respect to Ground........... +13.5V to 0.6V Vpp Supply Voltage with Respect to Ground During Programming ....+14V ta 0.6V Operating Conditions Symbol Description Min Max Units To Case Temperature (Instant On) ~55 +125 C Voc Digital Supply Voltage 4.50 5.50 v READ OPERATION D. C. CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Limits Comments Min Max Load Current 10 =.5V Current 10; 5.5V Current Read 5 =5.5V Voc Current 50 CE= Vcc Current Active CE=0E=Vv Low Low ; =2.1mA = 400 Read . Vec=5.0V +0.5V A.C. CHARACTERISTICS - 27 - Symbol Parameter M27128A-20 M27128A-30 * Unit Comments Min Max Min Max tacc Address to Output Delay 200 300 ns CE =0E=ViL tor CE to Output Delay 200 300 ns OE = Vit tog SE to Output Delay a5 110 ns CE = Vit tor) OE High to Output Float 0 65 0 80 ns CE=Vit ton(4) Output Hold from 0 0 ns CE = OF = Vit Addresses CE or OE Whichever Occurred First NOTES: 1. Veg must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. Vpp may be connected directly to Voc except during programming, The supply current would then be the sum of icc and Ippt. 3. Typical values are for Tc = 25C and nominal supply voltages. 4. Output Float is defined as the point where data is no longer drivensee timing diagram on the following page. 7-33intel M27128A CAPACITANCE T,.=25C, f=1 MHz Symbol Parameter Typ(?) | Max | Units | Conditions Cin Input Capacitance 4 6 pF Vin=0V Cout | Output Capacitance 8 12 | pF | Vour=0V A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V 2A 1N914 2.0 2.0 > TEST POINTS < 3.3K0. 0.8 08 DEVICE 0.45 UNDER out 210603-3 TEST c T A.C. Testing; Inputs are Driven at 2.4V for a Logic 1 and 0.45V = for a Logic 0. Timing Measurements are made at 2.0V fora C. = 100 pF 210603-4 Logic "1" and 0.8V for a Logic 0. Cy Includes Jig Capacitance A.C. WAVEFORMS rs) /~ ouee ADDRESSES x ADDRESS vi N eeee TY ror Vi eooee cg! Vin eent oe Vi jm oo 00 Ltt $tog . ? tace ton vin pam ese HIGH Z HI / ) HIGH Z OUTPUT: VALID OUTPUT ve WAL o 210603-5 NOTES: 1. apical values are for Tc= 25C and nominal supply voltages. 2. may be delayed up to tceto, after the falling edge of CE without impact on tce. 3. This parameter is only sampled and is not 100% tested. Output float is defined as the point where data is no longer driven.intel M27128A DEVICE OPERATION The seven modes of operation of the M27128A are listed in Table 1..A single 5V power supply is re- quired in the read mode. All inputs are TTL leveis except for Vpp and 12V on AQ for intgligent identifier mode. Table 1. Mode Selection Pins | CE | OE [Pam Ag! Vpp[ Vcc] Outputs Mode (20) | (22)) (27) ] (24) (1) | (28) | (11-13, 15-19) Read Vir] Vind] Vin | X J ec] Voc Dout Output Disable Vic} Vin} Vip | X [Yecl] oc High Z Standby Vin) X |X |X fVeclVoc| HighZ Verify Vic | Vic | Vin | X [Vee] Voc, - Dour Program Inhibit. | Vin] X | X | X |Vpp|Voc| HighZ Intgligent Identifier} Vir | Vir | Vin | Yu | Voc] Yoo Code intgligent Vir] Yin | Vin | X | Yep] Voc Din Programming NOTES: 1. X can be Vip or Vi. 2. Vy=12.0V +0.5V. Read Mode The M2712B8A has two control functions, both of which must be Iegically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output En- able (OE) is the output control and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- ble, the address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that ce has been low and address- es have been stable for at least tacc-tog. Standby Mode The M27128A has standby mode which reduces the maximum current from 100 mA to 40 mA. The M27128A is placed in the standby mode by applying a TTL-high signa! to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR-Tieing Because EPROMs are usually used in larger memo- ry arrays, intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur 7-35 To use these two control lines most efficiently, CE (pin 20) should be decoded and used as the primary device selecting function, while OE (pin 22) should be made a common connection to all devices in the array and connected to the READ line from the sys- tem control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. System Considerations The power switching characteristics of HMOSII-E EPROMs require careful decoupling of the devices. The supply current, Icc, has three segments that are of interast to the system designerthe standby cur- rent level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive loading of the device. The associated transient voltage peaks can be suppressed by com- plying with Intels Two-Line Control, as detailed in Intels Application Note AP-72, Order Number 8566, and by properly selected decoupling capacitors. It is recommended that a 0.1 uF ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor for low inher- ent inductance and should be placed as close to the device as possible. In addition, a 4.7 F bulk electro- lytic capacitor should be used between Voc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk ca- pacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces. This induc- tive effect should be further minimized through spe- cial layout considerations such as larger traces and gridding (refer to High Speed Memory System De- sign Using 2147H, AP-74). In particular, the Vss (Ground) plane should be as stable as possible. Programming Modes Caution: Exceeding 14V on pin 1 (Vpp) will perma- nently damage the M27128A. Initially, and after each erasure, all bits of the M27128A are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a t is by ultravio- let light erasure. The M27128A is in the programming mode when Vpp input is at 12.5V and CE and PGM are both at TTL low. The data to be programmed is appliedintel M27128A 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. intgligent Programming Algorithm The M27128A intgligent Programming Algorithm rapidly programs Intel M27128A EPROMs using an efficient and reliable method particularly suited to the production programming environment. Typical programming time for individual devices is less than one and a half minutes. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flow- chart of the M27128A intgligent Programming Algo- rithm is shown in Figure 3. The intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial CE pulse(s) is one millisecond, which will then be followed by a longer overprogram pulse of length 3X ms. X is an iteration counter and is equa! to the number of the initial one millisecond pulses applied to a particular M27128A location, be- fore a correct verify occurs. Up to 25 one-millisec- ond pulses per byte are provided for before the over- program puise is applied. The entire sequence of program pulses and byte verifications is performed at Voc = 6.0V and Vpp = 12.5V. When the intgligent Programming cy- cle has been completed, all bytes should be com- pared to the original data with Vcc = Vpp = 5.0V. Program Inhibit Programming of multiple M27128As in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input inhibits the other M27128As from being pro- grammed. Except for CE, all like inputs (inctuding OE) of the parallel M27128As may be common. A TTL low-lev- el pulse applied to the CE input with Vpp at 12.5V will program the selected M27128A. Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with OE at Vi, CE at Vi_, PGM at Viy and Vpp at 12.5V. . Inteligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the M27128A. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line AQ (pin 24) of the M27128A. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO (pin 10) from Vi, to Vjy. All other address lines must be held at Vi_ during the intgligent Identifier Mode. Byte 0 (AO= Vj.) represents the manufacturer code and byte 1 (AO= Vj) the device identifier code. For the Intel M27128A, these two identifier bytes are giv- en in Table 2. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (07) defined as the parity bit. ERASURE CHARACTERISTICS The erasure characteristics of the M27128A are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wave- lengths in the 3000-4000A range. Data show that constant exposure to room level fluorescent lighting could erase that typical M27128A in approximately 3 years, while it would take approximately 1 week Table 2. M27128A Intgligent Identifier Bytes Pins Ao O07 Og Os Og Og Oz QO; Oo Hex Identifier (10) | (19) | (18) | (17) | (16) | (15) | (13) | (12) | (11) | Data Manufacturer Code Vie 1 0 0 0 1 0 0 1 89 Device Code Vin 1 0 0 0 1 0 0 1 89 NOTES: : 41. Ag = 12.0V +0.5V. 2. Ay Ag, Ato Ata, CE, OF = Vit. 7-36M27128A START ADDA = FIRST LOCATION INCREMENT X DEVICE VERIFY ONE @YTE FAILEO INCREMENT ADOAR COMPARE ALL BYTES TO ORIGINAL DATA DEVICE FAILED. vi OEVICE PASSED 210603-6 Figure 3. M27128A inteligent Programming Flowchart 7-37intel M27128A to cause erasure when exposed to direct sunlight. If the M27128A is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the M27128A window to prevent unintentional erasure. # The recommended erasure procedure for the M27128A is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of 15 Wsec/cm2. inteligent Programming Algorithm The erasure time with this dosage is approximately 45 to 20 minutes using an ultraviolet lamp with a 12000 pW/cm2 power rating. The M27128A should be placed within 1 inch of the lamp tubes during era- sure. The maximum integrated dose a M27128A can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 pW/cm2). Exposure of the M27128A to high intensity UV light for longer periods may cause permanent damage. D.C. PROGRAMMING CHARACTERISTICS (Over Specified Operating Conditions) Symbol Parameter Limits Comments Min Max | Unit (Note 1) lu Input Current (All Inputs) 10 pA Vin = Vicor Vin ViL Input Low Level (All Inputs) 0.1 0.8 Vv Vin input High Level 2.0 Voc V VoL Output Low Voltage During Verify 0.45 Vv lol = 2.1 mA Vou Output High Voltage During Verify 2.4 Vv lou = 400 pA loca "Voc Supply Current (Program & Verify) 100 mA Ippo Vpp Suppiy Current (Program) 50 mA CE=Vit Vu Ag intgligent Identifier Voltage 11.5 12.5 Vv NOTE: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 7-38intel M27128A A.C. PROGRAMMING CHARACTERISTICS (Over Specified Operating Conditions) Symboi Parameter Limits Comments Min | Typ Max Unit (Note 1) tas Address Setup Time 2 pS toes OE Setup Time 2 BS tos Data Setup Time 2 ps taH Address Hold. Time 0 ps toy . Data Hold Time 2 ps tprp(4) OE High to Output Float Delay 0 130 ns tvps Vpp Setup Time 2 ps tycs Voc Setup Time 2 ps tces CE Setup Time 2 BS tpw PGM initial Program Pulse Width 0.95 1.0 1.05 ms (Note 3) topw PGM Overprogram Pulse Width 2.85 78.75 ms (Note 2) toe Data Valid from OE 150 ns NOTES: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. The length of the overprogram pulse may vary from 2.85 ms to 78.75 ms as a function of the iteration counter value X. 3. Initial Program Pulse width tolerance is 1 ms +5%. 4, Output Float is defined as the point where data is no longer drivensee timing diagram. *A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%)...... 20 ns Input Pulse Levels .................. 0.45V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level ...... 0.8V and 2.0V 7-39intel M27128A inteligent Programming WAVEFORMS ADDRESSES PROGRAM: VERIFY v we x ADORESS TABLE Vi mnt 2 Lg tas a + tan Vin HIGH Z fF ~ DATA IN STABLE DATA OUT VALID Vv. " t {pee tos es + 12,.5V >. 5.04 __/ lg !PS___p} 6.0V >> 5.ov g 'VCS__ I Vin Vi ve ces of V4, cece 2 Vie tow e NOES toe . Mn * e} lomw \ Viv 210603-7 NOTES: 1. The Input Timing Reference Level is 0.6V for Vj, and 2V for a Vip. 2. tog and tpgp are characteristics of the device but must be accommodated by the programmer. 3. When programming the M27128A, a 0.1 uF capacitor is required across Vpp and ground to supress spurious voltage transients which can damage the device. 7-40