4/27/07
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HEXFET® Power MOSFET
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
IRFB4310ZPbF
IRFS4310ZPbF
IRFSL4310ZPbF
D2Pak
IRFS4310ZPbF
TO-220AB
IRFB4310ZPbF
TO-262
IRFSL4310ZPbF
S
D
G
S
D
G
S
D
G
DDD
GDS
Gate Drain Source
S
D
G
VDSS 100V
RDS
(
on
)
typ. 4.8m:
max. 6.0m:
ID (Silicon Limited) 127A c
ID (Package Limited) 75A
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
IDM Pulsed Drain Current d
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
dv/dt Peak Diode Recovery fV/ns
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy emJ
IAR Avalanche Currentc A
EAR Repetitive Avalanche Energy gmJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k––– 0.6
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 k––– 62
RθJA Junction-to-Ambient (PCB Mount) , D2Pak jk ––– 40
130
See Fig. 14, 15, 22a, 22b,
250
18
-55 to + 175
± 20
1.7
10lbxin (1.1Nxm)
300
Max.
127c
90c
560
75
PD - 97115A
IRFB/S/SL4310ZPbF
2www.irf.com
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.047mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 75A, di/dt ≤ 600A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
S
D
G
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 4.8 6.0 mΩ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V
IDSS Drain-to-Source Leakage Current ––– ––– 20 μA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
RGInternal Gate Resistance ––– 0.7 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 150 ––– ––– S
QgTotal Gate Charge ––– 120 170 nC
Qgs Gate-to-Source Charge ––– 29 –––
Qgd Gate-to-Drain ("Miller") Charge ––– 35
Qsync Total Gate Charge Sync. (Qg - Qgd)––– 85 –––
td(on) Turn-On Delay Time ––– 20 ––– ns
trRise Time ––– 60 –––
td(off) Turn-Off Delay Time ––– 55 –––
tfFall Time ––– 57 –––
Ciss Input Capacitance ––– 6860 ––– pF
Coss Output Capacitance ––– 490 –––
Crss Reverse Transfer Capacitance ––– 220 –––
Coss eff. (ER) Effective Output Capacitance (Energy Related)
––– 570 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)h––– 920 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 127cA
(Body Diode)
ISM Pulsed Source Current ––– ––– 560 A
(Body Diode)d
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 40 ns TJ = 25°C VR = 85V,
––– 49 TJ = 125°C IF = 75A
Qrr Reverse Recovery Charge ––– 58 nC TJ = 25°C di/dt = 100A/μs g
––– 89 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
ID = 75A
RG = 2.7Ω
VGS = 10V g
VDD = 65V
ID = 75A, VDS =0V, VGS = 10V
TJ = 25°C, IS = 75A, VGS = 0V g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 5mAd
VGS = 10V, ID = 75A g
VDS = VGS, ID = 150μA
VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
VDS =50V
Conditions
VGS = 10V g
VGS = 0V
VDS = 50V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 0V to 80V i, See Fig. 11
VGS = 0V, VDS = 0V to 80V h
Conditions
VDS = 50V, ID = 75A
ID = 75A
VGS = 20V
VGS = -20V
IRFB/S/SL4310ZPbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60μs PULSE WIDTH
Tj = 25°C
4.5V
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
≤ 60μs PULSE WIDTH
Tj = 175°C
4.5V
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current
(Α)
VDS = 50V
≤ 60μs PULSE WIDTH
TJ = 25°C
TJ = 175°C
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
0
2000
4000
6000
8000
10000
12000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 40 80 120 160 200
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
VDS= 20V
ID= 75A
IRFB/S/SL4310ZPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
90
100
110
120
130
V(BR)DSS , Drain-to-Source Breakdown Voltage
ID = 5mA
020 40 60 80 100
VDS, Drain-to-Source Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Energy (μJ)
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
100
200
300
400
500
600
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 11A
19A
BOTTOM 75A
0.1 1 10 100
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100μsec
DC
25 50 75 100 125 150 175
TC, Case Temperature (°C)
0
20
40
60
80
100
120
140
ID, Drain Current (A)
LIMITED BY PACKAGE
IRFB/S/SL4310ZPbF
www.irf.com 5
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τι (sec)
0.018756 0.000373
0.159425 0.000734
0.320725 0.005665
0.101282 0.115865
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
Ci
i
/
Ri
Ci= τi/Ri
τ
τ
C
τ
4
τ
4
R
4
R
4
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
IRFB/S/SL4310ZPbF
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250μA
ID = 150μA
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
4
8
12
16
20
24
IRRM - (A)
IF = 30A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
100
200
300
400
500
600
QRR - (nC)
IF = 45A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
100
200
300
400
500
600
QRR - (nC)
IF = 30A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
4
8
12
16
20
24
IRRM - (A)
IF = 45A
VR = 85V
TJ = 125°C
TJ = 25°C
IRFB/S/SL4310ZPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
1K
VCC
DUT
0
L
20K
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
*** VGS = 5V for Logic Level Devices
***
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
**
*
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
IRFB/S/SL4310ZPbF
8www.irf.com
TO-220AB packages are not recommended for Surface Mount Application.
TO-220AB Part Marking Information
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
LOT CODE 1789
EXAMPLE: T HIS IS AN IRF1010
Note: "P" in assembly line position
indicates "Lead - Free"
IN THE ASSEMBLY LINE "C"
AS S EMBLED ON WW 19, 2000
INTERNATIONAL PART NUMBER
RECTIFIER
LOT CODE
ASSEMBLY
LOGO
YEAR 0 = 2000
DAT E CODE
WE E K 19
LINE C
IRFB/S/SL4310ZPbF
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TO-262 Part Marking Information
LOGO
RECTIFIER
INTERNATIONAL
LOT CODE
ASSEMBLY
LOGO
RECTIFIER
INTERNATIONAL
DAT E CODE
WE E K 19
YEAR 7 = 1997
PART NUMBER
A = AS S E MB L Y S I T E CODE
OR
PRODUCT (OPTIONAL)
P = DE S I GNAT E S L E AD- F R E E
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
ASSEMBLY
PART NUMBER
DAT E CODE
WEEK 19
LINE C
LOT CODE
YEAR 7 = 1997
AS S E MBL E D ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IRFB/S/SL4310ZPbF
10 www.irf.com
D2Pak Part Marking Information
F530S
THIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INT ERNATIONAL
RECTIFIER
LOGO
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
DAT E CODE
IN THE ASSEMBLY LINE "L"
AS S EMBLE D ON WW 02, 2000
T HIS IS AN IRF 530S WIT H
LOT CODE 8024 INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
PART NUMBER
F530S
For GB Production
IRFB/S/SL4310ZPbF
www.irf.com 11
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/07
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/