MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
All external terminals are treated with lead free solder (ingredient : Sn-Cu) plating.
Type name , Lot No.
QR
Code
22 23 24 25 26 27 28
2.54
±
0.3
30✕2.54(=76.2)
79
±
0.5
67
±
0.3
8
±
0.3
10.16
±
0.3
1. VUFS
2. VUFB
3. VP1
4. UP
5. VVFS
6. VVFB
7. VP1
8. VP
9. VWFS
10. VWFB
11. VP1
12. VPC
13. WP
14. VN1
15. VNC
16. CIN
17. CFO
18. FO
19. UN
20. VN
21. WN
22. P
23. U
24. V
25. W
26. NU
27. NV
28. NW
12 34 56 78 9
10 11 12 13 14 15 16 17 18 19 20 21
2-φ4.5
±
0.2
18.5
±
0.5
44
±
0.5
20.4
±
0.5
42.6
±
0.5
34
±
0.5
27.4
±
0.5
8.2
±
0.5
16.1
±
0.3
(2.5)
(2)
(2)
(0.3)
(1.7)
(0.3)
Heat sink side
A
48.6
±
0.6
Heat sink side
Detail : A
PS22052 INTEGRATED POWER FUNCTIONS
1200V/5A low-loss 4th generation IGBT inverter bridge for
3 phase DC-to-AC power conversion
APPLICATION
AC400V 0.2kW~0.4kW inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible (High active logic).
Dimensions in mm
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Protection against common-mode noise)
Note1: To prevent input signals oscillation, an RC coupling at each input terminal is recommended.
2: By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible.
3: Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kΩ resistor.
4: The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect DIP-IPM against catastrophic high
surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to mount closely to the
P and N1 terminals.
5: Fo output pulse width (t
FO
) should be determined by connecting external capacitor between CFO and V
NC
terminals. (Example : t
FO
=2.4ms(typ.)
at C
FO
=22nF)
6: High voltage (1200V or more) and fast recovery type (less than 100ns) diodes should be used for the bootstrap circuit.
7: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
8: To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between V
NC
and NU, NV, NW terminals.
CBU–
CBU+
CBV–
CBV+
CBW–
CBW+
F
O
CFO
M
(Note 7)
DIP-IPM
C2
C1
(Note 4)
Z
(15V line)
V
D
V
NC
C
H-side IGBT
S
L-side IGBT
S
W
V
U
P
N
1
NW
NV
NU
High-side input (PWM)
(5V line) (Note 1,2)
(Note 6)
AC line output
Input signal
conditioning
Level shifter
Drive circuit
Protection
circuit (UV)
Input signal
conditioning
Input signal
conditioning
circuit (UV)
Protection
circuit (UV)
Drive circuit Drive circuit
Level shifter Level shifter
Protection
Drive circuit
Input signal conditioning
Fo logic Protection
circuit
Control supply
Under-Voltage
protection (UV)
AC line input
Inrush current
limiter circuit
(5V line) (Note 1, 2) Fault output (5V line)
(Note 3, 5)
Low-side input (PWM)
C1 : Tight tolerance, temp-compensated electrolytic type
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering
(Note : The capacitance depends on the PWM control
scheme used in the applied system.)
(Note 8)
V
NC
CIN
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
Note1: In the recommended external protection circuit, please select the RC time
constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be
as short as possible.
Drive circuit
Drive circuit
Protection circuit
SC protection
trip level
I
C
(A)
t
w
(µs)
2
0
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) with a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output.
Since the SC fault may be repetitive, it is recommended to stop the system and check the fault,
when the Fo signal is received.
(Note 1)
(Note 2)
W
V
U
V
NC
CIN
A
P
N1
CR
Shunt
resistor
External protection circuit
DIP-IPM
L-side IGBT
S
H-side IGBT
S
NU
NV
NW
B
C
Collector current
waveform
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Note 2 : TC MEASUREMENT POINT
Power terminals
TC
Heat-sink
Heat sink boundary
Control terminals
TC
800
–20~+100
–40~+125
2500
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
VCC(PROT)
TC
Tstg
Viso
V
V
V
V
mA
V
20
20
–0.5~VD+0.5
–0.5~VD+0.5
1
–0.5~VD+0.5
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VPC,
UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Control supply voltage
Control supply voltage
Input voltage
Fault output supply voltage
Fault output current
Current sensing input voltage
VD
VDB
VIN
VFO
IFO
VSC
900
1000
1200
5
10
38.3
–20~+125
Applied between P-NU, NV, NW
Applied between P-NU, NV, NW
TC = 25°C
TC = 25°C, less than 1ms
TC = 25°C, per 1 chip
(Note 1)
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
ConditionSymbol Parameter Ratings Unit
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
V
V
V
A
A
W
°C
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
ConditionSymbol Parameter Ratings Unit
CONTROL (PROTECTION) PART
Symbol Ratings Unit
Self protection supply voltage limit
(short circuit protection capability)
Module case operation temperature
Storage temperature
Isolation voltage
V
°C
°C
Vrms
TOTAL SYSTEM
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).
Parameter Condition
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
3.4
3.2
2.9
2.2
—
0.7
3.8
0.7
1
10
2.61
3.18
0.047
mA
V
Tj = 25°C
Tj = 125°C
Tj = 25°C
Tj = 125°C
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
ConditionSymbol Parameter Limits
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
Case to fin, (per 1 module) thermal grease applied
Rth(j-c)Q
Rth(j-c)F
Rth(c-f)
Min.
THERMAL RESISTANCE
Typ. Max.
—
—
—
—
—
—
Unit
–IC = 5A, VIN = 0V
Condition
Symbol Parameter Limits
Min. Typ. Max.
—
—
—
0.8
—
—
—
—
—
—
Unit
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Collector-emitter saturation
voltage
FWDi forward voltage
Junction to case thermal
resistance
VD = VDB = 15V
VIN = 5V, IC = 5A
Switching times
VCC = 600V, VD = VDB = 15V
IC = 5A, Tj = 125°C, VIN = 0 ↔ 5V
Inductive load (upper-lower arm)
Collector-emitter cut-off
current VCE = VCES
2.7
2.5
2.4
1.5
0.2
0.4
2.8
0.4
—
—
V
µs
µs
µs
µs
µs
°C/W
°C/W
°C/W
CONTROL (PROTECTION) PART
Note 4: Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 1.7 times device current rating.
5:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 9.3 ✕ 10-6 ✕ tFO [F].
Symbol
ID
VFOH
VFOL
VSC(ref)
IIN
UVDBt
UVDBr
UVDt
UVDr
tFO
Vth(on)
Vth(off)
Parameter Condition Limits Unit
Circuit current
Fault output voltage
Short circuit trip level
Supply circuit under-voltage
protection
Fault output pulse width
ON threshold voltage
OFF threshold voltage
VD = VDB = 15V
VIN = 5V
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
VSC = 0V, FO circuit pull-up to 5V with 10kΩ
VSC = 1V, IFO = 1mA
Tj = 25°C, VD = 15V (Note 4)
VIN = 5V
Trip level
Reset level
Trip level
Reset level
CFO = 22nF (Note 5)
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
—
—
—
—
4.9
—
0.43
0.7
10.0
10.5
10.3
10.8
1.6
2.0
0.8
—
—
—
—
—
—
0.48
1.5
—
—
—
—
2.4
3.0
1.4
3.70
1.30
3.50
1.30
—
1.10
0.53
2.0
12.0
12.5
12.5
13.0
—
4.2
2.0
Min. Typ. Max.
mA
mA
mA
mA
V
V
V
mA
V
V
V
V
ms
V
V
VD = VDB = 15V
VIN = 0V
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Tj ≤ 125°C
Note 3: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100µm~+200µm on the con-
tacting surface of DIP-IPM and heat-sink.
Input current
Contact thermal resistance (Note 3)
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Note 6: Measurement point of heat-sink flatness
–
+
–
+
Measurement location
Heat-sink side
Heat-sink side
3.25mm
Mounting screw : M4
Condition
Parameter Limits
Mounting torque
Weight
Heat-sink flatness
Min.
MECHANICAL CHARACTERISTICS AND RATINGS
Typ. Max.
0.98
—
–50
Unit
—
77
—
1.47
—
100
N·m
g
µm
Recommended 1.18 N·m
(Note 6)
V
V
V
V/µs
µs
kHz
Arms
Applied between P-NU, NV, NW
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, TC ≤ 100°C
TC ≤ 100°C, Tj ≤ 125°C
VCC = 600V, VD = 15V, fC = 15kHz
P.F = 0.8, sinusoidal PWM
Tj ≤ 125°C, TC ≤ 100°C (Note 7)
(Note 8)
800
16.5
16.5
1
—
15
1.8
—
VCC
VD
VDB
∆VD, ∆VDB
tdead
fPWM
IO
PWIN(on)
PWIN(off)
Condition
Symbol Parameter Limits
Min. Typ. Max.
350
13.5
13.5
–1
3.3
—
—
1.5
Unit
RECOMMENDED OPERATION CONDITIONS
600
15.0
15.0
—
—
—
—
—
Note 7: The output r.m.s. current value depends on the actual application conditions.
8:DIP-IPM might not make response to the input on signal with pulse width less than PWIN (on).
9:DIP-IPM might not make response or work properly if the input off signal pulse width is less than PWIN (off).
Minimum input pulse width
VNC
Supply voltage
Control supply voltage
Control supply voltage
Control supply variation
Arm shoot-through blocking time
PWM input frequency
Output r.m.s. current
VNC variation V
5.0
–5.0 —
Between VNC-NU, NV, NW (including surge)
350 ≤ VCC ≤ 800V,
13.5 ≤ VD ≤ 16.5V,
13.5 ≤ VDB ≤ 16.5V,
–20°C ≤ TC ≤ 100°C,
N line wiring inductance less than
10nH (Note 9)
Ic ≤ 5A
5 < Ic ≤ 8.5A
µs
2.6
2.8
—
—
—
—
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
DIP-IPM
UOUT
UVNO
VVNO
VOUT
WOUT
WVNO
CFO
GND
Fo
WN
VN
UN
VCC
HVIC3
HVIC2
HVIC1
LVIC
CFO CIN
CIN
W
V
U
P
HO
IN
COM
VB
VS
VCC
HO
IN
COM
VB
VS
VCC
HO
IN
COM
VB
VS
VCC
Fo
WN
VN
UN
WP
VP
UP
VNC
VN1
VP1
VP1
VP1
VWFS
VVFS
VUFS
VWFB
VVFB
VUFB
NU
NV
NW
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
VPC
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Error output Fo
Output current Ic
Control supply voltage VD
Protection circuit state
Control input
b1
b2
b3
b4
b5
RESET
RESET
UVDt
UVDr
SET
b6
b7
Protection circuit state
Lower-arms control
input
Error output Fo
Sense voltage of the
shunt resistor
Output current Ic
Internal IGBT gate
SC reference voltage
CR circuit time
constant DELAY
a5
a8
a4
a3
a1
a2
SC
RESET
SET
a7a6
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS
[A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO output with a fixed pulse width determined by the external capacitor CFO.
a6. Input = “L” : IGBT OFF
a7. Input = “H” :
a8. IGBT OFF state in spite of input “H”.
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO keeps output during the UV period, however, FO pulse is not less than the fixed width for very short UV interval.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
MCU
10kΩ
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
V
NC
(Logic)
Fo
DIP-IPM
5V line
Error output Fo
Output current Ic
Control supply voltage V
DB
Protection circuit state
Control input
c6
c1
c2 c4
c5
c3
RESET
UV
DBt
UV
DBr
SET
RESET
High-level (no fault output)
[C] Under-Voltage Protection (Upper-side, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input signal level, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.
Fig. 6 MCU I/O INTERFACE CIRCUIT
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, pay attention to the turn-on threshold voltage requirement.
Fig. 7 WIRING CONNECTION WITH 1 SHUNT RESISTOR
Using low inductance chip resistor and reducing
wiring length to minimize the wiring inductance.
VNC NW
NV
NU
DIP-IPM
Shunt resistor
For 3 shunt resistors connection, please refer to Fig.9.
Please insert fast
recovery type diode
between V
NC
and
NU, NV, NW terminals.
Please make the wiring connection
of shunt resistor to GND as short as
possible.
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22052
TRANSFER-MOLD TYPE
INSULATED TYPE
May 2005
Fig. 8 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUT WITH 1 SHUNT RESISTOR
Note 1: To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
2: By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible.
3: Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kΩ resistor.
4: Fo output pulse width (tFO) should be determined by connecting external capacitor C4 between CFO and VNC terminals. (Example :
tFO=2.4ms(typ.) at CFO=22nF)
5: Input signal is High-Active type. There is a 2.5kΩ (Min.) resistor inside IC to pull down each input signal line to GND.
When employing RC coupling circuits at each input, set up RC couple such that input signal agree with turn-off/turn-on threshold voltage.
6: To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7: The time constant R5C1 of the protection circuit should be selected in the range of 1.5~2µs. SC interrupting time might vary with the
wiring pattern.
8: All capacitors should be mounted as close to the terminals of the DIP-IPM as possible.
9: To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible.
Generally a 0.1~0.22µF snubber between the P&N1 terminals is recommended.
10: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
11: To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW
terminals.
HO
HO
DIP-IPM
C3
C3
C3
C2
C2
C2
C1
C1
C1
HO
IN
IN
15V line
5V line
IN
COM
COM
COM
UOUT
VOUT
WOUT
WVNO
VVNO
UVNO
CFO
GND
Fo
WN
VN
VCC
C
B
A
C4(CFO)
CFO
R1
N1
C5
CIN
CIN
W
V
U
P
VS
VS
VS
VB
VB
VB
VCC
VCC
VCC
Fo
WN
VN
UN
UN
WP
VP
UP
VNC
VN1
VP1
VPC
VP1
VP1
VWFS
VVFS
VUFS
VWFB
VVFB
VUFB
M
C3
MCU
HVIC1
HVIC2
HVIC3
LVIC
NW
NV
NU
If this wiring is too
long, short circuit
might be caused.
Shunt
resistor
If this wiring is too long, the SC level fluctuation
might be larger and cause SC malfunction.
The long wiring of GND might generate noise
on input and cause IGBT to be malfunction.
C1:Tight tolerance temp-compensated electrolytic type
C2,C3: 0.1~0.22µF R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)
Shunt
resistor Comparator
OR logic
circuit
+
–
Vref
R
P
U
Drive circuit
Drive circuit
Protection circuit
V
W
CIN
DIP-IPM
External protection circuit
C
+
–
Vref
R
C
+
–
Vref
R
C
H-side IGBT
S
L-side IGBT
S
V
NC
• The time constant RC of external comparator should be selected in the range
of 1.5~2µs. SC interrupting time might vary with the wiring pattern.
• The threshold voltage Vref should be set up the same rating of short circuit
trip level (V
SC
(ref) typ. 0.48V).
• Please select the external shunt resistance such that the SC trip-level is less
than 1.7 times of the current rating.
• To avoid malfunction, the wiring of each input should be as short as possible.
• OR circuit output level should be set up the rating of short circuit trip level
(V
SC
(ref) typ. 0.48V).
• For extra precaution, please refer to Fig.8
NW
NV
NU
Fig. 9 EXAMPLE OF EXTERNAL PROTECTION CIRCUIT WITH 3 SHUNT RESISTORS
