74F193
Up/down binary counter with separate
up/down clocks
Product specification
IC15 Data Handbook
1995 Jul 17
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
2
1995 Jul 17 853-0353 15459
FEATURES
•Synchronous reversible 4-bit counting
•Asynchronous parallel load capability
•Asynchronous reset (clear)
•Cascadable without external logic
DESCRIPTION
The 74F193 is a 4-bit synchronous up/down counter in the binary
mode. Separate up/down clocks, CPU and CPD respectively,
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CPU clock is
pulsed while CPD is held High, the device will count up. If CPD clock
is pulsed while CPU is held High, the device will count down. The
device can be cleared at any time by the asynchronous reset pin. It
may also be loaded in parallel by activating the asynchronous
parallel load pin.
Inside the device are four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count
down functions.
Each flip-flop contains JK feedback from slave to master, such that a
Low-to-High transition on the CPD input will decrease the count by
one, while a similar transition on the CPU input will advance the
count by one.
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as
either clock input is Low. Applications requiring reversible operation
must make the reversing decision while the activating clock is High
to avoid erroneous counts.
The Terminal Count Up (TCU) and Terminal Count Down (TCD)
outputs are normally High. When the circuit has reached the
maximum count state of 15, the next High-to-Low transition of CPU
will cause TCU to go Low. TCU will stay Low until CPU goes High
again, duplicating the count up clock, although delayed by two gate
delays. Likewise, the TCD output will go Low when the circuit is in
the zero state and the CPD goes Low. The TC outputs can be used
as the clock input signals to the next higher order circuit in a
multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous since there is a
two-gate delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
during and after a reset or load operation, the next Low-to-High
transition of the clock will be interpreted as a legitimate signal and
will be counted.
TYPE TYPICAL fMAX TYPICAL
SUPPLY CURRENT
(TOTAL)
74F193 125MHz 32mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°CPKG DWG #
16-pin plastic DIP N74F193N SOT38-4
16-pin plastic SO N74F193D SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1D1
Q1
Q0
CPD
CPU
Q2
Q3
D0
TCD
TCU
D2
D3
PL
GND
MR
VCC
SF00745
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F(U.L.)
HIGH/LOW LOAD VALUE
HIGH/LOW
D0 - D3 Data inputs 1.0/1.0 20µA/0.6mA
CPUCount up clock input (active rising edge) 1.0/3.0 20µA/1.8mA
CPDCount down clock input (active rising edge) 1.0/3.0 20µA/1.8mA
PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA
MR Asynchronous master reset input 1.0/1.0 20µA/0.6mA
Q0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA
TCUTerminal count up (carry) output (active Low) 50/33 1.0mA/20mA
TCDTerminal count down (borrow) output (active Low) 50/33 1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 3
LOGIC SYMBOL
VCC = Pin 16
GND = Pin 8
11
15 1 10 9
7623
14
4
5CPU
CPD
Q0
D0 D1
Q1
D2
Q2 Q3
D3
PL 12
13
MR
TCU
TCD
SF00746
STATE DIAGRAM
TCU = Q0 . Q1 . Q2 . Q3 . CPU
TCD = Q0 . Q1 . Q2 . Q3 . CPD
Logic Equations for Terminal Count
COUNT UP
COUNT DOWN
01234
5
6
7
89101112
13
14
15
SF00748
LOGIC SYMBOL (IEEE/IEC)
11
[1]
R
15 3D 3
1–
C3
SF00747
2+
G1
CTR DIV 16
[2]
[4]
[8]
12
1CT=15
2CT=0
1
10
9
2
6
7
13
14
4
5
G2
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 4
LOGIC DIAGRAM
12
13
J
Q
CP
QSD
RD
KJ
Q
CP
QSD
RD
D0 D1 D3
Q1Q0
CPD
PL
15 1
23
14
4
11
VCC = Pin 16
GND = Pin 8
KJ
Q
CP
QSD
RD
Q1
10
6
K
J
Q
CP
QSD
RD
Q1
9
7
MR
CPU5
TCU
TCD
D2
SF00749
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
MR PL CPUCPDD0 D1 D2 D3 Q0 Q1 Q2 Q3 TCUTCDMODE
H X X L X X X X L L L L H L Reset (clear)
H X X H X X X X L LLLHH
L L X L L L L L L L L L H L
L L X H L L L L L LLLHHParallel load
L L L X H H H H H HHHLH
L L H X H H H H H HHHHH
L H ↑H X X X X Count up H1HCount up
L H H ↑X X X X Count down H H2Count down
H = High voltage level
L = Low voltage level
X = Don’t care
↑= Low-to-High clock transition
NOTES:
TCU=CPU at terminal count up (HHHH)
TCD=CPD at terminal count down (LLLL)
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 5
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5.0 mA
VOUT Voltage applied to output in High output state –0.5 to +VCC V
IOUT Current applied to output in Low output state 40 mA
Tamb Operating free-air temperature range 0 to +70 °C
Tstg Storage temperature –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIK Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
Tamb Operating free-air temperature range 0 +70 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
NO TAG
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
NO
TAG
MIN TYP
NO TAG MAX UNIT
VO
High level out
p
ut voltage
V
CC
= MIN
,
V
IL
= MAX
,
10%VCC 2.5 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
VCC
=
MIN,
VIL
=
MAX,
IOH = MAX, VIH = MIN 5%VCC 2.7 3.4 V
VO
Low level out
p
ut voltage
V
CC
= MIN
,
V
IL
= MAX
,
10%VCC 0.35 0.50 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VCC
=
MIN,
VIL
=
MAX,
IOL = MAX, VIH = MIN 5%VCC 0.35 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V
IIInput current at maximum
input voltage VCC = MAX, VI = 7.0V 100 µA
IIH High-level input current VCC = MAX, VI = 2.7V 20 µA
IIL Low-level input CPU, CPD
VCC = MAX V =05V
–1.8 mA
Low level
in ut
current Others
V
CC =
MAX
,
V
I =
0
.
5V
–0.6 mA
IOS Short-circuit output currentNO TAG VCC = MAX –60 –150 mA
ICC Supply current (total)4VCC = MAX 32 50 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with parallel load and Master reset inputs grounded, all other inputs at 4.5V and all outputs open.
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 6
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX
fMAX Maximum clock frequency W aveform 1 100 125 90 MHz
tPLH
tPHL Propagation delay
CPU or CPD to TCU or TCDWaveform 2 2.5
3.0 5.5
5.0 8.5
8.0 2.5
3.0 9.0
9.0 ns
ns
tPLH
tPHL Propagation delay
CPU or CPD to Qn W aveform 1 2.5
5.0 5.5
8.5 8.5
12.0 2.5
5.0 9.0
13.0 ns
ns
tPLH
tPHL Propagation delay
Dn to Qn W aveform 4 2.0
6.0 4.0
9.5 7.0
13.5 1.5
6.0 8.0
15.0 ns
ns
tPLH
tPHL Propagation delay
PL to Qn Waveform 3 4.5
5.5 6.5
8.5 10.0
12.0 4.0
5.0 11.0
13.0 ns
ns
tPHL Propagation delay
MR to Qn W aveform 5 5.0 7.5 11.0 5.0 12.0 ns
tPLH Propagation delay
MR to TCUW aveform 5 6.0 8.5 12.0 5.5 13.0 ns
tPHL Propagation delay
MR to TCDW aveform 5 5.0 7.5 11.0 5.0 12.0 ns
tPLH
tPHL Propagation delay
PL to TCU or TCDW aveform 3 6.0
6.0 9.5
9.0 13.5
12.0 6.0
6.0 15.0
13.0 ns
ns
tPLH
tPHL Propagation delay
Dn to TCU or TCDW aveform 4 5.5
4.5 9.0
8.5 13.0
12.5 5.0
4.5 14.0
13.5 ns
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb= 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX
ts(H)
ts(L) Setup time, High or Low
Dn to PL W aveform 6 4.5
4.5 5.0
5.0 ns
ns
th(H)
th(L) Hold time, High or Low
Dn to PL W aveform 6 2.0
2.0 2.0
2.0 ns
ns
tw(L) PL Pulse width
Low W aveform 3 6.0 6.0 ns
tw(H)
tw(L) CPU or CPD Pulse width
High or Low Waveform 1 3.5
5.0 3.5
5.0 ns
ns
tw(L) CPU or CPD Pulse width
Low (Change of direction) Waveform 1 10.0 10.0 ns
tw(H) MR Pulse width
High W aveform 5 6.0 6.0 ns
trec Recovery time,
PL to CPU or CPDW aveform 3 6.0 6.0 ns
trec Recovery time
MR to CPUor CPDW aveform 5 4.0 4.0 ns
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 7
AC WAVEFORMS
For all waveforms Vm = 1.5V
VM
tPLH
tPHL
VMVM
VM
CPU, CPD
Qn
1/fMAX
tW(L)
SF00750
tW(H)
W aveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width and Maximum Clock Frequency
trec
VM
VMVM
PL
tW(L)
VM
VMVM
tPLH tPHL
CPU, CPDVM
TCU, TCD, Qn
SF00751
W aveform 3. Parallel Pulse Width,
Parallel Load to Output Delays, and Parallel Load
to Clock Recovery Time
VMVM
VM
VM
tPLH
MR
tW(H) trec
VM
tPHL
CPU, CPD
Qn, TCD
TCU
SF00752
W aveform 5. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
VMVM
VMVM
tPLH
tPHL
CPU, CPD
TCU, TCD
SF00753
W aveform 2. Propagation Delay, Clock to Terminal Count
VM
VM
VM
tPHL
tPLH
VM
tPHL tPLH
VM
VM
Dn
Qn, TCU, TCD
Qn, TCU, TCD
SF00754
W aveform 4. Propagation Delay, Data to Flip-Flop Outputs,
Terminal Count Up and Down Outputs
VM
VM
Dn
PL
tS(H) th(H) tS(L) th(L)
VM
SF00755
The shaded areas indicate when the input is permitted
to change for predictable output performance.
W aveform 6. Data Setup and Hold Times
Philips Semiconductors Product specification
74F193Up/down binary counter with separate up/down clocks
1995 Jul 17 8
Timing Diagram (Typical clear, load, and count sequence)
NOTES:
1. Clear overrides load, data, and count inputs.
2. When counting up, count-down input must be High; when counting down, count-up input must be High.
Q0
Q1
Q2
Q3
0 13 14 15 0 1 2 1 0 15 14 13
COUNT UP COUNT DOWN
CLEAR PRESET
CLEAR1
LOAD
D0
D1
D2
D3
COUNT UP2
COUNT DOWN2
SEQUENCE
DATA
OUTPUTS
MR
PL
CPU
CPD
TCU
TCD
SF00756
Binary Counter
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
SF00006
Philips Semiconductors Product specification
74F193
Up/down binary counter with separate up/down clocks
1995 Juk 17 9
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Philips Semiconductors Product specification
74F193
Up/down binary counter with separate up/down clocks
1995 Juk 17 10
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product specification
74F193
Up/down binary counter with separate up/down clocks
1995 Juk 17 11
NOTES
Philips Semiconductors Product specification
74F193
Up/down binary counter with separate up/down clocks
yyyy mmm dd 12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05094
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
