FUJITSU SEMICONDUCTOR DS05-10180-2E DATA SHEET cs KO ==l""_f6 m@ DESCRIPTION The Fujitsu MB814265 is a fully decoded CMOS Dynamic RAM (DRAM) accessible in 16-bit increments. The MB814265 features the hyper p extended valid time for data output and higher speed random acce; same row than the fast page mode. The MB814265-60/-70 DRAW such as embedded control, buffer, portable computers, and. 4,194,304 memory cells peration which provides 312 x16-bits of data within the uited for memory applications quipment where very low power The MB814265 is fabricated using silicon gate CMOS ar process, coupled with three-dimensional stacked cap: and extends the time interval between memory r clvanced four-layer polysilicon process. This ry cells, reduces the possibility of soft errors m@ PRODUCT LINE & FEATURES Parameter MB814265-60 MB814265-70 RAS Access Time 60 ns max. 70 ns max. CAS Access Time 20 ns max. 20 ns max. Address Access Time 30 ns max. 35 ns max. Random Cycle Time 104 ns max. 119 ns min. Hyper Page Mode Cycle , 25 ns min. 30 ns min. oS Operating current 523 mW max. 462 mW max. Low Power Dissipation Standby current 11 mW max. (TTL level)/5.5 mW max. (CMOS level) * 262,144 words x 16 bit organization * Early Write or OE controlled Write capability Silicon gate, CMOS, Advanced Stacked RAS-only, CAS-before-RAS, or Hidden Refresh Capacitor Cell * Hyper page mode, Read-Modify-Write capability + All input and output are TTL compatible On chip substrate bias generator for high + 512 refresh cycles every 8.2 ms performance * 9 rows x 9 columns, addressing scheme This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.MB814265-60/MB814265-70 SAA m@ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit Voltage at any pin relative to Vss Vin, Vout 0.5 to +7.0 Vv Voltage of Vcc supply relative to Vss Vec 0.5 to +7.0 Vv Power Dissipation Pp 1.0 WwW Short Circuit Output Current lout 50 to +50 mA Storage Temperature Tste 55 to +125 C Temperature under Bias Taias 0 to 70 C WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability m@ PACKAGE Marking side Plastic SOJ Package Plastic TSOP Package (LCC-40P-M01) (FPT-44P-M07) (Normal Bend) Package and Ordering Information 40-pin plastic (400 mil) SOJ, order as MB814265-xxPJ 44-pin plastic (400 mil) TSOP-II with normal bend leads, order as MB814265-xxPFTNMB814265-60/MB814265-70 BW SAA Ao Ai Ae As Aa As As Az As Fig. 1 MB814265 DYNAMIC RAM - BLOCK DIAGRAM => DQ: to DQie m@ CAPACITANCE (Ta = 25C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance, Ao toAs Cint 5 pF Input Capacitance, RAS, LCAS, UCAS, WE, OE Cine 7 pF Input/Output Capacitance, DQ: to DQis Coa 7 pFMB814265-60/MB814265-70 SAA m@ PIN ASSIGNMENTS AND DESCRIPTIONS 40-Pin SOU: (TOP VIEW) Vec DQ: DQz2 DQs DQs Vec DQs DQs DQ; DQs N.C. N.C. WE RAS N.C. Ao Ai Ae As Vec Designator Function Ao to As Address inputs row : Ao to As column :Aoto As refresh :Aoto As RAS Row address strobe LCAS Lower column address strobe UCAS Upper column address strobe WE Write enable OE Output enable DQ: to DQis Data Input/Output Voc +5.0 volt power supply Vss Circuit ground N.C. No connection 44-Pin TSOP: (TOP VIEW) <Normal Bend>WwW MB814265-60/MB814265-70 Dn m@ RECOMMENDED OPERATING CONDITIONS Parameter Notes | Symbol | Min. | Typ. | Max. | Unit Operating Temp. Vec 45 5.0 55 Supply Voltage 1 Vv pply Voltag Ve 5 5 > Input High Voltage, all inputs Vin 2.4 6.5 V 0C to +70C Input Low Voltage, all inputs* Viv 0.3 0.8 V * -Undershoots of up to 2.0 volts with a pulse width not exceeding 20 ns are acceptable. m@ FUNCTIONAL OPERATION ADDRESS INPUTS Eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. Since only nine address bits (Ao to As) are available, the column and row inputs are separately strobed by LCAS or UCAS and RAS as shown in Figure 1. First, nine row address bits are input on pins Ao-through-As and latched with the row address strobe (RAS) then, nine column address bits are input and latched with the column address strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS and LCAS or UCAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tran (min) + tr is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUT Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or LCAS / UCAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data of DQ:-DQs is strobed by LCAS and DQs-DQi is strobed by UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low before LCAS/ UCAS. In a delayed write or a read-modify-write cycle, WE goes Low after LCAS /UCAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. DATA OUTPUT The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the following conditions: trac : from the falling edge of RAS when trco (max) is satisfied. tcac : from the falling edge of LCAS (for DQ:-DQs) UCAS (for DQe-DQis) when taco is greater than trep (max). taa : from column address input when trao is greater than trav (max), and taco (max) is satisfied. toca : from the falling edge of OE when OE is brought Low after trac, tcac, or taa. toez : from OE inactive. torr : from CAS inactive while RAS inactive. torr : from RAS inactive while CAS inactive. twez : from WE active while CAS inactive. The data remains valid after either OE is inactive, or both RAS and LCAS (and/or UCAS) are inactive, or CAS is reactived. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle.BW MB814265-60/MB814265-70 Dn HYPER PAGE MODE OPERATION The hyper page mode operation provides faster memory access and lower power dissipation. The hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each page of memory (within column address locations), any of 512 x 16-bits can be accessed and, when multiple MB814265s are used, CAS is decoded to select the desired memory page. Hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. Hyper page mode features that output remains valid when CAS is inactive until CAS is reactivated.BW MB814265-60/MB814265-70 Dn m@ DC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Notes 3 Value Parameter Notes | Symbol Conditions Unit Min. | Max. Output high voltage Vou |lox =5.0 mA 2.4 Vv Output low voltage Vo. lo. =+4.2mA | 04 OV<Vn<5.5V; . 45V<Vcc <5.5V; Input leakage current (any input) lw Vss = 0 V: All other pins -10 10 not under test = 0 V HA OV <Vour<5.5V; Output leakage current Iba) Data out disabled -10 10 Operating current MB814265-60 | 95 (Average power ' _| RAS, [CAS & UCAS cycling; _ mA supply current) MB814265-70 tre = min 84 Standby current TTL level RAS = LCAS = UCAS = Vi 2.0 (Power supply erer _ mA current) CMOS level RAS = LCAS = UCAS 2 Vec -0.2 V 1.0 Refresh current #1 MB814265-60 a __ 95 supply current) MB814265-70 tre = min 84 Hyper page mode MB81426560 |, |RAS=Vu.CCAS/UCAS cycling; | _ | % | current MB814265-70 thro = min 84 Refresh current #2 MB814265-60 RAS cycling: 95 (Average power Iccs | CAS-before-RAS; mA supply current) MB814265-70 tac = min 84MB814265-60/MB814265-70 Dn m@ AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 3, 4,5 No Parameter Notes | Symbol MB814265-60 MB814265-70 Unit y Min. | Max. | Min. | Max. 1 | Time Between Refresh tREF 8.2 8.2 ms 2 |Random Read/Write Cycle Time tro 104 119 ns 3 | Read-Modify-Write Cycle Time trwe 138 158 ns 4 | Access Time from RAS trac 60 70 ns 5 | Access Time from CAS teac 20 20 ns 6 |Column Address Access Time tan 30 35 ns 7 | Output Hold Time to 5 _ 5 _ ns 8 | Output Hold Time from CAS touc 5 5 ns 9 | Output Buffer Turn On Delay Time ton 0 0 ns 10 | Output Buffer Turn Off Delay Time torr 15 15 ns 11 | Output Buffer Turn Off Delay Time from RAS torr 15 15 ns 12 | Output Buffer Turn Off Delay Time from WE twez 15 15 ns 13 | Transition Time tr 1 50 1 50 ns 14 / RAS Precharge Time tre 40 45 ns 15 | RAS Pulse Width tras 60 100000 70 100000 | ns 16 | RAS Hold Time trsH 20 20 ns 17 | CAS to RAS Precharge Time tore 0 0 ns 18 |RAS to CAS Delay Time taco 14 40 14 50 ns 19 |CAS Pulse Width tcas 10 10 ns 20 | CAS Hold Time tesH 40 _ 50 _ ns 21 | CAS Precharge Time (Normal) topn 10 10 ns 22 | Row Address Set Up Time tasr 0 0 ns 23 | Row Address Hold Time tRaH 10 10 ns 24 | Column Address Set Up Time tasc 0 _ 0 _ ns 25 | Column Address Hold Time toa 10 _ 10 _ ns 26 | RAS to Column Address Delay Time trao 12 30 12 35 ns 27 |Column Address to RAS Lead Time tRAL 30 35 ns 28 | Column Address to CAS Lead Time toa 23 _ 28 _ ns 29 | Read Command Set Up Time tres 0 0 ns Read Command Hold Time 30 | Referenced to RAS {RR 0 0 ns Read Command Hold Time 31 | Referenced to CAS tron 0 0 ns BWMB814265-60/MB814265-70 BW SAA m@ AC CHARACTERISTICS (Continued) (At recommended operating conditions unless otherwise noted.) Notes 3, 4,5 No Parameter Notes | Symbol MB814265-60 MB814265-70 Unit y Min. | Max. | Min. | Max. 32 | Write Command Set Up Time twes 0 0 ns 33 | Write Command Hold Time twou 10 10 ns 34 | WE Pulse Width twe 10 10 ns 35 | Write Command to RAS Lead Time tRwL 15 20 ns 36 | Write Command to CAS Lead Time tow. 10 10 ns 37 | DIN Set Up Time tos 0 _ 0 _ ns 38 | DIN Hold Time tou 10 10 ns 39 | RAS to WE Delay Time trwo 77 87 ns 40 | CAS to WE Delay Time tcwo 37 37 ns 41 |Column Address to WE Delay Time tawo 47 52 ns RAS Precharge Time to CAS Active Time __ __ 42 (Refresh Cycles) trec 10 10 ns 43 | CAS Set Up Time for CAS-before-RAS Refresh| _ tcsr 0 0 ns 44 | CAS Hold Time for CAS-before-RAS Refresh tcHR 10 _ 10 _ ns 45 | Access Time from OE [9 | toEa 20 20 ns 46 ae but Buffer Turn Off Delay from toez __ 15 __ 15 ns 47 | OE to RAS Lead Time for Valid Data toeL 10 10 ns 48 | OE to CAS Lead Time tco. 5 5 ns 49 | OE Hold Time Referenced to WE toeH 0 0 ns 50 | OE to Data in Delay Time toep 15 15 ns 51 |DIN to CAS Delay Time tozc 0 0 ns 52 | DIN to OE Delay Time tozo 0 0 ns 53 | CAS to Data in Delay Time tcop 15 15 ns 54 | RAS to Data in Delay Time trop 15 _ 15 _ ns 55 | Column Address Hold Time from RAS tar 26 26 ns 56 | Write Command Hold Time from RAS twer 24 _ 24 ns 57 | DIN Hold Time Referenced to RAS toHR 24 _ 24 _ ns 58 | OE Precharge Time toeP 10 10 ns 59 |OE Hold Time Referenced to CAS toecH 10 10 ns 60 | WE Precharge Time twez 10 10 ns 61 | WE to Data in Delay Time twed 15 15 ns 62 | Hyper Page Mode RAS Pulse Width trasP 60 200000 70 200000 | ns10 MB814265-60/MB814265-70 Dn m@ AC CHARACTERISTICS (Continued) (At recommended operating conditions unless otherwise noted.) Notes 3, 4,5 No Parameter Notes | Symbol MB814265-60 MB814265-70 Unit y Min. | Max. | Min. | Max. 63 | Hyper Page Mode Read/Write Cycle Time tHec 25 _ 30 _ ns 64 Hyper Page Mode Read-Modify-Write Cycle tuprwe 66 _ 7 _ ns Time 65 | Access Time from CAS Precharge 9,18 tora _ 35 _ 40 ns 66 |Hyper Page Mode CAS Pulse Width tcp 10 10 ns Hyper Page Mode RAS Hold Time from CAS __ __ 67 Precharge truce 35 40 ns 68 Hyper Page Mode CAS Precharge to WE Delay topwo 52 _ 57 _ ime Notes: 1. Referenced to Vss. To all Vcc (Vss) pins, the same supply voltage should be applied. 2. a4 sk 12. 13. 14. 15. 7 OO ON Icc depends on the output load conditions and cycle rates; The specified values are obtained with the output open. Icc depends on the number of address change as RAS = Vi. and UCAS = Vin, LCAS = Vin, Vi > 0.3 V. Icc1, Iccs and Iccs are specified at one time of address change during RAS = Vi. and UCAS = Vin, LCAS = Vu. Icca iS Specified at one time of address change during one Page cycle. An initial pause (RAS = CAS = Vin) of 200 us is required after power-up followed by any eight RAS- only cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. AC characteristics assume tr = 5 ns. Vin (min) and Vit (max) are reference levels for measuring timing of input signals. Also transition times are measured between Vi (min) and Vit (max). Assumes that trcp < trcp (max), trap < trap (max). If tacp is greater than the maximum recommended value shown in this table, trac will be increased by the amount that trcp exceeds the value shown. Refer to Fig. 2 and 3. If tacp > trop (Max), trav = trap (Max), and tasc > taa tcac tr, access time is tcac. If trav > trap (Max) and tasc < taa tcac tr, access time is taa. Measured with a load equivalent to two TTL loads and 100 pF. torr and toez are specified that output buffer change to high impedance state. Operation within the taco (max) limit ensures that trac (max) can be met. trcp (max) is specified as a reference point only; if taco is greater than the specified tacp (max) limit, access time is controlled exclusively by tcac or taa. trcp (min) = tRaH (Min) + 2tr + tase (min). Operation within the trav (max) limit ensures that trac (max) can be met. trac (max) is specified as a reference point only; if trav is greater than the specified trap (max) limit, access time is controlled exclusively by tcac or taa. Either tary or tracy must be satisfied for a read cycle. twcs IS specified as a reference point only. If twcs > twcs (min) the data output pin will remain High-Z state through entire cycle. 16. Assumes that twes < twes (min). 17. Either tozc or tozo must be satisfied. 18. tcra is access time from the selection of a new column address (that is caused by changing both UCAS and LCAS from L to H). Therefore, if tc is long, tcra is longer than tcra (max). 19. Assumes that CAS-before-RAS refresh. 20. The last CAS rising edge. 21. The first CAS falling edge.BW MB814265-60/MB814265-70 Dn Fig. 2 trac VS. trcp Fig. 3 trac vS. trap Fig. 4 tcra vs. tcp trac (ns) trac (ns) tcra (Ns) A A 140 - 100 F- 70 120 [- 100 F- 70ns version 40 70ns version 80 F 70ns version 60ns version 60 F I : I 1 6Ons version , I 30 ! I a I ++ ' ao wt I | | LL | | 0 2 40 +60 80 100 0 10 20 30 40 50 60 0 10 2 30 40 50 trcp (ns) trap (ns) tcr(ns) m@ FUNCTIONAL TRUTH TABLE Clock Input Address Input/Output Data Operation | oe | oe DQ: to D@s | DQsto DQis | Refresh] Note ode RAS |LCAS|UCAS) WE | OE | Row /|Column Input | Output | Input / Output Standby H|H]H]|xX]xX ] |High-Z| |High-z| L | H Valid High-Z tees >t Read Cycle L | H | L | H } L | Valid | Valid | |High-Z| | Valid | Yes* (min) nes L |b Valid Valid L | H Valid Write Cycle | 1 | | cL} L | x | valid | valid | |High-z) valid |High-z} Yes* |tes2 tos (Early Write) L L Valid Valid (min) L | H Valid | Valid | |High-Z eae Meaty: L | H | L |HoL/LoH! valid | valid | |High-z| Valid | Valid | Yes* y L |b Valid | Valid | Valid | Valid RAS-only . . . Refresh Cycle | & | H | H } X | X | Valid | |High-Z| |High-Z| Yes CAS-before- tosa >t RAS Refresh | L L L |x }xf} |High-Z} |High-Z| Yes (min csr Cycle Hidden L H Valid High-2 Previous Refresh H->L} H L H L _ _ |High-7Z} | Valid | Yes |datais Cycle L L Valid Valid kept Note: X ;H or L * : It is impossible in Hyper Page Mode. 1412 MB814265-60/MB814265-70 Dn Vin RAS Vit LCAS Vie or UCAS VN Vin Ao to As Vit __ Vin WE Vit DQ Vou (Output) = yo DQ Viq (Input) Vit __ Vin OE Vit DESCRIPTION Fig.5 - READ CYCLE tras j__tcre tar tcsH tre 4 If trop > trop (max), access time = tcac. If trap > trap (max), access time = taa. If OE is brought Low after trac, tcac, or taa (whichever occurs later), access time = toca. However, if either CCAS/UCAS or OE goes High, the output returns to a high-impedance state after ton is satistied. WA H or "LV? Valid Data To implement a read operation, a valid address is latched by the RAS and LCAS or UCAS address strobes and with WE set to a High level and OE set to a Low level, the output is valid once the memory access time has elapsed. DQs-DQie pins is valid when RAS and CAS are High or until OE goes High. The access time is determined by RAS(trac), LCAS/UCAS (tcac), OE (toca) or column addresses (taa) under the following conditions: BWMB814265-60/MB814265-70 Dn H or "LV Fig.6 EARLY WRITE CYCLE tre tras _ ye _" RAS N Ve om pe tore tcsH tre trop tRSH CCAS tcas Vino \ or UCAS VE = Vin Ao to As Vit _ Vin WE Vit tos toH J DQ Vin (Input) Vit VALID DATA IN DQ VoH (Output) Vor HIGH-Z DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is a H or L signal. A write cycle can be implemented in either of three ways-early write, delayed write, or read-modify-write. During all write cycles, timing param- eters taw., tow, trac and tca. must be satisfied. In the early write cycle shown above twes satisfied, data on the DQ pins are latched with the falling edge of LCAS or UCAS and written into memory. 13 BWMB814265-60/MB814265-70 BW SAA 14 Fig. 7 DELAYED WRITE CYCLE (OE CONTROLLED) tre tras __ Ve 7"N RAS CC ts +| \ tcrp trep tcas trsH or uUcAS VET NY [CAS Vy, Ao to As tres -K towt _ Vin WE Vic DQ Vin VALID (Input) Vi DATA IN DQ Vou (Output) Vo Vin Vi - Invalid Data DESCRIPTION In the delayed write cycle, twcs is not satisfied; thus, the data on the DQ pins are latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (toep + tr + tos).MB814265-60/MB814265-70 BW SAA Ao to As DQ Vin (Input) ViL DQ VoH (Output) Vor Vino Vc = DESCRIPTION Fig. 8 READ-MODIFY-WRITE CYCLE trwe tras p_ trac Z tozo The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read- modify-write cycle, OE must be changed from Low to High after the memory access time. |}___ i K tou VALID toeD tcac tea | | Le tos DATA IN toea | | toEH | VALI HIGH-Z HIGH-Z ton 1516 MB814265-60/MB814265-70 Dn During one cycle is achieved, the input/output timing apply the same manner as the former cycle. ras ON Vic LCAS Via or Vi UCAS - A A Vin o to As Vin WE Vin Vi DQ Vin (Input) Vit DQ Vou (Output) Vor OE Vin Vio DESCRIPTION Fig.9 - HYPER PAGE MODE READ CYCLE trasP trcp | X trap | P HIGH-Z tRHcP tHec he {ROD tRRH H or "LV VL. Valid Data The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tcac, taa, tcra, or toca, whichever one is the latest in occurring. BWBW MB814265-60/MB814265-70 Dn Fig. 10 HYPER PAGE MODE READ CYCLE (OE = H or L) trasp Va tO | trHcp ! RAS Le tar Vi = N I trap _ | | tHPc troy trp tore tcsH w] e tc pa tcp ' ___ | | tcas tcas | | tar LCAS Vin t c or _ I _ A y ucAS Vi 7 tcaH os A A Vin o to As Vi WE Vin = Vi o- DQ Vin (Input) Vi I taa | I tas torF 1 [a tone Le tom oo | I DQ Vou f (Output) yo OE Vn Vi V///4 Nalid Data DESCRIPTION The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tcac, taa, tora, or toe, whichever one is the latest in occurring. 17MB814265-60/MB814265-70 Dn 18 pas ON Vic o- LCAS wy = or UcAS VET A A Vn o to As Vi = WE Vino Vio DQ Vqo (Input) Vit DQ Vou (Output) Vor OE Vin Vi During one cycle is achieved, the input/output timing apply the same manner as the former cycle. DESCRIPTION Fig. 11 HYPER PAGE MODE READ CYCLE (WE = H or L) trasP VL. H or "LV Valid Data The hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. This operation is performed by strobing in the row address and maintaining RAS at a Low level and WE at a High level during all successive memory cycles in which the row address is latched. The access time is determined by tcac, taa, tcra, or toca, whichever one is the latest in occurring. BWBW MB814265-60/MB814265-70 Dn Fig. 12 HYPER PAGE MODE EARLY WRITE CYCLE trasp Vin = Dae tRHcP RAS Vii = LE | trp tcosH Ao to As DQ (Input) DQ Vou (Output) Vor HIGH-Z During one cycle is achieved, the input/output timing apply the same manner as the former cycle. DESCRIPTION The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ: to DQs is latched on the falling edge of [CAS and one appearing on the DQs to DQie is latched on the falling edge of UCAS and the data is written into the memory. During the hyper page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, tcw. must be satisfied. 19BW MB814265-60/MB814265-70 Dn Fig. 13 HYPER PAGE MODE DELAYED WRITE CYCLE KS Veo Vu o tHec tRsH _ LCAS Va tcas or uUcAS Ve tcaH tow. Veo COL Ao to As V0 ADD WE Veo Vu DQ Vin o (Input) Vi DQ Vor (Output) yo. OE Veo Vu H or . Invalid Data DESCRIPTION The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the hyper page mode delayed write cycle, OE must be changed from Low to High before WE goes Low (toep + tr + tos). 20MB814265-60/MB814265-70 Dn Vin Vi LCAS Via Vi Ao to As Vin Vi DQ Vin (Input) Vit DQ Vou (Output) = Vor Vin Vi Fig. 14 HYPER PAGE MODE READ/WRITE MIXED CYCLE DESCRIPTION The hyper page mode performs read/write operations repetitively during one RAS cycle. At this time, tec (min) is invalid. | VALID DATA IN twez HIGH-Z UI or &L Valid Data 21 BW22 MB814265-60/MB814265-70 Dn Vin Vi LCAS) wy, Vi Ao to As Vin Vi DQ Vin (Input) Vit DQ Vor (Output) = Yo. Vin Vi Fig. 15 HYPER PAGE MODE READ-MODIFY-WRITE CYCLE tcrP trasP trcp trp tRwL ~| tHepRwc DESCRIPTION During the hyper page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle. UI or &L V/}) Valid Data BWBW MB814265-60/MB814265-70 Dn RAS ve Ao to Ag vi = LCAS Vi or Vi UCAS DQ Vou (up) Va > === HIGHZ H or DESCRIPTION Refresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every 8.2-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and LCAS and UCAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DQ pins are kept in a high-impedance state. Fig. 17 CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = H or L) V tras trp RAS vy, _ X tcpn } | tesa tcHR trrc tcsr l [CAS <___ tcrn ____ qo or Vi - WL UCAS torr DQ Vou HIGHZ H or L DESCRIPTION CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS is held Low for the specified setup time (tcsr) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. 23MB814265-60/MB814265-70 BW SAA 24 Fig. 18 HIDDEN REFRESH CYCLE tre tras ee Vino yy RAS Vc = \ tre 4 tcrP tcHR | LCAS Va = | or UcAS Vt ; ASR tra o| tasc Jt he tap Lt =| | | Je] toa Veo Vv / " Ao to As ROW COLUMN Vc = ADDRESS 7 ADDRESS tres | Vn = WE Vi tA lS SS ) IS. LL trac Le toze a] be tcac a> DQ Vin (Input) yy, HIGH-Z ton | DQ VoH (Output) yo. a HIGH-Z VALID DATA OUT ia Vin OE Vi DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of LCAS or UCAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability.MB814265-60/MB814265-70 Dn Fig. 19 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE Dre Vn RAS Vii _ tcHR LCAS tcsr Vn = or _ ucas Vt ActoAe Ym WE Vn = WE Vi 7 g DQ Vin (Input) Vi 7 DQ Vou = (Output) Vor 7 = Vn o- OE Vit DESCRIPTION tcp ] tFRSH | | tre trcas ////4 Nalid Data A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the functionality of CAS-before-RAS refresh circuitry. After a CAS-before-RAS refresh cycle, if LCAS or UCAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits Ao through As are defined by the on-chip refresh counter. Column Address: Bits Ao through As are defined by latching levels on Ao-As at the second falling edge of LCAS or UCAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Normalize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write O to all 512 row addresses at the same column address by using CBR refresh counter test cycles. 4) Read 0 written in procedure 3) by using normal read cycle and check; After reading 0 and check are completed (or simultaneously), write 1 to the same addresses by using normal write cycle (or read-modify-write cycle). 5) Read and check data 1 written in procedure 4) by using CBR refresh counter test cycle for all 512 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. Parameter Symbol MB814265-60 MB814265-70 Unit Min. Max. Min. Max. 90 Access Time from CAS trac 55 _ 55 us 91 Column Adress Hold Time trcaH 30 30 _ ns 92 CAS to WE Delay Time tecwo 80 _ 80 _ ns 93 CAS Pulse Width trcas 55 _ 55 _ us 94 RAS Hold Time trasu 55 _ 55 _ ns 95 CAS Hold Time trosH 85 _ 85 _ ns Note: Assumes that CAS-before-RAS refresh counter test cycle only. 25MB814265-60/MB814265-70 BW SAA 26 m@ PACKAGE DIMENSIONS (Suffix : PJ) 40 pin, Plastic SOJ (LCC-40P-MO01) * 26.03+0.13(1.025+0.05) @W. Nomen 1 10.16(.400) 11.18+0.13 INDEX NOM (.440+.005) OUOUOUOOOOOOOOOOOOOOOO a LEAD No Oo! 1.2740.13 (.050+.005) 24.13(.950)REE 2.60(.102)NOM T \ {]] 0.10(.004) 1995 FUJITSU LIMITED C400518-3C-1 3.50 020 (.138 eos) 2.31(.091)NOM 0.64{.025)MIN R0.89(.035)TYP = 9.40+0.51 (.370+.020) Dimensions in mm(inches).m@ PACKAGE DIMENSIONS (Continued) (Suffix :-PFTN) MB814265-60/MB814265-70 Dn 44 pin, Plastic TSOP(II) (FP T-44P-M07) @) @ @) PARBHHHAA ARAAeeead O) O) INDEX HAM HHOBHOBAOE POGU ORO Hao | 0.15(.006)MAX 0.40(.016)MAX | | | | 0.15(.006 | | 4 | __} | | 0.25(.010 | | | | | | 1904 FUJITSU LIMITED F44016S-1C-2 11.76+0.20 (463+.008) 10.16+0.10 (400+.004) 0.15+0.05 (.006+.002) | 10.76+0.20 LEAD No.7) (8) *18.41+0.10 (.725+.004) 0.30+0.10 40.10 (01 2+.004) $B 10.13(.005) @ le (043 t02) mi i zl 0.10(.004) 0.50+0.10 0.80(.0315)TYP O(0)MIN (.020+.004) ' (STAND OFF) 16.80(.661)REF (.424+.008) Dimensions in mm(inches). 27 BW