PDM31532 PDM31532 64K x 16 CMOS 3.3V Static RAM Features n n n n n n n n n 1 Description High-speed access times - Com'l: 9, 10, 12, 15 and 20 ns - Ind: 12, 15 and 20 ns Low power operation (typical) - PDM31532LA Active: 200 mW Standby: 10 mW - PDM31532SA Active: 250 mW Standby: 20 mW High-density 64K x 16 architecture 3.3V (0.3V) power supply Fully static operation TTL-compatible inputs and outputs Output buffer controls: OE Data byte controls: LB, UB Packages: Plastic SOJ (400 mil) - SO Plastic TSOP - T (II) The PDM31532 is a high-performance CMOS static RAM organized as 65,536 x 16 bits. The PDM31532 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The PDM31532 operates from a single 3.3V power supply and all inputs and outputs are fully TTLcompatible. The PDM31532 is available in a 44-pin 400 mil plastic SOJ and a plastic TSOP (II) package for highdensity surface assembly and is suitable for use in high-speed applications requiring high-speed storage. 2 3 4 5 6 7 A8-A0 Row Decoder Row Address Buffer Functional Block Diagram Data Input/ Output Buffer I/O15-I/O0 Memory Cell Array 25632K x 128 x 32 x 32 8 Vcc Vss 9 10 Sense Amp Column Decoder WE OE UB LB CE 11 Control Logic Clock Generator Column Address Buffer 12 A15-A9 Rev. 4.3 - 3/27/98 1 PDM31532 Pin Configuration SOJ TSOP (II) A4 1 44 A5 A4 1 44 A5 A3 2 43 A6 A3 2 43 A6 A2 3 42 A7 A2 3 42 A7 A1 4 41 OE A1 4 41 OE A0 5 40 UB A0 5 40 UB CE 6 39 LB CE 6 39 LB I/O0 7 38 I/O15 I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O2 9 36 I/O13 I/O3 10 35 I/O12 I/O3 10 35 I/O12 Vcc 11 34 Vss Vcc 11 34 Vss Vss 12 33 Vcc Vss 12 33 Vcc I/O4 32 I/O11 I/O4 I/O11 31 I/O10 I/O5 13 14 32 I/O5 13 14 31 I/O10 I/O6 15 30 I/O9 I/O6 15 30 I/O9 I/O7 16 29 I/O8 I/O7 16 29 I/O8 WE 28 NC WE 17 28 NC A15 17 18 27 A8 A15 18 19 26 A9 27 A8 A14 A14 26 20 21 22 25 A10 19 A9 A13 A13 20 A10 A11 25 24 A12 24 A11 23 NC 21 22 23 NC A12 NC NC Pin Description Name Description A15-A0 Address Inputs I/O15-I/O0 Data Inputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB, UB Data Byte Control Inputs NC No Connect Vss Ground VCC Power (+3.3V) Capacitance (1) (TA = +25C, f = 1.0 MHz) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = VSS 6 pF CI/O Output Capacitance VI/O = VSS 8 pF NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2 Rev. 4.3 - 3/27/98 PDM31532 Operating Mode Mode CE OE WE LB UB I/O7-I/O0 I/O15-I/O8 Power Read L L H L L Output Output ICC H L High Impedance Output ICC L H Output High Impedance ICC L L Input Input ICC H L High Impedance Input ICC L H Input High Impedance ICC Write L Output Disable Standby X L L H H X x High Impedance High Impedance ICC L X X H H High Impedance High Impedance ICC H X X X X High Impedance High Impedance ISB 1 2 3 4 NOTE: H = VIH, L = VIL, X = DON'T CARE 5 Absolute Maximum Ratings (2) Symbol Rating Com'l. Ind. Unit VTERM Terminal Voltage with Respect to VSS -0.5 to +4.6 -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 C TSTG Storage Temperature -55 to +125 -65 to +150 C PT Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA Tj Maximum Junction Temperature (3) 125 145 C 6 7 NOTE: 2. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja values: 8 9 10 SOJ: 59o C/W TSOP: 87o C/W 11 Recommended DC Operating Conditions Symbol Description VCC VSS Industrial Commercial Rev. 4.3 - 3/27/98 Min. Typ. Max. Unit Supply Voltage 3.0 3.3 3.6 V Supply Voltage 0 0 0 V Ambient Temperature -40 25 85 C Ambient Temperature 0 25 70 C 12 3 PDM31532 DC Electrical Characteristics (VCC = 3.3V 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = Vss to VCC Com'l/ Ind. -5 5 A ILO Output Leakage Current VCC= Max., CE = VIH, VOUT = Vss to VCC Com'l/ Ind. -5 5 A VIL Input Low Voltage -0.3(4) 0.8 V VIH Input High Voltage 2.2 Vcc + 0.3 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. -- 0.4 V VOH Output High Voltage IOH = -4 mA, VCC = Min. 2.4 -- V NOTE: 4. VIL(min) = -3.0V for pulse width less than 20 ns. Power Supply Characteristics -9 Symbol Parameter ICC Operating Current CE = VIL ISB ISB1 NOTE: 4 SA -10 -12 Com'l Com'l Com'l 175 165 150 -15 Ind. 160 -20 Com'l Ind. Com'l Ind. 130 140 120 130 Unit mA f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA LA 150 140 130 140 120 130 110 120 mA Standby Current CE = VIH SA 30 30 30 30 30 30 30 30 mA f = fMAX = 1/tRC VCC = Max. LA 15 15 15 15 15 15 15 15 mA Full Standby Current CE VCC - 0.2V SA 5 5 5 5 5 5 5 5 mA f=0 VCC = Max., VIN VCC - 0.2V or 0.2V LA 2 2 2 5 2 5 2 5 mA All values are maximum guaranteed values. Rev. 4.3 - 3/27/98 PDM31532 AC Test Conditions Input pulse levels 1 VSS to 3.0V Input rise and fall times 2.5 NS Input timing reference levels 1.5V Output reference levels 1.5V Output load 2 See Figures 1 and 2 3 4 5 +3.3V +3.3V 6 317 317 DOUT DOUT 351 Figure 1. Output Load 30 pF 351 5 pF 7 8 Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE, tLZBE, tHZBE) 9 10 11 12 Rev. 4.3 - 3/27/98 5 PDM31532 Read Timing Diagram tRC ADDRESSES tAA tOH tACE CE tAOE tHZCE(5) OE tBA tHZOE(5) UB, LB tLZBE(5) tHZBE(5) tLZOE(5) tLZCE(5) DOUT Output Data Valid AC Electrical Characteristics -9 (7) Description READ Cycle -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Min Max Unit READ cycle time tRC 9 -- 10 -- 12 -- 15 -- 20 -- ns Address access time tAA -- 9 -- 10 -- 12 -- 15 -- 20 ns Chip enable access time tACE -- 9 -- 10 -- 12 -- 15 -- 20 ns Byte access time tBA -- 6 -- 6 -- 7 -- 8 -- 9 ns Output hold from address change tOH 3 -- 3 -- 3 -- 3 -- 3 -- ns Byte disable to output in low-Z tLZBE 0 -- 0 -- 0 -- 0 -- 0 -- ns Byte enable to output in high-Z tHZBE -- 7 -- 7 -- 8 -- 9 -- 9 ns tLZCE 3 -- 3 -- 3 -- 3 -- 3 -- ns Chip disable to output high-Z(1, 5) tHZCE -- 6 -- 6 -- 7 -- 8 -- 9 ns Output enable access time Chip enable to output in 6 -10 (7) low-Z(1, 5) tAOE -- 6 -- 6 -- 7 -- 8 -- 9 ns Output enable to output in low-Z(1, 5) tLZOE 0 -- 0 -- 0 -- 0 -- 0 -- ns Output disable to output in high-Z(1, 5) tHZOE -- 6 -- 6 -- 7 -- 8 -- 9 ns Rev. 4.3 - 3/27/98 PDM31532 Write Cycle 1 Timing Diagram(8) (WE Controlled) tWC 1 ADDRESSES tAW tAS tWP tAH 2 WE tCW 3 CE tBW 4 UB, LB tHZWE(5) tLZWE(5) High Impedance (9) DOUT (10) tDS DIN 5 tDH Data Stable 6 7 Write Cycle 2 Timing Diagram(8) (CE Controlled) tWC 8 ADDRESSES tAW tAS tWP tAH 9 WE tCW 10 CE tBW UB, LB tLZBE(5) High Impedance DOUT tDS DIN Rev. 4.3 - 3/27/98 11 tHZWE(5) tLZCE(5) tDH 12 Data Stable 7 PDM31532 Write Cycle 3 Timing Diagram(8) (UB, LB Controlled) tWC ADDRESSES tAW tAS tWP tAH WE tCW CE tBW UB, LB tLZCE(5) tHZWE(5) tLZBE(5) High Impedance DOUT tDS DIN tDH Data Stable AC Electrical Characteristics -9 (7) Description -12 -15 -20 WRITE Cycle Sym WRITE cycle time tWC 9 -- 10 -- 12 -- 15 -- 20 -- ns Chip enable to end of write tCW 8 -- 9 -- 10 -- 11 -- 12 -- ns Address valid to end of write tAW 8 -- 9 -- 10 -- 11 -- 12 -- ns Byte pulse width tBW 8 -- 9 -- 10 -- 12 -- 13 -- ns Address setup time tAS 0 -- 0 -- 0 -- 0 -- 0 -- ns Address hold from end of write tAH 0 -- 0 -- 0 -- 0 -- 0 -- ns Write pulse width tWP 7 -- 7 -- 8 -- 9 -- 10 -- ns Data setup time tDS 6 -- 6 -- 7 -- 8 -- 9 -- ns ns Data hold time 8 -10 (7) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tDH 0 -- 0 -- 0 -- 0 -- 0 -- Byte disable to output in low Z(1, 5, 8) tLZBE 1 -- 1 -- 1 -- 1 -- 1 -- ns Byte enable to output in high Z(1, 5, 8) tHZBE -- 7 -- 7 -- 7 -- 8 -- 9 ns Output disable to output in low Z(1, 5, 8) tLZOE 0 -- 0 -- 0 -- 0 -- 0 -- ns Output enable to output in high Z(1, 5, 8) tHZOE -- 7 -- 7 -- 7 -- 8 -- 9 ns Write disable to output in low Z(1, 5, 8) tLZWE 1 -- 1 -- 1 -- 1 -- 1 -- ns Write enable to output in high Z(1, 5, 8) tHZWE -- 7 -- 7 -- 7 -- 8 -- 9 ns Rev. 4.3 - 3/27/98 PDM31532 Notes for AC Tables Measured with CL = 5 pF as in Figure 2. Transition is measured 200 mV from steady state voltage At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. Vcc = 3.3V +5% If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance state 10.If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance state. NOTES: 5. 6. 7. 8. 9. 1 2 3 4 5 6 Ordering Information XXXXX X Device Type Power XX Speed X X X Package Type Process Temp. Range Preferred Shipping Container 7 Blank Tubes TR Tape & Reel TY Tray 8 Blank Commercial (0 to +70C) I Industrial (-40C to +85C) A Automotive ( -40C to +105C) SO T 44-pin 400-mil Plastic SOJ 44-pin Plastic TSOP (II) 9 10 12 15 20 Commercial Only Commercial Only SA LA Standard Power Low Power 9 10 11 PDM31532 - (64Kx16) Static RAM 12 Faster Memories for a FasterWorld TM Rev. 4.3 - 3/27/98 9