LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 LMR70503 SIMPLE SWITCHER(R) Buck-Boost Converter For Negative Output Voltage in SMD Check for Samples: LMR70503 FEATURES 1 * * * * * * * * * * * Tiny 8-Bump Thin DSBGA Package: 0.84 mm x 1.615 mm x 0.6 mm 2.8 V to 5.5 V Input Voltage Range Adjustable Output Voltage: -0.9 V to -5.5 V 320 mA Switch Current Limit 500 kHz Minimum Switching Frequency Ground Referred Enable Input Under Voltage Lock Out (UVLO) No External Compensation Internal Soft Start 1 A Shutdown Supply Current Small Output Voltage Ripple WEBENCH(R) Enabled 80 70 EFFICIENCY (%) * 23 System Performance 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 30 0 10 20 30 40 50 60 70 80 90 100 LOAD (mA) Figure 1. Efficiency, VOUT= -5.0 V 80 APPLICATIONS * 70 General Purpose Negative Voltage Supply Negative Rail / Bias Supply For Op-amp And Data Converters LCD Biasing EFFICIENCY (%) * * 60 50 PERFORMANCE BENEFITS 40 * * 30 Easy To Use Tiny Overall Solution Size Reduces System Cost 0 30 60 90 120 LOAD (mA) 150 180 Figure 2. Efficiency, VOUT= -2.5 V DESCRIPTION The LMR70503 is a buck-boost converter with adjustable negative output voltage in a tiny 8-bump thin DSBGA package. Its unique control method is designed to provide fast transient response, low output noise, high efficiency, and tight regulation in the smallest possible PCB area. The LMR70503 has built in soft start, peak current limit, minimum switching frequency, and Under Voltage Lock Out (UVLO), with no external compensation required. For ease of use, the Enable pin is referred to the IC ground, instead of the lowest potential of the IC: the negative output voltage. VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V Typical Application Circuit L VIN (2.8V to 5.5V) VIN SW Cin Cout D VOUT LMR70503 1.8V 0V Rb Cff VOUT (-0.9V to -5.5V) EN FB Refer to GND Rt GND VREF 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2013, Texas Instruments Incorporated LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com Connection Diagram 1 2 A VREF FB B EN VOUT C GND GND D SW VIN Figure 3. LMR70503 Bump Locations - Top View 1 2 A B C D Figure 4. LMR70503 Package Marking - Top View (Diamond Denotes Bump A1) PIN DESCRIPTIONS 2 Pin Number Name Description A1 VREF Reference voltage output; connect to the bottom feedback resistor. B1 EN C1, C2 GND Analog ground for internal bias circuitry. D1 SW Switch node pin, connected to the internal high side MOSFET. The cathode of the external Schottky diode must be connected as close as possible to this pin, in order to reduce inductance in the discontinuous current path. A2 FB FB is connected to VOUT and VREF through two feedback resistors. It is compared to GND to regulate the output voltage. B2 VOUT D2 VIN Active high enable input for the device. Enable voltage level is referred to GND. Device must be enabled only with the presence of valid VIN (2.8 V to 5.5 V). The peak of the Enable input voltage must always lower than VIN voltage. Output voltage. The anode of the external Schottky diode and output filter capacitor(s) should be connected to this pin. Power supply input pin, connected to the internal high side MOSFET and powers the internal circuity. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) VIN to GND -0.5 V to 6.0 V VOUT to GND -6.5 V to 0.5 V SW to GND -6.5 V to VIN +0.2 V EN to GND -0.5 V to VIN FB to GND -0.5V to 5.5V ESD Rating (3) 2 kV Junction Temperature 150 C Storage Temperature Range -65 C to 150 C For Soldering Specs see: SNOA549 (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. Test method is per JESD22-A114. OPERATING RATINGS Input Voltage Range (VIN) 2.8 V to 5.5 V Output Voltage Range (VOUT) -0.9 V to -5.5 V Junction Temperature Range (TJ) -40C to 125C ELECTRICAL CHARACTERISTICS Specifications with standard typeface are for TJ = 25C only; limits in bold face type apply over the operating junction temperature (TJ) range of -40 C to +125 C. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, unless otherwise indicated in the conditions column. Min Typ Max (1) Units 1.166 1.19 1.214 V EN = 0 V VIN = 5.5 V 0.01 1 A EN = 1.8 V, VIN = 5.5 V, No Switching 245 300 A 2.55 2.7 V Symbol Parameter Conditions VREF Reference Voltage RREF=100 k to GND ISD Shutdown Current IQ Quiescent Current UVLORISE VIN Under Voltage Lock Out Threshold Rising UVLOHYS VIN Under Voltage Lock Out Hysteresis Band VEN-RISE EN Input Voltage Rising Threshold VIN = 5.5 V VEN-HYS EN Input Voltage Threshold Hysteresis VIN = 5.5 V IEN IFB FSW-MIN Minimum Switching frequency TON-MIN Minimum High Side Switch On Time RDSON Switch On State Resistance (1) (2) (1) 0.1 (2) 0.13 1.05 0.1 V 1.2 V 0.15 V Enable Current 30 nA FB pin current 10 nA 500 kHz Load = 0 A 70 ns VIN = 2.8V 1.1 400 2 Min and Max limits are 100% production tested at an ambient temperature (TA) of 25 C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Typical specifications represent the most likely parametric norm at 25C operation. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 3 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Specifications with standard typeface are for TJ = 25C only; limits in bold face type apply over the operating junction temperature (TJ) range of -40 C to +125 C. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, unless otherwise indicated in the conditions column. Symbol Parameter Conditions (3) Min Typ Max (1) Units 270 320 370 mA (1) (2) IPEAK-CL Switch Peak Current limit TSDTH-HIGH Thermal Shutdown Threshold - Rising Junction Temperature 165 C TSDHYS Thermal Shutdown Hysteresis Band Junction Temperature 10 C (3) 4 The switch peak current limit is internally trimmed. The actual peak current limit observed on the applications are dependant on the input voltage VIN, inductance value L and junction temperature TJ. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, the following conditions apply: VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, CIN = 10 F 6.3 V X5R ceramic capacitor; COUT = 2 x 22 F 6.3 V X5R ceramic capacitor; L = 6.8 H (VLS2012ET-6R8M); TAMBIENT = 25 C. Efficiency, VOUT = -5.0 V Output Regulation, VOUT = -5.0 V 80 5.10 |VOUT| REGULATION (V) 5.08 EFFICIENCY (%) 70 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 5.06 5.04 5.02 5.00 4.99 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 4.96 4.95 4.92 30 4.90 0 10 20 30 40 50 60 70 80 90 100 LOAD (mA) 0 10 20 30 40 50 60 70 80 90 100 LOAD (mA) Figure 5. Figure 6. Efficiency, VOUT = -3.3 V Output Regulation, VOUT = -3.3 V 3.40 80 3.38 |VOUT| REGULATION (V) EFFICIENCY (%) 70 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 3.36 3.34 3.32 3.30 3.28 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 3.26 3.24 3.22 30 3.20 0 20 40 60 80 100 120 140 LOAD (mA) 0 20 Figure 7. 40 60 80 100 120 140 LOAD (mA) Figure 8. Efficiency, VOUT = -2.5 V Output Regulation, VOUT = -2.5 V 80 2.60 |VOUT| REGULATION (V) 2.58 EFFICIENCY (%) 70 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 2.56 2.54 2.52 2.50 2.48 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 2.46 2.44 2.42 30 2.40 0 30 60 90 120 LOAD (mA) 150 180 Figure 9. 0 30 60 90 120 LOAD (mA) 150 180 Figure 10. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 5 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, CIN = 10 F 6.3 V X5R ceramic capacitor; COUT = 2 x 22 F 6.3 V X5R ceramic capacitor; L = 6.8 H (VLS2012ET-6R8M); TAMBIENT = 25 C. Efficiency, VOUT = -1.5 V Output Regulation, VOUT = -1.5 V 1.60 80 1.58 |VOUT| REGULAITON (V) EFFICIENCY (%) 70 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 1.56 1.54 1.52 1.50 1.48 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 1.46 1.44 1.42 30 1.40 0 30 60 90 120 150 180 210 LOAD (mA) 0 30 Figure 11. 60 90 120 150 180 210 LOAD (mA) Figure 12. Efficiency, VOUT = -0.9 V Output Regulation, VOUT = -0.9 V 1.00 80 0.98 |VOUT| REGULATION (V) EFFICIENCY (%) 70 60 50 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 40 0.96 0.94 0.92 0.90 0.88 VIN = 2.8V VIN = 3.3V VIN = 4.0V VIN = 5.0V VIN = 5.5V 0.86 0.84 0.82 30 0.80 0 50 100 150 LOAD (mA) 200 250 0 50 Figure 13. MAX LOADING (mA) 200 150 100 VOUT = -5V VOUT = -3.3V VOUT = -2.5V VOUT = -1.5V VOUT = -0.9V 0 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 600 580 560 540 520 500 Temp = -40C Temp = 25C Temp = 125C 480 460 Figure 15. 6 250 Minimum Switching Frequency MINIMUM SWITCHING FREQUENCY (kHz) Maximum Load Current 2.8 200 Figure 14. 250 50 100 150 LOAD (mA) 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 Figure 16. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, CIN = 10 F 6.3 V X5R ceramic capacitor; COUT = 2 x 22 F 6.3 V X5R ceramic capacitor; L = 6.8 H (VLS2012ET-6R8M); TAMBIENT = 25 C. No Load Supply Current Rds-on 3.0 2.0 1.8 NO LOAD CURRENT (mA) 2.5 1.6 RDS-ON ( ) 2.0 1.5 1.0 1.4 1.2 1.0 0.8 Vin = 2.8V Vin = 4.0V Vin = 5.5V 0.6 0.4 0.5 0.2 0.0 0.0 2.8 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 17. Figure 18. Enable Thresholds Soft Start Time (No Load) SOFT START TIME (NO LOAD) ( s) 800 EN THRESHOLDS (V) 1.1 1.0 0.9 0.8 0.7 Rising TH -40C Falling TH -40C Rising TH 25C Falling TH 25C Rising TH 125C Falling TH 125C 0.6 0.5 0.4 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 Vout = -5.0V Vout = -3.3V Vout = -2.5V Vout = -1.5V Vout = -0.9V 700 600 500 400 300 200 100 5.5 0 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 Figure 19. Figure 20. Soft Start Delay Time (From EN Rising Edge) Soft Off Time, VOUT = -5.5 V (No Load, From EN Falling Edge) SOFT OFF TIME (EN TO 10% VOUT) ( s) SOFT START DELAY TIME ( s) 160 140 120 100 80 60 40 Temp = -40C Temp = 25C Temp = 125C 20 0 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 Figure 21. 800 700 600 500 VIN = 2.8 V VIN = 3.0 V VIN = 4.0 V VIN = 5.0 V 400 300 0 10 20 30 40 50 60 70 80 90 TEMP (C) Figure 22. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 7 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, the following conditions apply: VIN = 3.3 V, VOUT = -5.0 V, VEN = 1.8 V, CIN = 10 F 6.3 V X5R ceramic capacitor; COUT = 2 x 22 F 6.3 V X5R ceramic capacitor; L = 6.8 H (VLS2012ET-6R8M); TAMBIENT = 25 C. Soft Start And Soft Off Waveform VIN = 5.0 V, VOUT = -5.0 V, No Load Soft Start And Soft Off Waveform VIN = 5.0 V, VOUT = -5.0 V, Load = 50 VSW 2V/Div EN VOUT VSW 2V/Div 1V/Div EN 1V/Div 1V/Div VOUT 100 mA/Div IL 1V/Div 100 mA/Div IL 500 s/Div 500 s/Div Figure 23. Figure 24. Typical Switching Waveform VIN = 5.0 V, VOUT = -5.0 V, No Load Typical Switching Waveform VIN = 5.0 V, VOUT = -5.0 V, IOUT = 70 mA 5V/Div VSW VSW 5V/Div 10 mV/Div, AC coupled VOUT VOUT 5 mV/Div AC coupled 200 mA/Div IL IL 200 mA/Div 2 s/Div 2 s/Div Figure 25. Figure 26. Load Transient, VIN = 4.0 V, VOUT = -5.5 V Load steps between 2 mA and 50 mA Short Circuit Waveform VIN = 5.0 V, VOUT = -5.5 V 2V/Div VSW VSW -5.5V 20 mV/Div, AC coupled VOUT 0V 0V VOUT 1V/Div -5.5V 10 mA/Div IOUT EN 0.5V/Div 100 mA/Div IL IL 100 mA/Div 5 ms/Div 2 ms/Div Figure 27. 8 2V/Div Figure 28. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 BLOCK DIAGRAM Peak Current Limit Modulation GND - FB + + + - VIN VIN CIN UVLO Current Sensing shutdown R R EN - LOGIC S FB + Minimal Frequency Detector Voltage Reference S Q Driver L SW shutdown GND Soft Pull Down VREF FB TSD R Min Off Timer R D COUT LOAD GND VOUT VOUT Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 9 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com OPERATING DESCRIPTION The LMR70503 integrates an inverting buck-boost controller and a high-side MOSFET in one tiny 8-bump thin DSBGA package. A simplified buck-boost converter schematic is shown in Figure 29. VIN SW VOUT Figure 29. Buck Boost Converter The LMR70503 controller incorporates a unique peak current mode control method with a minimum switching frequency limit. The integrated switch is turned off when its current crosses the peak current limit, while it is turned on when the magnitude of VOUT droops below a threshold. When the switch is off, the inductor current goes through the diode and charges the output capacitor(s). With fixed peak current limit, the switching frequency decreases with decreased load current. At light load, the switching frequency will decrease to the audible frequency range, which is not acceptable in many applications. The LMR70503 is designed to operate with peak current mode control and limit the switching frequency to 500 kHz (typical) minimum, to avoid audible frequency interference. At light load, when the switching frequency drops to the minimum, the inductor current limit is reduce instead of frequency to maintain regulation. The LMR70503 also incorporates an internal dummy load to compensate for the extra charges in the minimum ON-time (TON-MIN) condition. More details on the LMR70503 operation are described in the later sessions. Typical switching waveforms in discontinuous conduction mode (DCM) and continuous conduction mode (CCM), including the inductor current, the switch node voltage and the output voltage ripple (absolute value), are shown in Figure 30. DCM CCM Inductor Current Inductor Current VIN VIN 0V Switch Node Switch Node VOUT 0V VOUT |VOUT| |VOUT| Ts 2Ts t Ts 2Ts 3Ts t Figure 30. Typical Waveforms In Buck Boost Converter Figure 31 illustrates the switching frequency, the peak current limit, the output voltage and the dummy load with different load current. More details on each operation mode will be described later. 1. No load to very light load: high side switch is turned on for TON-MIN; switching frequency is limited at the minimum switching frequency; and the dummy load is turned on. 2. Light load: switching frequency is limited at the minimum switching frequency, peak current limit increases with increased load current; and the dummy load is off. 3. Heavy load: peak current equals the maximum peak current limit; switching frequency increases with increased load current; and the dummy load is off. 10 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 Switching frequency FSW-MIN 0 Load current |VOUT| 0 Load current Peak Inductor Current IPEAK-MAX 0 Load current Dummy Load Ton-min (1) 0 Const Frequency (2) Const Peak Current (3) Load current Figure 31. The LMR70503 Operation Modes vs. Load Current Minimum Switching Frequency Operation In a typical peak current mode controlled DC-DC converter, the peak current limit is constant and the switching frequency decreases when load current reduces. To maintain low noise operation and avoid audio frequency interference, the minimum switching frequency of the LMR70503 is limited at 500 kHz typically. At heavy load, the peak current limit remains constant and the switching frequency varies with the load to regulate the output voltage. With reduced loading, the absolute output voltage is going to be charged higher than regulation if the switching frequency cannot decrease accordingly. Therefore, to regulate the output voltage with minimum frequency at light load, the peak current limit is reduced, in proportional to the output voltage offset. In this mode, as shown in Figure 31, the switching frequency is fixed to the minimum switching frequency, the peak inductor current increases with load current, and the output voltage magnitude has a small offset above regulation. Minimum ON-Time and Dummy Load When load current is near zero, the peak inductor current can not reduce further due to TON-MIN of the high side switch. Under such conditions, an internal dummy load is turned on by sensing excessive output voltage offset, which removes the extra charge from the output capacitor(s). In this condition, the switching frequency is fixed to the minimum value. The peak inductor current value is at its minimum value, as shown in Figure 31. The dummy load current is zero when the LMR70503 operates with on time higher than TON-MIN. The minimum peak inductor current is determined by IPEAK-MIN = TON-MIN x VIN / L where * * VIN is the supply voltage L is the inductance value (1) The peak inductor current is higher with higher VIN. The inductor current falling slew rate is determined by SRFALLING = (|VOUT| + VF) / L where * * |VOUT| is the absolute value of the output voltage VF is the forward voltage drop of the power diode (2) At lower |VOUT|, it takes longer time to discharge the inductor current to zero. Therefore, there is more energy to charge the output capacitor(s). The output voltage will have more offset at higher VIN and lower VOUT. The dummy load current is a function of the FB voltage: the more the offset at the FB node, the higher the dummy load current, as shown in Figure 32. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 11 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com DUMMY LOAD CURRENT (mA) 10 VIN=5.5V -40C VIN=5.5V 25C VIN=5.5V 125C VIN=2.8V -40C VIN=2.8V 25C VIN=2.8V 125C 9 8 7 6 5 4 3 2 1 0 -50 -40 -30 -20 -10 FB VOLTAGE (mV) 0 Figure 32. Dummy Load Current vs. FB Voltage Constant Peak Current Operation If the load current increases in the minimum switching frequency mode, the peak current limit will reach the maximum peak current limit (IPEAK-MAX). After this point, the LMR70503 behaves as a constant peak current converter with frequency modulation. The transition load level between the constant frequency mode and the constant peak current mode varies with VIN, VOUT and L. The IPEAK-MAX is trimmed to 320 mA in the LMR70503. Due to propagation delays in the comparator and gate drive, the measured peak inductor current will be higher than the trimmed value. The additional offset on the maximum peak current is proportional to the inductor current rising slope: VIN / L, approximately. For a typical inductor, the inductance will reduce at hot temperature. Therefore, IPEAK-MAX is the highest with 5.5 V input voltage at hot temperature. In the constant peak current operation mode, the switching frequency will increase with the increased load current, until the high side switch off time equals the minimum off-time (TOFF-MIN) limit. If the load keeps increasing when the switch operates with TOFF-MIN, VOUT will drop out of regulation due to loading limits of buckboost type of converters. The maximum loading capability is higher with higher VIN, larger L, lower VOUT, and less losses in the converter. Figure 33 shows the measured maximum load current measured with the typical BOM shown in Table 1. To increase the maximum loading capability with given VIN and VOUT, one can choose a higher inductance value and a diode with lower forward voltage drop VF. MAX LOADING (mA) 250 200 150 100 VOUT = -5V VOUT = -3.3V VOUT = -2.5V VOUT = -1.5V VOUT = -0.9V 50 0 2.8 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 Figure 33. LMR70503 Loading Capability vs. VIN, L = 6.8 H 12 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 The built-in TOFF-MIN time is a function of both VIN and VOUT, as shown in Figure 34. 900 800 TOFF-MIN (ns) 700 600 500 400 300 VOUT = -0.9V VOUT = -1.5V VOUT = -2.5V VOUT = -3.3V VOUT = -5.0V 200 100 0 2.8 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 Figure 34. Minimum Off Time vs. VIN at room temperature Enable And UVLO The LMR70503 features an enable (EN) pin and associated comparator to allow the user to easily sequence the LMR70503 from an external voltage rail, or to manually set the input UVLO threshold. Enable threshold levels are referred to the LMR70503 ground, instead of the lowest potential: the negative output voltage. Enable turning on (rising) and turning off (falling) thresholds are shown in Figure 35. EN THRESHOLDS (V) 1.1 1.0 0.9 0.8 0.7 Rising TH -40C Falling TH -40C Rising TH 25C Falling TH 25C Rising TH 125C Falling TH 125C 0.6 0.5 0.4 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 Figure 35. Enable Rising And Falling Thresholds vs. VIN It is important to ensure that a valid input voltage (2.8 V VIN 5.5 V) is present on the VIN pin before the EN input is asserted. Also, as stated in the Absolute Maximum Ratings section of this data sheet, the voltage on the EN pin must always be less than VIN. This applies to both static and dynamic operation, and during start up and shut down sequences. If these precautions are not followed, an internal test mode may be activated; possibly damaging the regulator. The EN input must not be left floating. A resistor divider can be added from VIN to EN if an external enable signal is not available. An input under voltage lock-out (UVLO) circuit prevents the regulator from turning on when the input voltage is not great enough to properly bias the internal circuitry. The typical UVLO rising threshold is 2.55 V and typical hysteresis band is 0.13 V. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 13 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com Soft Start And Soft Off The LMR70503 begins to operate when EN goes high with the presence of valid VIN, or VIN swings below UVLO level and back up with the presence of valid EN voltage. The soft start action is inherent with the maximum peak current limit and minimum off time. During start up, the inductor current rises to the maximum peak current limit, then the high-side switch is turned off for TOFF-MIN and the output capacitor(s) is charged during this time. Then the high-side turns on to repeat the cycle. After the output voltage is charged to the regulation level, the LMR70503 will operate in steady state. The soft start time will be longer with more output capacitance, and / or lower supply voltage VIN, and / or more loading during start up. Figure 36 shows soft start vs VIN with L= 6.8 H and no load. Soft-start is reset any time the part is shut down or a thermal shutdown event occurs. SOFT START TIME (NO LOAD) ( s) 800 Vout = -5.0V Vout = -3.3V Vout = -2.5V Vout = -1.5V Vout = -0.9V 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 Figure 36. Soft Start Time (No Load) vs. VIN SOFT OFF TIME (EN TO 10% VOUT) ( s) The LMR70503 will shutdown when EN pin voltage goes below the falling threshold, or VIN goes below UVLO falling threshold. When shutdown, the LMR70503 incorporates an output voltage discharge feature to bring the output voltage to zero volts, regardless of the load current. When the EN input is taken below its lower threshold, an internal MOSFET turns on and discharges the output capacitors. Typical soft off times (from EN falling edge to 10% of Vout ) over VIN and temperature are shown in Figure 37. Figure 38 shows the typical off time from 90% to 10% of Vout. 800 700 600 500 VIN = 2.8 V VIN = 3.0 V VIN = 4.0 V VIN = 5.0 V 400 300 0 10 20 30 40 50 60 70 80 90 TEMP (C) Figure 37. Soft Off Time (EN Falling Edge To 10% Vout) vs. Temperature, VOUT = -5.5 V, No Load 14 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 SOFT OFF RAMP TIME (90% TO 10%) ( s) www.ti.com 800 700 600 500 400 VIN = 2.8 V VIN = 4.0 V VIN = 5.0 V 300 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) Figure 38. Soft Off Time (90% To 10% Vout) vs. Temperature, VOUT = -5.5 V, No Load Short Circuit Protection Peak current mode control has inherent short circuit protection. The protection level is the maximum inductor current limit level. It varies with VIN and temperature due to propagation delays. The minimum off-time limits the current going through the inductor during a short circuit condition. Over-Temperature Protection Internal thermal shutdown (TSD) circuitry protects the LMR70503 should the maximum junction temperature be exceeded. This protection is activated at 165 C (typical), with the result that the regulator will shutdown until the junction temperature drops below 155 C (typical). Of course the LMR70503 must not be operated continuously above 125 C. Design Guide Output Voltage Setting The output voltage of the LMR70503 is programmable by the voltage divider resistors. The reference voltage is typically 1.19 V. To avoid overloading the VREF circuity, the resistor RT tied between VREF and FB is recommended to be between 20 k and 100 k. With a selected RT, RB tied between VOUT and FB can be found by RB = RT * |VOUT| / VREF (3) A feed-forward capacitor CFF can be used between VOUT and FB nodes to improve transient performance. 10 pF C0G, NP0 type of capacitor is recommended in LMR70503 applications. Input Capacitor And Output Capacitor Selection The input capacitor selection is based on both input voltage ripple and RMS current. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the regulator current during switch on-time. Low ESR ceramic capacitors are preferred. A minimum value of 10F at 6.3 V, is required at the input of the LMR70503. Larger values of input capacitance are desirable to reduce voltage ripple and noise on the input supply. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 15 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com The output capacitor is responsible for filtering the output voltage and suppling load current during transients and during the power diode off-time. Best performance is achieved with ceramic capacitors. For most applications, a minimum value of 22 F, 6.3 V capacitor is required at the output of the LMR70503. The percentage of ripple coupled to the FB node can be found by RIPPLE PERCENTAGE = VREF / ( |VOUT| + VREF) where * * |VOUT| is the magnitude of the output voltage VREF is the reference voltage (4) With lower magnitude VOUT, a higher percentage of output voltage ripple is coupled to the FB node. Output voltage ripple is also coupled to the FB node via the feed-forward capacitor CFF. Excessive ripple at the FB node may trigger peak current limit modulation causing unstable operation. Higher output capacitance is needed at lower magnitude output voltage. For VOUT = -0.9 V, a minimum of 44 F, 6.3 V capacitor is required. Avoid using too much capacitance at CFF. A capacitor between VIN and VOUT also can be used to provide high frequency bypass. This capacitor is equivalent to the output capacitors in the small signal model. It also reduces the output voltage ripple if sufficiency capacitance is used. The voltage rating for this capacitor should be higher than VIN + |VOUT|. All ceramic capacitors have large voltage coefficients, in addition to normal tolerances and temperature coefficients. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum capacitance up to the desired value. This may also help with RMS current constraints by sharing the current among several capacitors. With the LMR70503, ceramic capacitors rated at 6.3 V, or higher, are suitable for all input and output voltage combinations. Many times it is desirable to use an electrolytic capacitor on the input, in parallel with the ceramics. The moderate ESR of this capacitor can help to damp any ringing on the input supply caused by long power leads. This method can also help to reduce voltage spikes that may exceed the maximum input voltage rating of the LMR70503. Power Inductor Selection The power inductor selection is critical to the operation of the LMR70503. It affects the efficiency, the operation mode transition point, the maximum loading capability and the size / cost of the solution. A 4.7 H or 6.8 H inductor is recommended for most LMR70503 applications. The maximum loading capability is reduced with smaller inductance value. The no load VOUT offset is higher at low VOUT with smaller inductance value, due to higher peak current with the same TON-MIN. Higher inductance value usually comes with higher DCR with the same size and cost. Higher DCR will reduce the efficiency especially at heavy load. The inductor must be rated above the maximum peak current limit to prevent saturation. Good design practice requires that the inductor rating be adequate for the maximum IPEAK-MAX over VIN and temperature, plus some safety margin. If the inductor is not rated for the maximum expected current, saturation at high current may cause damage to the LMR70503 and/or the power diode. The DCR of the inductor should be as small as possible with given size / cost constrains to achieve optimal efficiency. Power Diode Selection A Schottky type power diode is required for all LMR70503 applications. The parameters of interests include the reverse voltage rating, the DC current rating, the repetitive peak current rating, the forward voltage drop, the reverse leakage current and the parasitic capacitance. In a buck-boost, this diode sees a reverse voltage of : VR-DIODE = |VOUT| + VIN (5) The reverse breakdown voltage rating of the diode should be selected for this value, plus safety margin. A good rule of thumb is to select a diode with a reverse voltage rating of 1.3 times this maximum. Select a diode with a DC current rating at least equal to the maximum load current that will be seen in the application and the repetitive peak current rating higher than IPEAK-MAX over VIN and temperature. The forward voltage drop of the power diode is a big part of the power loss in a buck-boost converter. It is preferred to be as low as possible. The reverse leakage current and the parasitic capacitance are also part of the power losses in the converter, but usually less pronounced than the forward voltage drop loss. Pay attention to the temperature coefficients of all the parameters. Some of them may vary greatly over temperature and may adversely affect the efficiency over temperature. 16 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 PC Board Layout Guidelines Board layout is critical for the proper operation of switching power converters. Switch mode converters are very fast switching devices. In such cases, the rapid increase of current combined with the parasitic trace inductance generates unwanted L*di/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This noise may turn into electromagnetic interference (EMI) and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The most important layout rule is to keep the AC current loops as small as possible. Figure 29 shows the current flow in a buck-boost converter. The two dotted arrows indicate the current paths when the high side switch is on and when the power diode is on, respectively. The components and traces that contain discontinuous currents are critical in PCB layout design, since discontinuous currents contain high di/dt and high frequency noise. The components that carry critical discontinuous currents include the input capacitor(s), the high side switch, the power diode and the output capacitor(s). These components need to be placed as close as possible to each other and the traces between them must be made as short and wide as possible: place the input capacitor(s) as close as possible to the VIN pin of the LMR70503; place the cathode of the diode as close as possible to the SW pin; the anode of the diode should be as close as possible to the output capacitor(s); the GND end of the output capacitor(s) should be as close as possible to that of the input capacitor(s). Doing so will yield a small loop area, reducing the loop inductance and EMI. The feedback resistors RB and RT should be placed as close as possible to the FB pin. Since FB is a high impedance node, noise is likely be coupled to the FB node if the trace is long. The traces from VOUT to the resistor divider and from the divider to the FB pin should be far away from the discontinuous current path. It is recommended to use 4-layer board with ground plane as an internal layer, route the discontinuous current path on the top layer and the feedback path on the other side of the ground plane. Then the feedback path will be shielded from switching noise. To avoid functional problems due to layout, review the PCB layout example in Figure 39. It is also recommended to use 1oz copper boards or heavier to help reducing the parasitic inductances of board traces. PCB Layout Example Figure 39. PCB Layout Example (top layer and top overlay) Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 17 LMR70503 SNVS850A - JUNE 2012 - REVISED APRIL 2013 www.ti.com LMR70503 Typical Application Circuit L VIN VIN SW Cin D Cout1 Cout2 VOUT VOUT LMR70503 Ren1 Cff Rb EN FB Ren2 Rt GND VREF LMR70503 Application Circuit Bill of Materials VIN = 2.8 V to 5.5 V, VOUT has options of -0.9 V, -1.5 V, -2.5 V, -3.3 V and -5.0 V. Optimized for minimum solution size. Table 1. Bill of Materials Designator Description Case Size Manufacturer Manufacturer P/N U1 Inverting Buck-Boost 8-bump thin DSBGA Texas Instruments LMR70503TM NOPB CIN Ceramic 10 F 10 V X5R 0603 0603 TDK C1608X5R1A106M COUT1, COUT2 Ceramic 22 F 6.3 V X5R 0603 0603 TDK C1608X5R0J226M Cff CAP CER 10PF 50V 5% NP0 0402 0402 Murata GRM1555C1H100JZ01D D Schottky 30 V 500 mA SOD882 NXP Semi PMEG3005EL L 6.8 H, 0.76 A 362 m 2.0*2.0*1.2mm TDK VLS2012ET-6R8M RT RES, 100k ohm, 1%, 0.063W, 0402 0402 Vishay Dale CRCW0402100KFKED 422 k For Vout = -5.0V 0402 Vishay Dale CRCW0402422KFKED 274 k For Vout = -3.3V 0402 Vishay Dale CRCW0402274KFKED 210 k For Vout = -2.5V 0402 Vishay Dale CRCW0402210KFKED 127 k For Vout = -1.5V 0402 Vishay Dale CRCW0402127KFKED 75 k For Vout = -0.9V 0402 Vishay Dale CRCW040275K0FKED RES, 20k ohm, 5%, 0.063W, 0402 0402 Vishay Dale CRCW040220K0JNED RB (1) REN1, REN2 (1) 18 RB is represented by R1 in Figure 39. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 LMR70503 www.ti.com SNVS850A - JUNE 2012 - REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR70503 19 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMR70503TM/NOPB ACTIVE DSBGA YFX 8 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 S3 LMR70503TMX/NOPB ACTIVE DSBGA YFX 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 S3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMR70503TM/NOPB DSBGA YFX 8 250 178.0 8.4 LMR70503TMX/NOPB DSBGA YFX 8 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 0.91 1.69 0.7 4.0 8.0 Q1 0.91 1.69 0.7 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR70503TM/NOPB DSBGA YFX LMR70503TMX/NOPB DSBGA YFX 8 250 210.0 185.0 35.0 8 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFX0008xxx D 0.6000.075 E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE TMP08XXX (Rev A) D: Max = 1.64 mm, Min = 1.58 mm E: Max = 0.855 mm, Min =0.795 mm 4215093/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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