EV71571BCR - E2V Technologies (UK), Ltd.

EV71571

320 MHz 12k Pixels

Datasheet B&W Linear CCD

Features

• Data rate: Up to 320 MPixels/s (8 outputs at 40MHz each)

• Line rate: Up to 25 kLines/s

• Pixel size: 5µm square

• 300 to 1100 nm Spectral Range

• High sensitivity, lag free Photo Diodes

• Low noise

• Anti-blooming x100 Esat

• Exposure control

• PGA64 0.75”

Applications

Speed and performance make this device suitable for:

• Web inspection

• Food sorting

• Document scanning

• Industrial control

Description

The EV71571 is a monochrome linear sensor based on charge coupled device (CCD) technology

with lag-free photodiodes. The EV71571’s linear array consists of a photosensitive line of 12 288

useful pixels with height CCD shift registers and height output amplifiers.

Visit our website: www.e2v.com

for the latest version of the datasheet

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1. Pin Identification

Description Name N° “Top view” N° Name Description

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Amplifier reference output n°1 VS1 1 64 VS5 Amplifier reference output n°5

Output n°1 VO1 2 63 VO5 Output n°5

Amplifier DC supply - outputs 1 & 2 VDD12 3 62 VDD56 Amplifier DC supply - outputs 5 & 6

Reset clock - outputs 1 & 2 4

ΦRA 61

ΦRC Reset clock - outputs 5 & 6

Output clock – outputs 1 & 2 5

ΦLSA 60

ΦLSC Output clock – outputs 5 & 6

Substrate VSS 6 59 VSS Substrate

Output gate bias- outputs 1 & 2 VGS12 7 58 VGS56 Output gate bias- outputs 5 & 6

Reset bias - outputs 1 & 2 VDR12 8 57 VDR56 Reset bias - outputs 5 & 6

Output n°2 VO2 9 56 VO6 Output n°6

Amplifier reference output n°2 VS2 10 55 VS6 Amplifier reference output n°6

Substrate VSS 11 54 VSS Substrate

Shift register clocks - outputs 1 & 2 12

ΦL2A 53

ΦL2C Shift register clocks - outputs 5 & 6

Shift register clocks - outputs 1 & 2 13

ΦL1A 52

ΦL1C Shift register clocks - outputs 5 & 6

Anti-blooming bias - outputs 1 to 4 VA1 15 51 VSS Substrate

Substrate VSS 14 50 VST2 Storage gate bias - outputs 5 to 8

Anti-blooming bias - outputs 1 to 4 16

ΦA1 49

ΦP2 Transfer clock, outputs 5 to 8

Transfer clock – outputs 1 to 4 17

ΦP1 48

ΦA2 Anti-blooming bias - outputs 5 to 8

Storage gate bias - outputs 1 to 4 VST1 18 47 VA2 Anti-blooming bias - outputs 5 to 8

Substrate VSS 19 46 VSS Substrate

Shift register clocks - outputs 3 & 4 20

ΦL1B 45

ΦL1D Shift register clocks - outputs 7 & 8

Shift register clocks - outputs 3 & 4 21

ΦL2B 44

ΦL2D Shift register clocks - outputs 7 & 8

Substrate VSS 22 43 VSS Substrate

Amplifier reference output n°3 VS3 23 42 VS7 Amplifier reference output n°7

Output n°3 VO3 24 41 VO7 Output n°7

Reset bias - outputs 3 & 4 VDR34 25 40 VDR78 Reset bias - outputs 7 & 8

Output gate bias- outputs 3 & 4 VGS34 26 39 VGS78 Output gate bias- outputs 7 & 8

VOS1 VOS2 VOS3 VOS4

VOS5 VOS6 VOS7 VOS8

1

12288

Substrate VSS 27 38 VSS Substrate

Output clock – outputs 3 & 4 28 37 Output clock – outputs 7 & 8

ΦLSB ΦLSD

Reset clock - outputs 3 & 4 29 36 Reset clock - outputs 7 & 8

ΦRB ΦRD

Amplifier DC supply - outputs 3 & 4 VDD34 30 35 VDD78 Amplifier DC supply - outputs 7 & 8

Output n°4 VO4 31 34 VO8 Output n°8

33 VS8 Amplifier reference output n°8

Amplifier reference output n°4 VS4 32

2. Absolute Maximum Rating

Table 1. Maximum Applied Voltages with respect to VSS

Parameter Min Max

Storage temperature - 55 °C 150 °C

Operating temperature - 40 °C 85 °C

Thermal Cycling 15°C/mn

Maximum applied voltages:

CCD Clocks -0.3 V 17 V

ΦRi (4, 29, 36, 61)

ΦLij (12, 13, 20, 21, 44, 45, 52, 53)

ΦLSi (5, 28, 37, 60)

ΦAi (16, 48)

ΦP (17, 49)

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CCD Polarization -0.3 V 17 V

VGSij (7, 26, 39, 58)

VDDij (3, 30, 35, 62)

VDRij (8, 25, 40, 57) Warning: see note below.

VAi (15, 47)

VST (18, 50)

i0 V 0 V

Grounds

VSS (6, 11, 14, 19, 22, 27, 38, 43, 46, 51, 54, 59)

VS (1, 10, 23, 32, 33, 42, 55, 64)

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Max temperature / Maximum Time for soldering 245°C 10s

Notes:

• Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum

ratings for extended periods may affect device reliability.

• Shorting the outputs even temporarily may destroy the device.

• When VDD > 10V, VDR should not be set at less than VDD-10V.

• All Grounds (VSS & VS) must be connected

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3. Handling & Mechanical Precautions

The EV71571 is sensitive to ESD (ElectroStatic Discharges). To avoid accumulation of charges and

to prevent electrical field formation, the following precautions must be taken during manipulation:

• Wear anti-static gloves or finger cots, anti-static clothes and shoes.

• Protect workstation with a conductive ground sheet.

• Use conductive boxes.

The EV71571 sensor is an optical device. All precautions must be taken to prevent dust or scratches

on the input window.

Due to the length of the sensor it is recommended to not fix the sensor directly on a camera front

face without a soft thermal interface.

Due to PGA manufacturing there are two areas on the package sides with electrical contacts.

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4. Operating Conditions

Table 2. DC Characteristics Value

Parameter Symbol

Min Typical Max Current

Amplifier drain supply VDD 14.5V 15V 15.5V < 4x30 mA @ 55°C

Anti blooming diode bias VA 14.5V 15V 15.5V < 10µA

Reset bias VDR 12V 12.5V 13V < 5µA

Storage gate bias VST 2V 2.5V 3V < 5µA

Output gate VGS 2V 2.5V 3V < 5µA

Amplifier source bias VS 0V < 8x15 mA @ 55°C

Substrate bias VSS 0V

Table 3. Clock Characteri stics Value

Parameter Symbol

Min Typ Max Peak current

Transfer clock Low level

High level

ΦP

0

8.5

0.2

9

0.5

9.5 IMAX < 100 mA

Shift register clocks

Low level

High level – Low level

ΦLi

0

5.5

0.2

6

0.5

7 IMAX < 400 mA

Output clock Low lev el

High level – Low level

ΦLS

0

5.5

0.2

6

0.5

7 IMAX < 30 mA

Reset clock Low level

High level

ΦR

5

13

7

14

7.5

15 IMAX < 30 mA

Anti blooming gate

Bias when exposure time

control not required see

§ 0

ΦA 2.5V 3V 5V < 5µA

When exposure adjustment

is required Low level

High level

ΦAL

ΦAH

2.5

9

3

11

5

12

IMAX < 50 mA

Table 4. Clock Capacitances, Rising and Falling Times Rising and falling times

Parameter Symbol Capacitance

Min Typical Max

Transfer clock 75pF 10ns 15ns 20ns

ΦP

Shift register clocks See figure bellow 5ns 8ns 10ns

ΦLi

Output clock 20pF 2ns 3ns 5ns

ΦLS

Reset clock 20pF 2ns 3ns 5ns

ΦR

Anti blooming gate

(when exposure control

is used) 50pF 10ns 15ns 20ns

ΦA

Figure 1. Horizontal Clock

ØL2

ØL1

Vss

160pF

55pF

150pF

5. Timing Diagrams

Figure 2. Timing Diagram without Integration Time Control

ФL1

ФA

ФP

Line Period

ФL2

ФR

Transfer Period

ФLS

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Figure 3. Timing Diagram with Integration Time Control

ФL1

ФA

ФP

Line Period

ФL2

ФR

Transfer Period

In te g ra tio n time

> 10 ns

ФLS

Figure 4. Line Transfer Detail

ФL1

400ns typ

ФL2

ФR

First prescan pixel

ФA

ФP

> 20ns > 20ns

600ns max

ФLS

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Figure 5. Pixel Timing

1/Fpixel # 25ns

Crossover of complementary clocks

ΦL1 & ΦL2 at 50% of their amplitude

ΦL1

ΦL2

ΦLS

ΦR

VOS

Phase tolerance

Φ

LS/

Φ

L2 : TrΦLS 0ns / +2 ns later than TrΦL2

1/Fpixel # 25ns

15 to 20ns

Phase tolerance

Φ

R/

Φ

LS : TrΦLS 0ns / +2 ns later than TrΦR

3 to 5ns

3 to 4ns

6 to 8ns

3 to 5ns 3 to 4ns

6 to 8 ns

Table 5. Pixel Output Order (All outputs are in pha se)

VO1 VO2 VO3 VO4 VO5 VO6 VO7 VO8

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

Ø Ø Ø Ø Ø Ø Ø Ø

Pre-scan 15 15 15 15 15 15 15 15

16 16 16 16 16 16 16 16

1 3 073 9 215 12 287 2 3 074 9 216 12 288

3 3 075 9 213 12 285 4 3 076 9 214 12 286

5 3 077 9 211 12 283 6 3 078 9 212 12 284

7 3 079 9 209 12 281 8 3 080 9 210 12 282

Ø Ø Ø Ø Ø Ø Ø Ø

useful pixels

3 067 6 139 6 149 9 221 3 068 6 140 6 150 9 222

3 069 6 141 6 147 9 219 3 070 6 142 6 148 9 220

3 071 6 143 6 145 9 217 3 072 6 144 6 146 9 218

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6. Electrical Performance

Table 6. Geometrical Characteristic Values

Parameters Symbol

Min. Typ. Max. Units Remark

Pixel aperture Pa 5 µm square pixel

Pixel pitch Pp 5 µm

Pixel number 12 288

Image size Is 61.44 mm

Table 7. DC Characteristic Values

Parameters Symbol

Min. Typ.l Max. Units Remark

Amplifier supply current IDD 10 12 15 mA For each of the 8 ampl.

DC Output level VREF 7 9 10 V

Output impedance Zs 150 200 250 Ω

Amplifier bandwidth BW 115 MHz With 5pF load

Amplifier gain Ga 0.55 @ 40MHz

Conversion factor CVF 9 µV/e-

Max Readout frequency FH40 MHz

Max Line rate LH25 klines/s

Table 8. Electro-optical Characteristic

@ 35°C – 8 x 40 MHz – Light source 3200 K + BG38 2mm @ F#/3.5

Values Units Remark

Parameters Symbol

Min. Typ Max. Anti-blooming efficient on

all pixels (Pulsed mode)

Useful Saturation Level V 0.8 1 V

SAT

+/-

400

Saturation Non Uniformity +/- 250 mV

ΔVSAT

Pixel Dark Signal DSPIX 150 400 mV/s Depends on integration

time

Register Dark Signal DS 300 800 mV/s Depends on readout time

REG

Dark Signal Non Uniformity σDSNU 25 120 mV/s

Depends on integration

time

Temporal noise in

darkness 300 450 µV RMS value VN

Dynamic range DR 65 70 dB = VSAT / VN

Responsivity R 4 5 V/(µJ/cm²) 3200K + BG38 2mm

Photo response non

uniformity 8 %

PRNUPP

Photo Response Non

Uniformity PRNUHF 6 12 %

With or without exposure

time control

Photo response non

uniformity, low frequency

component +/- 4 +/- 6 % 15 pixels median filter

PRNULF

Output responsivity

imbalance 5 10 %

Non linearity NL +/-1 % of V From 10% to 90% of V

SAT SAT

Modulation Transfer

Function MTF 45 50 % FNY = 100lp/mm

LAG LAG 1 % For Vos > Vsat/10

Charge transfer

inefficiency Per stage - From 5% to

100% of V

HCTI 2e-5 5e-5 % SAT

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Figure 6. Spectral Response

0,0

1,0

2,0

3,0

4,0

5,0

6,0

400 500 600 700 800 900 1000

Wavelength (nm)

Responsivity V/(μJ/cm

2

)

Figure 7 Saturation Level versus ΦA Voltage

AT 71571 - Ty pical Sat uration Level Con t r ol

0

500

1000

1500

012345678910

VØA (V)

Average Output Level (mV

)

VST=2,5V VST=2V VST=3V

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7. Package Information

Figure 8. Mechanical References Position

Black triangles show the references used during assembly step. Best positioning is reached when

using them also during camera assembly.

Figure 9. First Pixel Position (zoom of the above drawing)

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Figure 10. Package Outline

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Figure 11. Package Outline (zoom of the cross section)

Table 9. Package Tolerances Values

Parameters Symbol

Min Typ Max

Units Remark

X 4680 4780 4880

µm

Y 12400 12500 12600

Zmeca 0.64 0.70 0.76 Top of die / Z ref on above

figure

First pixel vs. package

reference mm Focus plane / Z ref on above

figure

Zopt 1.02 1.08 1.14

Die orientation vs. package

reference in Y axis +/- 100 µm

θ

Die orientation vs. package

reference in Z axis +/- 35 µm = tilt

Flatness (peak to peak) 10 20 µm Without tilt

8. Ordering Codes

EV71571BCR

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How to reach us

Home page: www.e2v.com

Sales offices:

Americas

Europe Regional sales office e2v inc.

e2v ltd

106 Waterhouse Lane 520 White Plains Road

Suite 450 Tarrytown, NY 10591 Chelmsford Essex CM1 2QU USA England

Tel: +44 (0)1245 493493 Tel: +1 (914) 592 6050 or 1-800-342-5338

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Tel: +33 (0) 1 60 19 55 00 29 Wyndham Street,

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E-Mail: enquiries-fr@e2v.com Tel: +852 3679 364 8/9

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E-Mail: enquiries-de@e2v.com Hotline: hotline.EyeOnSi@e2v.com

Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of

any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in

its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance

with information contained herein.

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