Winbond Clock Generator W83195CW-NP For Intel Napa Platform Date: Feb/2006 Revision: 0.5 W83195CW-NP W83195CW-NP Data Sheet Revision History 1 PAGES DATES VERSION WEB VERSION MAIN CONTENTS n.a. 2/14/2006 0.5 n.a. All of the versions before 0.50 are for internal use. 2 3 4 5 6 7 8 9 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP Tables of Content1. GENERAL DESCRIPTION ......................................................................................................... 1 2. PRODUCT FEATURES .............................................................................................................. 1 3. PIN CONFIGURATION ............................................................................................................... 2 4. BLOCK DIAGRAM ...................................................................................................................... 3 5. PIN DESCRIPTION..................................................................................................................... 4 5.1 Crystal I/O.................................................................................................................................4 5.2 CPU, SRC, and PCIEX, PCI, Clock Outputs ..........................................................................4 5.3 Fixed Frequency Outputs.........................................................................................................5 5.4 I2C Control Interface ................................................................................................................5 5.5 Power Management Pins.........................................................................................................5 5.6 Power Pins................................................................................................................................6 6. FREQUENCY SELECTION BY HARDWARE ............................................................................ 6 7. I2C CONTROL AND STATUS REGISTERS............................................................................... 7 8. ACCESS INTERFACE .............................................................................................................. 12 9. 8.1 Block Write protocol ...............................................................................................................12 8.2 Block Read protocol ...............................................................................................................12 8.3 Byte Write protocol .................................................................................................................12 8.4 Byte Read protocol.................................................................................................................12 SPECIFICATIONS .................................................................................................................... 13 9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................13 9.2 General Operating Characteristics ........................................................................................13 9.3 Skew Group timing clock........................................................................................................13 9.4 CPU 0.7V Electrical Characteristics ......................................................................................14 9.5 SRC 0.7V Electrical Characteristics ......................................................................................14 9.6 9.6 PCIE 0.7V Electrical Characteristics ...............................................................................14 9.7 PCI Electrical Characteristics.................................................................................................15 9.8 48M Electrical Characteristics................................................................................................15 9.9 REF Electrical Characteristics ...............................................................................................15 9.10 DOT 0.7V Electrical Characteristics ......................................................................................16 10. ORDERING INFORMATION..................................................................................................... 16 11. HOW TO READ THE TOP MARKING...................................................................................... 17 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 18 - II - W83195CW-NP 1. GENERAL DESCRIPTION The W83195CW-NP is a CK410M compliant Clock Synthesizer for Intel P4 processors. W83195CWNP provides all clocks required for high-speed microprocessor and provides, 8 different frequencies of CPU, PCI, PCI-Express clocks setting. Simultaneously W83195CW-NP supports DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195CW-NP programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195CW-NP is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply. 2. PRODUCT FEATURES * * * * * * * * * * * * * 2 pair 0.7 V current mode Differential clock outputs for CPU 6 pair 0.7V current mode Differential clock outputs for SRC and PCIEX. 1 pair 0.7V current mode Differential clock outputs for SATA. 1 pair 0.7 V current mode Differential clock outputs select for CPUCLK_ITP/SRC. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 4 PCI clock outputs for PCI 2 PCI clock free running outputs for PCI 1 48 MHz clock output for USB. 1 14.318MHz REF clock outputs. I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% spread spectrum Programmable spread spectrum scale to reduce EMI Programmable registers to enable/stop each output. * 56 pin TSSOP package -1- Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 3. PIN CONFIGURATION VDDPCI GND PCI3 PCI4 PCI5 GND VDDPCI &ITP_EN/PCICLK_F0 PCICLK_F1 Vtt_PWRGd#/PD VDD48 48MHZ/*FS_A GND DOTT_96MHZ DOTC_96MHZ &FS_B SRCT0 SRCC0 SRCT1 SRCC1 VDDSRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDDSRC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 #: Active low *: Internal pull up resistor 120K to VDD & : Internal Pull-down resistor 120K to GND -2- PCI2 PCI/SRC_STOP# CPU_STOP# &FS_C REF GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/SRCT7 CPUCLKC2_ITP/SRCC7 VDDSRC SRCT6 SRCC6 SRCT5 SRCC5 GND W83195CW-NP 4. BLOCK DIAGRAM 48MHz PLL2 Divider DOTT DOTC XIN XOUT XTAL OSC REF 2 PLL1 Spread Spectrum VCOCLK 8 M/N/Ratio ROM CPUT 0:1 CPUC 0:1 2 CPUCLKT2_ITP /SRCT7 CPUCLKC2_ITP /SRCC7 Divider 8 2 FS(A:C) VTT_PWRGD# SDATA SCLK 4 PCI_F 0:1 PCI 2:5 Control Logic &Config Register IREF PCI/SRC_STOP# CPU_STOP# PD & ITP_EN Latch &POR SRCT 0:6 SRCC 0:6 475 I2C Interface -3- Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN Input INtp120k Latched input at power up, internal 120k pull up. INtd120k Latched input at power up, internal 120k pull down. OUT 5.1 Output OD Open Drain I/OD Bi-directional Pin, Open Drain. # Active Low * Internal 120k pull-up & Internal 120k pull-down Crystal I/O PIN 5.2 DESCRIPTION PIN NAME 50 XIN 49 XOUT TYPE IN OUT DESCRIPTION Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). CPU, SRC, and PCIEX, PCI, Clock Outputs PIN PIN NAME 44,43,41,40 CPUT [0:1] CPUC [0:1] 17,18,19,20, SRCT[0:6] 22,23,24,25, SRCC[0:6] 26,27,31,30, 33,32 36,35 SRCT/C 7 CPUCLKT/C2_ITP TYPE OUT OUT OUT OUT 8 PCI_F0 & ITP_EN OUT INtd120k 9 56,3,4,5 PCI_F1 PCI [2:5] OUT OUT DESCRIPTION Low skew (< 85ps) 0.7V Current mode differential clock outputs for host frequencies of CPU 0.7V current mode differential clock outputs for SRC. SRC4_SATA is fixed 100MHz for serial ATA. 0.7V Current mode differential clock outputs for SRC (default), select by ITP_EN pin =0. 0.7V Current mode differential clock outputs for host frequency, select by ITP_EN pin =1. 3.3V free running PCI clock output. Latched input for at initial power up to select CPUCLK2_ITP/SRC7 output. 1: CPUCLK2 clock output. 0: SRC7 clock output. This pin has internal 120K pull down. 3.3V free running PCI clock output. Low skew (< 250ps) 3.3V PCI clock outputs -4- W83195CW-NP 5.3 Fixed Frequency Outputs PIN 52 REF 48MHz 12 * 14,15 5.4 PIN NAME FSA DOTT/C DESCRIPTION OUT OUT 3.3V REF 14.318Mhz clock output. 48MHz clock output for USB. Latched iNQut for FSA at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. 0.7V current mode 96MHz differential clock outputs for DOT Latched iNQut for FSB at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. Latched input for FS2 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. INtp120k OUT 16 & INtd120k 53 & INtd120k FSB FSC I2C Control Interface PIN 5.5 TYPE PIN NAME TYPE DESCRIPTION 47 SDATA I/O Serial data of I C 2-wire control interface 46 SCLK IN Serial clock of I2C 2-wire control interface 2 Power Management Pins PIN 39 54 55 10 PIN NAME IREF TYPE DESCRIPTION OUT Deciding the reference current for the differential pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. CPU clock stop control pin, This pin is low active. Internal 120k pull-up. PCI clock stop control pin, This pin is low active. Internal 120k pull-up. Power good is a low active input signal used to determine when FS [2:0] are valid to be sample. Power Down Function. This is power down pin, high active (PD). Internal 120K pull down CPU_STOP#* IN PCI/SRC_STOP#* IN VTT_PWRGD# IN PD INtd120k -5- Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 5.6 Power Pins PIN PIN NAME TYPE DESCRIPTION 37 VDDA PWR 3.3V power supply for PLL core. 1,7 VDDP PWR 3.3V power supply for PCI. 21,28,34 VDDS PWR 3.3V power supply for SRC pair. 11 VDD48 PWR 3.3V power supply for 48MHz. 42 VDDC PWR 3.3V power supply for CPU. 48 VDDR PWR 3.3V power supply for REF. 38 GNDA PWR Ground pin for PLL core. 2,6,13,29,45,51 GND PWR Ground pin 6. FREQUENCY SELECTION BY HARDWARE FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU (MHZ) 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 -6- DOT (MHZ) 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 SRC (MHZ) 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI (MHZ) 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 W83195CW-NP 7. I2C CONTROL AND STATUS REGISTERS Register 0: ( Default : FFh ) BIT 7 AFFECTED PIN/FUNCTION NAME(S) CPUEN<2> PWD 1 6 SRCEN<6> 1 5 SRCEN<5> 1 4 SRCEN<4> 1 3 SRCEN<3> 1 2 SRCEN<2> 1 1 SRCEN<1> 1 0 SRCEN<0> 1 AFFECTED PIN / FUNCTION DESCRIPTION TYPE CPUCLK2_ITP/SRCCLK7 output control 1: Enable 0: Disable SRCCLK6 output control 1: Enable 0: Disable SRCCLK5 output control 1: Enable 0: Disable SRCCLK4 output control 1: Enable 0: Disable SRCCLK3 output control 1: Enable 0: Disable SRCCLK2 output control 1: Enable 0: Disable SRCCLK1 output control 1: Enable 0: Disable SRCCLK0 output control 1: Enable 0: Disable R/W R/W R/W R/W R/W R/W R/W R/W Register 1: ( Default : FEh ) BIT 7 6 5 AFFECTED PIN/FUNCTION NAME(S) PCIFEN<0> F96EN F48EN PWD 1 1 1 4 REFEN<0> 1 3 Reserved 1 FUNCTION DESCRIPTION PCI_F0 output control 1: Enable 0: Disable DOT96_T/C output control 1: Enable 0: Disable USB48M output control 1: Enable 0: Disable REFOUT output control 1: Enable 0: Disable Reserved -7- TYPE R/W R/W R/W R/W R/W Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP Register 1: ( Default : BIT FEh ), continued AFFECTED PIN/FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE CPUCLK1 output control 2 CPUEN<1> 1 1: Enable R/W 0: Disable CPUCLK0 output control 1 CPUEN<0> 1 1: Enable R/W 0: Disable 0 SPSPEN 0 Enable spread spectrum mode under clock output. 0 = Spread Spectrum mode disable R/W 1 = Spread Spectrum mode enable Register 2: ( Default : FFh) BIT AFFECTED PIN/FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE PCICLK5 output control 7 PCIEN<5> 1 1: Enable R/W 0: Disable PCICLK4 output control 6 PCIEN<4> 1 1: Enable R/W 0: Disable PCICLK3 output control 5 PCIEN<3> 1 1: Enable R/W 0: Disable PCICLK2 output control 4 PCIEN<2> 1 1: Enable R/W 0: Disable 3 Reserved 1 Reserved R/W 2 Reserved 1 Reserved R/W 1 Reserved 1 Reserved R/W PCI_F1 output control 0 PCIFEN<1> 1 1: Enable 0: Disable -8- R/W W83195CW-NP Register 3: ( Default : 00h ) BIT 7 AFFECTED PIN/FUNCTION NAME(S) PWD SRC7_STOP 0 6 SRC6_STOP 0 5 SRC5_STOP 0 4 SRC4_STOP 0 3 SRC3_STOP 0 2 SRC2_STOP 0 1 SRC1_STOP 0 0 SRC0_STOP 0 FUNCTION DESCRIPTION PCI_SRC_STOP# for SRC7 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC6 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC5 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC4 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC3 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC2 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC1 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for SRC0 control. 1: Stoppable 0:Free-Running TYPE R/W R/W R/W R/W R/W R/W R/W R/W Register 4: ( Default : 87) BIT AFFECTED PIN/FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE 7 Reserved 1 Reserved R/W 6 Reserved 0 Reserved R/W 5 Reserved 0 R/W 4 PCIF<1> 0 Reserved PCI_SRC_STOP# for PCIF1 control. 1: Stoppable 0:Free-Running PCI_SRC_STOP# for PCIF0 control. 1: Stoppable 0:Free-Running 1: Enable CPUCLK2_ITP stop feature 0: Disable stop feature 1: Enable CPUCLK1 stop feature 0: Disable stop feature 1: Enable CPUCLK0 stop feature 0: Disable stop feature 3 PCIF<0> 0 2 CPUCLK2_FS_ITP 1 1 CPUCLK1_FS 1 0 CPUCLK0_FS 1 -9- R/W R/W R/W R/W R/W Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP Register 5: ( Default : 00h ) BIT AFFECTED PIN/FUNCTION NAME(S) PWD FUNCTION DESCRIPTION TYPE CPUT / SRCT / PCI_EXP / DOT96_T output state in during POWER DOWN assertion. 1: Driven (2*Iref) 0: Tristate (Floating) 7 DRI_CONT (Reserved) 0 6 5 4 3 2 1 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 SEL_ITP 0 CPUT / SRCT / PCI_EXP / DOT96_T output R/W state in during STOP Mode assertion. 1: Driven (6*Iref) 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. Reserved Reserved Reserved Reserved Reserved Reserved Power on latched value of ITP_EN/PCICLK_F0 pin. SRCCLK/CPU_ITP output clock selection : 1: CPU_ITP clock output 0: SRCCLK clock output R/W R/W R/W R/W R/W R/W R/W Register 6: ( Default : XXh ) BIT AFFECTED PIN/FUNCTION NAME(S) PWD 7 Reserved 1 6 Reserved 0 5 Reserved 0 4 Reserved PCI/SRCCLK_STOP 0 3 2 1 0 1 FSC_BACK FSB_BACK FSA_BACK X X X FUNCTION DESCRIPTION Reserved To stop all PCICLK and SRCCLK output 1: Disable 0: Enable Power on latched value of FSC pin. Power on latched value of FSB pin. Power on latched value of FSA pin. - 10 - TYPE R/W R/W R R R W83195CW-NP Register 7: Winbond Chip ID - Project Code Register ( Default : 11h ) BIT 7 6 5 4 3 2 1 0 AFFECTED PIN/FUNCTION NAME(S) CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0] PWD 0 0 0 1 0 0 0 1 FUNCTION DESCRIPTION Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. - 11 - TYPE R R R R R R R R Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 8. ACCESS INTERFACE The W83195CW-NP provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195CW-NP is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8'h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 12 - W83195CW-NP 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). 9.2 PARAMETER RATING Absolute 3.3V Core Supply Voltage -0.5V to +4.6V Absolute 3.3V I/O Supple Voltage - 0.5V to + 4.6V Operating 3.3V Core Supply Voltage 3.135V to 3.465V Operating 3.3V I/O Supple Voltage 3.135V to 3.465V Storage Temperature - 65C to + 150C Ambient Temperature - 55C to + 125C Operating Temperature 0C to + 70C Input ESD protection (Human body model) 2000V General Operating Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, PARAMETER SYMBOL Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance 9.3 VIL VIH VOL VOH MIN MAX UNITS 0.8 Vdc Vdc Vdc Vdc 2.0 0.4 2.4 Idd 350 mA Cin Cout Lin 5 6 7 pF pF nH TEST CONDITIONS CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Skew Group timing clock VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF PARAMETER MIN MAX UNITS CPU pair to CPU pair Skew 100 ps Measure Crossing point PCIE pair to PCIE pair Skew 85 ps Measure Crossing point PCI to PCI Skew 500 ps Measured at 1.5V 48MHz to 48MHz Skew 1000 ps Measured at 1.5V - 13 - TEST CONDITIONS Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 9.4 CPU 0.7V Electrical Characteristics VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 125 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 9.5 45 TEST CONDITIONS SRC 0.7V Electrical Characteristics VDDS= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Min Max Units Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 9.6 45 Test Conditions mV Measure Single Ended waveform 85 ps Measure Differential waveform 55 % Measure Differential waveform 9.6 PCIE 0.7V Electrical Characteristics VDDPE= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS 175 700 ps Measure Single Ended waveform 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 85 ps Measure Differential waveform 55 % Measure Differential waveform Rise Time Fall Time Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 45 - 14 - TEST CONDITIONS W83195CW-NP 9.7 PCI Electrical Characteristics VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 250 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min Vout=1.0V -33 mA Vout=3.135V mA Vout=1.95V 38 mA Vout=0.4V 30 Pull-Down Current Max 9.8 mA 48M Electrical Characteristics VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 500 ps Measured at 1.5V 55 % Measured at 1.5V Long term jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min -33 30 Pull-Down Current Max 9.9 38 TEST CONDITIONS mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V REF Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 1000 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -29 Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max -23 29 27 TEST CONDITIONS mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V - 15 - Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 9.10 DOT 0.7V Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 250 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 45 TEST CONDITIONS 10. ORDERING INFORMATION PART NUMBER W83195CW-NP PACKAGE TYPE 56 PIN TSSOP (Lead free part) - 16 - PRODUCTION FLOW Commercial, 0C to +70C W83195CW-NP 11. HOW TO READ THE TOP MARKING W83195CW-NP 28051234 504GAABA 1st line: Winbond logo and the part number: W83195CW-NP(Lead free) 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 504 G A A BA 504: packages made in '2005, week 04 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision BA: Internal use code All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date: Feb. 2006 Revision 0.5 W83195CW-NP 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN TSSOP-240mil Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 18 - W83195CW-NP Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 19 - Publication Release Date: Feb. 2006 Revision 0.5