ADC122S706EB/NOPB - NATIONAL SEMICONDUCTOR

November 16, 2007

ADC122S706

Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling

A/D Converter

General Description

The ADC122S706 is a dual 12-bit, 500 kSPS to 1 MSPS si-

multaneous sampling Analog-to-Digital (A/D) converter. The

analog inputs on both channels are sampled simultaneously

to preserve their relative phase information to each other. The

converter is based on a successive-approximation register

architecture where the differential nature of the analog inputs

is maintained from the internal track-and-hold circuits

throughout the A/D converter to provide excellent common-

mode signal rejection. The ADC122S706 features an external

reference that can be varied from 1.0V to VA.

The ADC122S706 offers dual high-speed serial data outputs

that are binary 2's complement and are compatible with sev-

eral standards, such as SPI™, QSPI™, MICROWIRE™, and

many common DSP serial interfaces. Channel A's conversion

result is outputted on DOUTA while Channel B's conversion re-

sult is outputted on DOUTB. This feature makes the AD-

C122S706 an excellent replacement for systems using two

distinct ADCs in a simultaneous sampling application. The

serial clock (SCLK) and chip select bar (CS) are shared by

both channels. For lower power consumption, a single serial

data output mode is externally selectable.

The ADC122S706 may be operated with independent analog

(VA) and digital (VD) supplies. VA can range from 4.5V to 5.5V

and VD can range from 2.7V to VA. With the ADC122S706

operating with a VA of 5V and a VD of 3V, the power con-

sumption at 1 MSPS is typically 25 mW. Operating in power-

down mode, the power consumption of the ADC122S706

decreases to 3 µW. The differential input, low power con-

sumption, and small size make the ADC122S706 ideal for

direct connection to sensors in motor control applications.

Operation is guaranteed over the industrial temperature

range of −40°C to +105°C and clock rates of 8 MHz to 16 MHz.

The ADC122S706 is available in a 14-lead TSSOP package.

Features

■True Simultaneous Sampling Differential Inputs

■Guaranteed performance from 500 kSPS to 1 MSPS

■External Reference

■Wide Input Common-Mode Voltage Range

■Single or Dual High-Speed Serial Data Outputs

■Operating Temperature Range of −40°C to +105°C

■SPI™/QSPI™/MICROWIRE™/DSP compatible Serial

Interface

Key Specifications

■Conversion Rate 500 kSPS to 1 MSPS

■INL ±1 LSB (max)

■DNL ±0.95 LSB (max)

■SNR 71 dBc (min)

■THD -72 dBc (min)

■ENOB 11.25 bits (min)

■Power Consumption at 1 MSPS

■— Converting, VA = 5V, VD = 3V 20 mW (typ)

— Converting, VA = 5V, VD = 5V 25 mW (typ)

— Power-Down 3 µW (typ)

Applications

■Motor Control

■Power Meters/Monitors

■Multi-Axis Positioning Systems

■Instrumentation and Control Systems

■Data Acquisition Systems

■Medical Instruments

■Direct Sensor Interface

Connection Diagram

30017105

TRI-STATE® is a trademark of National Semiconductor Corporation.

MICROWIRE™ is a trademark of National Semiconductor Corporation.

QSPI™ and SPI™ are trademarks of Motorola, Inc.

ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter

Ordering Information

Order Code Temperature Range Description Top Mark

ADC122S706CIMT −40°C to +105°C 14-Lead TSSOP Package, 1000 Units Tape & Reel 2S706

ADC122S706CIMTX −40°C to +105°C 14-Lead TSSOP Package, 3500 Units Tape & Reel 2S706

ADC122S706EB Evaluation Board

Block Diagram

30017102

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ADC122S706

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

1VREF

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1

µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended

for enhanced performance.

2 CHA+ Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential

signal applied to Channel A.

3 CHA− Inverting Input for Channel A. CHA− is the negative analog input for the differential signal

applied to Channel A.

4 GND Ground. GND is the ground reference point for all signals applied to the ADC122S706.

5 CHB− Inverting Input for Channel B. CHB− is the negative analog input for the differential signal

applied to Channel B.

6 CHB+ Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential

signal applied to Channel B.

7VA

Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to

this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in

parallel with a bulk capacitor value of 1.0 µF to 10 µF.

8 DUAL

Applying a logic high to this pin causes the conversion result of Channel A to be output

on DOUTA and the conversion result of Channel B to be output on DOUTB. Grounding this

pin causes the conversion result of Channel A and B to be output on DOUTA, with the result

of Channel A being output first. DOUTB is in a high impedance state when DUAL is

grounded.

9 GND Ground. GND is the ground reference point for all signals applied to the ADC122S706.

10 VD

Digital Power Supply input. A voltage source between 2.7V and VA must be applied to

this input. VD must be decoupled to GND with a ceramic capacitor value of 0.1 µF in

parallel with a bulk capacitor value of 1.0 µF to 10 µF.

11 DOUTA

Serial Data Output for Channel A. With DUAL at a logic high state, the conversion result

for Channel A is provided on DOUTA. The serial data output word is comprised of 4 null

bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling

edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state,

the conversion result of Channel A and B is outputted on DOUTA.

12 DOUTB

Serial Data Output for Channel B. With DUAL at a logic high state, the conversion result

for Channel B is provided on DOUTB. The serial data output word is comprised of 4 null

bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling

edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state,

DOUTB is in a high impedance state.

13 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

14 CS Chip Select Bar. CS is active low. The ADC122S706 is in Normal Mode when CS is LOW

and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.

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ADC122S706

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Digital Supply Voltage VD−0.3V to (VA +0.3V)

max 6.5V

Voltage on Any Pin to GND −0.3V to (VA +0.3V)

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±50 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Charge Device Model

2500V

250V

1000V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40°C ≤ TA ≤ +105°C

Supply Voltage, VA+4.5V to +5.5V

Supply Voltage, VD+2.7V to VA

Reference Voltage, VREF 1.0V to VA

Input Common-Mode Voltage, VCM See Figure 10 (Sect 2.3)

Digital Input Pins Voltage Range 0 to VD

Clock Frequency 8 MHz to 16 MHz

Differential Analog Input Voltage −VREF to +VREF

Package Thermal Resistance

Package θJA

14-lead TSSOP 121°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC122S706 Converter Electrical Characteristics (Note 8)

The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 to 16 MHz, DUAL = VD, fIN =

100 kHz, CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX; all other limits are at TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

(Note 7)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL Integral Non-Linearity ±0.5 ±1 LSB (max)

Integral Non-Linearity Matching 0.02 LSB

DNL Differential Non-Linearity ±0.4 ±0.95 LSB (max)

Differential Non-Linearity Matching 0.02 LSB

OE Offset Error 0.2 ±3 LSB (max)

Offset Error Matching 0.1 LSB

Positive Gain Error −2 ±5 LSB (max)

Positive Gain Error Matching 0.2 LSB

Negative Gain Error 3 ±8 LSB (max)

Negative Gain Error Matching 0.2 LSB

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz, −0.1 dBFS 72.5 69.5 dBc (min)

SNR Signal-to-Noise Ratio fIN = 100 kHz, −0.1 dBFS 73.2 71 dBc (min)

THD Total Harmonic Distortion fIN = 100 kHz, −0.1 dBFS −83 −72 dBc (max)

SFDR Spurious-Free Dynamic Range fIN = 100 kHz, −0.1 dBFS 84 72 dBc (min)

ENOB Effective Number of Bits fIN = 100 kHz, −0.1 dBFS 11.8 11.25 bits (min)

FPBW −3 dB Full Power Bandwidth Output at 70.7%FS with

FS Input

Differential

Input 26 MHz

Single-Ended

Input 22 MHz

ISOL Channel-to-Channel Isolation fIN < 1 MHz −90 dBc

ANALOG INPUT CHARACTERISTICS

VIN Differential Input Range −VREF V (min)

+VREF V (max)

IDCL DC Leakage Current VIN = VREF or VIN = -VREF ±1 µA (max)

CINA Input Capacitance In Track Mode 20 pF

In Hold Mode 3 pF

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ADC122S706

Symbol Parameter Conditions Typical Limits Units

(Note 7)

CMRR Common Mode Rejection Ratio See the Specification Definitions for the

test condition −90 dB

VREF Reference Voltage Range 1.0 V (min)

VAV (max)

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage 2.4 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current (Note 11) VIN = 0V or VA ±1 µA (max)

CIND Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VD − 0.02 VD − 0.2 V (min)

ISOURCE = 1 mA VD − 0.09 V

VOL Output Low Voltage ISINK = 200 µA 0.01 0.4 V (max)

ISINK = 1 mA 0.08 V

IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA ±1 µA (max)

COUT TRI-STATE Output Capacitance Force 0V or VA24pF (max)

Output Coding Binary 2'S Complement

POWER SUPPLY CHARACTERISTICS

VAAnalog Supply Voltage 4.5 V (min)

5.5 V (max)

VDDigital Supply Voltage 2.7 V (min)

VAV (max)

IVA (Conv)

Analog Supply Current, Continuously

Converting (Dual Data Output Mode)

fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100

kHz, VA = 5V, DUAL = VD

3.3 4.2 mA (max)

Analog Supply Current, Continuously

Converting (Single Data Output Mode)

fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100

kHz, VA = 5V, DUAL = 0V 1.8 2.9 mA (max)

IVD (Conv)

Digital Supply Current, Continuously

Converting (Dual Data Output Mode)

fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100

kHz, VD = 5V, DUAL = 5V 1.7 2.0 mA (max)

fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100

kHz, VD = 3V, DUAL = 3V 1.0 1.3 mA (max)

Digital Supply Current, Continuously

Converting (Single Data Output Mode)

fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100

kHz, VD = 5V, DUAL = 0V 0.9 1.2 mA (max)

fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100

kHz, VD = 3V, DUAL = 0V 0.6 0.7 mA (max)

IVREF

(Conv)

Reference Current, Continuously

Converting (Dual Data Output Mode)

fSCLK = 16 MHz, fS = 1 MSPS, VREF =

2.5V, DUAL = VD

90 105 µA (max)

Reference Current, Continuously

Converting (Single Data Output Mode)

fSCLK = 16 MHz, fS = 500 kSPS, VREF =

2.5V, DUAL = 0V 45 60 µA (max)

IVA (PD) Analog Supply Current, Power Down

Mode (CS high)

fSCLK = 16 MHz, VA = 5.0V 10 µA

fSCLK = 0, VA = 5.0V (Note 8) 0.5 1µA (max)

IVD (PD) Digital Supply Current, Power Down

Mode (CS high)

fSCLK = 16 MHz, VD = 5.0V 10 µA

fSCLK = 0 (Note 8) 0.1 0.2 µA (max)

IVREF (PD) Reference Current, Power Down Mode

(CS high)

fSCLK = 16 MHz 0.05 µA

fSCLK = 0 (Note 8) 0.05 0.1 µA (max)

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ADC122S706

Symbol Parameter Conditions Typical Limits Units

(Note 7)

PWR

(Conv)

Power Consumption, Continuously

Converting (Dual Data Output Mode)

fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100

kHz, VA = VD = 5V, VREF = 2.5V, DUAL

= VD

25 31.3 mW (max)

fSCLK = 16 MHz, fS = 1 MSPS, fIN = 100

kHz, VA = 5V, VD = 3V, VREF = 2.5V,

DUAL = VD

20 25.2 mW (max)

Power Consumption, Continuously

Converting (Single Data Output Mode)

fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100

kHz, VA = VD = 5V, VREF = 2.5V, DUAL

= 0V

13.6 20.6 mW (max)

fSCLK = 16 MHz, fS = 500 kSPS, fIN = 100

kHz, VA = 5V, VD = 3V, VREF = 2.5V,

DUAL = 0V

10.9 16.8 mW (max)

PWR

(PD)

Power Consumption, Power Down Mode

(CS high)

fSCLK = 16 MHz, VA = VD = 5.0V, VREF =

2.5V 100 µW

fSCLK = 0, VA = VD = 5.0V, VREF = 2.5V 3.1 6.5 µW (max)

PSRR Power Supply Rejection Ratio See the Specification Definitions for the

test condition −85 dB

AC ELECTRICAL CHARACTERISTICS

fSCLK Maximum Clock Frequency 20 16 MHz (min)

fSCLK Minimum Clock Frequency 0.8 8MHz (max)

fSMaximum Sample Rate 1.25 1MSPS (min)

tACQ Track/Hold Acquisition Time 3SCLK cycles

tCONV Conversion Time 12 SCLK cycles

tAD Aperture Delay 6 ns

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ADC122S706

ADC122S706 Timing Specifications (Note 8)

The following specifications apply for VA = +4.5V to 5.5V, VD = +2.7V to VA, VREF = 2.5V, fSCLK = 8 MHz to 16 MHz, CL = 25 pF,

unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

tCSSU CS Setup Time prior to an SCLK rising edge

VD = +2.7V to 3.6V 511 ns (min)

1/ fSCLK 1/ fSCLK - 3 ns (max)

VD = +4.5V to 5.5V 47ns (min)

1/ fSCLK 1/ fSCLK - 3 ns (max)

tEN DOUT Enable Time after the falling edge of CS VD = +2.7V to 3.6V 22 39 ns (max)

VD = +4.5V to 5.5V 920 ns (max)

tDH DOUT Hold time after an SCLK Falling edge 9 6ns (min)

tDA DOUT Access time after an SCLK Falling edge VD = +2.7V to 3.6V 24 39 ns (max)

VD = +4.5V to 5.5V 20 26 ns (max)

tDIS

DOUT Disable Time after the rising edge of CS

(Note 10) 10 20 ns (max)

tCH SCLK High Time 25 ns (min)

tCL SCLK Low Time 25 ns (min)

trDOUT Rise Time 7 ns

tfDOUT Fall Time 7 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC122S706 is operated in a severe fault condition (e.g. when input or output pins

are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge

device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 9: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/16.

Note 10: tDIS is the time for DOUT to change 10%.

Note 11: The digital input pin, DUAL, has a leakage current of ±5 µA.

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ADC122S706

Timing Diagrams

30017101

FIGURE 1. ADC122S706 Single Conversion Timing Diagram (DUAL Data Output Mode)

30017142

FIGURE 2. ADC122S706 Single Conversion Timing Diagram (SINGLE Data Output Mode)

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ADC122S706

30017104

FIGURE 3. ADC122S706 Continuous Conversion Timing Diagram (DUAL Data Output Mode)

30017106

FIGURE 4. DOUT Rise and Fall Times

30017111

FIGURE 5. DOUT Hold and Access Times

30017110

FIGURE 6. Valid CS Assertion Times

30017112

FIGURE 7. Voltage Waveform for tDIS

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ADC122S706

Specification Definitions

APERTURE DELAY is the time between the fourth falling

edge of SCLK and the time when the input signal is acquired

or held for conversion.

COMMON MODE REJECTION RATIO (CMRR) is a measure

of how well in-phase signals common to both input pins are

rejected.

To calculate CMRR, the change in output offset is measured

while the common mode input voltage is changed from 2V to

3V.

CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD − 1.76) /

6.02 and says that the converter is equivalent to a perfect

ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC122S706 is guaranteed not

to have any missing codes.

NEGATIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions from negative full scale to the next code and −VREF + 0.5

LSB.

NEGATIVE GAIN ERROR is the difference between the neg-

ative full-scale error and the offset error.

OFFSET ERROR is the difference between the differential

input voltage at which the output code transitions from code

000h to 001h and 1/2 LSB.

POSITIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions to positive full scale and VREF minus 1.5 LSB.

POSITIVE GAIN ERROR is the difference between the pos-

itive full-scale error and the offset error.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well a change in supply voltage is rejected. PSRR is

calculated from the ratio of the change in offset error for a

given change in supply voltage, expressed in dB. For the AD-

C122S706, VA is changed from 4.5V to 5.5V.

PSRR = 20 LOG (ΔOffset / ΔVA)

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component,

where a spurious spectral component is any signal present in

the output spectrum that is not present at the input and may

or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first five harmonic components at the output

to the rms level of the input signal frequency as seen at the

output, expressed in dB. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion.

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

DNL - 1 MSPS

30017121

INL - 1 MSPS

30017122

DNL vs. VA

30017123

INL vs. VA

30017124

DNL vs. VREF

30017118

INL vs. VREF

30017119

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

DNL vs. SCLK FREQUENCY

30017125

INL vs. SCLK FREQUENCY

30017126

DNL vs. TEMPERATURE

30017129

INL vs. TEMPERATURE

30017130

SINAD vs. VA

30017133

THD vs. VA

30017132

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

SINAD vs. VREF

30017137

THD vs. VREF

30017136

SINAD vs. SCLK FREQUENCY

30017141

THD vs. SCLK FREQUENCY

30017140

SINAD vs. INPUT FREQUENCY

30017149

THD vs. INPUT FREQUENCY

30017148

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

SINAD vs. TEMPERATURE

30017172

THD vs. TEMPERATURE

30017171

VA CURRENT vs. VA

30017174

VA CURRENT vs. SCLK FREQ

30017155

VA CURRENT vs. TEMPERATURE

30017154

VREF CURRENT vs. SCLK FREQ

30017152

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

VREF CURRENT vs. TEMP

30017151

VD CURRENT vs. SCLK FREQ

30017156

VD CURRENT vs. TEMP

30017158

VA CURRENT vs. VA (SINGLE DOUT)

30017175

VA CURRENT vs. SCLK FREQ (SINGLE DOUT)

30017176

VA CURRENT vs. TEMP (SINGLE DOUT)

30017177

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ADC122S706

Typical Performance Characteristics VA = VD = 5.0V, VREF = 2.5V, TA = +25°C, fSAMPLE = 1 MSPS,

fSCLK = 16 MHz, DUAL = VD, fIN = 100 kHz unless otherwise stated.

VREF CURRENT vs. SCLK (SINGLE DOUT)

30017178

VREF CURRENT vs. TEMP (SINGLE DOUT)

30017179

VD CURRENT vs. SCLK (SINGLE DOUT)

30017157

VD CURRENT vs. TEMP (SINGLE DOUT)

30017159

CMRR vs. CM RIPPLE FREQ

30017173

SPECTRAL RESPONSE - 1 MSPS

30017114

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ADC122S706

Functional Description

The ADC122S706 is a dual 12-bit, simultaneous sampling

Analog-to-Digital (A/D) converter. The converter is based on

a successive-approximation register (SAR) architecture

where the differential nature of the analog inputs is main-

tained from the internal track-and-hold circuits throughout the

A/D converter. The analog inputs on both channels are sam-

pled simultaneously to preserve their relative phase informa-

tion to each other. The architecture and process allow the

ADC122S706 to acquire and convert dual analog signals at

sample rates up to 1 MSPS while consuming very little power.

The ADC122S706 operates from independent analog and

digital supplies. The analog supply (VA) can range from 4.5V

to 5.5V and the digital supply (VD) can range from 2.7V to

VA. The ADC122S706 utilizes an external reference. The ex-

ternal reference can be any voltage between 1V and VA. The

value of the reference voltage determines the range of the

analog input, while the reference input current depends upon

the conversion rate.

Analog inputs are presented at the inputs of Channel A and

Channel B. Upon initiation of a conversion, the differential in-

put at these pins is sampled on the internal capacitor array.

The inputs are disconnected from the internal circuitry while

a conversion is in progress.

The ADC122S706 requires an external clock. The duty cycle

of the clock is essentially unimportant, provided the minimum

clock high and low times are met. The minimum clock fre-

quency is set by internal capacitor leakage. Each conversion

requires 16 SCLK cycles to complete. If less than 12 bits of

conversion data are required, CS can be brought high at any

point during the conversion.

The ADC122S706 offers dual high-speed serial data outputs

that are binary 2's complement and are compatible with sev-

eral standards, such as SPI™, QSPI™, MICROWIRE™, and

many common DSP serial interfaces. Channel A's conversion

result is outputted on DOUTA while Channel B's conversion re-

sult is outputted on DOUTB. This feature makes the AD-

C122S706 an excellent replacement for systems using two

distinct ADCs in a simultaneous sampling application. The

serial clock (SCLK) and chip select bar (CS) are shared by

both channels. The digital conversion of channel A and B is

clocked out by the SCLK input and is provided serially, most

significant bit first, at DOUTA and DOUTB, respectively. The

digital data that is provided at DOUTA and DOUTB is that of the

conversion currently in progress. With CS held low after the

conversion is complete, the ADC122S706 continuously con-

verts the analog inputs. For lower power consumption, a

single serial data output mode is externally selectable. This

feature makes the ADC122S706 an excellent replacement for

two independent ADCs that are part of a daisy chain config-

uration.

1.0 REFERENCE INPUT

The externally supplied reference voltage sets the analog in-

put range. The ADC122S706 will operate with a reference

voltage in the range of 1V to VA.

Operation with a reference voltage below 1V is also possible

with slightly diminished performance. As the reference volt-

age (VREF) is reduced, the range of acceptable analog input

voltages is reduced. Assuming a proper common-mode input

voltage, the differential peak-to-peak input range is limited to

twice VREF. See Section 2.3 for more details. Reducing the

value of VREF also reduces the size of the least significant bit

(LSB). The size of one LSB is equal to twice the reference

voltage divided by 4096. When the LSB size goes below the

noise floor of the ADC122S706, the noise will span an in-

creasing number of codes and overall performance will suffer.

For example, dynamic signals will have their SNR degrade,

while D.C. measurements will have their code uncertainty in-

crease. Since the noise is Gaussian in nature, the effects of

this noise can be reduced by averaging the results of a num-

ber of consecutive conversions.

Additionally, since offset and gain errors are specified in LSB,

any offset and/or gain errors inherent in the A/D converter will

increase in terms of LSB size as the reference voltage is re-

duced.

The reference input and the analog inputs are connected to

the capacitor array through a switch matrix when the input is

sampled. Hence, the current requirements at the reference

and at the analog inputs are a series of transient spikes that

occur at a frequency dependent on the operating sample rate

of the ADC122S706.

The reference current changes only slightly with temperature.

See the curves, “Reference Current vs. SCLK Frequency”

and “Reference Current vs. Temperature” in the Typical Per-

formance Curves section for additional details.

2.0 ANALOG SIGNAL INPUTS

The ADC122S706 has dual differential inputs where the ef-

fective input voltage that is digitized is CHA+ minus CHA−

(DIFFINA) and CHB+ minus CHB− (DIFFINB). As is the case

with all differential input A/D converters, operation with a fully

differential input signal or voltage will provide better perfor-

mance than with a single-ended input. However, the

ADC122S706 can be presented with a single-ended input.

The current required to recharge the input sampling capacitor

will cause voltage spikes at the + and − inputs. Do not try to

filter out these noise spikes. Rather, ensure that the transient

settles out during the acquisition period (three SCLK cycles

after the fall of CS).

2.1 Differential Input Operation

With a fully differential input voltage or signal, a positive full

scale output code (0111 1111 1111b or 7FFh) will be obtained

when DIFFINA or DIFFINB is greater than or equal to VREF −

1.5 LSB. A negative full scale code (1000 0000 0000b or

800h) will be obtained when DIFFINA or DIFFINB is greater

than or equal to −VREF + 0.5 LSB. This ignores gain, offset

and linearity errors, which will affect the exact differential input

voltage that will determine any given output code. Figure 8

shows the ADC122S706 being driven by a full-scale differen-

tial source.

30017180

FIGURE 8. Differential Input

17 www.national.com

ADC122S706

2.2 Single-Ended Input Operation

For single-ended operation, the non-inverting inputs of the

ADC122S706 can be driven with a signal that has a maximum

to minimum value range that is equal to or less than twice the

reference voltage. The inverting inputs should be biased at a

stable voltage that is halfway between these maximum and

minimum values. In order to utilize the entire dynamic range

of the ADC122S706, the reference voltage is limited at VA /

2. This allows the non-inverting inputs the maximum swing

range of ground to VA. Figure 9 shows the ADC122S706 be-

ing driven by a full-scale single-ended source.

30017181

FIGURE 9. Single-Ended Input

Since the design of the ADC122S706 is optimized for a dif-

ferential input, the performance degrades slightly when driven

with a single-ended input. Linearity characteristics such as

INL and DNL typically degrade by 0.1 LSB and dynamic char-

acteristics such as SINAD typically degrades by 2 dB. Note

that single-ended operation should only be used if the perfor-

mance degradation (compared with differential operation) is

acceptable.

2.3 Input Common Mode Voltage

The allowable input common mode voltage (VCM) range de-

pends upon the supply and reference voltages used for the

ADC122S706. The ranges of VCM are depicted in Figure 10

and Figure 11. Equations for calculating the minimum and

maximum common mode voltages for differential and single-

ended operation are shown in Table 1.

30017161

FIGURE 10. VCM range for Differential Input operation

30017162

FIGURE 11. VCM range for single-ended operation

TABLE 1. Allowable VCM Range

Input Signal Minimum VCM Maximum VCM

Differential VREF / 2 VA − VREF / 2

Single-Ended VREF VA − VREF

3.0 SERIAL DIGITAL INTERFACE

The ADC122S706 communicates via a synchronous serial

interface as shown in the Timing Diagram section. CS, chip

select, initiates conversions and frames the serial data trans-

fers. SCLK (serial clock) controls both the conversion process

and the timing of the serial data. DOUTA and DOUTB are the

serial data output pins, where the conversion results of Chan-

nel A and Channel B are sent as serial data streams, MSB

first.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. The ADC122S706's data output pins

are in a high impedance state when CS is high and are active

when CS is low; thus CS acts as an output enable. A timing

diagram for a single conversion is shown in Figure 1.

During the first three cycles of SCLK, the ADC122S706 is in

acquisition mode (tACQ), tracking the input voltage. For the

next twelve SCLK cycles (tCONV), the conversion is accom-

plished and the data is clocked out. SCLK falling edges one

through four clock out leading zeros while falling edges five

through sixteen clock out the conversion result, MSB first. If

there is more than one conversion in a frame (continuous

conversion mode), the ADC122S706 will re-enter acquisition

mode on the falling edge of SCLK after the N*16th rising edge

of SCLK and re-enter the conversion mode on the N*16+4th

falling edge of SCLK as shown in Figure 3. "N" is an integer

value.

The ADC122S706 can enter acquisition mode under three

different conditions. The first condition involves CS going low

(asserted) with SCLK high. In this case, the ADC122S706

enters acquisition mode on the first falling edge of SCLK after

CS is asserted. In the second condition, CS goes low with

SCLK low. Under this condition, the ADC122S706 automati-

cally enters acquisition mode and the falling edge of CS is

seen as the first falling edge of SCLK. In the third condition,

CS and SCLK go low simultaneously and the ADC122S706

enters acquisition mode. While there is no timing restriction

with respect to the falling edges of CS and the falling edge of

SCLK, see Figure 6 for setup and hold time requirements for

the falling edge of CS with respect to the rising edge of SCLK.

www.national.com 18

ADC122S706

3.1 CS Input

The CS (chip select bar) is an active low input that is TTL and

CMOS compatible. The ADC122S706 is in conversion mode

when CS is low and power-down mode when CS is high. As

a result, CS frames the conversion window. The falling edge

of CS marks the beginning of a conversion and the rising edge

of CS marks the end of a conversion window. Multiple con-

versions can occur within a given conversion frame with each

conversion requiring sixteen SCLK cycles. This is referred to

as continuous conversion mode and is shown in Figure 3 of

the Timing Diagram section.

Proper operation requires that the fall of CS not occur simul-

taneously with a rising edge of SCLK. If the fall of CS occurs

during the rising edge of SCLK, the data might be clocked out

one bit early. Whether or not the data is clocked out early

depends upon how close the CS transition is to the SCLK

transition, the device temperature, and characteristics of the

individual device. To ensure that the MSB is always clocked

out at a given time (the 5th falling edge of SCLK), it is essential

that the fall of CS always meet the timing requirement speci-

fied in the Timing Specification table.

3.2 SCLK Input

The SCLK (serial clock) serves two purposes in the AD-

C122S706. It is used by the ADC as the conversion clock and

it is used as the serial clock to output the conversion results.

This SCLK input is CMOS compatible. Internal settling time

requirements limit the maximum clock frequency while inter-

nal capacitor leakage limits the minimum clock frequency.

The ADC122S706 offers guaranteed performance with the

clock rates indicated in the electrical table.

3.3 Data Output(s)

The ADC122S706 enables system designers two options for

receiving converted data from the ADC122S706. Data can be

received from separate data output pins (DOUTA and DOUTB)

or from a single data output line. These options are controlled

by the digital input pin DUAL. With the DUAL pin set to a logic

high level, the dual high-speed serial outputs are enabled.

Channel A's conversion result is outputted on DOUTA while

Channel B's conversion result is outputted on DOUTB. With the

DUAL pin set to a logic low level, the conversion result of

Channel A and Channel B is outputted on DOUTA, with the

result of Channel A being outputted before the result of Chan-

nel B. The DOUTB pin is in a high impedance state during this

condition. See Figure 1 and Figure 2 in the Timing Diagram

section for more details on DUAL and SINGLE DOUT mode.

The output data format of the ADC122S706 is two’s comple-

ment, as shown in Table 2. This table indicates the ideal

output code for the given input voltage and does not include

the effects of offset, gain error, linearity errors, or noise. Each

data bit is output on the falling edge of SCLK.

TABLE 2. Ideal Output Code vs. Input Voltage

Analog Input

(+IN) − (−IN)

2's

Complement

Binary Output

2's

Comp.

Hex Code

2's

Comp.

Dec Code

VREF − 1.5 LSB 0111 1111 1111 7FF 2047

+ 0.5 LSB 0000 0000 0001 001 1

− 0.5 LSB 0000 0000 0000 000 0

0V − 1.5 LSB 1111 1111 1111 FFF −1

−VREF + 0.5 LSB 1000 0000 0000 800 −2048

While data is output on the falling edges of SCLK, receiving

systems have the option of capturing the data on the subse-

quent rising or falling edge of SCLK. The maximum specifi-

cation for tDA (DOUT access time after an SCLK falling edge)

is provided for two power supply ranges. If the system is op-

erating at the maximum clock frequency of 16MHz and a VD

supply voltage of 3V, it would be necessary for the receiver

to capture data on the subsequent falling edge of SCLK in

order to guarantee performance over the entire temperature

range. Operating at a VD supply voltage of 5V or an SCLK

frequency less than 10MHz allows data to be captured on ei-

ther edge of SCLK. If a receiving system is going to capture

data on the subsequent falling edge of SCLK, it is important

to make sure that the minimum hold time after an SCLK falling

edge (tDH) is acceptable. See Figure 5 for DOUT hold and ac-

cess times.

DOUT is enabled on the falling edge of CS and disabled on the

rising edge of CS. If CS is raised prior to the 16th falling edge

of SCLK, the current conversion is aborted and DOUT will go

into its high impedance state. A new conversion will begin

when CS is taken LOW.

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC122S706:

−40°C ≤ TA ≤ +105°C

+4.5V ≤ VA ≤ +5.5V

+2.7V ≤ VD ≤ VA

1V ≤ VREF ≤ VA

8 MHz ≤ fSCLK ≤ 16 MHz

VCM: See Section 2.3

4.0 POWER CONSUMPTION

The architecture, design, and fabrication process allow the

ADC122S706 to operate at conversion rates up to 1 MSPS

while consuming very little power. The ADC122S706 con-

sumes the least amount of power while operating in power

down mode. For applications where power consumption is

critical, the ADC122S706 should be operated in power down

mode as often as the application will tolerate. To further re-

duce power consumption, stop the SCLK while CS is high.

4.1 Short Cycling

Short cycling refers to the process of halting a conversion af-

ter the last needed bit is outputted. Short cycling can be used

to lower the power consumption in those applications that do

not need a full 12-bit resolution, or where an analog signal is

being monitored until some condition occurs. For example, it

may not be necessary to use the full 12-bit resolution of the

ADC122S706 as long as the signal being monitored is within

certain limits. In some circumstances, the conversion could

be terminated after the first few bits. This will lower power

consumption in the converter since the ADC122S706 spends

more time in power down mode and less time in the conver-

sion mode.

Short cycling is accomplished by pulling CS high after the last

required bit is received from the ADC122S706 output. This is

possible because the ADC122S706 places the latest con-

verted data bit on DOUT as it is generated. If only 8-bits of the

conversion result are needed, for example, the conversion

can be terminated by pulling CS high after the 8th bit has been

clocked out.

19 www.national.com

ADC122S706

4.2 Burst Mode Operation

Normal operation of the ADC122S706 requires the SCLK fre-

quency to be sixteen times the sample rate and the CS rate

to be the same as the sample rate. However, in order to min-

imize power consumption in applications requiring sample

rates below 500 kSPS, the ADC122S706 should be run with

an SCLK frequency of 16 MHz and a CS rate as slow as the

system requires. When this is accomplished, the

ADC122S706 is operating in burst mode. The ADC122S706

enters into power down mode at the end of each conversion,

minimizing power consumption. This causes the converter to

spend the longest possible time in power down mode. Since

power consumption scales directly with conversion rate, min-

imizing power consumption requires determining the lowest

conversion rate that will satisfy the requirements of the sys-

tem.

4.3 Single DOUT mode

With the DUAL pin connected to a logic low level, the AD-

C122S706 is operating in single DOUT mode. In single DOUT

mode, the conversion result of Channel A and Channel B are

both output on DOUTA (see Figure 2). Operating in this mode

causes the maximum conversion rate to be reduced to 500k-

SPS while operating with an SCLK frequency of 16MHz. This

is a result of the conversion window changing from 16 clock

cycles to 32 clock cycles to receive the conversion result of

Channel A and Channel B. Since the conversion of Channel

A and Channel B are still performed simultaneously, the AD-

C122S706 still enters a power down state on the 16th falling

edge of SCLK. The increased time spent in power down mode

causes the power consumption of the ADC122S706 to reduce

nearly by a factor of two. See the Power Supply Characteris-

tics Table for more details.

5.0 POWER SUPPLY CONSIDERATIONS AND PCB

LAYOUT

For best performance, care should be taken with the physical

layout of the printed circuit board. This is especially true with

a low reference voltage or when the conversion rate is high.

At high clock rates there is less time for settling, so it is im-

portant that any noise settles out before the conversion be-

gins.

5.1 Analog and Digital Power Supplies

Any ADC architecture is sensitive to spikes on the power sup-

ply, reference, and ground pins. These spikes may originate

from switching power supplies, digital logic, high power de-

vices, and other sources. Power to the ADC122S706 should

be clean and well bypassed. A 0.1 µF ceramic bypass ca-

pacitor and a 1 µF to 10 µF capacitor should be used to

bypass the ADC122S706 supply, with the 0.1 µF capacitor

placed as close to the ADC122S706 package as possible.

Since the ADC122S706 has both an analog and a digital sup-

ply pin, the user has three options. The first option is to tie the

analog and digital supply pins together and power them with

the same power supply. This is the most cost effective way of

powering the ADC122S706 but it is also the least ideal. As

stated previously, noise from the digital supply pin can couple

into the analog supply pin and adversely affect performance.

The other two options involve the user powering the analog

and digital supply pins with separate supply voltages. These

supply voltages can have the same amplitude or they can be

different. The only design constraint is that the digital supply

voltage be less than the analog supply voltage. This is not

usually a problem since many applications prefer a digital in-

terface of 3V while operating the analog section of the AD-

C122S706 at 5V. Operating the digital supply pin at 3V as

apposed to 5V offers two advantages. It lowers the power

consumption of the ADC122S706 and it decreases the noise

created by charging and discharging the capacitance of the

digital interface pins.

5.2 Voltage Reference

The reference source must have a low output impedance and

needs to be bypassed with a minimum capacitor value of 0.1

µF. A larger capacitor value of 1 µF to 10 µF placed in parallel

with the 0.1 µF is preferred. While the ADC122S706 draws

very little current from the reference on average, there are

higher instantaneous current spikes at the reference input.

The reference input of the ADC122S706, like all A/D convert-

ers, does not reject noise or voltage variations. Keep this in

mind if the reference voltage is derived from the power supply.

Any noise and/or ripple from the supply that is not rejected by

the external reference circuitry will appear in the digital re-

sults. The use of an active reference source is recommended.

The LM4040 and LM4050 shunt reference families and the

LM4132 and LM4140 series reference families are excellent

choices for a reference source.

5.3 PCB Layout

Capacitive coupling between the noisy digital circuitry and the

sensitive analog circuitry can lead to poor performance. The

solution is to keep the analog circuitry separated from the

digital circuitry and the clock line as short as possible. Digital

circuits create substantial supply and ground current tran-

sients. The logic noise generated could have significant im-

pact upon system noise performance. To avoid performance

degradation of the ADC122S706 due to supply noise, avoid

using the same supply for the VA and VREF of the AD-

C122S706 that is used for digital circuity on the board.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated. The analog in-

put should be isolated from noisy signal traces to avoid cou-

pling of spurious signals into the input. Any external

component (e.g., a filter capacitor) connected between the

converter's input pins and ground or to the reference input pin

and ground should be connected to a very clean point in the

ground plane.

A single, uniform ground plane and the use of split power

planes are recommended. The power planes should be lo-

cated within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry and I/

O lines should be placed over the digital power plane. Fur-

thermore, the GND pin on the ADC122S706 and all the

components in the reference circuitry and input signal chain

that are connected to ground should be connected to the

ground plane at a quiet point. Avoid connecting these points

too close to the ground point of a microprocessor, microcon-

troller, digital signal processor, or other high power digital

device.

www.national.com 20

ADC122S706

6.0 APPLICATION CIRCUITS

The following figures are examples of the ADC122S706 in

typical application circuits. These circuits are basic and will

generally require modification for specific circumstances.

6.1 Data Acquisition

Figure 12 shows a basic low cost, low power data acquisition

circuit. The analog and digital supply pins are powered by the

system +5V supply and the 2.5V reference voltage is gener-

ated by the LM4040-2.5 shunt reference.

30017134

FIGURE 12. Low cost, low power Data Acquisition

System

6.2 Current Sensing Application

Figure 13 shows an example of interfacing a pair of current

transducers to the ADC122S706. The current transducers

convert an input current into a voltage that is converted by the

ADC. Since the output voltage of the current transducers are

single-ended and centered around a common-mode voltage

of 2.5V, the ADC122S706 is configured with the output of the

transducer driving the non-inverting inputs and the common-

mode output voltage of the transducer driving the inverting

input. The output of the transducer has an output range of ±2V

around the common-mode voltage of 2.5V. As a result, a se-

ries reference voltage of 2.0V is connected to the AD-

C122S706. This will allow all of the codes of the ADC122S706

to be available for the application. This configuration of the

ADC122S706 is referred to as a single-ended application of

a differential ADC. All of the elements in the application are

conveniently powered by the same +5V power supply, keep-

ing circuit complexity and cost to a minimum.

30017138

FIGURE 13. Interfacing the ADC122S706 to a Current Transducer

21 www.national.com

ADC122S706

6.3 Bridge Sensor Application

Figure 14 shows an example of interfacing the ADC122S706

to a pair of bridge sensors. The application assumes that the

bridge sensors require buffering and amplification to fully uti-

lize the dynamic range of the ADC and thus optimize the

performance of the entire signal path. The amplification stage

for each ADC input consists of a pair of opamps from the

LMP7704. The amplification stage offers the benefit of high

input impedance and potentially high amplification. On the

other hand, it offers no common-mode rejection of noise com-

ing from the bridge sensors. The application circuit assumes

the bridge sensors are powered from the same +5V power

supply voltage as the analog supply pin on the ADC122S706.

This has the benefit of providing the ideal common-mode in-

put voltage for the ADC122S706 while keeping design com-

plexity and cost to a minimum. The LM4132-4.1, a 4.1V series

reference, is used as the reference voltage in the application.

30017135

FIGURE 14. Interfacing the ADC122S706 to Bridge Sensors

www.national.com 22

ADC122S706

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead TSSOP

Order Number ADC122S706CIMM

NS Package Number MTC14

23 www.national.com

ADC122S706

Notes

ADC122S706 Dual 12-Bit, 500 kSPS to 1 MSPS, Simultaneous Sampling A/D Converter

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