D17606BG100V - Renesas Electronics

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Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

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April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.

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of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.

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4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

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and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by

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8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation

characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or

damages arising out of the use of Re nesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

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(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.

SH7606 Group

Hardware Manual

User’s Manual

Rev.4.00 2007.09

Renesas 32-Bit RISC

Microcomputer

SuperH™ RISC engine Family /

SH7606 Series

SH7606 HD6417606

Rev. 4.00 Sep. 13, 2007 Page ii of xxvi

Rev. 4.00 Sep. 13, 2007 Page iii of xxvi

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

Renesas products for their use. Renesas neither makes warranties or representations with respect to the

accuracy or completeness of the information contained in this document nor grants any license to any

intellectual property rights or any other rights of Renesas or any third party with respect to the information in

this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising

out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,

programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military

applications such as the development of weapons of mass destruction or for the purpose of any other military

use. When exporting the products or technology described herein, you should follow the applicable export

control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and

application circuit examples, is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas products listed in this

document, please confirm the latest product information with a Renesas sales office. Also, please pay regular

and careful attention to additional and different information to be disclosed by Renesas such as that disclosed

through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas

assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information

included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in

light of the total system before deciding about the applicability of such information to the intended application.

Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any

particular application and specifically disclaims any liability arising out of the application and use of the

information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas

products are not designed, manufactured or tested for applications or otherwise in systems the failure or

malfunction of which may cause a direct threat to human life or create a risk of human injury or which require

especially high quality and reliability such as safety systems, or equipment or systems for transportation and

traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication

transmission. If you are considering the use of our products for such purposes, please contact a Renesas

sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who

elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas

Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect

to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or

damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific

characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use

conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and

injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for

hardware and software including but not limited to redundancy, fire control and malfunction prevention,

appropriate treatment for aging degradation or any other applicable measures. Among others, since the

evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or

system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas

products are attached or affixed, the risk of accident such as swallowing by infants and small children is very

high. You should implement safety measures so that Renesas products may not be easily detached from your

products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written

approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this

document, Renesas semiconductor products, or if you have any other inquiries.

Notes regarding these materials

Rev. 4.00 Sep. 13, 2007 Page iv of xxvi

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

they are used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where the states are

undefined, the register settings and the output state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 4.00 Sep. 13, 2007 Page v of xxvi

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each

section includes notes in relation to the descriptions given, and usage notes are given, as required,

as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see the actual locations in this

manual.

11. Index

Rev. 4.00 Sep. 13, 2007 Page vi of xxvi

Preface

The SH7606 Group RISC (Reduced Instruction Set Computer) microcomputers include a Renesas

Technology-original RISC CPU as its core, and the peripheral functions required to configure a

system.

Target Users: This manual was written for users who will be using the SH7606 in the design of

application systems. Target users are expected to understand the fundamentals of

electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the SH7606 to the target users.

Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the

instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the SH-1/SH-2/SH-DSP Software Manual.

• In order to understand the details of a register when its name is known

The addresses, bits, and initial values of the registers are summarized in section 18, List of

Registers.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial

communication interface, is implemented on more than one

channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order: The MSB is on the left and the LSB is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.

Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.renesas.com

Rev. 4.00 Sep. 13, 2007 Page vii of xxvi

SH7606 Group manuals:

Document Title Document No.

SH7606 Group Hardware Manual This manual

SH-1/SH-2/SH-DSP Software Manual REJ09B0171

User's manuals for development tools:

Document Title Document No.

SuperHTM RISC engine C/C++ Compiler, Assembler, Optimizing Linkage

Editor User's Manual

REJ10B0152

SuperH RISC engine High-performance Embedded Workshop 3 User's

Manual

REJ10B0025

SuperH RISC engine High-performance Embedded Workshop 3 Tutorial REJ10B0023

Application note:

Document Title Document No.

SuperH RISC engine C/C++ Compiler REJ05B0463

All trademarks and registered trademarks are the property of their respective owners.

Rev. 4.00 Sep. 13, 2007 Page viii of xxvi

Contents

Section 1 Overview ...............................................................................................1

1.1 Features.................................................................................................................................. 1

1.2 Block Diagram....................................................................................................................... 5

1.3 Pin Assignments .................................................................................................................... 6

1.4 Pin Functions ......................................................................................................................... 7

Section 2 CPU .....................................................................................................19

2.1 Features................................................................................................................................ 19

2.2 Register Configuration......................................................................................................... 19

2.2.1 General Registers (Rn)............................................................................................ 21

2.2.2 Control Registers .................................................................................................... 21

2.2.3 System Registers..................................................................................................... 23

2.2.4 Initial Values of Registers....................................................................................... 23

2.3 Data Formats........................................................................................................................ 24

2.3.1 Register Data Format.............................................................................................. 24

2.3.2 Memory Data Formats............................................................................................ 24

2.3.3 Immediate Data Formats......................................................................................... 25

2.4 Features of Instructions........................................................................................................25

2.4.1 RISC Type .............................................................................................................. 25

2.4.2 Addressing Modes .................................................................................................. 28

2.4.3 Instruction Formats................................................................................................. 31

2.5 Instruction Set...................................................................................................................... 35

2.5.1 Instruction Set by Type........................................................................................... 35

2.6 Processing States.................................................................................................................. 48

2.6.1 State Transition....................................................................................................... 48

Section 3 Cache ...................................................................................................51

3.1 Features................................................................................................................................ 51

3.1.1 Cache Structure....................................................................................................... 51

3.1.2 Divided Areas and Cache ....................................................................................... 53

3.2 Register Descriptions...........................................................................................................54

3.2.1 Cache Control Register 1 (CCR1) .......................................................................... 54

3.2.2 Cache Control Register 3 (CCR3) .......................................................................... 55

3.3 Operation ............................................................................................................................. 55

3.3.1 Searching Cache ..................................................................................................... 55

3.3.2 Read Access............................................................................................................ 56

Rev. 4.00 Sep. 13, 2007 Page ix of xxvi

3.3.3 Write Access........................................................................................................... 57

3.3.4 Write-Back Buffer .................................................................................................. 57

3.3.5 Coherency of Cache and External Memory............................................................ 58

3.4 Memory-Mapped Cache ...................................................................................................... 58

3.4.1 Address Array......................................................................................................... 58

3.4.2 Data Array .............................................................................................................. 59

3.4.3 Usage Examples...................................................................................................... 61

Section 4 U Memory............................................................................................63

4.1 Features................................................................................................................................ 63

Section 5 Exception Handling .............................................................................65

5.1 Overview.............................................................................................................................. 65

5.1.1 Types of Exception Handling and Priority.............................................................. 65

5.1.2 Exception Handling Operations.............................................................................. 66

5.1.3 Exception Handling Vector Table........................................................................... 67

5.2 Resets................................................................................................................................... 69

5.2.1 Types of Resets....................................................................................................... 69

5.2.2 Power-On Reset ...................................................................................................... 69

5.2.3 H-UDI Reset ........................................................................................................... 70

5.3 Address Errors ..................................................................................................................... 71

5.3.1 Address Error Sources ............................................................................................ 71

5.3.2 Address Error Exception Source............................................................................. 71

5.4 Interrupts.............................................................................................................................. 72

5.4.1 Interrupt Sources..................................................................................................... 72

5.4.2 Interrupt Priority ..................................................................................................... 72

5.4.3 Interrupt Exception Handling ................................................................................. 73

5.5 Exceptions Triggered by Instructions .................................................................................. 74

5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 74

5.5.2 Trap Instructions..................................................................................................... 74

5.5.3 Illegal Slot Instructions........................................................................................... 75

5.5.4 General Illegal Instructions..................................................................................... 75

5.6 Cases When Exceptions are Accepted ................................................................................. 76

5.7 Stack States after Exception Handling Ends........................................................................ 77

5.8 Usage Notes ......................................................................................................................... 79

5.8.1 Value of Stack Pointer (SP) .................................................................................... 79

5.8.2 Value of Vector Base Register (VBR).................................................................... 79

5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling.......... 79

5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 79

Rev. 4.00 Sep. 13, 2007 Page x of xxvi

Section 6 Interrupt Controller (INTC).................................................................81

6.1 Features................................................................................................................................ 81

6.2 Input/Output Pins................................................................................................................. 83

6.3 Register Descriptions...........................................................................................................83

6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 84

6.3.2 IRQ Control Register (IRQCR) .............................................................................. 84

6.3.3 IRQ Status Register (IRQSR) ................................................................................. 88

6.3.4 Interrupt Priority Registers A to E (IPRA to IPRE)................................................ 94

6.4 Interrupt Sources.................................................................................................................. 98

6.4.1 External Interrupts .................................................................................................. 98

6.4.2 On-Chip Peripheral Module Interrupts ................................................................... 99

6.4.3 User Break Interrupt ............................................................................................... 99

6.4.4 H-UDI Interrupt.................................................................................................... 100

6.5 Interrupt Exception Handling Vector Table....................................................................... 100

6.6 Interrupt Operation ............................................................................................................ 102

6.6.1 Interrupt Sequence ................................................................................................ 102

6.6.2 Stack after Interrupt Exception Handling ............................................................. 104

6.7 Interrupt Response Time.................................................................................................... 104

Section 7 Bus State Controller (BSC) .............................................................107

7.1 Features.............................................................................................................................. 107

7.2 Input/Output Pins...............................................................................................................110

7.3 Area Overview...................................................................................................................111

7.3.1 Area Division........................................................................................................ 111

7.3.2 Shadow Area......................................................................................................... 111

7.3.3 Address Map......................................................................................................... 112

7.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 114

7.3.5 Data Alignment..................................................................................................... 114

7.4 Register Descriptions......................................................................................................... 115

7.4.1 Common Control Register (CMNCR) .................................................................. 116

7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 3, 4, 5B, 6B)....................... 117

7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) .................... 122

7.4.4 SDRAM Control Register (SDCR)....................................................................... 138

7.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 139

7.4.6 Refresh Timer Counter (RTCNT)......................................................................... 141

7.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 142

7.5 Operation ........................................................................................................................... 143

7.5.1 Endian/Access Size and Data Alignment.............................................................. 143

7.5.2 Normal Space Interface ........................................................................................ 148

7.5.3 Access Wait Control ............................................................................................. 152

Rev. 4.00 Sep. 13, 2007 Page xi of xxvi

7.5.4 Extension of Chip Select (CSn) Assertion Period................................................. 153

7.5.5 SDRAM Interface................................................................................................. 155

7.5.6 Byte-Selection SRAM Interface ........................................................................... 180

7.5.7 PCMCIA Interface................................................................................................ 184

7.5.8 Wait between Access Cycles ................................................................................ 190

7.5.9 Others.................................................................................................................... 190

Section 8 Clock Pulse Generator (CPG)............................................................193

8.1 Features.............................................................................................................................. 193

8.2 Input/Output Pins...............................................................................................................196

8.3 Clock Operating Modes ..................................................................................................... 196

8.4 Register Descriptions ......................................................................................................... 198

8.4.1 Frequency Control Register (FRQCR) ................................................................. 198

8.5 Changing Frequency .......................................................................................................... 200

8.5.1 Changing Multiplication Ratio ............................................................................. 200

8.5.2 Changing Division Ratio....................................................................................... 201

8.5.3 Changing Clock Operating Mode ......................................................................... 202

8.6 Notes on Board Design ...................................................................................................... 203

Section 9 Watchdog Timer (WDT)....................................................................205

9.1 Features.............................................................................................................................. 205

9.2 Register Descriptions ......................................................................................................... 206

9.2.1 Watchdog Timer Counter (WTCNT).................................................................... 206

9.2.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 207

9.2.3 Notes on Register Access...................................................................................... 209

9.3 WDT Operation ................................................................................................................. 210

9.3.1 Canceling Software Standbys ............................................................................... 210

9.3.2 Changing Frequency............................................................................................. 211

9.3.3 Using Watchdog Timer Mode .............................................................................. 211

9.3.4 Using Interval Timer Mode .................................................................................. 212

9.4 Usage Note......................................................................................................................... 212

Section 10 Power-Down Modes ........................................................................213

10.1 Features.............................................................................................................................. 213

10.1.1 Types of Power-Down Modes .............................................................................. 213

10.2 Input/Output Pins...............................................................................................................215

10.3 Register Descriptions ......................................................................................................... 215

10.3.1 Standby Control Register (STBCR)...................................................................... 216

10.3.2 Standby Control Register 2 (STBCR2)................................................................. 217

10.3.3 Standby Control Register 3 (STBCR3)................................................................. 218

Rev. 4.00 Sep. 13, 2007 Page xii of xxvi

10.3.4 Standby Control Register 4 (STBCR4)................................................................. 219

10.4 Sleep Mode ........................................................................................................................ 220

10.4.1 Transition to Sleep Mode...................................................................................... 220

10.4.2 Canceling Sleep Mode.......................................................................................... 220

10.5 Software Standby Mode..................................................................................................... 220

10.5.1 Transition to Software Standby Mode .................................................................. 220

10.5.2 Canceling Software Standby Mode ...................................................................... 222

10.6 Module Standby Mode....................................................................................................... 223

10.6.1 Transition to Module Standby Mode .................................................................... 223

10.6.2 Canceling Module Standby Function.................................................................... 223

Section 11 Compare Match Timer (CMT) ........................................................225

11.1 Features.............................................................................................................................. 225

11.2 Register Descriptions......................................................................................................... 226

11.2.1 Compare Match Timer Start Register (CMSTR).................................................. 226

11.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 227

11.2.3 Compare Match Counter (CMCNT)..................................................................... 228

11.2.4 Compare Match Constant Register (CMCOR) ..................................................... 228

11.3 Operation ........................................................................................................................... 229

11.3.1 Interval Count Operation ...................................................................................... 229

11.3.2 CMCNT Count Timing......................................................................................... 229

11.4 Interrupts............................................................................................................................ 230

11.4.1 Interrupt Sources................................................................................................... 230

11.4.2 Timing of Setting Compare Match Flag ............................................................... 230

11.4.3 Timing of Clearing Compare Match Flag............................................................. 230

11.5 Usage Notes....................................................................................................................... 231

11.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 231

11.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 231

11.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 232

11.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and

CMCOR................................................................................................................ 233

Section 12 Serial Communication Interface with FIFO (SCIF)........................ 235

12.1 Overview............................................................................................................................ 235

12.1.1 Features................................................................................................................. 235

12.2 Pin Configuration...............................................................................................................238

12.3 Register Description .......................................................................................................... 239

12.3.1 Receive Shift Register (SCRSR) .......................................................................... 240

12.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 240

12.3.3 Transmit Shift Register (SCTSR) ......................................................................... 240

Rev. 4.00 Sep. 13, 2007 Page xiii of xxvi

12.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 241

12.3.5 Serial Mode Register (SCSMR)............................................................................ 241

12.3.6 Serial Control Register (SCSCR).......................................................................... 245

12.3.7 Serial Status Register (SCFSR) ............................................................................ 249

12.3.8 Bit Rate Register (SCBRR) .................................................................................. 257

12.3.9 FIFO Control Register (SCFCR) .......................................................................... 263

12.3.10 FIFO Data Count Register (SCFDR).................................................................... 267

12.3.11 Serial Port Register (SCSPTR) ............................................................................. 268

12.3.12 Line Status Register (SCLSR) .............................................................................. 272

12.4 Operation ........................................................................................................................... 273

12.4.1 Overview............................................................................................................... 273

12.4.2 Operation in Asynchronous Mode ........................................................................ 275

12.4.3 Synchronous Mode ............................................................................................... 286

12.5 SCIF Interrupts .................................................................................................................. 294

12.6 Serial Port Register (SCSPTR) and SCIF Pins .................................................................. 295

12.7 Usage Notes ....................................................................................................................... 298

Section 13 Host Interface (HIF).........................................................................301

13.1 Features.............................................................................................................................. 301

13.2 Input/Output Pins...............................................................................................................303

13.3 Parallel Access................................................................................................................... 304

13.3.1 Operation .............................................................................................................. 304

13.3.2 Connection Method............................................................................................... 304

13.4 Register Descriptions ......................................................................................................... 305

13.4.1 HIF Index Register (HIFIDX) .............................................................................. 305

13.4.2 HIF General Status Register (HIFGSR)................................................................ 307

13.4.3 HIF Status/Control Register (HIFSCR) ................................................................ 307

13.4.4 HIF Memory Control Register (HIFMCR)........................................................... 310

13.4.5 HIF Internal Interrupt Control Register (HIFIICR) .............................................. 312

13.4.6 HIF External Interrupt Control Register (HIFEICR) ............................................ 313

13.4.7 HIF Address Register (HIFADR) ......................................................................... 314

13.4.8 HIF Data Register (HIFDATA) ............................................................................ 315

13.4.9 HIF Boot Control Register (HIFBCR).................................................................. 315

13.4.10 HIFDREQ Trigger Register (HIFDTR)................................................................ 316

13.4.11 HIF Bank Interrupt Control Register (HIFBICR)................................................. 317

13.5 Memory Map ..................................................................................................................... 319

13.6 Interface (Basic)................................................................................................................. 320

13.7 Interface (Details) .............................................................................................................. 321

13.7.1 HIFIDX Write/HIFGSR Read .............................................................................. 321

13.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR................... 321

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13.7.3 Consecutive Data Writing to HIFRAM by External Device................................. 322

13.7.4 Consecutive Data Reading from HIFRAM to External Device............................ 322

13.8 External DMAC Interface.................................................................................................. 323

13.9 Interface When External Device Power is Cut Off............................................................ 329

Section 14 Pin Function Controller (PFC) ........................................................333

14.1 Register Descriptions......................................................................................................... 343

14.1.1 Port A IO Register H (PAIORH).......................................................................... 343

14.1.2 Port A Control Register H1 and H2 (PACRH1 and PACRH2) ............................ 344

14.1.3 Port B IO Register L (PBIORL) ........................................................................... 347

14.1.4 Port B Control Register L1 and L2 (PBCRL1 and PBCRL2)............................... 347

14.1.5 Port C IO Register H and L (PCIORH and PCIORL) .......................................... 352

14.1.6 Port D IO Register L (PDIORL)........................................................................... 352

14.1.7 Port D Control Register L2 (PDCRL2) ................................................................ 353

14.1.8 Port E IO Register H and L (PEIORH and PEIORL) ........................................... 355

14.1.9 Port E Control Register H1, H2, L1, and L2 (PECRH1, PECRH2, PECRL1,

and PECRL2)........................................................................................................ 355

Section 15 I/O Ports...........................................................................................363

15.1 Port A................................................................................................................................. 363

15.1.1 Register Description ............................................................................................. 363

15.1.2 Port A Data Register H (PADRH)........................................................................ 363

15.2 Port B................................................................................................................................. 365

15.2.1 Register Description ............................................................................................. 365

15.2.2 Port B Data Register L (PBDRL) ......................................................................... 365

15.3 Port C................................................................................................................................. 367

15.3.1 Register Description ............................................................................................. 368

15.3.2 Port C Data Registers H and L (PCDRH and PCDRL) ........................................ 368

15.4 Port D................................................................................................................................. 370

15.4.1 Register Description ............................................................................................. 370

15.4.2 Port D Data Register L (PDDRL)......................................................................... 370

15.5 Port E ................................................................................................................................. 372

15.5.1 Register Description ............................................................................................. 373

15.5.2 Port E Data Registers H and L (PEDRH and PEDRL)......................................... 373

15.6 Usage Note......................................................................................................................... 375

Section 16 User Break Controller (UBC).......................................................... 377

16.1 Features.............................................................................................................................. 377

16.2 Register Descriptions......................................................................................................... 379

16.2.1 Break Address Register A (BARA)...................................................................... 379

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16.2.2 Break Address Mask Register A (BAMRA)......................................................... 380

16.2.3 Break Bus Cycle Register A (BBRA)................................................................... 380

16.2.4 Break Address Register B (BARB) ...................................................................... 381

16.2.5 Break Address Mask Register B (BAMRB) ......................................................... 382

16.2.6 Break Data Register B (BDRB)............................................................................ 382

16.2.7 Break Data Mask Register B (BDMRB)............................................................... 383

16.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 383

16.2.9 Break Control Register (BRCR) ........................................................................... 385

16.2.10 Execution Times Break Register (BETR)............................................................. 387

16.2.11 Branch Source Register (BRSR)........................................................................... 388

16.2.12 Branch Destination Register (BRDR)................................................................... 389

16.3 Operation ........................................................................................................................... 390

16.3.1 Flow of User Break Operation.............................................................................. 390

16.3.2 Break on Instruction Fetch Cycle.......................................................................... 391

16.3.3 Break on Data Access Cycle................................................................................. 391

16.3.4 Sequential Break................................................................................................... 392

16.3.5 Value of Saved Program Counter (PC)................................................................. 392

16.3.6 PC Trace ............................................................................................................... 393

16.3.7 Usage Examples.................................................................................................... 394

16.3.8 Usage Notes .......................................................................................................... 397

Section 17 User Debugging Interface (H-UDI) .................................................399

17.1 Features.............................................................................................................................. 399

17.2 Input/Output Pins...............................................................................................................401

17.3 Register Descriptions ......................................................................................................... 402

17.3.1 Bypass Register (SDBPR) .................................................................................... 402

17.3.2 Instruction Register (SDIR) .................................................................................. 402

17.3.3 Boundary Scan Register (SDBSR) ....................................................................... 403

17.3.4 ID Register (SDID)............................................................................................... 409

17.4 Operation ........................................................................................................................... 410

17.4.1 TAP Controller ..................................................................................................... 410

17.4.2 Reset Configuration .............................................................................................. 411

17.4.3 TDO Output Timing ............................................................................................. 411

17.4.4 H-UDI Reset ......................................................................................................... 412

17.4.5 H-UDI Interrupt .................................................................................................... 412

17.5 Boundary Scan...................................................................................................................413

17.5.1 Supported Instructions .......................................................................................... 413

17.5.2 Points for Attention............................................................................................... 414

17.6 Usage Notes ....................................................................................................................... 414

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Section 18 List of Registers...............................................................................415

18.1 Register Addresses (Address Order).................................................................................. 415

18.2 Register Bits....................................................................................................................... 421

18.3 Register States in Each Processing State ........................................................................... 433

Section 19 Electrical Characteristics ................................................................. 439

19.1 Absolute Maximum Ratings .............................................................................................. 439

19.2 Power-On and Power-Off Order ........................................................................................ 439

19.3 DC Characteristics ............................................................................................................. 442

19.4 AC Characteristics ............................................................................................................. 444

19.4.1 Clock Timing........................................................................................................ 445

19.4.2 Control Signal Timing .......................................................................................... 448

19.4.3 Bus Timing ........................................................................................................... 450

19.4.4 Basic Timing......................................................................................................... 452

19.4.5 Synchronous DRAM Timing................................................................................ 458

19.4.6 PCMCIA Timing .................................................................................................. 475

19.4.7 SCIF Timing ......................................................................................................... 479

19.4.8 Port Timing........................................................................................................... 480

19.4.9 HIF Timing ........................................................................................................... 481

19.4.10 Related Pin Timing............................................................................................... 483

19.4.11 AC Characteristic Test Conditions ....................................................................... 485

19.4.12 Delay Time Variation Due to Load Capacitance (Reference Values) .................. 486

Appendix .........................................................................................................487

A. Port States in Each Pin State.............................................................................................. 487

B. Product Code Lineup ......................................................................................................... 490

C. Package Dimensions .......................................................................................................... 491

Main Revisions and Additions in this Edition.....................................................493

Index .........................................................................................................497

Rev. 4.00 Sep. 13, 2007 Page xvii of xxvi

Figures

Section 1 Overview

Figure 1.1 Block Diagram .............................................................................................................. 5

Figure 1.2 Pin Assignments............................................................................................................ 6

Section 2 CPU

Figure 2.1 CPU Internal Register Configuration .......................................................................... 20

Figure 2.2 Register Data Format...................................................................................................24

Figure 2.3 Memory Data Format ..................................................................................................24

Figure 2.4 CPU State Transition................................................................................................... 48

Section 3 Cache

Figure 3.1 Cache Structure ...........................................................................................................51

Figure 3.2 Cache Search Scheme ................................................................................................. 56

Figure 3.3 Write-Back Buffer Configuration................................................................................ 58

Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access............................. 60

Section 6 Interrupt Controller (INTC)

Figure 6.1 INTC Block Diagram .................................................................................................. 82

Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................... 99

Figure 6.3 Interrupt Sequence Flowchart.................................................................................... 103

Figure 6.4 Stack after Interrupt Exception Handling.................................................................. 104

Section 7 Bus State Controller (BSC)

Figure 7.1 Block Diagram of BSC..............................................................................................109

Figure 7.2 Address Space ........................................................................................................... 112

Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)............................................ 148

Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 Bits,

Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0).............. 149

Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 Bits,

Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0).............. 150

Figure 7.6 Example of 16-Bit Data-Width SRAM Connection .................................................. 151

Figure 7.7 Example of 8-Bit Data-Width SRAM Connection.................................................... 151

Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only) ................................. 152

Figure 7.9 Wait Cycle Timing for Normal Space Access

(Wait Cycle Insertion Using WAIT) ......................................................................... 153

Figure 7.10 Example of Timing When CSn Assertion Period is Extended ................................ 154

Figure 7.11 Example of 16-Bit Data-Width SDRAM Connection ............................................. 156

Figure 7.12 Burst Read Basic Timing (Auto Precharge) ............................................................ 164

Figure 7.13 Burst Read Wait Specification Timing (Auto Precharge) .......................................165

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Figure 7.14 Basic Timing for Single Read (Auto Precharge)..................................................... 166

Figure 7.15 Basic Timing for Burst Write (Auto Precharge) ..................................................... 167

Figure 7.16 Basic Timing for Single Write (Auto-Precharge).................................................... 168

Figure 7.17 Burst Read Timing (No Auto Precharge)................................................................ 170

Figure 7.18 Burst Read Timing (Bank Active, Same Row Address) ......................................... 171

Figure 7.19 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 172

Figure 7.20 Single Write Timing (No Auto Precharge).............................................................. 173

Figure 7.21 Single Write Timing (Bank Active, Same Row Address)....................................... 174

Figure 7.22 Single Write Timing (Bank Active, Different Row Addresses).............................. 175

Figure 7.23 Auto-Refreshing Timing ......................................................................................... 176

Figure 7.24 Self-Refreshing Timing........................................................................................... 178

Figure 7.25 Write Timing for SDRAM Mode Register (Based on JEDEC)............................... 180

Figure 7.26 Basic Access Timing for Byte-Selection SRAM (BAS = 0)................................... 181

Figure 7.27 Basic Access Timing for Byte-Selection SRAM (BAS = 1)................................... 182

Figure 7.28 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)............. 183

Figure 7.29 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 184

Figure 7.30 Example of PCMCIA Interface Connection............................................................ 185

Figure 7.31 Basic Access Timing for PCMCIA Memory Card Interface................................... 186

Figure 7.32 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010,

TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)................................. 186

Figure 7.33 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10,

CS6BWCR.SA[1:0] = B'10) ................................................................................... 187

Figure 7.34 Basic Timing for PCMCIA I/O Card Interface ....................................................... 188

Figure 7.35 Wait Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010,

TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)................................. 189

Figure 7.36 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface

(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ............................. 189

Section 8 Clock Pulse Generator (CPG)

Figure 8.1 Block Diagram of CPG ............................................................................................. 194

Figure 8.2 Points for Attention When Using Crystal Resonator................................................. 203

Section 9 Watchdog Timer (WDT)

Figure 9.1 Block Diagram of WDT............................................................................................ 206

Figure 9.2 Writing to WTCNT and WTCSR.............................................................................. 210

Section 10 Power-Down Modes

Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR.............................................. 222

Section 11 Compare Match Timer (CMT)

Figure 11.1 Block Diagram of Compare Match Timer............................................................... 225

Figure 11.2 Counter Operation................................................................................................... 229

Rev. 4.00 Sep. 13, 2007 Page xix of xxvi

Figure 11.3 Count Timing .......................................................................................................... 229

Figure 11.4 Timing of CMF Setting ...........................................................................................230

Figure 11.5 Conflict between Write and Compare-Match Processes of CMCNT...................... 231

Figure 11.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 232

Figure 11.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ....................... 233

Section 12 Serial Communication Interface with FIFO (SCIF)

Figure 12.1 Block Diagram of SCIF........................................................................................... 237

Figure 12.2 Example of Data Format in Asynchronous Communication

(8-Bit Data with Parity and Two Stop Bits) ............................................................ 275

Figure 12.3 Sample Flowchart for SCIF Initialization ............................................................... 278

Figure 12.4 Sample Flowchart for Transmitting Serial Data...................................................... 279

Figure 12.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)........................ 281

Figure 12.6 Example of Operation Using Modem Control (CTS).............................................. 281

Figure 12.7 Sample Flowchart for Receiving Serial Data ..........................................................282

Figure 12.8 Sample Flowchart for Receiving Serial Data (cont)................................................ 283

Figure 12.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 285

Figure 12.10 Example of Operation Using Modem Control (RTS)............................................ 285

Figure 12.11 Data Format in Synchronous Communication ...................................................... 286

Figure 12.12 Sample Flowchart for SCIF Initialization.............................................................. 288

Figure 12.13 Sample Flowchart for Transmitting Serial Data.................................................... 289

Figure 12.14 Example of SCIF Transmit Operation................................................................... 290

Figure 12.15 Sample Flowchart for Receiving Serial Data (1)................................................... 291

Figure 12.16 Sample Flowchart for Receiving Serial Data (2)................................................... 291

Figure 12.17 Example of SCIF Receive Operation .................................................................... 292

Figure 12.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 293

Figure 12.19 RTSIO Bit, RTSDT Bit, and RTS Pin...................................................................295

Figure 12.20 CTSIO Bit, CTSDT Bit, and CTS Pin...................................................................296

Figure 12.21 SCKIO Bit, SCKDT Bit, and SCK Pin ................................................................. 297

Figure 12.22 SPBIO Bit, SPBDT Bit, and TxD Pin ...................................................................297

Figure 12.23 SPBDT Bit and RxD Pin ....................................................................................... 298

Figure 12.24 Receive Data Sampling Timing in Asynchronous Mode ...................................... 299

Section 13 Host Interface (HIF)

Figure 13.1 Block Diagram of HIF............................................................................................. 302

Figure 13.2 HIF Connection Example ........................................................................................ 304

Figure 13.3 Basic Timing for HIF Interface ............................................................................... 320

Figure 13.4 HIFIDX Write and HIFGSR Read .......................................................................... 321

Figure 13.5 HIF Register Settings .............................................................................................. 321

Figure 13.6 Consecutive Data Writing to HIFRAM................................................................... 322

Figure 13.7 Consecutive Data Reading from HIFRAM ............................................................. 322

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Figure 13.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)............................................. 323

Figure 13.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)............................................. 324

Figure 13.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)........................................... 324

Figure 13.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)........................................... 324

Figure 13.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin .......................... 329

Section 15 I/O Ports

Figure 15.1 Port A ...................................................................................................................... 363

Figure 15.2 Port B ...................................................................................................................... 365

Figure 15.3 Port C ...................................................................................................................... 367

Figure 15.4 Port D ...................................................................................................................... 370

Figure 15.5 Port E....................................................................................................................... 372

Section 16 User Break Controller (UBC)

Figure 16.1 Block Diagram of UBC........................................................................................... 378

Section 17 User Debugging Interface (H-UDI)

Figure 17.1 Block Diagram of H-UDI........................................................................................ 400

Figure 17.2 TAP Controller State Transitions ............................................................................ 410

Figure 17.3 H-UDI Data Transfer Timing.................................................................................. 412

Figure 17.4 H-UDI Reset............................................................................................................ 412

Section 19 Electrical Characteristics

Figure 19.1 External Clock Input Timing................................................................................... 446

Figure 19.2 CKIO Clock Output Timings .................................................................................. 446

Figure 19.3 Oscillation Settling Timing after Power-On............................................................ 446

Figure 19.4 Oscillation Settling Timing after Standby Mode (By Reset)................................... 447

Figure 19.5 Oscillation Settling Timing after Standby Mode (By NMI or IRQ)........................ 447

Figure 19.6 PLL Synchronize Settling Timing by Reset or NMI ............................................... 447

Figure 19.7 Reset Input Timing.................................................................................................. 448

Figure 19.8 Interrupt Input Timing............................................................................................. 449

Figure 19.9 Pin Drive Timing in Standby Mode ........................................................................ 449

Figure 19.10 Basic Bus Timing: No Wait Cycle ........................................................................ 452

Figure 19.11 Basic Bus Timing: One Software Wait Cycle ....................................................... 453

Figure 19.12 Basic Bus Timing: One External Wait Cycle........................................................ 454

Figure 19.13 Basic Bus Timing: One Software Wait Cycle, External Wait Enabled

(WM Bit = 0), No Idle Cycle ................................................................................ 455

Figure 19.14 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle,

One Asynchronous External Wait Cycle, CSnWCR.BAS = 0

(UB-/LB-Controlled Write Cycle) ........................................................................ 456

Rev. 4.00 Sep. 13, 2007 Page xxi of xxvi

Figure 19.15 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle,

One Asynchronous External Wait Cycle, CSnWCR.BAS = 1

(WE-Controlled Write Cycle) ............................................................................... 457

Figure 19.16 Synchronous DRAM Single Read Bus Cycle

(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)...... 458

Figure 19.17 Synchronous DRAM Single Read Bus Cycle

(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)...... 459

Figure 19.18 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)

(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)....... 460

Figure 19.19 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)

(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)....... 461

Figure 19.20 Synchronous DRAM Single Write Bus Cycle

(Auto-Precharge, TRWL = 1 Cycle) ..................................................................... 462

Figure 19.21 Synchronous DRAM Single Write Bus Cycle

(Auto-Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) .................................. 463

Figure 19.22 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)

(Auto-Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) ....................................464

Figure 19.23 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)

(Auto-Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) ....................................465

Figure 19.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active

Mode: ACT + READ Commands, CAS Latency = 2, WTRCD = 0 Cycle) ......... 466

Figure 19.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)

(Bank Active Mode: READ Command, Same Row Address,

CAS Latency = 2, WTRCD = 0 Cycle)................................................................ 467

Figure 19.26 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)

(Bank Active Mode: PRE + ACT + READ Commands,

Different Row Addresses, CAS Latency = 2, WTRCD = 0 Cycle) ..................... 468

Figure 19.27 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)

(Bank Active Mode: ACT + WRITE Commands,

WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 469

Figure 19.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)

(Bank Active Mode: WRITE Command, Same Row Address,

WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 470

Figure 19.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)

(Bank Active Mode: PRE + ACT + WRITE Commands,

Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) ..................... 471

Figure 19.30 Synchronous DRAM Auto-Refreshing Timing

(WTRP = 1 Cycle, WTRC = 3 Cycles)................................................................. 472

Figure 19.31 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 473

Figure 19.32 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 474

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Figure 19.33 PCMCIA Memory Card Interface Bus Timing ..................................................... 475

Figure 19.34 PCMCIA Memory Card Interface Bus Timing (TED = 2.5 Cycles,

TEH = 1.5 Cycles, One Software Wait Cycle, One External Wait Cycle) ........... 476

Figure 19.35 PCMCIA I/O Card Interface Bus Timing.............................................................. 477

Figure 19.36 PCMCIA I/O Card Interface Bus Timing (TED = 2.5 Cycles,

TEH = 1.5 Cycles, One Software Wait Cycle, One External Wait Cycle) ........... 478

Figure 19.37 SCK Input Clock Timing ...................................................................................... 479

Figure 19.38 SCI Input/Output Timing in Clocked Synchronous Mode .................................... 480

Figure 19.39 I/O Port Timing ..................................................................................................... 480

Figure 19.40 HIF Access Timing ............................................................................................... 482

Figure 19.41 HIFINT and HIFDREQ Timing ............................................................................ 482

Figure 19.42 HIFRDY and HIF Pin Enable/Disable Timing...................................................... 483

Figure 19.43 TCK Input Timing.................................................................................................484

Figure 19.44 TCK Input Timing in Reset Hold State................................................................. 484

Figure 19.45 H-UDI Data Transmission Timing........................................................................ 484

Figure 19.46 Output Load Circuit ..............................................................................................485

Figure 19.47 Load Capacitance versus Delay Time ................................................................... 486

Appendix

Figure C.1 Package Dimensions (BP-176)................................................................................. 491

Rev. 4.00 Sep. 13, 2007 Page xxiii of xxvi

Tables

Section 1 Overview

Table 1.1 Pin Functions ............................................................................................................ 7

Table 1.2 Pin Features ............................................................................................................12

Section 2 CPU

Table 2.1 Initial Values of Registers.......................................................................................23

Table 2.2 Word Data Sign Extension......................................................................................25

Table 2.3 Delayed Branch Instructions................................................................................... 26

Table 2.4 T Bit........................................................................................................................ 26

Table 2.5 Access to Immediate Data ...................................................................................... 27

Table 2.6 Access to Absolute Address.................................................................................... 27

Table 2.7 Access with Displacement ...................................................................................... 28

Table 2.8 Addressing Modes and Effective Addresses...........................................................28

Table 2.9 Instruction Formats .................................................................................................32

Table 2.10 Instruction Types .................................................................................................... 35

Section 3 Cache

Table 3.1 LRU and Way to be Replaced ................................................................................52

Table 3.2 Correspondence between Divided Areas and Cache............................................... 53

Section 5 Exception Handling

Table 5.1 Types of Exceptions and Priority............................................................................ 65

Table 5.2 Timing for Exception Detection and Start of Exception Handling .........................66

Table 5.3 Vector Numbers and Vector Table Address Offsets............................................... 67

Table 5.4 Calculating Exception Handling Vector Table Addresses...................................... 68

Table 5.5 Reset Status............................................................................................................. 69

Table 5.6 Bus Cycles and Address Errors............................................................................... 71

Table 5.7 Interrupt Sources..................................................................................................... 72

Table 5.8 Interrupt Priority .....................................................................................................73

Table 5.9 Types of Exceptions Triggered by Instructions ...................................................... 74

Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions............... 76

Table 5.11 Stack Status after Exception Handling Ends........................................................... 77

Section 6 Interrupt Controller (INTC)

Table 6.1 Pin Configuration....................................................................................................83

Table 6.2 Interrupt Exception Handling Vectors and Priorities............................................ 101

Table 6.3 Interrupt Response Time....................................................................................... 105

Section 7 Bus State Controller (BSC)

Table 7.1 Pin Configuration.................................................................................................. 110

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Table 7.2 Address Map 1 (CMNCR.MAP = 0) .................................................................... 112

Table 7.3 Address Map 2 (CMNCR.MAP = 1) .................................................................... 113

Table 7.4 Correspondence between External Pin (MD3), Memory Type,

and Bus Width for CS0......................................................................................... 114

Table 7.5 Correspondence between External Pin (MD5) and Endians................................. 114

Table 7.6 16-Bit External Device/Big Endian Access and Data Alignment......................... 144

Table 7.7 8-Bit External Device/Big Endian Access and Data Alignment........................... 145

Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment...................... 146

Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment........................ 147

Table 7.10 Relationship between Register Settings and Address Multiplex Output (1)......... 157

Table 7.11 Relationship between Register Settings and Address Multiplex Output (2)......... 158

Table 7.12 Relationship between Register Settings and Address Multiplex Output (3)......... 159

Table 7.13 Relationship between Register Settings and Address Multiplex Output (4)......... 160

Table 7.14 Relationship between Register Settings and Address Multiplex Output (5)......... 161

Table 7.15 Relationship between Register Settings and Address Multiplex Output (6)......... 162

Table 7.16 Relationship between Access Size and Number of Bursts.................................... 163

Table 7.17 Access Address for SDRAM Mode Register Write.............................................. 179

Section 8 Clock Pulse Generator (CPG)

Table 8.1 Pin Configuration.................................................................................................. 196

Table 8.2 Mode Control Pins and Clock Operating Modes .................................................. 196

Table 8.3 Possible Combination of Clock Modes and FRQCR Values................................ 197

Section 10 Power-Down Modes

Table 10.1 States of Power-Down Modes .............................................................................. 214

Table 10.2 Pin Configuration.................................................................................................. 215

Table 10.3 Register States in Software Standby Mode........................................................... 221

Section 12 Serial Communication Interface with FIFO (SCIF)

Table 12.1 SCIF Pins.............................................................................................................. 238

Table 12.2 SCSMR Settings ................................................................................................... 258

Table 12.3 Bit Rates and SCBRR Settings in Asynchronous Mode....................................... 258

Table 12.4 Bit Rates and SCBRR Settings in Synchronous Mode ......................................... 261

Table 12.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode) .......................................................................................... 262

Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)............... 263

Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ................. 263

Table 12.8 SCSMR Settings and SCIF Communication Formats .......................................... 274

Table 12.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection......................... 274

Table 12.10 Serial Communication Formats (Asynchronous Mode).................................... 276

Table 12.11 SCIF Interrupt Sources ..................................................................................... 294

Rev. 4.00 Sep. 13, 2007 Page xxv of xxvi

Section 13 Host Interface (HIF)

Table 13.1 Pin Configuration..................................................................................................303

Table 13.2 HIF Operations ..................................................................................................... 304

Table 13.3 Memory Map ........................................................................................................ 319

Table 13.4 Consecutive Write Procedure to HIFRAM by External DMAC........................... 326

Table 13.5 Consecutive Read Procedure from HIFRAM by External DMAC....................... 327

Table 13.6 Input/Output Control for HIF Pins........................................................................ 330

Section 14 Pin Function Controller (PFC)

Table 14.1 List of Multiplexed Pins (Port A) ......................................................................... 333

Table 14.2 List of Multiplexed Pins (Port B).......................................................................... 334

Table 14.3 List of Multiplexed Pins (Port C).......................................................................... 336

Table 14.4 List of Multiplexed Pins (Port D) ......................................................................... 336

Table 14.5 List of Multiplexed Pins (Port E).......................................................................... 337

Table 14.6 Pin Functions in Each Operating Mode ................................................................ 338

Section 15 I/O Ports

Table 15.1 Port A Data Register H (PADRH) Read/Write Operation.................................... 364

Table 15.2 Port B Data Register L (PBDRL) Read/Write Operation ..................................... 366

Table 15.3 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operation .... 369

Table 15.4 Port D Data Register L (PDDRL) Read/Write Operation..................................... 371

Table 15.5 Port E Data Registers H, L (PEDRH, PEDRL) Read/Write Operation ................ 374

Section 16 User Break Controller (UBC)

Table 16.1 Data Access Cycle Addresses and Operand Size Comparison Conditions........... 391

Section 17 User Debugging Interface (H-UDI)

Table 17.1 Pin Configuration..................................................................................................401

Table 17.2 H-UDI Commands................................................................................................ 403

Table 17.3 External Pins and Boundary Scan Register Bits ................................................... 404

Table 17.4 Reset Configuration .............................................................................................. 411

Section 19 Electrical Characteristics

Table 19.1 Absolute Maximum Ratings ................................................................................. 439

Table 19.2 Recommended Timing at Power-On..................................................................... 440

Table 19.3 Recommended Timing in Power-Off.................................................................... 441

Table 19.4 DC Characteristics (1)...........................................................................................442

Table 19.4 DC Characteristics (2)...........................................................................................443

Table 19.5 Permissible Output Currents................................................................................. 444

Table 19.6 Maximum Operating Frequency ........................................................................... 444

Table 19.7 Clock Timing ........................................................................................................ 445

Table 19.8 Control Signal Timing .......................................................................................... 448

Table 19.9 Bus Timing ........................................................................................................... 450

Rev. 4.00 Sep. 13, 2007 Page xxvi of xxvi

Table 19.10 SCIF Timing ..................................................................................................... 479

Table 19.11 Port Timing....................................................................................................... 480

Table 19.12 HIF Timing ....................................................................................................... 481

Table 19.13 H-UDI-Related Pin Timing .............................................................................. 483

Appendix

Table A.1 Port States in Each Pin State................................................................................. 487

Section 1 Overview

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REJ09B0239-0400

Section 1 Overview

This LSI is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an

original Renesas Technology RISC (Reduced Instruction Set Computer) architecture with

supporting a variety of peripheral functions.

The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The

CPU basically operates at a rate of one instruction per cycle, offering a great improvement in

instruction execution speed. In addition, the 32-bit internal architecture provides improved data

processing power. With this CPU, it has become possible to assemble low-cost, high-

performance/high-functionality systems even for applications such as realtime control, which

could not previously be handled by microcontrollers because of their high-speed processing

requirements.

This LSI supports peripheral functions necessary for system configuration, such as cache memory,

RAM, timers, a serial communication interface with on-chip FIFO (SCIF), host interface (HFI),

interrupt controller (INTC), and I/O ports.

The external memory access support function of this LSI enables direct connection to various

types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system

cost.

1.1 Features

The features of this LSI are shown below.

CPU:

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)

architecture

• Instruction length: 16-bit fixed length for improved code efficiency

• Load-store architecture (basic operations are executed between registers)

• Sixteen 32-bit general registers

• Five-stage pipeline

• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to

five cycles

• C language-oriented 62 basic instructions

Note: Some specifications on the slot illegal instruction differ from the conventional SH2 core.

For details, see section 5.8, Usage Notes, in section 5, Exception Handling.

Section 1 Overview

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User break controller (UBC):

• Address, data value, access type, and data size are available for setting as break conditions

• Supports the sequential break function

• Two break channels

U memory:

• 4 kbytes

Cache memory:

• Unified cache, mixture of instructions and data

• 4-way set associative type

• Selection of write-back or write-through mode

• 16 Kbytes

Bus state controller (BSC):

• Address space is divided into five areas: three areas 0, 3, and 4; each a maximum of 64

Mbytes, and two areas 5B and 6B; each a maximum of 32 Mbytes (address map 1 mode).

• Address space is divided into five areas, 0, 3, 4, 5, and 6; each a maximum of 64 Mbytes

(address map 2 mode).

• 16-bit external bus

• The following features are settable for each area.

 Bus size (8 or 16 bits)

 Number of access wait cycles

 Setting of idle wait cycles

 Specifying the memory to be connected to each area enables direct connection to SRAM,

SDRAM, and PCMCIA.

 Outputs chip select signals (CS0, CS3, CS4, CS5B, and CS6B) for corresponding area

• SDRAM refresh function

 Supports auto-refresh and self-refresh modes

• SDRAM burst access function

• PCMCIA access function

 Conforms to the JEIDA Ver. 4.2 standard, two slots

• Selection of big or little endian mode (The mode of all the areas is switched collectively by a

mode pin.)

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Interrupt controller (INTC):

• Supports nine external interrupt pins (NMI, IRQ7 to IRQ0)

• On-chip peripheral interrupt: Priority level is independently selected for each module

• Vector address: Specified vector address for each interrupt source

User debugging interface (H-UDI):

• Supports the JTAG interface emulator

• JTAG standard pins arranged

Clock pulse generator (CPG):

• Clock mode: Clock source selectable between an external supply and crystal resonator

• Three types of clocks generated:

 CPU clock: 100 MHz (max.)

 Bus clock: 50 MHz (max.)

 Peripheral clock: 50 MHz (max.)

• Supports power-down modes:

 Sleep mode

 Software standby mode

• Selection of four types of clock modes (PLL2 ×2/×4 and clock/crystal resonator are selectable)

Host interface (HIF):

• 1 kbyte × 2 banks: in total 2-kbyte buffer RAM

• The buffer RAM and the external device are connected in parallel via 16 data pins

• The buffer RAM and the CPU of this LSI are connected in parallel via internal bus

• The external device can access the desired register after the register index has been specified.

(However, when the buffer RAM is accessed successively, the address is updated

automatically.)

• Selection of endian mode

• Interrupt requested to the external device

• Internal interrupt requested to the CPU of this LSI

• Booting from the buffer RAM is enabled if the external device has stored the instruction code

in the buffer RAM

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Compare match timer (CMT):

• 16-bit counter

• Generates compare match interrupts

• Two channels

Serial communication interface with FIFO (SCIF):

• Synchronous and asynchronous modes

• 16 bytes each for transmit/receive FIFO

• High-speed UART

• The UART supports FIFO stop and FIFO trigger

• Flow control enabled (channel 0 and channel 1 only)

• Three channels

I/O ports:

• 78 general input/output pins

• Input or output can be set per bit within the input/output common port

Package:

• BP1313-176 (0.8 pitch)

Power supply voltage:

• I/O: 3.0 to 3.6 V

Internal: 1.5±0.1 V (Two power sources are externally provided.)

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1.2 Block Diagram

Figure 1.1 is a block diagram of this LSI.

SuperH

CPU core

User break

controller

(UBC)

Cache

access

controller

(CCN)

U memory

4 kbytes

Cache

memory

16 kbytes

Bus state

controller

(BSC)

Peripheral

bus

controller

CPU bus (I clock)

Internal bus (B clock)

External bus

Notes:

Host

interface

(HIF)

User

debugging

interface

(H-UDI)

Interrupt

controller

(INTC)

Power-

down

mode

control

Watchdog

timer

(WDT)

Clock pulse

generator

(CPG)

Serial

communication

interface

with FIFO

(SCIF)*1

Peripheral bus (P clock)

I/O port,

Pin function

controller

(PFC)

Compare

match timer

(CMT)

1-kbyte

SRAM

1. SCIF includes three channels.

2. CMT includes two channels.

Figure 1.1 Block Diagram

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1.3 Pin Assignments

BP1313-176

(Top view)

2 3 4 5 6 7 8 9 10 11 12 13 14 15

VccQ

VssQ

PD3

PD0

Vss

PE22

PE18

PE16

PE12

VccQ

PE06

Vcc

PE02

PC17

VccQ

PA25

PD7

PD5

PD2

Vcc

PE21

PE17

PE15

PE11

VssQ

PE05

Vss

PE00

PC16

VssQ

PA22

PA24

PD6

PD4

PE08

PE23

PE19

Vss

PE13

PE09

PE07

PE03

PC09

PC15

PC00

Vcc

Vss

PA21

PA23

PA18

PA19

PA17

PA20

PB08

PA16

PB07

PB10

VccQ

VssQ

PB09

PB01

PB05

PB06

PB00

CS0

PB11

PB13

A15

A13

A14

A12

A11

Vss

Vcc

A10

A08

PD1

PE24

PE20

Vcc

PE14

PE10

PE04

PE01

PC08

PC01

PC03

PC02

PC10

Vcc

Vss

PC18

PC11

PC04

PC13

PC05

PC06

PC12

PC07

Vcc

Vss

PC20

PC14

PC19

TESTOUT

MD3

TESTOUT2

MD5

TCK

VssQ

VccQ

TRST

TDO

TMS

TDI

A09

A07

A05

PB12

PB02

D09

Vcc

D15

Vcc

D04

D00

VccQ

ASEMD

NMI

RES

A06

A04

A03

PB03

WE0/

DQMLL

D08

Vss

D14

Vss

D05

D01

Vcc(PLL2)

Vcc(PLL1)

EXTAL

TESTMD

VssQ

A02

A00

Vss

RD/(WR)

VssQ

D10

D12

MD2

D07

D02

VssQ

Vss(PLL2)

VssQ

XTAL

VccQ

A01

PB04

Vcc

WE1/

DQMLU/

VccQ

D11

D13

CKIO

D06

D03

VccQ

MD1

Vss(PLL1)

MD0

12 3456789101112131415

Figure 1.2 Pin Assignments

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1.4 Pin Functions

Table 1.1 Pin Functions

Classifi-

cation Abbr. I/O Pin Name Description

Power

supply

Vcc Input Power Supply Power supply for the internal logic of this LSI. All the Vcc

pins must be connected to the system power supply. This

LSI does not operate correctly if there is a pin left open.

Vss Input Ground Ground pins. All the Vss pins must be connected to the

system power supply (0 V). This LSI does not operate

correctly if there is a pin left open.

VccQ Input Power Supply Power supply for input/output pins. All the VccQ pins must

be connected to the system power supply. This LSI does not

operate correctly if there is a pin left open.

VssQ Input Ground Ground pins. All the VssQ pins must be connected to the

system power supply (0 V). This LSI does not operate

correctly if there is a pin left open.

Clock Vcc (PLL1) Input Power Supply

for PLL1

Power supply pin for the on-chip PLL1 oscillator

Vss (PLL1) Input Ground for

PLL1

Ground pin for the on-chip PLL1 oscillator

Vcc (PLL2) Input Power Supply

for PLL2

Power supply pin for the on-chip PLL2 oscillator

Vss (PLL2) Input Ground for

PLL2

Ground pin for the on-chip PLL2 oscillator

EXTAL Input External Clock Connects to a crystal resonator. An external clock is also

input on this pin. For details on connection of an external

clock, see section 8, Clock Pulse Generator (CPG).

XTAL Output Crystal Connects to a crystal resonator.

CKIO Output System Clock Supplies the system clock to external devices.

Operating

mode

control

MD5, MD3

to MD0

Input Mode Setting Sets operating mode. The signal levels of these pins must

not be changed during operation.

Pins MD2 to MD0 are used for setting clock mode, pin MD3

is for setting bus width mode for area 0, and pin MD5 is for

setting endian.

System

control

RES Input Power-On

Reset

This LSI enters the reset state when this signal goes low.

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Classifi-

cation Abbr. I/O Pin Name Description

Interrupt NMI Input Non-Maskable

Interrupt

Non-maskable interrupt request signal. When this pin is not

in use, this signal must be fixed high.

IRQ7 to

IRQ0

Input Interrupt

Request 7 to 0

Maskable interrupt request pins.

Level-input or edge-input detection can be selected. When

the edge-input detection is selected, the rising or falling edge

can also be selected.

Address

bus

A25 to A0 Output Address Bus Outputs addresses.

Data bus D15 to D0 Input/

output

Data Bus 16-bit bidirectional bus

Bus

control

CS0, CS3,

CS4, CS5B,

CS6B

Output Chip Select 0,

3, 4, 5B, 6B

Chip select signals for external memory and devices.

RD Output Read Indicates that data is read from an external device.

RD/WR Output Read/Write Read/write signal

BS Output Bus Cycle

Start

Indicates start of a bus cycle.

WE1 Output Upper Side

Write

Indicates that bits 15 to 8 of data of external memory or

devices are written to.

WE0 Output Lower Side

Write

Indicates that bits 7 to 0 of data of external memory or

devices are written to.

WAIT Input Wait Input pin used to insert wait cycles when accessing the

external space

RAS Output RAS Connects to the RAS pin of SDRAM.

CAS Output CAS Connects to the CAS pin of SDRAM.

CKE Output Clock Enable Connects to the CKE pin of SDRAM.

DQMLU Output Upper Side

Select

Selects bits 15 to 8 of SDRAM data bus.

DQMLL Output Lower Side

Select

Selects bits 7 to 0 of SDRAM data bus.

CE1A Output PCMCIA Card

Select Lower

Side

Chip enable for PCMCIA allocated to area 5

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Classifi-

cation Abbr. I/O Pin Name Description

Bus

control

CE1B Output PCMCIA Card

Select Lower

Side

Chip enable for PCMCIA allocated to area 6

CE2A Output PCMCIA Card

Select Upper

Side

Chip enable for PCMCIA allocated to area 5

CE2B Output PCMCIA Card

Select Upper

Side

Chip enable for PCMCIA allocated to area 6

ICIOWR Output PCMCIA I/O

Write Strobe

Connects to the PCMCIA I/O write strobe pin.

ICIORD Output PCMCIA I/O

Read Strobe

Connects to the PCMCIA I/O read strobe pin.

WE Output PCMCIA

Memory Write

Strobe

Connects to the PCMCIA memory write strobe.

IOIS16 Input PCMCIA

Dynamic Bus

Sizing

In little endian mode, this signal indicates 16-bit bus width of

PCMCIA. In big endian mode, fix this pin low.

Serial

communic

ations

interface

with FIFO

TXD2 to

TXD0

Output Transmit Data Transmit data pins

RXD2 to

RXD0

Input Receive Data Receive data pins

SCK2 to

SCK0

Input/

output

Serial clock Clock input pins

RTS1 and

RTS0

Output Transmit

Request

Modem control pin. Supported only by SCIF0 and SCIF1.

CTS1 and

CTS0

Input Transmit

Enable

Modem control pin. Supported only by SCIF0 and SCIF1.

Host

interface

HIFD15 to

HIFD0

Input/

output

HIF Data Bus Address, data, and command input/output pins for the HIF.

HIFCS Input HIF Chip

Select

Chip select input for the HIF

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Classifi-

cation Abbr. I/O Pin Name Description

Host

interface

HIFRS Input HIF Register

Select

Controls the access type switching for the HIF.

HIFWR Input HIF Write Write strobe signal

HIFRD Input HIF Read Read strobe signal

HIFINT Output HIF Interrupt Interrupt request to external devices by the HIF

HIFMD Input HIF Mode Specifies HIF boot mode.

HIFDREQ Output HIF DMAC

Transfer

Request

Requests DMAC transfer for the HIFRAM to external

devices.

HIFRDY Output HIF Boot

Ready

Indicates that a reset of the HIF has been cleared in this LSI

and the HIF is ready for accesses to it.

HIFEBL Input HIF Pin

Enable

HIF pins other than this pin are enabled by driving this pin

high.

User

debugging

interface

(H-UDI)

TCK Input Test Clock Test clock input pin

TMS Input Test Mode

Select

Input pin for test mode select signal

TDI Input Test Data

Input

Serial input pin for an instruction and data

TDO Output Test Data

Output

Serial output pin for an instruction and data

TRST Input Test Reset Input pin for initialization

I/O port PA25 to

PA16

Input/

output

General port Pins for 10-bit general input/output port

PB13 to

PB00

Input/

output

General port Pins for 14-bit general input/output port

PC20 to

PC00

Input/

output

General port Pins for 21-bit general input/output port

PD07 to

PD00

Input/

output

General port Pins for 8-bit general input/output port

PE24 to

PE00

Input/

output

General port Pins for 25-bit general input/output port

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Classifi-

cation Abbr. I/O Pin Name Description

Emulator

interface

ASEMD Input ASE Mode Specifies ASE mode.

This LSI enters ASE mode when this signal goes low and

normal mode when this pin goes high. In ASE mode,

functions for the emulator are available.

Test Mode TESTMD Input Test Mode Specifies test mode.

This LSI enters test mode when this signal goes low. Fix this

signal high.

TESTOUT2 Output Test Output Output pin for testing. This pin should be open.

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Table 1.2 Pin Features

Pin No. Pin Name I/O Features

A1 VCCQ Power

A2 PA25/A25 IO/O

A3 PA22/A22 IO/O

A4 VCC Power

A5 PA18/A18 IO/O

A6 PB08/(CS6B/CE1B) IO/O/O

A7 VCCQ Power

A8 PB05/ICIORD IO/O

A9 RD O

A10 A13 O

A11 VSS Power

A12 A09 O

A13 A06 O

A14 VSSQ Power

A15 VCCQ Power

B1 VSSQ Power

B2 PD7/IRQ7/SCK2 IO/I/IO

B3 PA24/A24 IO/O

B4 VSS Power

B5 PA19/A19 IO/O

B6 PA16/A16 IO/O

B7 VSSQ Power

B8 PB06/ICIOWR IO/O

B9 PB11/CS4 IO/O

B10 A14 O

B11 VCC Power

B12 A07 O

B13 A04 O

B14 A02 O

B15 A01 O

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Pin No. Pin Name I/O Features

C1 PD3/IRQ3/RxD1 IO/I/I

C2 PD5/IRQ5/TxD2 IO/I/O

C3 PD6/IRQ6/RxD2 IO/I/I

C4 PA21/A21 IO/O

C5 PA17/A17 IO/O

C6 PB07/CE2B IO/O

C7 PB09/CE2A IO/O

C8 PB00/WAIT IO/I

C9 PB13/BS IO/O

C10 A12 O

C11 A10 O

C12 A05 O

C13 A03 O

C14 A00 O

C15 PB04/RAS IO/O

D1 PD0/IRQ0 IO/I

D2 PD2/IRQ2/TxD1 IO/I/O

D3 PD4/IRQ4/SCK1 IO/I/IO

D4 PA23/A23 IO/O

D5 PA20/A20 IO/O

D6 PB10/(CS5B/CE1A) IO/O/O

D7 PB01/IOIS16 IO/I

D8 CS0 O

D9 A15 O

D10 A11 O

D11 A08 O

D12 PB12/CS3 IO/O

D13 PB03/CAS IO/O

D14 VSS Power

D15 VCC Power

E1 VSS Power

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Pin No. Pin Name I/O Features

E2 VCC Power

E3 PE08/HIFCS IO/I

E4 PD1/IRQ1 IO/I

E12 PB02/CKE IO/O

E13 (WE0/DQMLL) O/O

E14 RD/(WR) O

E15 (WE1/DQMLU/WE) O/O/O

F1 PE22/HIFD13/CTS0 IO/IO/I

F2 PE21/HIFD12/RTS0 IO/IO/O

F3 PE23/HIFD14/RTS1 IO/IO/O

F4 PE24/HIFD15/CTS1 IO/IO/I

F12 D09 IO

F13 D08 IO

F14 VSSQ Power

F15 VCCQ Power

G1 PE18/HIFD09/TxD1 IO/IO/O

G2 PE17/HIFD08/SCK0 IO/IO/IO

G3 PE19/HIFD10/RxD1 IO/IO/I

G4 PE20/HIFD11/SCK1 IO/IO/IO

G12 VCC Power

G13 VSS Power

G14 D10 IO

G15 D11 IO

H1 PE16/HIFD07/RxD0 IO/IO/I

H2 PE15/HIFD06/TxD0 IO/IO/O

H3 VSS Power

H4 VCC Power

H12 D15 IO

H13 D14 IO

H14 D12 IO

H15 D13 IO

J1 PE12/HIFD03 IO/IO

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Pin No. Pin Name I/O Features

J2 PE11/HIFD02 IO/IO

J3 PE13/HIFD04 IO/IO

J4 PE14/HIFD05 IO/IO

J12 VCC Power

J13 VSS Power

J14 MD2 I

J15 CKIO IO

K1 VCCQ Power

K2 VSSQ Power

K3 PE09/HIFD00 IO/IO

K4 PE10/HIFD01 IO/IO

K12 D04 IO

K13 D05 IO

K14 D07 IO

K15 D06 IO

L1 PE06/HIFWR IO/I

L2 PE05/HIFRD IO/I

L3 PE07/HIFRS IO/I

L4 PE04/HIFINT IO/O

L12 D00 IO

L13 D01 IO

L14 D02 IO

L15 D03 IO

M1 VCC Power

M2 VSS Power

M3 PE03/HIFMD IO/I

M4 PE01/HIFRDY IO/O

M5 PC02 IO

M6 PC18 IO

M7 PC05 IO

M8 VCC Power

M9 PC19 IO

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Pin No. Pin Name I/O Features

M10 MD5 I

M11 TRST I

M12 VCCQ Power

M13 VCC (PLL2) Power

M14 VSSQ Power

M15 VCCQ Power

N1 PE02/HIFDREQ IO/O

N2 PE00/HIFEBL IO/I

N3 PC09 IO

N4 PC08 IO

N5 PC10 IO

N6 PC11 IO

N7 PC06 IO

N8 VSS Power

N9 TESTOUT O

N10 TCK I

N11 TDO O

N12 ASEMD I

N13 VCC (PLL1) Power

N14 VSS (PLL2) Power

N15 MD1 I

P1 PC17 IO

P2 PC16 IO/

P3 PC15 IO

P4 PC01 IO

P5 VCC Power

P6 PC04 IO

P7 PC12 IO

P8 PC20 IO

P9 MD3 I

P10 VSSQ Power

P11 TMS I

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Pin No. Pin Name I/O Features

P12 NMI I

P13 EXTAL I

P14 VSSQ Power

P15 VSS (PLL1) Power

R1 VCCQ Power

R2 VSSQ Power

R3 PC00 IO

R4 PC03 IO

R5 VSS Power

R6 PC13 IO

R7 PC07 IO

R8 PC14 IO

R9 TESTOUT2 O

R10 VCCQ Power

R11 TDI I

R12 RES I

R13 TESTMD I

R14 XTAL O

R15 MD0 I

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Section 2 CPU

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Section 2 CPU

2.1 Features

• General registers: 32-bit register × 16

• Basic instructions: 62

• Addressing modes: 11

Post-increment register indirect (@Rn+)

Pre-decrement register indirect (@-Rn)

Index register indirect (@R0, Rn)

GBR indirect with displacement (@disp:8, GBR)

Index GBR indirect (@R0, GBR)

PC relative with displacement (@disp:8, PC)

PC relative (disp:8/disp:12/Rn)

Immediate (#imm:8)

2.2 Register Configuration

There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and

system registers (32-bit × 4).

Section 2 CPU

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31 0

R0*

R10

R11

R12

R13

R14

R15, SP (hardware stack pointer)0*

31 9 8 7 6 5 4 3 2 1 0

GBR

VBR

QI3I2I1I0 ST

31 0

MACH

31 0

MACL

Notes: 1. R0 can be used as an index register in index register indirect or index GBR

indirect addressing mode. For some instructions, only R0 is used as the

source or destination register.

2. R15 is used as a hardware stack pointer during exception handling.

General register (Rn)

Status register (SR)

Global base register (GBR)

Vector base register (VBR)

Multiply and accumulate register (MAC)

Procedure register (PR)

Program counter (PC)

Figure 2.1 CPU Internal Register Configuration

Section 2 CPU

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2.2.1 General Registers (Rn)

There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are

used for data processing and address calculation. R0 is also used as an index register. With a

number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack

pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the

status register (SR) and program counter (PC) values.

2.2.2 Control Registers

There are three 32-bit control registers, designated status register (SR), global base register

(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base

address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.

VBR is used as a base address of the exception handling (including interrupts) vector table.

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• Status register (SR)

Bit

name Default

Read/

Write Description

31 to 10  All 0 R/W Reserved

These bits are always read as 0. The write value

should always be 0.

9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.

8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions.

R/W

Interrupt Mask

3, 2  All 0 R/W Reserved

These bits are always read as 0. The write value

should always be 0.

1 S Undefined R/W S

Used by the multiply and accumulate instruction.

0 T Undefined R/W T

Indicates true (1) or false (0) in the following

instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S),

BF (BF/S), SETT, CLRT

Indicates carry, borrow, overflow, or underflow in the

following instructions: ADDV, ADDC, SUBV, SUBC,

NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,

SHLL, ROTR, ROTL, ROTCR, ROTCL

• Global-base register (GBR)

This register indicates a base address in GBR indirect addressing mode. The GBR indirect

addressing mode is used for data transfer of the on-chip peripheral module registers and logic

operations.

• Vector-base register (VBR)

This register indicates the base address of the exception handling vector table.

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2.2.3 System Registers

There are four 32-bit system registers, designated two multiply and accumulate registers (MACH

and MACL), a procedure register (PR), and program counter (PC).

• Multiply and accumulate registers (MAC)

This register stores the results of multiplication and multiply-and-accumulate operation.

• Procedure register (PR)

This register stores the return-destination address from subroutine procedures.

• Program counter (PC)

The PC indicates the point which is four bytes (two instructions) after the current execution

instruction.

2.2.4 Initial Values of Registers

Table 2.1 lists the initial values of registers after a reset.

Table 2.1 Initial Values of Registers

Type of register Register Default

General register R0 to R14 Undefined

R15 (SP) SP value set in the exception handling vector table

Control register SR I3 to I0: 1111 (H'F)

Reserved bits: 0

Other bits: Undefined

GBR Undefined

VBR H'00000000

System register MACH, MACL, PR Undefined

PC PC value set in the exception handling vector table

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2.3 Data Formats

2.3.1 Register Data Format

The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word

(16 bits) data in memory into a register, the data is sign-extended to longword and stored in the

Longword

31 0

Figure 2.2 Register Data Format

2.3.2 Memory Data Formats

Memory data formats are classified into byte, word, and longword.

Byte data can be accessed from any address. If word data starting from boundary other than 2n or

longword data starting from a boundary other than 4n is accessed, an address error will occur. In

such cases, the data accessed cannot be guaranteed. See figure 2.3.

Byte 0 Byte 1 Byte 2 Byte 3

Word 0 Word 1

Longword

Big endian

31 23 15 7

Address A + 1

Address A + 4

Address A + 8

Address A

Address A + 3

Address A + 2

Byte 3 Byte 2 Byte 1 Byte 0

Word 1 Word 0

Longword

Little endian

31 23 15 7

Address A + 10

Address A + 4

Address A + 8

Address A + 11

Address A

Address A + 8

Address A + 9

Figure 2.3 Memory Data Format

Either big endian and little endian formats can be selected according to the mode pin setting at a

reset. For details on mode pin settings, see section 7, Bus State Controller (BSC).

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2.3.3 Immediate Data Formats

Immediate data of eight bits is placed in the instruction code.

For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword

and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero-

extended to longword and then calculated. Thus, if the immediate data is used for the AND

instruction, the upper 24 bits in the destination register are always cleared.

The immediate data of word or longword is not placed in the instruction code. It is placed in a

table in memory. The table in memory is accessed by the MOV immediate data instruction in PC

relative addressing mode with displacement.

2.4 Features of Instructions

2.4.1 RISC Type

The instructions are RISC-type instructions with the following features:

Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code

efficiency.

One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one

cycle. One cycle is 25ns with 40 MHz operation.

Data Size: The basic data size for operations is longword. Byte, word, or longword can be

selected as the memory access size. Byte or word data in memory is sign-extended to longword

and then calculated. Immediate data is sign-extended to longword for arithmetic operations or

zero-extended to longword size for logical operations.

Table 2.2 Word Data Sign Extension

CPU in this LSI Description Example of Other CPUs

MOV.W @(disp,PC),R1

ADD R1,R0

........

.DATA.W H'1234

Sign-extended to 32 bits, R1

becomes H'00001234, and is

then operated on by the ADD

instruction.

ADD.W #H'1234,R0

Note: * Immediate data is accessed by @(disp,PC).

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Load/Store Architecture: Basic operations are executed between registers. In operations

involving memory, data is first loaded into a register (load/store architecture). However, bit

manipulation instructions such as AND are executed directly in memory.

Delayed Branching: Unconditional branch instructions mean the delayed branch instructions.

With a delayed branch instruction, the branch is made after execution of the instruction

immediately following the delayed branch instruction. This minimizes disruption of the pipeline

when a branch is made. The conditional branch instructions have two types of instructions:

conditional branch instructions and delayed branch instructions.

Table 2.3 Delayed Branch Instructions

CPU in this LSI Description Example of Other CPUs

BRA TRGET

ADD R1,R0

ADD is executed before branch to TRGET. ADD.W R1,R0

BRA TRGET

Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is

executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two

to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and-

accumulate operation are each executed in two to four cycles.

T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is

performed according to whether the result is True or False. Processing speed has been improved

by keeping the number of instructions that modify the T bit to a minimum.

Table 2.4 T Bit

CPU in this LSI Description Example of Other CPUs

CMP/GE R1,R0 When R0 ≥ R1, the T bit is set. CMP.W R1,R0

BT TRGET0 When R0 ≥ R1, a branch is made to TRGET0. BGE TRGET0

BF TRGET1 When R0 < R1, a branch is made to TRGET1. BLT TRGET1

ADD #−1,R0 The T bit is not changed by ADD. SUB.W #1,R0

CMP/EQ #0,R0 When R0 = 0, the T bit is set. BEQ TRGET

BT TRGET A branch is made when R0 = 0.

Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword

immediate data is not placed in the instruction code. It is placed in a table in memory. The table in

memory is accessed with the MOV immediate data instruction using PC relative addressing mode

with displacement.

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Table 2.5 Access to Immediate Data

Type This LSI′s CPU Example of Other CPU

8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0

16-bit immediate MOV.W @(disp,PC),R0

........

.DATA.W H'1234

MOV.W #H'1234,R0

32-bit immediate MOV.L @(disp,PC),R0

........

.DATA.L H'12345678

MOV.L

#H'12345678,

Note: * Immediate data is accessed by @(disp,PC).

Absolute Addresses: When data is accessed by absolute address, place the absolute address value

in a table in memory beforehand. The absolute address value is transferred to a register using the

method whereby immediate data is loaded when an instruction is executed, and the data is

accessed using the register indirect addressing mode.

Table 2.6 Access to Absolute Address

Type CPU in this LSI Example of Other CPUs

Absolute address MOV.L @(disp,PC),R1

MOV.B @R1,R0

........

.DATA.L H'12345678

MOV.B

@H'12345678,

Note: * Immediate data is referenced by @(disp,PC).

16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement

addressing mode, the displacement value is placed in a table in memory beforehand. Using the

method whereby immediate data is loaded when an instruction is executed, this value is

transferred to a register and the data is accessed using index register indirect addressing mode.

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Table 2.7 Access with Displacement

Type CPU in this LSI Example of Other CPUs

16-bit displacement MOV.W @(disp,PC),R0

MOV.W @(R0,R1),R2

........

.DATA.W H'1234

MOV.W

@(H'1234,R1),

Note: * Immediate data is referenced by @(disp,PC).

2.4.2 Addressing Modes

Table 2.8 lists addressing modes and effective address calculation methods.

Table 2.8 Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format Effective Address Calculation Method

Calculation

Formula

direct

Rn Effective address is register Rn.

(Operand is register Rn contents.)



indirect

@Rn Effective address is register Rn contents.

Rn Rn

indirect with

post-increment

@Rn+ Effective address is register Rn contents. A

constant is added to Rn after instruction

execution: 1 for a byte operand, 2 for a word

operand, 4 for a longword operand.

Rn Rn

1/2/4

Rn + 1/2/4

After instruction

execution

Byte: Rn + 1 →

Word: Rn + 2 →

Longword: Rn + 4

→ Rn

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Addressing

Mode

Instruction

Format Effective Address Calculation Method

Calculation

Formula

indirect with

pre-decrement

@–Rn Effective address is register Rn contents,

decremented by a constant beforehand: 1 for a

byte operand, 2 for a word operand, 4 for a

longword operand.

Rn - 1/2/4

1/2/4

Rn - 1/2/4

Byte: Rn – 1 →

Word: Rn – 2 →

Longword: Rn – 4

→ Rn

(Instruction

executed with Rn

after calculation)

indirect with

displacement

@(disp:4,

Rn)

Effective address is register Rn contents with

4-bit displacement disp added. After disp is

zero-extended, it is multiplied by 1 (byte), 2

(word), or 4 (longword), according to the

operand size.

1/2/4

disp

(zero-extended)

+ disp × 1/2/4

Byte: Rn + disp

Word: Rn + disp ×

Longword: Rn +

disp × 4

Index

@(R0, Rn) Effective address is sum of register Rn and R0

contents.

Rn + R0

GBR indirect

with

displacement

@(disp:8,

GBR)

Effective address is register GBR contents with

8-bit displacement disp added. After disp is

zero-extended, it is multiplied by 1 (byte), 2

(word), or 4 (longword), according to the

operand size.

GBR

1/2/4

disp

(zero-extended)

GBR

+ disp × 1/2/4

Byte: GBR + disp

Word: GBR + disp

× 2

Longword: GBR +

disp × 4

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Addressing

Mode

Instruction

Format Effective Address Calculation Method

Calculation

Formula

Index GBR

indirect

@(R0,

GBR)

Effective address is sum of register GBR and

R0 contents.

GBR

GBR + R0

PC relative with

displacement

@(disp:8,

PC)

Effective address is PC with 8-bit displacement

disp added. After disp is zero-extended, it is

multiplied by 2 (word) or 4 (longword), according

to the operand size. With a longword operand,

the lower 2 bits of PC are masked.

PC + disp × 2

PC&

H'FFFFFFFC

+ disp × 4

H'FFFFFFFC

2/4

disp

(zero-extended)

*With longword operand

Word: PC + disp

× 2

Longword:

PC&H'FFFFFFFC

+ disp × 4

PC relative disp:8 Effective address is PC with 8-bit displacement

disp added after being sign-extended and

multiplied by 2.

disp

(sign-extended) PC + disp × 2

PC + disp × 2

disp:12 Effective address is PC with 12-bit displacement

disp added after being sign-extended and

multiplied by 2.

disp

(sign-extended) PC + disp × 2

PC + disp × 2

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Addressing

Mode

Instruction

Format Effective Address Calculation Method

Calculation

Formula

PC relative Rn Effective address is sum of PC and Rn.

PC + Rn

Immediate #imm:8 8-bit immediate data imm of TST, AND, OR,

or XOR instruction is zero-extended.



#imm:8 8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.



#imm:8 8-bit immediate data imm of TRAPA instruction

is zero-extended and multiplied by 4.



2.4.3 Instruction Formats

This section describes the instruction formats, and the meaning of the source and destination

operands. The meaning of the operands depends on the instruction code. The following symbols

are used in the table.

xxxx: Instruction code

mmmm: Source register

nnnn: Destination register

iiii: Immediate data

dddd: Displacement

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Table 2.9 Instruction Formats

Instruction Format Source Operand

Destination

Operand Sample Instruction

0 type

xxxx xxxx xxxx xxxx

15 0

  NOP

 nnnn: register

direct

MOVT Rn

Control register or

system register

nnnn: register

direct

STS MACH,Rn

n type

xxxx nnnn xxxx xxxx

15 0

Control register or

system register

nnnn: pre-

decrement register

indirect

STC.L SR,@-Rn

mmmm: register

direct

Control register or

system register

LDC Rm,SR

mmmm: post-

increment register

indirect

Control register or

system register

LDC.L @Rm+,SR

mmmm: register

indirect

 JMP @Rm

m type

xxxx mmmm xxxx xxxx

15 0

PC relative using

 BRAF Rm

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Instruction Format Source Operand

Destination

Operand Sample Instruction

mmmm: register

direct

nnnn: register

direct

ADD Rm,Rn

mmmm: register

direct

nnnn: register

indirect

MOV.L Rm,@Rn

mmmm: post-

increment register

indirect (multiply-

and-accumulate

operation)

nnnn: * post-

increment register

indirect (multiply-

and-accumulate

operation)

MACH, MACL MAC.W @Rm+,@Rn+

mmmm: post-

increment register

indirect

nnnn: register

direct

MOV.L @Rm+,Rn

mmmm: register

direct

nnnn: pre-

decrement register

indirect

MOV.L Rm,@-Rn

nm type

xxxx nnnn mmmm xxxx

15 0

mmmm: register

direct

nnnn: index

MOV.L Rm,@(R0,Rn)

md type

xxxx xxxx mmmm dddd

15 0

mmmmdddd:

with displacement

R0 (register direct) MOV.B @(disp,Rm),R0

nd4 type

xxxx xxxx nnnn dddd

15 0

R0 (register direct) nnnndddd:

with displacement

MOV.B R0,@(disp,Rn)

mmmm: register

direct

nnnndddd:

with displacement

MOV.L Rm,@(disp,Rn) nmd type

xxxx nnnn mmmm dddd

15 0

mmmmdddd:

with displacement

nnnn: register

direct

MOV.L @(disp,Rm),Rn

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Instruction Format Source Operand

Destination

Operand Sample Instruction

dddddddd: GBR

indirect with

displacement

R0 (register direct) MOV.L

@(disp,GBR),R0

R0 (register direct) dddddddd: GBR

indirect with

displacement

MOV.L

R0,@(disp,GBR)

dddddddd:

PC relative with

displacement

R0 (register direct) MOVA @(disp,PC),R0

d type

xxxx xxxx dddd dddd

15 0

 dddddddd:

PC relative

BF label

d12 type

xxxx dddd dddd dddd

15 0

 dddddddddddd:

PC relative

BRA label

(label=disp+PC)

nd8 type

xxxx nnnn dddd dddd

15 0

dddddddd: PC

relative with

displacement

nnnn: register

direct

MOV.L @(disp,PC),Rn

iiiiiiii:

immediate

Index GBR indirect AND.B

#imm,@(R0,GBR)

iiiiiiii:

immediate

R0 (register direct) AND #imm,R0

i type

xxxx xxxx iiii iiii

15 0

iiiiiiii:

immediate

 TRAPA #imm

ni type

xxxx nnnn iiii iiii

15 0

iiiiiiii:

immediate

nnnn: register

direct

ADD #imm,Rn

Note: * In multiply and accumulate instructions, nnnn is the source register.

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2.5 Instruction Set

2.5.1 Instruction Set by Type

Table 2.10 lists the instructions classified by type.

Table 2.10 Instruction Types

Type

Kinds of

Instruction Op Code Function

Number of

Instructions

MOV Data transfer

Immediate data transfer

Peripheral module data transfer

Structure data transfer

MOVA Effective address transfer

MOVT T bit transfer

SWAP Upper/lower swap

Data transfer

instructions

XTRCT Extraction of middle of linked registers

ADD Binary addition

ADDC Binary addition with carry

ADDV Binary addition with overflow

CMP/cond Comparison

DIV1 Division

DIV0S Signed division initialization

DIV0U Unsigned division initialization

DMULS Signed double-precision multiplication

DMULU Unsigned double-precision

multiplication

DT Decrement and test

EXTS Sign extension

EXTU Zero extension

MAC Multiply-and-accumulate, double-

precision multiply-and-accumulate

Arithmetic

operation

instructions

MUL Double-precision multiplication

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Type

Kinds of

Instruction Op Code Function

Number of

Instructions

MULS Signed multiplication

MULU Unsigned multiplication

NEG Sign inversion

NEGC Sign inversion with borrow

SUB Binary subtraction

SUBC Binary subtraction with carry

Arithmetic

operation

instructions

SUBV Binary subtraction with underflow

AND Logical AND

NOT Bit inversion

OR Logical OR

TAS Memory test and bit setting

TST T bit setting for logical AND

Logic

operation

instructions

XOR Exclusive logical OR

ROTL 1-bit left shift

ROTR 1-bit right shift

ROTCL 1-bit left shift with T bit

ROTCR 1-bit right shift with T bit

SHAL Arithmetic 1-bit left shift

SHAR Arithmetic 1-bit right shift

SHLL Logical 1-bit left shift

SHLLn Logical n-bit left shift

SHLR Logical 1-bit right shift

Shift

instructions

SHLRn Logical n-bit right shift

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Type

Kinds of

Instruction Op Code Function

Number of

Instructions

BF Conditional branch, delayed conditional

branch (T = 0)

BT Conditional branch, delayed conditional

branch (T = 1)

BRA Unconditional branch

BRAF Unconditional branch

BSR Branch to subroutine procedure

BSRF Branch to subroutine procedure

JMP Unconditional branch

JSR Branch to subroutine procedure

Branch

instructions

RTS Return from subroutine procedure

CLRT T bit clear

CLRMAC MAC register clear

LDC Load into control register

LDS Load into system register

NOP No operation

RTE Return from exception handling

SETT T bit setting

SLEEP Transition to power-down mode

STC Store from control register

STS Store from system register

System

control

instructions

TRAPA Trap exception handling

Total: 62 142

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The instruction code, operation, and execution cycles of the instructions are listed in the following

tables, classified by type.

Instruction Instruction Code

Summary of

Operation

Execution

Cycles T Bit

Indicated by mnemonic.

Explanation of Symbols

OP.Sz SRC, DEST

OP: Operation code

Sz: Size

SRC: Source

DEST: Destination

Rm: Source register

Rn: Destination

imm: Immediate data

disp: Displacement*2

Indicated in MSB ↔

LSB order.

Explanation of Symbols

mmmm: Source register

nnnn: Destination

0000: R0

0001: R1

.........

1111: R15

iiii: Immediate data

dddd: Displacement

Indicates summary of

operation.

Explanation of Symbols

→, ←: Transfer direction

(xx): Memory operand

M/Q/T: Flag bits in SR

&: Logical AND of each bit

|: Logical OR of each bit

^: Exclusive logical OR of

each bit

–: Logical NOT of each bit

<<n: n-bit left shift

>>n: n-bit right shift

Value when no

wait cycles are

inserted*1

Value of T bit after

instruction is

executed

Explanation of

Symbols

: No change

Notes: 1. The table shows the minimum number of execution states. In practice, the number of

instruction execution states will be increased in cases such as the following:

• When there is contention between an instruction fetch and a data access

• When the destination register of a load instruction (memory → register) is also

used by the following instruction

2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc.

For details, see SH-1/SH-2/SH-DSP Software Manual.

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• Data Transfer Instructions

Instruction Operation Code

Execution

Cycles T Bit

MOV #imm,Rn imm → Sign extension

→ Rn

1110nnnniiiiiiii 1 

MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign

extension → Rn

1001nnnndddddddd 1 

MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd 1 

MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 1 

MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 1 

MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 1 

MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 1 

MOV.B @Rm,Rn (Rm) → Sign extension

→ Rn

0110nnnnmmmm0000 1 

MOV.W @Rm,Rn (Rm) → Sign extension

→ Rn

0110nnnnmmmm0001 1 

MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 1 

MOV.B Rm,@–Rn Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 1 

MOV.W Rm,@–Rn Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 1 

MOV.L Rm,@–Rn Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1 

MOV.B @Rm+,Rn (Rm) → Sign extension

→ Rn, Rm + 1 → Rm

0110nnnnmmmm0100 1 

MOV.W @Rm+,Rn (Rm) → Sign extension

→ Rn, Rm + 2 → Rm

0110nnnnmmmm0101 1 

MOV.L @Rm+,Rn (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 1 

MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd 1 

MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd 1 

MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1 

MOV.B @(disp,Rm),R0 (disp + Rm) → Sign

extension → R0

10000100mmmmdddd 1 

MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign

extension → R0

10000101mmmmdddd 1 

MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1 

MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 1 

MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 1 

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Instruction Operation Code

Execution

Cycles T Bit

MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 1 

MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign

extension → Rn

0000nnnnmmmm1100 1 

MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign

extension → Rn

0000nnnnmmmm1101 1 

MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 1 

MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd 1 

MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1 

MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1 

MOV.B @(disp,GBR),R0 (disp + GBR) → Sign

extension → R0

11000100dddddddd 1 

MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →

Sign extension → R0

11000101dddddddd 1 

MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1 

MOVA @(disp,PC),R0 disp × 4 + PC → R0 11000111dddddddd 1 

MOVT Rn T → Rn 0000nnnn00101001 1 

SWAP.B Rm,Rn Rm → Swap lowest two

bytes → Rn

0110nnnnmmmm1000 1 

SWAP.W Rm,Rn Rm → Swap two

consecutive words → Rn

0110nnnnmmmm1001 1 

XTRCT Rm,Rn Rm: Middle 32 bits of

Rn → Rn

0010nnnnmmmm1101 1 

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• Arithmetic Operation Instructions

Instruction Operation Code

Execution

Cycles T Bit

ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 1 

ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii 1 

ADDC Rm,Rn Rn + Rm + T → Rn,

Carry → T

0011nnnnmmmm1110 1 Carry

ADDV Rm,Rn Rn + Rm → Rn,

Overflow → T

0011nnnnmmmm1111 1 Overflow

CMP/EQ #imm,R0 If R0 = imm, 1 → T 10001000iiiiiiii 1 Comparison

result

CMP/EQ Rm,Rn If Rn = Rm, 1 → T 0011nnnnmmmm0000 1 Comparison

result

CMP/HS Rm,Rn If Rn ≥ Rm with

unsigned data, 1 → T

0011nnnnmmmm0010 1 Comparison

result

CMP/GE Rm,Rn If Rn ≥ Rm with signed

data, 1 → T

0011nnnnmmmm0011 1 Comparison

result

CMP/HI Rm,Rn If Rn > Rm with

unsigned data, 1 → T

0011nnnnmmmm0110 1 Comparison

result

CMP/GT Rm,Rn If Rn > Rm with signed

data, 1 → T

0011nnnnmmmm0111 1 Comparison

result

CMP/PZ Rn If Rn ≥ 0, 1 → T 0100nnnn00010001 1 Comparison

result

CMP/PL Rn If Rn > 0, 1 → T 0100nnnn00010101 1 Comparison

result

CMP/STR Rm,Rn If Rn and Rm have an

equivalent byte, 1 → T

0010nnnnmmmm1100 1 Comparison

result

DIV1 Rm,Rn Single-step division

(Rn/Rm)

0011nnnnmmmm0100 1 Calculation

result

DIV0S Rm,Rn MSB of Rn → Q, MSB

of Rm → M, M^ Q → T

0010nnnnmmmm0111 1 Calculation

result

DIV0U 0 → M/Q/T 0000000000011001 1 0

DMULS.L Rm,Rn Signed operation of

Rn × Rm → MACH,

MACL 32 × 32 → 64 bits

0011nnnnmmmm1101 2 to 5* 

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Instruction Operation Code

Execution

Cycles T Bit

DMULU.L Rm,Rn Unsigned operation of

Rn × Rm → MACH,

MACL 32 × 32 → 64 bits

0011nnnnmmmm0101 2 to 5* 

DT Rn Rn - 1 → Rn, if Rn = 0, 1 →

T, else 0 → T

0100nnnn00010000 1 Comparison

result

EXTS.B Rm,Rn A byte in Rm is sign-

extended → Rn

0110nnnnmmmm1110 1 

EXTS.W Rm,Rn A word in Rm is sign-

extended → Rn

0110nnnnmmmm1111 1 

EXTU.B Rm,Rn A byte in Rm is zero-

extended → Rn

0110nnnnmmmm1100 1 

EXTU.W Rm,Rn A word in Rm is zero-

extended → Rn

0110nnnnmmmm1101 1 

MAC.L @Rm+,@Rn+ Signed operation of (Rn)

× (Rm) + MAC → MAC,

32 × 32 + 64 → 64 bits

0000nnnnmmmm1111 2 to 5* 

MAC.W @Rm+,@Rn+ Signed operation of (Rn)

× (Rm) + MAC → MAC,

16 × 16 + 64 → 64 bits

0100nnnnmmmm1111 2 to 4* 

MUL.L Rm,Rn Rn × Rm → MACL

32 × 32 → 32 bits

0000nnnnmmmm0111 2 to 5* 

MULS.W Rm,Rn Signed operation of Rn

× Rm → MAC

16 × 16 → 32 bits

0010nnnnmmmm1111 1 (3)* 

MULU.W Rm,Rn Unsigned operation of

Rn × Rm → MAC

16 × 16 → 32 bits

0010nnnnmmmm1110 1 (3)* 

NEG Rm,Rn 0-Rm → Rn 0110nnnnmmmm1011 1 

NEGC Rm,Rn 0-Rm-T → Rn,

Borrow → T

0110nnnnmmmm1010 1 Borrow

SUB Rm,Rn Rn-Rm → Rn 0011nnnnmmmm1000 1 

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Instruction Operation Code

Execution

Cycles T Bit

SUBC Rm,Rn Rn-Rm–T → Rn,

Borrow → T

0011nnnnmmmm1010 1 Borrow

SUBV Rm,Rn Rn-Rm → Rn,

Underflow → T

0011nnnnmmmm1011 1 Overflow

Note: * Indicates the number of execution cycles for normal operation. The values in

parentheses indicate the number of execution cycles when conflicts occur with the

previous or next instruction.

• Logic Operation Instructions

Instruction Operation Code

Execution

Cycles T Bit

AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 1 

AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1 

AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →

(R0 + GBR)

11001101iiiiiiii 3 

NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 1 

OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1 

OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1 

OR.B #imm,@(R0,GBR) (R0 + GBR) | imm →

(R0 + GBR)

11001111iiiiiiii 3 

TAS.B @Rn If (Rn) is 0, 1 → T;

1 → MSB of (Rn)

0100nnnn00011011 4 Test result

TST Rm,Rn Rn & Rm; if the result

is 0, 1 → T

0010nnnnmmmm1000 1 Test result

TST #imm,R0 R0 & imm; if the result

is 0, 1 → T

11001000iiiiiiii 1 Test result

TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;

if the result is 0, 1 → T

11001100iiiiiiii 3 Test result

XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 1 

XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii 1 

XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm →

(R0 + GBR)

11001110iiiiiiii 3 

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• Shift Instructions

Instruction Operation Code

Execution

Cycles T Bit

ROTL Rn T ← Rn ← MSB 0100nnnn00000100 1 MSB

ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB

ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB

ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB

SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB

SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB

SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB

SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB

SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 1 

SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 1 

SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 1 

SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 1 

SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 1 

SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 1 

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• Branch Instructions

Instruction Operation Code

Execution

Cycles T Bit

BF label If T = 0, disp × 2 + PC →

PC;

if T = 1, nop

10001011dddddddd 3/1* 

BF/S label Delayed branch, if T = 0,

disp × 2 + PC → PC;

if T = 1, nop

10001111dddddddd 2/1* 

BT label If T = 1, disp × 2 + PC →

PC;

if T = 0, nop

10001001dddddddd 3/1* 

BT/S label Delayed branch, if T = 1,

disp × 2 + PC → PC;

if T = 0, nop

10001101dddddddd 2/1* 

BRA label Delayed branch,

disp × 2 + PC → PC

1010dddddddddddd 2 

BRAF Rm Delayed branch,

Rm + PC → PC

0000mmmm00100011 2 

BSR label Delayed branch, PC → PR,

disp × 2 + PC → PC

1011dddddddddddd 2 

BSRF Rm Delayed branch, PC → PR,

Rm + PC → PC

0000mmmm00000011 2 

JMP @Rm Delayed branch, Rm → PC 0100mmmm00101011 2 

JSR @Rm Delayed branch, PC → PR,

Rm → PC

0100mmmm00001011 2 

RTS Delayed branch, PR → PC 0000000000001011 2 

Note: * One cycle when the branch is not executed.

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• System Control Instructions

Instruction Operation Code

Execution

Cycles T Bit

CLRT 0 → T 0000000000001000 1 0

CLRMAC 0 → MACH, MACL 0000000000101000 1 

LDC Rm,SR Rm → SR 0100mmmm00001110 6 LSB

LDC Rm,GBR Rm → GBR 0100mmmm00011110 4 

LDC Rm,VBR Rm → VBR 0100mmmm00101110 4 

LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 8 LSB

LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 →

0100mmmm00010111 4 

LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 →

0100mmmm00100111 4 

LDS Rm,MACH Rm → MACH 0100mmmm00001010 1 

LDS Rm,MACL Rm → MACL 0100mmmm00011010 1 

LDS Rm,PR Rm → PR 0100mmmm00101010 1 

LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 →

0100mmmm00000110 1 

LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 →

0100mmmm00010110 1 

LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1 

NOP No operation 0000000000001001 1 

RTE Delayed branch,

Stack area → PC/SR

0000000000101011 5 

SETT 1 → T 0000000000011000 1 1

SLEEP Sleep 0000000000011011 4* 

STC SR,Rn SR → Rn 0000nnnn00000010 1 

STC GBR,Rn GBR → Rn 0000nnnn00010010 1 

STC VBR,Rn VBR → Rn 0000nnnn00100010 1 

STC.L SR,@–Rn Rn–4 → Rn, SR → (Rn) 0100nnnn00000011 1 

STC.L GBR,@–Rn Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 1 

STC.L VBR,@–Rn Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 1 

STS MACH,Rn MACH → Rn 0000nnnn00001010 1 

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Instruction Operation Code

Execution

Cycles T Bit

STS MACL,Rn MACL → Rn 0000nnnn00011010 1 

STS PR,Rn PR → Rn 0000nnnn00101010 1 

STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1 

STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1 

STS.L PR,@–Rn Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 1 

TRAPA #imm PC/SR → Stack area,

(imm × 4 + VBR) → PC

11000011iiiiiiii 8 

Note: * Number of execution cycles until this LSI enters sleep mode.

About the number of execution cycles:

The table lists the minimum number of execution cycles. In practice, the number of

execution cycles will be increased depending on the conditions such as:

• When there is a conflict between instruction fetch and data access

• When the destination register of a load instruction (memory → register) is also used

by the instruction immediately after the load instruction.

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2.6 Processing States

2.6.1 State Transition

The CPU has the four processing states: reset, exception handling, program execution, and power-

down. Figure 2.4 shows the CPU state transition. Note that some products do not support the

manual reset function and the MRES pin.

Software standby mode

RES = 0

in any state

RES = 1 and MRES = 0

in any state

Power-on reset state Manual reset state

Reset state

Request for internal power-on reset

or internal manual reset by the WDT

Exception handling state

Request for

exception handling End of

exception handling

Program execution state

SLEEP instruction by

clearing SSBY bit SLEEP instruction by

setting SSBY bit

Sleep mode

Request for NMI

or IRQ interrupt

Power-down mode

Figure 2.4 CPU State Transition

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• Reset state

The CPU is reset. When the RES pin is driven low, the CPU enters the power-on reset state.

When the RES pin is high and MRES pin is low, the CPU enters the manual reset state.

• Exception handling state

This state is a transitional state in which the CPU processing state changes due to a request for

exception handling such as a reset or an interrupt.

When a reset occurs, the execution start address as the initial value of the program counter

(PC) and the initial value of the stack pointer (SP) are fetched from the exception handling

vector table. Then, a branch is made for the start address to execute a program.

When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to

by SP. The start address of an exception handling routine is fetched from the exception

handling vector table and a branch to the address is made to execute a program.

Then the processing state enters the program execution state.

• Program execution state

The CPU executes programs sequentially.

• Power-down state

The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter

sleep mode or software standby mode.

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Section 3 Cache

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Section 3 Cache

3.1 Features

• Capacity: 16 kbytes

• Structure: Instructions/data unified, 4-way set associative

• Line size: 16 bytes

• Number of entries: 256 entries/way in 4-kbyte mode

• Write method: Write-back/write-through is selectable

• Replacement method: Least-recently-used (LRU) algorithm

3.1.1 Cache Structure

The cache holds both instructions and data and employs a 4-way set associative system. It is

composed of four ways (banks), and each of which is divided into an address section and a data

section. Each of the address and data sections is divided into 256 entries. The data of an entry is

called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes

(16 bytes × 256 entries), with a total of 16 kbytes in the cache (4 ways).

Figure 3.1 shows the cache structure.

24 (1 + 1 + 22) bits 128 (32 × 4) bits 6 bits

LW0 to LW3: Longword data 0 to 3

Entry 0

Entry 1

Entry 255

255

V U Tag address LW0 LW1 LW2 LW3

Address array (ways 0 to 3) Data array (ways 0 to 3) LRU

Figure 3.1 Cache Structure

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Address Array: The V bit indicates whether or not the entry data is valid. When the V bit is 1,

data is valid; when 0, data is not valid. The U bit indicates whether or not the entry has been

written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has

not. The tag address is composed of 22 bits (address bits 31 to 10) used for comparison during

cache searches.

In this LSI, the upper three bits of 32 address bits are used as shadow bits (see section 7, Bus State

Controller (BSC)), therefore, the upper three bits of the tag address are cleared to 0.

The V and U bits are initialized to 0 by a power-on reset. The tag address is not initialized by a

power-on reset.

Data Array: Holds 16-byte instruction and data. Entries are registered in the cache in line units

(16 bytes). The data array is not initialized by a power-on reset.

LRU: With the 4-way set associative system, up to four instructions or data with the same entry

address can be registered in the cache. When an entry is registered, LRU shows which of the four

ways it is registered in. There are six LRU bits, controlled by hardware. The least-recently-used

(LRU) algorithm is used to select the way.

When a cache miss occurs, six LRU bits indicate the way to be replaced. If a bit pattern other than

those listed in table 3.1 is set in the LRU bits by software, the cache will not function correctly.

When changing the LRU bits by software, set one of the patterns listed in table 3.1.

The LRU bits are initialized to 000000 by a power-on reset.

Table 3.1 LRU and Way to be Replaced

LRU (Bits 5 to 0) Way to be Replaced

000000, 000100, 010100, 100000, 110000, 110100 3

000001, 000011, 001011, 100001, 101001, 101011 2

000110, 000111, 001111, 010110, 011110, 011111 1

111000, 111001, 111011, 111100, 111110, 111111 0

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3.1.2 Divided Areas and Cache

A 4-G byte address space is divided into five areas with the architecture of this LSI. The cache

access methods can be specified for each area. Table 3.2 lists the correspondence between the

divided areas and cache.

Table 3.2 Correspondence between Divided Areas and Cache

Address Area Cacheable Cache Operating

Control

H'00000000 to H'7FFFFFFF P0 Cacheable WT bit in CCR1

H'80000000 to H'9FFFFFFF P1 Cacheable CB bit in CCR1

H'A0000000 to H'BFFFFFFF P2 Non cacheable 

H'C0000000 to H'DFFFFFFF P3 Cacheable WT bit in CCR1

H'E0000000 to H'FFFFFFFF P4 Non cacheable (internal I/O) 

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3.2 Register Descriptions

The cache has the following registers. For details on register addresses and register states during

each process, refer to section 18, List of Registers.

• Cache control register 1 (CCR1)

• Cache control register 3 (CCR3)

3.2.1 Cache Control Register 1 (CCR1)

The cache is enabled or disabled by the CE bit in CCR1. CCR1 also has the CF bit (which

invalidates all cache entries), and the WT and CB bits (which select either write-through mode or

write-back mode). Programs that change the contents of CCR1 should be placed in the address

space that is not cached.

Bit Bit Name

Initial

Value R/W Description

31 to 4 — All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

3 CF 0 R/W Cache Flush

Writing 1 flushes all cache entries meaning that it

clears the V, U, and LRU bits of all cache entries to

0. This bit is always read as 0. Write-back to

external memory is not performed when the cache is

flushed.

2 CB 0 R/W Write-Back

Indicates the cache operating mode for H'80000000

to H'9FFFFFFF.

0: Write-through mode

1: Write-back mode

1 WT 0 R/W Write-Through

Indicates the cache operating mode for H'00000000

to H'7FFFFFFF and H'C0000000 to H'DFFFFFFF.

0: Write-back mode

1: Write-through mode

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Bit Bit Name

Initial

Value R/W Description

0 CE 0 R/W Cache Enable

Indicates whether or not the cache function is used.

0: Cache function is not used.

1: Cache function is used.

3.2.2 Cache Control Register 3 (CCR3)

CCR3 specifies the cache size. Programs that change the contents of CCR3 should be placed in the

address space that is not cached.

Bit Bit Name

Initial

Value R/W Description

31 to 17 — All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

CSIZE2

CSIZE1

CSIZE0

R/W

Cache Size

Writing B'100 to these bits specifies the cache size

16 Kbytes. Write B'100 before enabling the cache by

the CE bit in CCR1.

13 to 0 — All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

3.3 Operation

3.3.1 Searching Cache

If the cache is enabled (the CE bit in CCR1 is set to 1), whenever an instruction or data in

H'00000000 to H'7FFFFFFF, H'8000000 to H'9FFFFFFF, and H'C0000000 to H'DFFFFFFF is

accessed, the cache will be searched to see if the desired instruction or data is in the cache. Figure

3.2 illustrates the method by which the cache is searched.

Entries are selected using bits 11 to 4 of the memory access address and the tag address of that

entry is read. The address comparison is performed on all four ways. When the comparison shows

a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not

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show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 3.2 shows a hit

on way 1.

255

V U Tag address LW0 LW1 LW2 LW3

Ways 0 to 3 Ways 0 to 3

31 12 11 4 3 2 1 0

Address

CMP0 CMP1 CMP2 CMP3

CMP0: Comparison circuit 0

CMP1: Comparison circuit 1

CMP2: Comparison circuit 2

CMP3: Comparison circuit 3

Hit signal 1

Entry selection Longword (LW) selection

Figure 3.2 Cache Search Scheme

3.3.2 Read Access

Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The

LRU bits are updated so that they point to the most recently hit way.

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Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown

in table 3.1. Data is updated in units of 16 bytes by updating the entry. When the desired

instruction or data is loaded from external memory to the cache, the instruction or data is

transferred to the CPU in parallel. When it is loaded to the cache, the U bit is cleared to 0, the V

bit is set to 1, the LRU bits are updated so that they point to the most recently hit way. When the U

bit of the entry which is to be replaced by entry updating in write-back mode is 1, the cache-

update cycle starts after the entry is transferred to the write-back buffer. After the cache completes

its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte

units.

3.3.3 Write Access

Write Hit: In a write access in write-back mode, the data is written to the cache and no external

memory write cycle is generated. The U bit of the entry that has been written to is set to 1, and the

LRU bits are updated to indicate that the hit way is the most recently hit way. In write-through

mode, the data is written to the cache and an external memory write cycle is generated. The U bit

of the entry that has been written to is not updated, and the LRU bits are updated to indicate that

the hit way is the most recently hit way.

Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the

entry is updated. The way to be replaced is shown in table 3.1. When the U bit of the entry which

is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been

transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set

to 1. The LRU bits are updated to indicate that the replaced way is the most recently updated way.

After the cache has completed its update cycle, the write-back buffer writes the entry back to the

memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write

miss; the write is only to the external memory.

3.3.4 Write-Back Buffer

When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back

to the external memory. To increase performance, the entry to be replaced is first transferred to the

write-back buffer and fetching of new entries to the cache takes priority over writing back to the

external memory. After the fetching of new entries to the cache completes, the write-back buffer

writes the entry back to the external memory. During the write-back cycles, the cache can be

accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical

address. Figure 3.3 shows the configuration of the write-back buffer.

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Longword 0 Longword 1 Longword 2 Longword 3PA (31 to 4)

PA (31 to 4):

Longword 0 to 3:

Physical address to be written to external memory

One line of cache data to be written to external memory

Figure 3.3 Write-Back Buffer Configuration

3.3.5 Coherency of Cache and External Memory

Coherency between the cache and the external memory must be ensured by software. When

memory shared by this LSI and another device is allocated to a cacheable address space, invalidate

and write back the cache by accessing the memory-mapped cache, as required.

3.4 Memory-Mapped Cache

To allow software management of the cache, cache contents can be read from or written to by the

MOV instructions. The address array is allocated to addresses H'F0000000 to H'F0FFFFFF, and

the data array to addresses H'F1000000 to H'F1FFFFFF. The address array and data array must be

accessed in longwords, and instruction fetches cannot be performed.

3.4.1 Address Array

The address array is allocated to H'F0000000 to H'F0FFFFFF. To access an address array, the 32-

bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be

specified. The address field specifies information for selecting the entry to be accessed; the data

field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.

In the address field, specify the entry address for selecting the entry, W for selecting the way, A

for enabling or disabling the associative operation, and H'F0 for indicating address array access.

As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3.

In the data field, specify the tag address, LRU bits, U bit, and V bit. Always clear the upper three

bits (bits 31 to 29) of the tag address to 0. Figure 3.4 shows the address and data formats. The

following three operations are available in the address array.

Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that

corresponds to the entry address and way specified by the address field of the read instruction. In

reading, the associative operation is not performed, regardless of whether the associative bit (A

bit) specified in the address is 1 or 0.

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Address-Array Write (Non-Associative Operation): Write the tag address, LRU bits, U bit, and

V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry

address and way as specified by the address field of the write instruction. Ensure that the

associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U

bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag

address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is

written to the V bit, 0 must also be written to the U bit for that entry.

Address-Array Write (Associative Operation): When writing with the associative bit (A bit) of

the address field set to 1, the addresses in the four ways for the entry specified by the address field

of the write instruction are compared with the tag address that is specified by the data field of the

write instruction. Write the U bit and the V bit specified by the data field of the write instruction to

the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.

When there is no way that has a hit, nothing is written and there is no operation. This function is

used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1

at this time, writing back should be performed. However, when 0 is written to the V bit, 0 must

also be written to the U bit of that entry.

3.4.2 Data Array

The data array is allocated to H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit

address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.

The address field specifies information for selecting the entry to be accessed; the data field

specifies the longword data to be written to the data array.

In the address field, specify the entry address for selecting the entry, L for indicating the longword

position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array

access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2,

and 11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates

way 2, and 11 indicates way 3.

Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be

set to 00.

Figure 3.4 shows the address and data formats.

The following two operations on the data array are available. The information in the address array

is not affected by these operations.

Data-Array Read: Read the data specified by L of the address field, from the entry that

corresponds to the entry address and the way that is specified by the address field.

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Data-Array Write: Write the longword data specified by the data field, to the position specified

by L of the address field, in the entry that corresponds to the entry address and the way specified

by the address field.

(1) Address array access

(a) Address specification

Read access

Write access

(b) Data specification (both read and write accesses)

(2) Data array access (both read and write accesses)

(a) Address specification

1111 0000 *--------*WEntry address

1111 0000 *--------*WEntry address A

31 30 29 10 4 3 0

LRU

X00 0 X

Tag address (28 to 10) U V

31 24 23 4 3 0

1111 0001 *--------*W Entry address

(b) Data specification

31 0

Longword

[Legend]

*: Don't care

X: 0 for read, don't care for write

*00

31 24 23 4 3 012

31 24 23 14 13 12 11

14 13 12 11

43 012

*00

Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access

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3.4.3 Usage Examples

Invalidating Specific Entries: Specific cache entries can be invalidated by writing 0 to the entry's

V bit in the memory-mapped cache access. When the A bit is 1, the tag address specified by the

write data is compared to the tag address within the cache selected by the entry address, and the V

bit and U bit specified by the write data are written when a match is found. If no match is found,

there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written

back if the entry's U bit is 1. In the example shown below, R0 specifies the write data and R1

specifies the address.

; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0

; R1=H'F0000088; address array access, entry=B'00001000, A=1

;

MOV.L R0,@R1

Reading Data of Specific Entry: The data section of a specific entry can be read from by the

memory-mapped cache access. The longword indicated in the data field of the data array in

figure 3.4 is read into the register. In the example shown below, R0 specifies the address and R1

shows what is read.

; R0=H'F100004C; data array access, entry=B'00000100

; Way = 0, longword address = 3

;

MOV.L @R0,R1 ; Longword 3 is read.

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Section 4 U Memory

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Section 4 U Memory

This LSI has on-chip U memory which can be used to store instructions and data.

4.1 Features

Features of the U Memory are shown below.

• Size

4 kbytes

• Address

H'E55F_F000 to H'E55F_FFFF

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Section 5 Exception Handling

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Section 5 Exception Handling

5.1 Overview

5.1.1 Types of Exception Handling and Priority

Exception handling is started by four sources: resets, address errors, interrupts and instructions and

have the priority, as shown in table 5.1. When several exceptions are detected at once, they are

processed according to the priority.

Table 5.1 Types of Exceptions and Priority

Exception Exception Source Priority

Reset Power-on reset High

H-UDI reset

Interrupt User break (break before instruction execution)

Address error CPU address error (instruction fetch)

Instruction General illegal instructions (undefined code)

Illegal slot instruction (undefined code placed immediately after a

delayed branch instruction*1 or instruction that changes the PC value*2)

Trap instruction (TRAPA instruction)

Address error CPU address error (data access)

Interrupt User break (break after instruction execution or operand break)

NMI

H-UDI

IRQ

Watchdog timer (WDT)

On-chip

peripheral

modules: Compare match timer 0 and 1 (CMT0 and CMT1)

Serial communication interface with FIFO (SCIF0,

SCIF1, and SCIF2)

Host interface (HIF) Low

Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and

BRAF.

2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,

TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.

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5.1.2 Exception Handling Operations

The exceptions are detected and the exception handling starts according to the timing shown in

table 5.2.

Table 5.2 Timing for Exception Detection and Start of Exception Handling

Exception Timing of Source Detection and Start of Exception Handling

Reset Power-on reset Started when the RES pin changes from low to high or when the

WDT overflows.

H-UDI reset Started when the reset assert command and the reset negate

command are input to the H-UDI in this order.

Address error

Interrupt

Detected during the instruction decode stage and started after the

execution of the current instruction is completed.

Instruction Trap instruction Started by the execution of the TRAPA instruction.

General illegal

instructions

Started when an undefined code placed at other than a delay slot

(immediately after a delayed branch instruction) is decoded.

Illegal slot

instructions

Started when an undefined code placed at a delay slot

(immediately after a delayed branch instruction) or an instruction

that changes the PC value is detected.

When exception handling starts, the CPU operates

Exception Handling Triggered by Reset: The initial values of the program counter (PC) and

stack pointer (SP) are fetched from the exception handling vector table (PC from the address

H'A0000000 and SP from the address H'A0000004). For details, see section 5.1.3, Exception

Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F

(B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program

starts from the PC address fetched from the exception handling vector table.

Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are

saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is

written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception

handling, bits I3 to I0 are not affected. The start address is then fetched from the exception

handling vector table and the program starts from that address.

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5.1.3 Exception Handling Vector Table

Before exception handling starts, the exception handling vector table must be set in memory. The

exception handling vector table stores the start addresses of exception handling routines. (The

reset exception handling table holds the initial values of PC and SP.)

All exception sources are given different vector numbers and vector table address offsets. The

vector table addresses are calculated from these vector numbers and vector table address offsets.

During exception handling, the start addresses of the exception handling routines are fetched from

the exception handling vector table that is indicated by this vector table address.

Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector

table addresses are calculated.

Table 5.3 Vector Numbers and Vector Table Address Offsets

Exception Handling Source Vector Number Vector Table Address Offset

Power-on reset PC 0 H'00000000 to H'00000003

H-UDI reset SP 1 H'00000004 to H'00000007

(Reserved by

system)

2 H'00000008 to H'0000000B

3 H'0000000C to H'0000000F

General illegal instruction 4 H'00000010 to H'00000013

(Reserved by system) 5 H'00000014 to H'00000017

Illegal slot instruction 6 H'00000018 to H'0000001B

(Reserved by system) 7 H'0000001C to H'0000001F

8 H'00000020 to H'00000023

CPU address error 9 H'00000024 to H'00000027

(Reserved by system) 10 H'00000028 to H'0000002B

Interrupt NMI 11 H'0000002C to H'0000002F

User break 12 H'00000030 to H'00000033

H-UDI 13 H'00000034 to H'00000037

(Reserved by system) 14 H'00000038 to H'0000003B

: :

31 H'0000007C to H'0000007F

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Exception Handling Source Vector Number Vector Table Address Offset

Trap instruction (user vector) 32 H'00000080 to H'00000083

: :

63 H'000000FC to H'000000FF

Interrupt IRQ0 64 H'00000100 to H'00000103

IRQ1 65 H'00000104 to H'00000107

IRQ2 66 H'00000108 to H'0000010B

IRQ3 67 H'0000010C to H'0000010F

(Reserved by system) 68 H'00000110 to H'00000113

: :

79 H'0000013C to H'0000013F

IRQ4 80 H'00000140 to H'00000143

IRQ5 81 H'00000144 to H'00000147

IRQ6 82 H'00000148 to H'0000014B

IRQ7 83 H'0000014C to H'0000014F

On-chip peripheral module* 84 H'00000120 to H'00000124

: :

255 H'000003FC to H'000003FF

Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral

module interrupts, see table 6.2 in section 6, Interrupt Controller (INTC).

Table 5.4 Calculating Exception Handling Vector Table Addresses

Exception Source Vector Table Address Calculation

Resets Vector table address = H'A0000000 + (vector table address offset)

= H'A0000000 + (vector number) × 4

Address errors, interrupts,

instructions

Vector table address = VBR + (vector table address offset)

= VBR + (vector number) × 4

Notes: 1. VBR: Vector base register

2. Vector table address offset: See table 5.3.

3. Vector number: See table 5.3.

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5.2 Resets

5.2.1 Types of Resets

Resets have priority over any exception source. As table 5.5 shows, a power-on reset initializes all

modules in this LSI.

Table 5.5 Reset Status

Conditions for Transition to

Reset State Internal State

Type RES

WDT

Overflow

H-UDI

Command CPU, INTC

On-Chip

Peripheral

Module PFC, I/O Port

Low   Initialized Initialized Initialized Power-on reset

High Overflow  Initialized Initialized Initialized

H-UDI reset High Not

overflowed

Reset assert

command

Initialized Initialized Initialized

5.2.2 Power-On Reset

Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on

reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation

settling time when applying the power or when in standby mode (when the clock is halted) or at

least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and

all registers of on-chip peripheral modules are initialized.

In the power-on reset state, power-on reset exception handling starts when driving the RES pin

high after driving the pin low for the given time. The CPU operates as follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in PC and SP, then the

program starts.

Be certain to always perform power-on reset exception handling when turning the system power

on.

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Power-On Reset by WDT: When TCNT of the WDT overflows while a setting is made so that a

power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-

on reset state.

If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur

simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.

When the power-on reset exception handling caused by the WDT is started, the CPU operates as

follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in the PC and SP, then the

program starts.

5.2.3 H-UDI Reset

The H-UDI reset is generated by issuing the H-UDI reset assert command. The CPU operation is

described below. For details, see section 17, User Debugging Interface (H-UDI).

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception handling vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

in the status register (SR) are set to H'F (B'1111).

4. The values fetched from the exception handling vector table are set in PC and SP, then the

program starts.

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5.3 Address Errors

5.3.1 Address Error Sources

Address errors occur when instructions are fetched or data is read from or written to, as shown in

table 5.6.

Table 5.6 Bus Cycles and Address Errors

Bus Cycle

Type Bus Master Bus Cycle Description Address Errors

CPU Instruction fetched from even address None (normal) Instruction

fetch Instruction fetched from odd address Address error occurs

CPU Word data accessed from even address None (normal) Data

read/write Word data accessed from odd address Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

5.3.2 Address Error Exception Source

When an address error exception is generated, the bus cycle which caused the address error ends,

the current instruction finishes, and then the address error exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address

of the instruction which caused an address error exception. When the instruction that caused

the exception is placed in the delay slot, the address of the delayed branch instruction which is

placed immediately before the delay slot.

3. The start address of the exception handling routine is fetched from the exception handling

vector table that corresponds to the generated address error, and the program starts executing

from that address. This branch is not a delayed branch.

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5.4 Interrupts

5.4.1 Interrupt Sources

Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break,

H-UDI, IRQ and on-chip peripheral modules.

Table 5.7 Interrupt Sources

Type Request Source

Number of

Sources

NMI NMI pin (external input) 1

User break User break controller (UBC) 1

H-UDI User debug interface (H-UDI) 1

IRQ IRQ0 to IRQ7 pins (external input) 8

On-chip peripheral module Watchdog timer (WDT) 1

Compare match timer (CMT0 and CMT1) 2

Serial communication interface with FIFO

(SCIF0, SCIF1, and SCIF2)

Host interface (HIF) 2

All interrupt sources are given different vector numbers and vector table address offsets. For

details on vector numbers and vector table address offsets, see table 6.2 in section 6, Interrupt

Controller (INTC).

5.4.2 Interrupt Priority

The interrupt priority is predetermined. When multiple interrupts occur simultaneously

(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and

starts the exception handling according to the results.

The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and

priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always

accepted. The priority level of the user break interrupt and H-UDI is 15. IRQ interrupt and on-chip

peripheral module interrupt priority levels can be set freely using the interrupt priority level setting

registers A to E (IPRA to IPRE) of the INTC as shown in table 5.8. The priority levels that can be

set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRE, see section 6.3.4, Interrupt

Priority Registers A to E (IPRA to IPRE).

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Table 5.8 Interrupt Priority

Type Priority Level Comment

NMI 16 Fixed priority level. Cannot be masked.

User break 15 Fixed priority level. Can be masked.

H-UDI 15 Fixed priority level.

IRQ 0 to 15

On-chip peripheral module

Set with interrupt priority level setting registers

A through E (IPRA to IPRE).

5.4.3 Interrupt Exception Handling

When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is

always accepted, but other interrupts are only accepted if they have a priority level higher than the

priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).

When an interrupt is accepted, exception handling begins. In interrupt exception handling, the

CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted

interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set

in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched

from the exception handling vector table for the accepted interrupt, and program execution

branches to that address and the program starts. For details on the interrupt exception handling, see

section 6.6, Interrupt Operation.

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5.5 Exceptions Triggered by Instructions

5.5.1 Types of Exceptions Triggered by Instructions

Exception handling can be triggered by the trap instruction, illegal slot instructions, and general

illegal instructions, as shown in table 5.9.

Table 5.9 Types of Exceptions Triggered by Instructions

Type Source Instruction Comment

Trap instruction TRAPA 

Illegal slot

instructions*

Undefined code placed

immediately after a delayed

branch instruction (delay slot) or

instructions that changes the PC

value

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that changes the PC value:

JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,

TRAPA, BF/S, BT/S, BSRF, BRAF, LDC

Rm,SR, LDC.L @Rm+,SR

General illegal

instructions*

Undefined code anywhere

besides in a delay slot



Note: * The operation is not guaranteed when undefined instructions other than H'FC00 to

H'FFFF are decoded.

5.5.2 Trap Instructions

When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The CPU reads the start address of the exception handling routine from the exception handling

vector table that corresponds to the vector number specified in the TRAPA instruction,

program execution branches to that address, and then the program starts. This branch is not a

delayed branch.

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5.5.3 Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is called “instruction placed

in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot

exception handling starts after the undefined code is decoded. Illegal slot exception handling also

starts when an instruction that changes the program counter (PC) value is placed in a delay slot

and the instruction is decoded. The CPU handles an illegal slot instruction as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the

delayed branch instruction immediately before the undefined code or the instruction that

rewrites the PC.

3. The start address of the exception handling routine is fetched from the exception handling

vector table that corresponds to the exception that occurred. Program execution branches to

that address and the program starts. This branch is not a delayed branch.

5.5.4 General Illegal Instructions

When an undefined code placed anywhere other than immediately after a delayed branch

instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts.

The CPU handles the general illegal instructions in the same procedures as in the illegal slot

instructions. Unlike processing of illegal slot instructions, however, the program counter value that

is stacked is the start address of the undefined code.

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5.6 Cases When Exceptions are Accepted

When an exception other than resets occurs during decoding the instruction placed in a delay slot

or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in

table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the

exception is accepted.

Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions

Exception

Occurrence Timing

Address

Error

General

Illegal

Instruction

Slot Illegal

Instruction

Trap

Instruction Interrupt

Instruction in delay slot ×*2  ×*2  ×*3

Immediately after interrupt

disabled instruction*1

√ √ √ √ ×*4

[Legend]

√: Accepted

×: Not accepted

: Does not occur

Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L

2. An exception is accepted before the execution of a delayed branch instruction.

However, when an address error or a slot illegal instruction exception occurs in the

delay slot of the RTE instruction, correct operation is not guaranteed.

3. An exception is accepted after a delayed branch (between instructions in the delay slot

and the branch destination).

4. An exception is accepted after the execution of the next instruction of an interrupt

disabled instruction (before the execution two instructions after an interrupt disabled

instruction).

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5.7 Stack States after Exception Handling Ends

The stack states after exception handling ends are shown in table 5.11.

Table 5.11 Stack Status after Exception Handling Ends

Types Stack State

Address error (when the instruction

that caused an exception is placed in

the delay slot)

SP Address of

delayed branch instruction

→32 bits

32 bits

Address error (other than above)

→32 bits

32 bits

Address of instruction that

caused exception

Interrupt

→32 bits

32 bits

Address of instruction

after executed instruction

Trap instruction

→32 bits

32 bits

Address of instruction

after TRAPA instruction

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Types Stack State

Illegal slot instruction

SP Address of

delayed branch instruction

→32 bits

32 bits

General illegal instruction

→32 bits

32 bits

Address of

general illegal instruction

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5.8 Usage Notes

5.8.1 Value of Stack Pointer (SP)

The SP value must always be a multiple of 4. If it is not, an address error will occur when the

stack is accessed during exception handling.

5.8.2 Value of Vector Base Register (VBR)

The VBR value must always be a multiple of 4. If it is not, an address error will occur when the

stack is accessed during exception handling.

5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling

When the SP value is not a multiple of 4, an address error will occur when stacking for exception

handling (interrupts, etc.) and address error exception handling will start after the first exception

handling is ended. Address errors will also occur in the stacking for this address error exception

handling. To ensure that address error exception handling does not go into an endless loop, no

address errors are accepted at that point. This allows program control to be passed to the handling

routine for address error exception and enables error processing.

When an address error occurs during exception handling stacking, the stacking bus cycle (write) is

executed. When stacking the SR and PC values, the SP values for both are subtracted by 4,

therefore, the SP value is still not a multiple of 4 after the stacking. The address value output

during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is

undefined.

5.8.4 Notes on Slot Illegal Instruction Exception Handling

Some specifications on slot illegal instruction exception handling in this LSI differ from those on

the conventional SH2.

• Conventional SH2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot

illegal instructions.

• This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal

instructions.

Section 5 Exception Handling

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The supporting status on our software products regarding this note is as follows:

Compiler

This instruction is not allocated in the delay slot in the compiler V.4 or later versions.

Real-time OS for µITRON specifications

1. HI7000/4, HI-SH7

This instruction does not exist in the delay slot within the OS.

2. HI7000

This instruction is in part allocated to the delay slot within the OS, which may cause the slot

illegal instruction exception handling in this LSI.

3. Others

The slot illegal instruction exception handling may be generated in this LSI in case where the

instruction is described in assembler or when the middleware of the object is introduced.

Note that a check-up program (checker) to pick up this instruction is available on our website.

Download and utilize this checker as needed.

Section 6 Interrupt Controller (INTC)

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Section 6 Interrupt Controller (INTC)

The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt

requests to the CPU.

6.1 Features

• 16 levels of interrupt priority

Figure 6.1 shows a block diagram of the INTC.

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NMI

IRQ0

IRQ7

UBC

H-UDI

WDT

CMT0

CMT1

SCIF0

SCIF1

SCIF2

HIF

(Interrupt request)

Input

control

Com-

parator

Interrupt

request

CPU

I3 I2 I1 I0

Internal bus

Bus

interface

IPRA to IPRE

ICR0

IRQSR

IRQCR

Module bus

INTC

HIF: Host interface

ICR0: Interrupt control register 0

IRQCR: IRQ control register

IRQSR: IRQ status register

IPRA to IPRE: Interrupt priority registers A to E

SR: Status register

IPR

DTER

DTC

[Legend]

UBC: User break controller

H-UDI: User debugging interface

WDT: Watchdog timer

CMT: Compare match timer

SCIF: Serial communications interface with FIFO

Priority

determination

Figure 6.1 INTC Block Diagram

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6.2 Input/Output Pins

Table 6.1 shows the INTC pin configuration.

Table 6.1 Pin Configuration

Name Abbr. I/O Function

Non-maskable interrupt input pin NMI Input Input of non-maskable interrupt request

signal

Interrupt request input pins IRQ0 to

IRQ7

Input Input of maskable interrupt request

signals

6.3 Register Descriptions

The interrupt controller has the following registers. For details on the addresses of these registers

and the states of these registers in each processing state, see section 18, List of Registers.

• Interrupt control register 0 (ICR0)

• IRQ control register (IRQCR)

• IRQ status register (IRQSR)

• Interrupt priority register A (IPRA)

• Interrupt priority register B (IPRB)

• Interrupt priority register C (IPRC)

• Interrupt priority register D (IPRD)

• Interrupt priority register E (IPRE)

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6.3.1 Interrupt Control Register 0 (ICR0)

ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin

NMI and indicates the input signal level on the NMI pin.

Bit Bit Name

Initial

Value R/W Description

15 NMIL 1/0 R NMI Input Level

Indicates the state of the signal input to the NMI pin.

This bit can be read to determine the NMI pin level.

This bit cannot be modified.

0: State of the NMI input is low

1: State of the NMI input is high

14 to 9  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

8 NMIE 0 R/W NMI Edge Select

0: Interrupt request is detected on the falling edge of

the NMI input

1: Interrupt request is detected on the rising edge of

the NMI input

7 to 0  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

6.3.2 IRQ Control Register (IRQCR)

IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input

pins IRQ0 to IRQ7.

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Bit Bit Name

Initial

Value R/W Description

IRQ71S

IRQ70S

R/W

IRQ7 Sense Select

Set the interrupt request detection mode for pin

IRQ7.

00: Interrupt request is detected at the low level of

pin IRQ7

01: Interrupt request is detected at the falling edge

of pin IRQ7

10: Interrupt request is detected at the rising edge

of pin IRQ7

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ7

IRQ61S

IRQ60S

R/W

IRQ6 Sense Select

Set the interrupt request detection mode for pin

IRQ6.

00: Interrupt request is detected at the low level of

pin IRQ6

01: Interrupt request is detected at the falling edge

of pin IRQ6

10: Interrupt request is detected at the rising edge

of pin IRQ6

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ6

IRQ51S

IRQ50S

R/W

IRQ5 Sense Select

Set the interrupt request detection mode for pin

IRQ5.

00: Interrupt request is detected at the low level of

pin IRQ5

01: Interrupt request is detected at the falling edge

of pin IRQ5

10: Interrupt request is detected at the rising edge

of pin IRQ5

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ5

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Bit Bit Name

Initial

Value R/W Description

IRQ41S

IRQ40S

R/W

IRQ4 Sense Select

Set the interrupt request detection mode for pin

IRQ4.

00: Interrupt request is detected at the low level of

pin IRQ4

01: Interrupt request is detected at the falling edge

of pin IRQ4

10: Interrupt request is detected at the rising edge

of pin IRQ4

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ4

IRQ31S

IRQ30S

R/W

IRQ3 Sense Select

Set the interrupt request detection mode for pin

IRQ3.

00: Interrupt request is detected at the low level of

pin IRQ3

01: Interrupt request is detected at the falling edge

of pin IRQ3

10: Interrupt request is detected at the rising edge

of pin IRQ3

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ3

IRQ21S

IRQ20S

R/W

IRQ2 Sense Select

Set the interrupt request detection mode for pin

IRQ2.

00: Interrupt request is detected at the low level of

pin IRQ2

01: Interrupt request is detected at the falling edge

of pin IRQ2

10: Interrupt request is detected at the rising edge

of pin IRQ2

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ2

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Bit Bit Name

Initial

Value R/W Description

IRQ11S

IRQ10S

R/W

IRQ1 Sense Select

Set the interrupt request detection mode for pin

IRQ1.

00: Interrupt request is detected at the low level of

pin IRQ1

01: Interrupt request is detected at the falling edge

of pin IRQ1

10: Interrupt request is detected at the rising edge

of pin IRQ1

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ1

IRQ01S

IRQ00S

R/W

IRQ0 Sense Select

Set the interrupt request detection mode for pin

IRQ0.

00: Interrupt request is detected at the low level of

pin IRQ0

01: Interrupt request is detected at the falling edge

of pin IRQ0

10: Interrupt request is detected at the rising edge

of pin IRQ0

11: Interrupt request is detected at both the falling

and rising edges of pin IRQ0

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6.3.3 IRQ Status Register (IRQSR)

IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to

IRQ7 and the status of interrupt request.

Bit Bit Name

Initial

Value R/W Description

15 IRQ7L 0/1 R Indicates the state of pin IRQ7.

0: State of pin IRQ7 is low

1: State of pin IRQ7 is high

14 IRQ6L 0/1 R Indicates the state of pin IRQ6.

0: State of pin IRQ6 is low

1: State of pin IRQ6 is high

13 IRQ5L 0/1 R Indicates the state of pin IRQ5.

0: State of pin IRQ5 is low

1: State of pin IRQ5 is high

12 IRQ4L 0 or 1 R Indicates the state of pin IRQ4.

0: State of pin IRQ4 is low

1: State of pin IRQ4 is high

11 IRQ3L 0 or 1 R Indicates the state of pin IRQ3.

0: State of pin IRQ3 is low

1: State of pin IRQ3 is high

10 IRQ2L 0 or 1 R Indicates the state of pin IRQ2.

0: State of pin IRQ2 is low

1: State of pin IRQ2 is high

9 IRQ1L 0 or 1 R Indicates the state of pin IRQ1.

0: State of pin IRQ1 is low

1: State of pin IRQ1 is high

8 IRQ0L 0 or 1 R Indicates the state of pin IRQ0.

0: State of pin IRQ0 is low

1: State of pin IRQ0 is high

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Bit Bit Name

Initial

Value R/W Description

7 IRQ7F 0 R/W Indicates the status of an IRQ7 interrupt request.

• When level detection mode is selected

0: An IRQ7 interrupt has not been detected

[Clearing condition]

Driving pin IRQ7 high

1: An IRQ7 interrupt has been detected

[Setting condition]

Driving pin IRQ7 low

• When edge detection mode is selected

0: An IRQ7 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ7F = 1

 Accepting an IRQ7 interrupt

1: An IRQ7 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ7

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Bit Bit Name

Initial

Value R/W Description

6 IRQ6F 0 R/W Indicates the status of an IRQ6 interrupt request.

• When level detection mode is selected

0: An IRQ6 interrupt has not been detected

[Clearing condition]

Driving pin IRQ6 high

1: An IRQ6 interrupt has been detected

[Setting condition]

Driving pin IRQ6 low

• When edge detection mode is selected

0: An IRQ6 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ6F = 1

 Accepting an IRQ6 interrupt

1: An IRQ6 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ6

5 IRQ5F 0 R/W Indicates the status of an IRQ5 interrupt request.

• When level detection mode is selected

0: An IRQ5 interrupt has not been detected

[Clearing condition]

Driving pin IRQ5 high

1: An IRQ5 interrupt has been detected

[Setting condition]

Driving pin IRQ5 low

• When edge detection mode is selected

0: An IRQ5 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ5F = 1

 Accepting an IRQ5 interrupt

1: An IRQ5 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ5

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Bit Bit Name

Initial

Value R/W Description

4 IRQ4F 0 R/W Indicates the status of an IRQ4 interrupt request.

• When level detection mode is selected

0: An IRQ4 interrupt has not been detected

[Clearing condition]

Driving pin IRQ4 high

1: An IRQ4 interrupt has been detected

[Setting condition]

Driving pin IRQ4 low

• When edge detection mode is selected

0: An IRQ4 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ4F = 1

 Accepting an IRQ4 interrupt

1: An IRQ4 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ4

3 IRQ3F 0 R/W Indicates the status of an IRQ3 interrupt request.

• When level detection mode is selected

0: An IRQ3 interrupt has not been detected

[Clearing condition]

Driving pin IRQ3 high

1: An IRQ3 interrupt has been detected

[Setting condition]

Driving pin IRQ3 low

• When edge detection mode is selected

0: An IRQ3 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ3F = 1

 Accepting an IRQ3 interrupt

1: An IRQ3 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ3

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Bit Bit Name

Initial

Value R/W Description

2 IRQ2F 0 R/W Indicates the status of an IRQ2 interrupt request.

• When level detection mode is selected

0: An IRQ2 interrupt has not been detected

[Clearing condition]

Driving pin IRQ2 high

1: An IRQ2 interrupt has been detected

[Setting condition]

Driving pin IRQ2 low

• When edge detection mode is selected

0: An IRQ2 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ2F = 1

 Accepting an IRQ2 interrupt

1: An IRQ2 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ2

1 IRQ1F 0 R/W Indicates the status of an IRQ1 interrupt request.

• When level detection mode is selected

0: An IRQ1 interrupt has not been detected

[Clearing condition]

Driving pin IRQ1 high

1: An IRQ1 interrupt has been detected

[Setting condition]

Driving pin IRQ1 low

• When edge detection mode is selected

0: An IRQ1 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ1F = 1

 Accepting an IRQ1 interrupt

1: An IRQ1 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ1

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Bit Bit Name

Initial

Value R/W Description

0 IRQ0F 0 R/W Indicates the status of an IRQ0 interrupt request.

• When level detection mode is selected

0: An IRQ0 interrupt has not been detected

[Clearing condition]

Driving pin IRQ0 high

1: An IRQ0 interrupt has been detected

[Setting condition]

Driving pin IRQ0 low

• When edge detection mode is selected

0: An IRQ0 interrupt has not been detected

[Clearing conditions]

 Writing 0 after reading IRQ0F = 1

 Accepting an IRQ0 interrupt

1: An IRQ0 interrupt request has been detected

[Setting condition]

Detecting the specified edge of pin IRQ0

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6.3.4 Interrupt Priority Registers A to E (IPRA to IPRE)

Interrupt priority registers are five 16-bit readable/writable registers that set priority levels from 0

to 15 for interrupts except NMI. For the correspondence between interrupt request sources and

IPR, refer to table 6.2. Each of the corresponding interrupt priority ranks are established by setting

a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved

bits that are not assigned should be set H'0 (B'0000).

Bit Bit Name

Initial

Value R/W Description

IPR15

IPR14

IPR13

IPR12

R/W

Set priority levels for the corresponding interrupt

source.

0000: Priority level 0 (lowest)

0001: Priority level 1

0010: Priority level 2

0011: Priority level 3

0100: Priority level 4

0101: Priority level 5

0110: Priority level 6

0111: Priority level 7

1000: Priority level 8

1001: Priority level 9

1010: Priority level 10

1011: Priority level 11

1100: Priority level 12

1101: Priority level 13

1110: Priority level 14

1111: Priority level 15 (highest)

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Bit Bit Name

Initial

Value R/W Description

IPR11

IPR10

IPR9

IPR8

R/W

Set priority levels for the corresponding interrupt

source.

0000: Priority level 0 (lowest)

0001: Priority level 1

0010: Priority level 2

0011: Priority level 3

0100: Priority level 4

0101: Priority level 5

0110: Priority level 6

0111: Priority level 7

1000: Priority level 8

1001: Priority level 9

1010: Priority level 10

1011: Priority level 11

1100: Priority level 12

1101: Priority level 13

1110: Priority level 14

1111: Priority level 15 (highest)

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Bit Bit Name

Initial

Value R/W Description

IPR7

IPR6

IPR5

IPR4

R/W

Set priority levels for the corresponding interrupt

source.

0000: Priority level 0 (lowest)

0001: Priority level 1

0010: Priority level 2

0011: Priority level 3

0100: Priority level 4

0101: Priority level 5

0110: Priority level 6

0111: Priority level 7

1000: Priority level 8

1001: Priority level 9

1010: Priority level 10

1011: Priority level 11

1100: Priority level 12

1101: Priority level 13

1110: Priority level 14

1111: Priority level 15 (highest)

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Bit Bit Name

Initial

Value R/W Description

IPR3

IPR2

IPR1

IPR0

R/W

Set priority levels for the corresponding interrupt

source.

0000: Priority level 0 (lowest)

0001: Priority level 1

0010: Priority level 2

0011: Priority level 3

0100: Priority level 4

0101: Priority level 5

0110: Priority level 6

0111: Priority level 7

1000: Priority level 8

1001: Priority level 9

1010: Priority level 10

1011: Priority level 11

1100: Priority level 12

1101: Priority level 13

1110: Priority level 14

1111: Priority level 15 (highest)

Note: Name in the tables above is represented by a general name. Name in the list of register is,

on the other hand, represented by a module name.

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6.4 Interrupt Sources

6.4.1 External Interrupts

There are five types of interrupt sources: User break, NMI, H-UDI, IRQ, and on-chip peripheral

modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 15 the

highest). Giving an interrupt a priority level of 0 masks it.

NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI

interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt

control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception

handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15.

IRQ7 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ7. Use

the IRQ sense select bits (IRQ71S to IRQ 01S and IRQ70S to IRQ00S) in the IRQ control register

(IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge

detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each

pin using the interrupt priority registers A and B (IPRA and IPRB).

In the case that the low level detection is selected, an interrupt request signal is sent to the INTC

while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the

IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ

flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR).

In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when

the following change on the IRQ pin is detected: from high to low in falling edge detection mode,

from low to high in rising edge detection mode, and from low to high or from high to low in both

edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the

interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been

detected by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). An IRQ

interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag

after reading 1.

In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register

(SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block

diagram of the IRQ7 to IRQ0 interrupts.

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IRQCR.IRQn1S

IRQCR.IRQn0S IRQSR.IRQnF

IRQSR.IRQnL

IRQn pins

RESIRQn

Level

detection

Edge

detection SQ

Selection

CPU interrupt

request

(Acceptance of IRQn interrupt/

writing 0 after reading IRQnF = 1) n = 7 to 0

Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control

6.4.2 On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral

modules.

Since a different interrupt vector is allocated to each interrupt source, the exception handling

routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can

be allocated to individual on-chip peripheral modules in interrupt priority registers C to E (IPRC

to IPRE). On-chip peripheral module interrupt exception handling sets the interrupt mask level

bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module

interrupt that was accepted.

6.4.3 User Break Interrupt

A user break interrupt has a priority level of 15, and occurs when the break condition set in the

user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are

held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3

to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see

section 16, User Break Controller (UBC).

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6.4.4 H-UDI Interrupt

User debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI

interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held

until accepted. H-UDI exception handling sets the interrupt mask level bits (I3-I0) in the status

Interface (H-UDI).

6.5 Interrupt Exception Handling Vector Table

Table 6.2 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt

priorities.

Individual interrupt sources are allocated to different vector numbers and vector table address

offsets. Vector table addresses are calculated from the vector numbers and vector table address

offsets. For interrupt exception handling, the start address of the exception handling routine is

fetched from the vector table address in the vector table. For the details on calculation of vector

table addresses, see table 5.4, Calculating Exception Handling Vector Table Addresses in

section 5, Exception Handling.

IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0

and 15 for each pin or module by setting interrupt priority registers A to E (IPRA to IPRE).

However, when interrupt sources whose priority levels are allocated with the same IPR are

requested, the interrupt of the smaller vector number has priority. This priority cannot be changed.

Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0

at a power-on reset. If the same priority level is allocated to two or more interrupt sources and

interrupts from those sources occur simultaneously, they are processed by the default priority

order shown in table 6.2.

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Table 6.2 Interrupt Exception Handling Vectors and Priorities

Interrupt

Source Name

Vector

No.

Vector Table

Starting Address IPR

Default

Priority

User break 12 H'00000030  High

External pin NMI 11 H'0000002C 

H-UDI 13 H'00000034 

External pin IRQ0 64 H'00000100 IPRA15 to IPRA12

IRQ1 65 H'00000104 IPRA11 to IPRA8

IRQ2 66 H'00000108 IPRA7 to IPRA4

IRQ3 67 H'0000010C IPRA3 to IPRA0

IRQ4 80 H'00000140 IPRB15 to IPRB12

IRQ5 81 H'00000144 IPRB11 to IPRB8

IRQ6 82 H'00000148 IPRB7 to IPRB4

IRQ7 83 H'0000014C IPRB3 to IPRB0

WDT ITI 84 H'00000150 IPRC15 to IPRC12

CMT channel 0 CMI0 86 H'00000158 IPRC7 to IPRC4

CMT channel 1 CMI1 87 H'0000015C IPRC3 to IPRC0

ERI_0 88 H'00000160 IPRD15 to IPRD12

RXI_0 89 H'00000164

BRI_0 90 H'00000168

SCIF channel 0

TXI_0 91 H'0000016C

ERI_1 92 H'00000170 IPRD11 to IPRD8

RXI_1 93 H'00000174

BRI_1 94 H'00000178

SCIF channel 1

TXI_1 95 H'0000017C

ERI_2 96 H'00000180 IPRD7 to IPRD4

RXI_2 97 H'00000184

BRI_2 98 H'00000188

SCIF channel 2

TXI_2 99 H'0000018C

HIF HIFI 100 H'00000190 IPRE15 to IPRE12

HIFBI 101 H'00000194 IPRE11 to IPRE8 Low

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6.6 Interrupt Operation

6.6.1 Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the

operations.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest priority interrupt from interrupt requests sent,

according to the priority levels set in interrupt priority level setting registers A to E (IPRA to

IPRE). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If

interrupts that have the same priority level or interrupts within a same module occur

simultaneously, the interrupt with the highest priority is selected according to the priority

shown in table 6.2.

3. The interrupt controller compares the priority level of the selected interrupt request with the

interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the

selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If

the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt

controller accepts the request and sends an interrupt request signal to the CPU.

4. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of

an instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception handling (see figure 6.5).

5. SR and PC are saved onto the stack.

6. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR.

7. The CPU reads the start address of the exception handling routine from the exception vector

table for the accepted interrupt, branches to that address, and starts executing the program.

This branch is not a delayed branch.

Note: * Interrupt requests that are designated as edge-detect type are held pending until the

interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing

the IRQ status register (IRQSR). Interrupts held pending due to edge detection are

cleared by a power-on reset or an H-UDI reset.

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Program

execution state

Interrupt?

User break?

I3 to I0 ≤

level 14?

Level 14

interrupt?

Level 1

interrupt?

I3 to I0 ≤

level 13?

I3 to I0 =

level 0?

Yes

Save SR to stack

Save PC to stack

Copy interrupt

level to I3 to I0

Read exception

vector table

Branch to exception

handling routine

H-UDI

interrupt?

Yes

Level 15

interrupt?

Note: I3 to I0 are Interrupt mask bits in the status register (SR) of the CPU

NMI?

I3 to I0 ≤

level 14? No

Yes

Figure 6.3 Interrupt Sequence Flowchart

Section 6 Interrupt Controller (INTC)

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6.6.2 Stack after Interrupt Exception Handling

Figure 6.4 shows the stack after interrupt exception handling.

32 bits

PC*1

Address

4n – 8

4n – 4

SP*2

Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed

instruction.

2. Always make sure that SP is a multiple of 4

Figure 6.4 Stack after Interrupt Exception Handling

6.7 Interrupt Response Time

Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt

request until the interrupt exception handling starts and fetching of the first instruction of the

interrupt handling routine begins. Figure 6.5 shows an example of the pipeline operation when an

IRQ interrupt is accepted.

Section 6 Interrupt Controller (INTC)

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Table 6.3 Interrupt Response Time

Number of Cycles

Item

NMI, H-UDI

IRQ, Peripheral

Modules

Remarks

Interrupt priority decision

and comparison with mask

bits in SR

1 × Icyc + 2 × Pcyc 1 × Icyc + 3 × Pcyc

Wait for completion of

sequence currently being

executed by CPU

X (≥ 0) X (≥ 0) The longest sequence

is for interrupt or

address-error

exception handling (X =

7 × Icyc + m1 + m2

+ m3 + m4). If an

interrupt-masking

instruction follows,

however, the time may

be even longer.

Time from start of interrupt

exception handling until

fetch of first instruction of

exception handling routine

starts

8 × Icyc + m1 + m2

+ m3

8 × Icyc + m1 + m2

+ m3

Performs the saving

PC and SR, and vector

address fetch.

Interrupt

response

time

Total: 9 × Icyc + 2 × Pcyc

+ m1 + m2 + m3

+ X

9 × Icyc + 3 × Pcyc

+ m1 + m2 + m3

+ X

Minimum*: 12 × Icyc +

2 × Pcyc

12 × Icyc +

3 × Pcyc

SR, PC, and vector

table are all in on-chip

RAM, or cache hit

occurs (in write back

mode).

Maximum: 16 × Icyc +

2 × Pcyc + 2 ×

(m1 + m2 + m3) +

16 × Icyc +

3 × Pcyc + 2 ×

(m1 + m2 + m3) +

Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc.

m1 to m4 are the number of cycles needed for the following memory accesses.

m1: SR save (longword write)

m2: PC save (longword write)

m3: Vector address read (longword read)

m4: Fetch first instruction of interrupt service routine

Section 6 Interrupt Controller (INTC)

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Section 7 Bus State Controller (BSC)

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Section 7 Bus State Controller (BSC)

The bus state controller (BSC) outputs control signals for various types of memory that is

connected to the external address space and external devices. The BSC functions enable this LSI

to connect directly with SRAM, SDRAM, and other memory storage devices, and external

devices.

7.1 Features

The BSC has the following features.

• External address space

 A maximum 32 or 64 Mbytes for each of the areas, CS0, CS3, CS4, CS5B, and CS6B,

totally 256 Mbytes (divided into five areas)

 A maximum 64 Mbytes for each of the six areas, CS0, CS3, CS4, CS5, and CS6, totally

320 Mbytes (divided into five areas)

 Can specify the normal space interface, byte-selection SRAM, SDRAM, PCMCIA for each

address space

 Can select the data bus width (8 or 16 bits) for each address space

 Can control the insertion of wait cycles for each address space

 Can control the insertion of wait cycles for each read access and write access

 Can control the insertion of idle cycles in the consecutive access for five cases

independently: read-write (in same space/different space), read-read (in same

space/different space), or the first cycle is a write access

• Normal space interface

 Supports the interface that can directly connect to the SRAM

• SDRAM interface

 Can connect directly to SDRAM in area 3

 Multiplex output for row address/column address

 Efficient access by single read/single write

 High-speed access by bank-active mode

 Supports auto-refreshing and self-refreshing

• Byte-selection SRAM interface

 Can connect directly to byte-selection SRAM

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• PCMCIA direct interface

 Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver

4.2 (PCMCIA2.1 Rev 2.1)

 Controls the insertion of wait cycles by software

 Supports the bus sizing function of the I/O bus width (only in little endian mode)

• Refresh function

 Supports the auto-refreshing and self-refreshing functions

 Specifies the refresh interval by setting the refresh counter and clock selection

 Can execute consecutive refresh cycles by specifying the refresh counts (1, 2, 4, 6, or 8)

The block diagram of the BSC is shown in figure 7.1.

Section 7 Bus State Controller (BSC)

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CMNCR

CS0WCR

CS6BWCR

CS0BCR

CS6BBCR

SDCR

RTCSR

RTCNT

RTCOR

Comparator

Bus

mastership

controller

Wait

controller

Area

controller

Internal master

module

Internal slave

module

Internal bus

Memory

controller

Refresh

controller

Module bus

BSC

CS0, CS3, CS4,

CS5B (CE1A),

CS6B (CE1B)

WAIT

MD5

IOIS16

A25 to A0, D15 to D0,

BS, RD/WR, RD,

WE1 (BE1, DQMLU, WE),

WE0 (BE0, DQMLL),

ICIOWR, ICIORD,

RAS, CAS,

CKE, CE2A, CE2B

[Legend]

CMNCR: Common control register

CSnWCR: CSn space wait control register (n = 0, 3, 4, 5B, 6B)

RWTCNT: Reset wait counter

CSnBCR: CSn space bus control register (n = 0, 3, 4, 5B, 6B)

SDCR: SDRAM control register

RTCSR: Refresh timer control/status register

RTCNT: Refresh timer counter

RTCOR: Refresh time constant register

. . .

. . . . . .

RWTCNT

Figure 7.1 Block Diagram of BSC

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7.2 Input/Output Pins

Table 7.1 lists the pin configuration of the BSC.

Table 7.1 Pin Configuration

Abbreviation I/O Function

A25 to A0 Output Address Bus*

D15 to D0 I/O Data Bus

BS Output Bus Cycle Start

Asserted when a normal space, burst ROM (clock synchronous

/asynchronous), or PCMCIA is accessed. Asserted at the same timing

as CAS assertion in SDRAM access.

CS0, CS3, CS4 Output Chip Select

CS5B/CE1A Output Chip Select

Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use

CE2A Output Chip enable for PCMCIA allocated to area 5 when PCMCIA is in use

CS6B/CE1B Output Chip Select

Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use

CE2B Output Chip enable for PCMCIA allocated to area 6 when PCMCIA is in use

RD/WR Output Read/Write

Connects to WE pins when SDRAM or byte-selection SRAM is used.

RD Output Read Pulse Signal (read data output enable signal)

Strobe signal to indicate a memory read cycle when PCMCIA is in use.

WE1(BE1)/WE Output Indicates that D15 to D8 are being written to.

Connected to the byte select signal when byte-selection SRAM is in

use.

Strove signal to indicate a memory write cycle when PCMCIA is in use.

WE0(BE0) Output Indicates that D7 to D0 are being written to.

Connected to the byte select signal when a byte-selection SRAM is in

use.

RAS Output Connected to RAS pin when SDRAM is in use.

CAS Output Connected to CAS pin when SDRAM is in use.

CKE Output Connected to CKE pin when SDRAM is in use.

Section 7 Bus State Controller (BSC)

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Abbreviation I/O Function

IOIS16 Input PCMCIA 16-bit I/O Signal

Enabled only in little endian mode.

Drive this signal low in big endian mode.

DQMLU,

DQMLL

Output Connected to the DQMxx pin when SDRAM is in use.

DQMLU: Select signal for D15 to D8

DQMLL: Select signal for D7 to D0

WAIT Input External wait input

MD5, MD3 Input MD5: Selects data alignment (big endian or little endian)

MD3: Specifies area 0 bus width (8/16 bits)

Note: * As pins A25 to A16 act as general I/O ports immediately after a power-on reset, pull up

or pull down these pins outside the LSI as needed.

7.3 Area Overview

7.3.1 Area Division

The architecture of this LSI has 32-bit address space. The upper three address bits divide the space

into areas P0 to P4, and the cache access methods can be specified for each area. For details, see

section 3, Cache. Each area indicated by the remaining 29 bits is divided into ten areas (five areas

are reserved) when address map 1 is selected or eight areas (three areas are reserved) when address

map 2 is selected. The address map is selected by the MAP bit in CMNCR. The BSC controls the

areas indicated by the 29 bits.

As listed in tables 7.2 and 7.3, memory can be connected directly to five physical areas of this

LSI, and the chip select signals (CS0, CS3, CS4, CS5B, and CS6B) are output for each area. CS0

is asserted during area 0 access.

7.3.2 Shadow Area

Areas 0, 3, 4, 5B, and 6B are divided by decoding physical address bits A28 to A25, which

correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of

area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space

is the address space in P1 to P3 areas obtained by adding to it H'20000000 × n (n = 1 to 6).

The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +

H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7

shadow spaces are reserved, so do not use it.

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Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is allocated to internal register

addresses. Therefore, area P4 does not become shadow space.

Area 0 (CS0)

H'00000000

H'20000000

H'40000000

H'60000000

H'80000000

H'A0000000

H'C0000000

H'E0000000

Area 1 (reserved)

Area 2 (reserved)

Area 3 (CS3)

Area 4 (CS4)

Area 5A (reserved)

Area 6A (reserved)

Area 7 (reserved)

Physical address space

Address Space

Area 5B (CS5B)

Area 6B (CS6B)

Figure 7.2 Address Space

7.3.3 Address Map

The external address space has a capacity of 256 Mbytes and is divided into five areas. Types of

memory to be connected and the data bus width are specified for individual areas. The address

map for the external address space is shown in table 7.2.

Table 7.2 Address Map 1 (CMNCR.MAP = 0)

Physical Address Area Memory to be Connected Capacity

H'00000000 to H'03FFFFFF Area 0 Normal memory 64 Mbytes

H'04000000 to H'07FFFFFF Area 1 Reserved area* 64 Mbytes

H'08000000 to H'0BFFFFFF Area 2 Reserved area* 64 Mbytes

H'0C000000 to H'0FFFFFFF Area 3 Normal memory

Byte-selection SRAM

SDRAM

64 Mbytes

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Physical Address Area Memory to be Connected Capacity

H'10000000 to H'13FFFFFF Area 4 Normal memory

Byte-selection SRAM

64 Mbytes

H'14000000 to H'15FFFFFF Area 5A Reserved area* 32 Mbytes

H'16000000 to H'17FFFFFF Area 5B Normal memory

Byte-selection SRAM

32 Mbytes

H'18000000 to H'19FFFFFF Area 6A Reserved area* 32 Mbytes

H'1A000000 to H'1BFFFFFF Area 6B Normal memory

Byte-selection SRAM

32 Mbytes

H'1C000000 to H'1FFFFFFF Area 7 Reserved area* 64 Mbytes

Note: * Do not access the reserved area. If the reserved area is accessed, the correct

operation cannot be guaranteed.

Table 7.3 Address Map 2 (CMNCR.MAP = 1)

Physical Address Area Memory to be Connected Capacity

H'00000000 to H'03FFFFFF Area 0 Normal memory 64 Mbytes

H'04000000 to H'07FFFFFF Area 1 Reserved area*1 64 Mbytes

H'08000000 to H'0BFFFFFF Area 2 Reserved area*1 64 Mbytes

H'0C000000 to H'0FFFFFFF Area 3 Normal memory

Byte-selection SRAM

SDRAM

64 Mbytes

H'10000000 to H'13FFFFFF Area 4 Normal memory

Byte-selection SRAM

64 Mbytes

H'14000000 to H'17FFFFFF Area 5*2 Normal memory

Byte-selection SRAM

PCMCIA

64 Mbytes

H'18000000 to H'1BFFFFFF Area 6*2 Normal memory

Byte-selection SRAM

PCMCIA

64 Mbytes

H'1C000000 to H'1FFFFFFF Area 7 Reserved area*1 64 Mbytes

Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct

operation cannot be guaranteed.

2. For area 5, CS5BBCR and CS5BWCR are enabled.

For area 6, CS6BBCR and CS6BWCR are enabled.

Section 7 Bus State Controller (BSC)

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7.3.4 Area 0 Memory Type and Memory Bus Width

The memory bus width in this LSI can be set for each area. In area 0, the bus width is selected

from 8 bits and 16 bits at a power-on reset by the external pin setting. The bus width of other areas

is set by the register. The correspondence between the memory type, external pin (MD3), and bus

width is listed in table 7.4.

Table 7.4 Correspondence between External Pin (MD3), Memory Type, and Bus Width

for CS0

MD3 Memory Type Bus Width

1 Normal memory 8 bits

0 16 bits

7.3.5 Data Alignment

This LSI supports the big endian and little endian methods of data alignment. The data alignment

is specified using the external pin (MD5) at a power-on reset as shown in table 7.5.

Table 7.5 Correspondence between External Pin (MD5) and Endians

MD5 Endian

0 Big endian

1 Little endian

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7.4 Register Descriptions

The BSC has the following registers. For the addresses and access size for these registers, see

section 18, List of Registers.

Do not access spaces other than CS0 until setting the memory interfaces is complete.

• Common control register (CMNCR)

• CS0 space bus control register for area 0 (CS0BCR)

• CS3 space bus control register for area 3 (CS3BCR)

• CS4 space bus control register for area 4 (CS4BCR)

• CS5B space bus control register for area 5B (CS5BBCR)

• CS6B space bus control register for area 6B (CS6BBCR)

• CS0 space wait control register for area 0 (CS0WCR)

• CS3 space wait control register for area 3 (CS3WCR)

• CS4 space wait control register for area 4 (CS4WCR)

• CS5B space wait control register for area 5B (CS5BWCR)

• CS6B space wait control register for area 6B (CS6BWCR)

• SDRAM control register (SDCR)

• Refresh timer control/status register (RTCSR)

• Refresh timer counter (RTCNT)

• Refresh time constant register (RTCOR)

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7.4.1 Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. Do not access external

memory other than area 0 until setting CMNCR is complete.

Bit Bit Name

Initial

Value R/W Description

31 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

12 MAP 0 R/W Space Specification

Selects the address map for the external address space.

The address maps to be selected are shown in tables 7.2

and 7.3.

0: Selects address map 1

1: Selects address map 2

11 to 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

4  1 R Reserved

This bit is always read as 1. The write value should

always be 1.

3 ENDIAN 0/1* R Endian Flag

Fetches the external pin (MD5) state for specifying

endian at a power-on reset. The endian setting for all the

address spaces are set by this bit. This is a read-only bit.

0: External pin (MD5) for specifying endian was driven

low at a power-on reset. This LSI is operated as big

endian.

1: External pin (MD5) for specifying endian was driven

high at a power-on reset. This LSI is being operated

as little endian.

2  1 R Reserved

This bit is always read as 1. The write value should

always be 1.

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Bit Bit Name

Initial

Value R/W Description

1 HIZMEM 0 R/W Hi-Z Memory Control

Specifies the pin state in standby mode for pins A25 to

A0, BS, CSn, RD/WR, WEn (BEn)/DQMxx, and RD.

0: High impedance in standby mode

1: Driven in standby mode

0 HIZCNT 0 R/W Hi-Z Control

Specifies the pin state in standby mode for the CKIO,

CKE, RAS, and CAS pins.

0: High impedance in standby mode

1: Driven in standby mode

Note: * The external pin (MD5) state for specifying endian is sampled at a power-on reset.

When big endian is specified, this bit is read as 0 and when little endian is specified,

this bit is read as 1.

7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 3, 4, 5B, 6B)

CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and

the number of wait cycles between access cycles.

Do not access external memory other than area 0 until setting CSnBCR is completed.

Bit Bit Name

Initial

Value R/W Description

31, 30  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

IWW1

IWW0

R/W

Idle Cycles between Write-Read Cycles and Write-Write

Cycles

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

write and read cycles or write and write cycles performed

consecutively are the target cycle.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

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Bit Bit Name

Initial

Value R/W Description

27  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

IWRWD1

IWRWD0

R/W

Idle Cycles for Another Space Read-Write

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and write cycles which are performed consecutively

and are accessed to different areas are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

24  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

IWRWS1

IWRWS0

R/W

Idle Cycles for Read-Write in Same Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and write cycles which are performed consecutively

and are accessed to the same area are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

21  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

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Bit Bit Name

Initial

Value R/W Description

IWRRD1

IWRRD0

R/W

Idle Cycles for Read-Read in Another Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and read cycles which are performed consecutively

and are accessed to different areas are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

18  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

IWRRS1

IWRRS0

R/W

Idle Cycles for Read-Read in Same Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and read cycles which are performed consecutively

and are accessed to the same area are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

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Bit Bit Name

Initial

Value R/W Description

TYPE3

TYPE2

TYPE1

TYPE0

R/W

Memory Type

Specify the type of memory connected to the area.

0000: Normal space

0001: Reserved (setting prohibited)

0010: Reserved (setting prohibited)

0011: Byte-selection SRAM

0100: SDRAM

0101: PCMCIA

0110: Reserved (setting prohibited)

0111: Reserved (setting prohibited)

1000: Reserved (setting prohibited)

1001: Reserved (setting prohibited)

1010: Reserved (setting prohibited)

1011: Reserved (setting prohibited)

1100: Reserved (setting prohibited)

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

For details on memory type in each area, see tables 7.2

and 7.3.

11  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

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Bit Bit Name

Initial

Value R/W Description

BSZ1

BSZ0

R/W

Data Bus Size

Specify the data bus width of each area.

00: Reserved (setting prohibited)

01: 8 bits

10: 16 bits

11: Reserved (setting prohibited)

Notes: 1. The data bus width for area 0 is specified by

the external pin. These bits are ignored.

2. When area 5 or 6 is specified as PCMCIA

space, the bus width can be specified as

either 8 bits or 16 bits.

3. If area 3 is specified as SDRAM space, the

bus width must be specified as 16 bits.

4. These bits must be specified to either 01 or

11 before accessing to memory in other than

area 0.

8 to 0  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

Note: * CS0BCR fetches the external pin state (MD3) that specify the bus width at a power-on

reset.

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7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B)

CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register

varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0)

specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the

target area. Specify CSnBCR first, then specify CSnWCR.

Normal Space, Byte-Selection SRAM:

• CS0WCR

Bit Bit Name

Initial

Value R/W Description

31 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address, CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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Bit Bit Name

Initial

Value R/W Description

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read or write access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait is valid

1: External wait is ignored

5 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from RD, WEn (BEn) negation

to Address, CSn negation

Specify the number of delay cycles from RD and WEn

(BEn) negation to address and CSn negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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• CS3WCR

Bit Bit Name

Initial

Value R/W Description

31 to 21  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM

Specifies the WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the WEn (BEn) signal at the read/write timing

(signal used as strobe) and asserts the RD/WR signal

during the write access cycle (signal used as status)

1: Asserts the WEn (BEn) signal during the read/write

access cycle (used as status) and asserts the RD/WR

signal at the write timing (used as strobe)

19 to 11  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

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Bit Bit Name

Initial

Value R/W Description

6 WM 0 R/W External Wait Mask Specification

Specify whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait is valid

1: External wait is ignored

5 to 0  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

• CS4WCR

Bit Bit Name

Initial

Value R/W Description

31 to 21  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM

Specifies the WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the WEn (BEn) signal at the read/write timing

(signal used as strobe) and asserts the RD/WR signal

during the write access cycle (signal used as status)

1: Asserts the WEn (BEn) signal during the read/write

access cycle (signal used as status) and asserts the

RD/WR signal at the write timing (signal used as

strobe)

19  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

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Bit Bit Name

Initial

Value R/W Description

WW2

WW1

WW0

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for write

access.

000: Same number of cycles as WR3 to WR0 setting

(read access wait)

001: 0 cycle

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address, CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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Bit Bit Name

Initial

Value R/W Description

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycles is 0.

0: External wait is valid

1: External wait is ignored

5 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from RD, WEn (BEn) negation

to Address, CSn negation

Specify the number of delay cycles from RD and WEn

(BEn) negation to address and CSn negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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• CS5BWCR

Bit Bit Name

Initial

Value R/W Description

31 to 19  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

WW2

WW1

WW0

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for write

access.

000: Same number of cycles as WR3 to WR0 setting

(read access wait)

001: 0 cycle

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address, CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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Bit Bit Name

Initial

Value R/W Description

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specify whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait is valid

1: External wait is ignored

5 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from RD, WEn (BEn) negation

to Address, CSn negation

Specify the number of delay cycles from RD and WEn

(BEn) negation to address and CSn negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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• CS6BWCR

Bit Bit Name

Initial

Value R/W Description

31 to 21  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM

Specifies the WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the WEn (BEn) signal at the read/write timing

(signal used as strobe) and asserts the RD/WR signal

during the write access cycle (signal used as status)

1: Asserts the WEn (BEn) signal during the read/write

access cycle (used as status) and asserts the RD/WR

signal at the write timing (used as strobe)

19 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address, CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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Bit Bit Name

Initial

Value R/W Description

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read or write access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait is valid

1: External wait is ignored

5 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from RD, WEn (BEn) negation

to Address, CSn negation

Specify the number of delay cycles from RD and WEn

(BEn) negation to address and CSn negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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SDRAM*:

• CS3WCR

Bit Bit Name

Initial

Value R/W Description

31 to 15  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

WTRP1

WTRP0

R/W

Wait Cycle Number for Precharge Completion

Specify the number of minimum wait cycles inserted to

wait for the completion of precharge in the following

cases.

• From the start of auto-precharge to the issuing of the

ACTV command for the same bank.

• From the issuing of the PRE/PALL command to the

issuing of the ACTV command for the same bank.

• From the issuing of the PALL command during auto-

refreshing to the issuing of the REF command.

• From the issuing of the PALL command during self-

refreshing to the issuing of the SELF command.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles

12  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

WTRCD1

WTRCD0

R/W

Wait Cycle Number from ACTV Command to

READ(A)/WRIT(A) Command

Specify the number of minimum wait cycles from issuing

the ACTV command to issuing the READ(A)/WRIT(A)

command.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles

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Bit Bit Name

Initial

Value R/W Description

9  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

A3CL1

A3CL0

R/W

CAS Latency for Area 3.

Specify the CAS latency for area 3.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: Reserved (setting prohibited)

6, 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

TRWL1

TRWL0

R/W

Wait Cycle Number for Precharge Start Wait

Specify the number of minimum wait cycles inserted to

wait for the start of precharge in the following cases.

• From the issuing of the WRITA command by this LSI

to the start of the auto-precharge in the SDRAM.

The ACTV command for the same bank is issued

after issuing the WRITA command in non-bank active

mode.

To confirm how many cycles should be needed in the

SDRAM between receiving the WRITA command and

the auto-precharge start, refer to the data sheets for

each SDRAM. Set this bit so that the cycle number in

that data sheets should not exceed the cycle number

set by this bit.

• From the issuing of the WRIT command by this LSI to

the issuing of the PRE command.

A different row address in the same bank is accessed

in bank active mode.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles

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Bit Bit Name

Initial

Value R/W Description

2  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

WTRC1

WTRC0

R/W

Idle Cycle Number from REF Command/Self-Refreshing

Release to ACTV/REF/MRS Command

Specify the number of minimum idle cycles in the

following cases.

• From the issuing of the REF command to the issuing

of the ACTV/REF/MRS command.

• From the self-refreshing release to the issuing of the

ACTV/REF/MRS command.

00: 2 cycles

01: 3 cycles

10: 5 cycles

11: 8 cycles

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PCMCIA:

• CS5BWCR, CS6BWCR

Bit Bit Name

Initial

Value R/W Description

31 to 22  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

SA1

SA0

R/W

Space Attribute Specification

Specify memory card interface or I/O card interface when

the PCMCIA interface is selected.

• SA1

0: Specifies memory card interface when A25 = 1

1: Specifies I/O card interface when A25 = 1

• SA0

0: Specifies memory card interface when A25 = 0

1: Specifies I/O card interface when A25 = 0

19 to 15  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

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Bit Bit Name

Initial

Value R/W Description

TED3

TED2

TED1

TED0

R/W

Delay from Address to RD or WE Assert

Specify the delay time from address output to RD or WE

assertion in PCMCIA interface.

0000: 0.5 cycles

0001: 1.5 cycles

0010: 2.5 cycles

0011: 3.5 cycles

0100: 4.5 cycles

0101: 5.5 cycles

0110: 6.5 cycles

0111: 7.5 cycles

1000: Reserved (setting prohibited)

1001: Reserved (setting prohibited)

1010: Reserved (setting prohibited)

1011: Reserved (setting prohibited)

1100: Reserved (setting prohibited)

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

PCW3

PCW2

PCW1

PCW0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles to be inserted.

0000: 3 cycles

0001: 6 cycles

0010: 9 cycles

0011: 12 cycles

0100: 15 cycles

0101: 18 cycles

0110: 22 cycles

0111: 26 cycles

1000: 30 cycles

1001: 33 cycles

1010: 36 cycles

1011: 38 cycles

1100: 52 cycles

1101: 60 cycles

1110: 64 cycles

1111: 80 cycles

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Bit Bit Name

Initial

Value R/W Description

6 WM 0 R/W External Wait Mask Specification

Specify whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait is valid

1: External wait is ignored

5, 4  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

TEH3

TEH2

TEH1

TEH0

R/W

Delay from RD or WE Negate to Address

Specify the address hold time from RD or WE negation in

the PCMCIA interface.

0000: 0.5 cycle

0001: 1.5 cycles

0010: 2.5 cycles

0011: 3.5 cycles

0100: 4.5 cycles

0101: 5.5 cycles

0110: 6.5 cycles

0111: 7.5 cycles

1000: 8.5 cycles

1001: 9.5 cycles

1010: 10.5 cycles

1011: 11.5 cycles

1100: 12.5 cycles

1101: 13.5 cycles

1110: 14.5 cycles

1111: 15.5 cycles

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7.4.4 SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be

connected.

Bit Bit Name

Initial

Value R/W Description

31 to 12  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

11 RFSH 0 R/W Refresh Control

Specifies whether or not the refreshing SDRAM is

performed.

0: Refreshing is not performed

1: Refreshing is performed

10 RMODE 0 R/W Refresh Control

Specifies whether to perform auto-refreshing or self-

refreshing when the RFSH bit is 1. When the RFSH bit is

1 and this bit is 1, self-refreshing starts immediately.

When the RFSH bit is 1 and this bit is 0, auto-refreshing

starts according to the contents that are set in RTCSR,

RTCNT, and RTCOR.

0: Auto-refreshing is performed

1: Self-refreshing is performed

9  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

8 BACTV 0 R/W Bank Active Mode

Specifies whether to access in auto-precharge mode

(using READA and WRITA commands) or in bank active

mode (using READ and WRIT commands).

0: Auto-precharge mode (using READA and WRITA

commands)

1: Bank active mode (using READ and WRIT

commands)

7 to 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

Section 7 Bus State Controller (BSC)

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Bit Bit Name

Initial

Value R/W Description

A3ROW1

A3ROW0

R/W

Number of Bits of Row Address for Area 3

Specify the number of bits of the row address for area 3.

00: 11 bits

01: 12 bits

10: 13 bits

11: Reserved (setting prohibited)

2  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

A3COL1

A3COL0

R/W

Number of Bits of Column Address for Area 3

Specify the number of bits of the column address for

area 3.

00: 8 bits

01: 9 bits

10: 10 bits

11: Reserved (setting prohibited)

7.4.5 Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM.

When RTCSR is written to, the upper 16 bits of the write data must be H'A55A to cancel write

protection.

Bit Bit Name

Initial

Value R/W Description

31 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

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Bit Bit Name

Initial

Value R/W Description

7 CMF 0 R/W Compare Match Flag

Indicates that a compare match occurs between the

refresh timer counter (RTCNT) and refresh time constant

[Clearing condition]

When 0 is written to this bit after reading RTCSR with

CMF = 1.

[Setting condition]

When RTCNT value matches RTCOR value

6  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

CKS2

CKS1

CKS0

R/W

Clock Select

Select the clock input to count-up the refresh timer

counter (RTCNT).

000: Stop the counting-up

001: Bφ/4

010: Bφ/16

011: Bφ/64

100: Bφ/256

101: Bφ/1024

110: Bφ/2048

111: Bφ/4096

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Bit Bit Name

Initial

Value R/W Description

RRC2

RRC1

RRC0

R/W

Refresh Count

Specify the number of consecutive refresh cycles, when

the refresh request occurs after the coincidence of the

values of the refresh timer counter (RTCNT) and the

refresh time constant register (RTCOR). Using

consecutive refresh cycles can prolong cycles between

refreshing.

000: Once

001: Twice

010: 4 times

011: 6 times

100: 8 times

101: Reserved (setting prohibited)

110: Reserved (setting prohibited)

111: Reserved (setting prohibited)

7.4.6 Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in

RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns

to 0 after counting up to 255. When RTCNT is written to, the upper 16 bits of the write data must

be H'A55A to cancel write protection.

Bit Bit Name

Initial

Value R/W Description

31 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 to 0  All 0 R/W 8-bit Counter

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7.4.7 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1

and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued.

The request is maintained until the refresh operation is performed. If the request is not processed

when the next matching occurs, the previous request is ignored.

When the RTCOR is written to, the upper 16 bits of the write data must be H'A55A to cancel write

protection.

Bit Bit Name

Initial

Value R/W Description

31 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 to 0  All 0 R/W 8-bit Counter

Section 7 Bus State Controller (BSC)

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7.5 Operation

7.5.1 Endian/Access Size and Data Alignment

This LSI supports big endian, in which the most significant byte (MSByte) of multiple byte data is

stored in the lower address, and little endian, in which the least significant byte (LSByte) of

multiple byte data is stored in the lower address. Endian is specified at a power-on reset by the

external pin (MD5). When pin MD5 is driven low at a power-on reset, the endian will become big

endian and when pin MD5 is driven high at a power-on reset, the endian will become little endian.

Two data bus widths (8 bits and 16 bits) are available for normal memory and byte-selection

SRAM. Only 16-bit data bus width is available for SDRAM. Two data bus widths (8 bits and 16

bits) are available for PCMCIA interface. Data alignment is performed in accordance with the data

bus width of the device and endian. This also means that when longword data is read from a byte-

width device, the read operation must be done four times. In this LSI, data alignment and

conversion of data length is performed automatically between the respective interfaces.

Tables 7.6 to 7.9 show the relationship between endian, device data width, and access unit.

Section 7 Bus State Controller (BSC)

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Table 7.6 16-Bit External Device/Big Endian Access and Data Alignment

Data Bus Strobe Signals

Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0

WE3(BE3),

DQMUU

WE2(BE2),

DQMUL

WE1(BE1),

DQMLU

WE0(BE0),

DQMLL

Byte access at 0   Data

7 to 0

   Assert 

Byte access at 1    Data

7 to 0

   Assert

Byte access at 2   Data

7 to 0

   Assert 

Byte access at 3    Data

7 to 0

   Assert

Word access at 0   Data

15 to 8

Data

7 to 0

  Assert Assert

Word access at 2   Data

15 to 8

Data

15 to 8

  Assert Assert

Longword

access at 0

1st time

at 0

  Data

31 to 24

Data

23 to 16

  Assert Assert

2nd time

at 2

  Data

15 to 8

Data

7 to 0

  Assert Assert

Section 7 Bus State Controller (BSC)

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Table 7.7 8-Bit External Device/Big Endian Access and Data Alignment

Data Bus Strobe Signals

Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0

WE3(BE3),

DQMUU

WE2(BE2),

DQMUL

WE1(BE1),

DQMLU

WE0(BE0),

DQMLL

Byte access at 0    Data

7 to 0

   Assert

Byte access at 1    Data

7 to 0

   Assert

Byte access at 2    Data

7 to 0

   Assert

Byte access at 3    Data

7 to 0

   Assert

1st time

at 0

   Data

15 to 8

   Assert Word

access at 0

2nd time

at 1

   Data

7 to 0

   Assert

1st time

at 2

   Data

15 to 8

   Assert Word

access at 2

2nd time

at 3

   Data

7 to 0

   Assert

1st time

at 0

   Data

31 to 24

   Assert

2nd time

at 1

   Data

23 to 16

   Assert

3rd time

at 2

   Data

15 to 8

   Assert

Longword

access at 0

4th time

at 3

   Data

7 to 0

   Assert

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Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment

Data Bus Strobe Signals

Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0

WE3(BE3),

DQMUU

WE2(BE2),

DQMUL

WE1(BE1),

DQMLU

WE0(BE0),

DQMLL

Byte access at 0    Data

7 to 0

   Assert

Byte access at 1   Data

7 to 0

   Assert 

Byte access at 2    Data

7 to 0

   Assert

Byte access at 3   Data

7 to 0

   Assert 

Word access at 0   Data

15 to 8

Data

7 to 0

  Assert Assert

Word access at 2   Data

15 to 8

Data

7 to 0

  Assert Assert

Longword

access at 0

1st time

at 0

  Data

15 to 8

Data

7 to 0

  Assert Assert

2nd time

at 2

  Data

31 to 24

Data

23 to 16

  Assert Assert

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Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment

Data Bus Strobe Signals

Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0

WE3(BE3),

DQMUU

WE2(BE2),

DQMUL

WE1(BE1),

DQMLU

WE0(BE0),

DQMLL

Byte access at 0    Data

7 to 0

   Assert

Byte access at 1    Data

7 to 0

   Assert

Byte access at 2    Data

7 to 0

   Assert

Byte access at 3    Data

7 to 0

   Assert

1st time

at 0

   Data

7 to 0

   Assert Word

access at 0

2nd time

at 1

   Data

15 to 8

   Assert

1st time

at 2

   Data

7 to 0

   Assert Word

access at 2

2nd time

at 3

   Data

15 to 8

   Assert

1st time

at 0

   Data

7 to 0

   Assert

2nd time

at 1

   Data

15 to 8

   Assert

3rd time

at 2

   Data

23 to 16

   Assert

Longword

access at 0

4th time

at 3

   Data

31 to 24

   Assert

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7.5.2 Normal Space Interface

Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of

the fact that mainly static RAM will be directly connected. When using SRAM with a byte-

selection pin, see section 7.5.6, Byte-Selection SRAM Interface. Figure 7.3 shows the basic

timings of normal space access. A no-wait normal access is completed in two cycles. The BS

signal is asserted for one cycle to indicate the start of a bus cycle.

CKIO

RD/WR

CSn

T1 T2

WEn(BEn)

Read

Write

Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)

There is no output signal which informs external devices of the access size when reading.

Although the least significant bit of the address indicates the correct address when the access

starts, 16-bit data is always read from a 16-bit device. When writing, only the WEn (BEn) signal

for the byte to be written to is asserted.

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When buffers are placed on the data bus, the RD signal should be used to control the buffers. The

RD/WR signal indicates the same state as a read cycle (driven high) when no access has been

carried out. Therefore, care must be taken when controlling the buffers with the RD/WR signal, to

avoid data conflict.

Figures 7.4 and 7.5 show the basic timings of normal space consecutive access. If the WM bit in

CSnWCR is cleared to 0, a Tnop cycle is inserted to check the external wait (figure 7.4). If the

WM bit in CSnWCR is set to 1, an external wait request is ignored and no Tnop cycle is inserted

(figure 7.5).

CKIO

A25 to A0

RD/WR

D15 to D0

WEn(BEn)

D15 to D0

WAIT

CSn

T1 T2 Tnop T1 T2

Read

Write

Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 Bits,

Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0)

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T1 T2 T1 T2

CKIO

A25 to A0

RD/WR

D15 to D0

CSn

WEn(BEn)

WAIT

D15 to D0

Read

Write

Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 Bits,

Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0)

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A16

I/O7

I/O0

••••••••

•••• ••••

••••

A17

CSn

D15

WE1(BE1)

WE0(BE0)

This LSI

128 kwords × 8 bits

SRAM

••••

A16

I/O7

I/O0

••••

••••••••

••••

Figure 7.6 Example of 16-Bit Data-Width SRAM Connection

This LSI

128 kwords x 8 bits

SRAM

A16

I/O7

I/O0

. . .

A16

CSn

WE0(BE0)

. . .

Figure 7.7 Example of 8-Bit Data-Width SRAM Connection

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7.5.3 Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to

WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in

read access and in write access. The areas other than 4, 5A, and 5B have the same access wait for

read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a

normal space access shown in figure 7.9.

CKIO

A25 to A0

CSn

RD/WR

D15 to D0

WEn(BEn)

Read

Write

Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)

When the WM bit in CSnWCR is cleared to 0, the external wait signal (WAIT) is also sampled.

The WAIT pin sampling is shown in figure 7.9. In this example, two wait cycles are inserted as

software wait. The WAIT signal is sampled at the falling edge of the CKIO signal in the cycle

immediately before the T2 cycle (T1 or Tw cycle).

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CKIO

A25 to A0

CSn

RD/WR

D15 to D0

WEn(BEn)

D15 to D0

WAIT

Tw Tw Twx T2

Read

Write

Wait cycles inserted

by WAIT signal

Figure 7.9 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT)

7.5.4 Extension of Chip Select (CSn) Assertion Period

The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by

setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation

to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to

an external device can be obtained. Figure 7.10 shows an example. A Th cycle and a Tf cycle are

added before and after a normal cycle, respectively. In these cycles, RD and WEn (BEn) are not

asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this

prolongation is useful for devices with slow writing operations.

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CKIO

A25 to A0

CSn

RD/WR

D15 to D0

WEn(BEn)

Read

Write

T2 Tf

Figure 7.10 Example of Timing When CSn Assertion Period is Extended

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7.5.5 SDRAM Interface

SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has

11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin

for setting precharge mode in read and write command cycles.

The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMLU, DQMLL,

CKE, and CS3. Signals other than CKE are valid when CS3 is asserted. SDRAM can be connected

to area 2. The data bus width of the area that is connected to SDRAM can be set to 16 bits.

Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as

the SDRAM operating mode.

Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals.

These commands are shown below.

• NOP

• Auto-refreshing (REF)

• Self-refreshing (SELF)

• All banks precharge (PALL)

• Specified bank precharge (PRE)

• Bank active (ACTV)

• Read (READ)

• Read with precharge (READA)

• Write (WRIT)

• Write with precharge (WRITA)

• Write mode register (MRS)

The byte to be accessed is specified by DQMLU and DQMLL. Reading or writing is performed

for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx

and the byte to be accessed, refer to section 7.5.1, Endian/Access Size and Data Alignment.

Figures 7.11 shows an example of the connection of the SDRAM with the LSI.

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A14

CKE

CKIO

CSn

RAS

CAS

RD/WR

D15

DQMLU

DQMLL

64-Mbit SDRAM

(1 Mword x 16 bits x 4 banks)

. . .

A13

CKE

CLK

RAS

CAS

I/O15

I/O0

DQMU

DQML

. . .

This LSI

Figure 7.11 Example of 16-Bit Data-Width SDRAM Connection

Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected

without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in

CSnBCR, AnROW1 and AnROW0 and AnCOL1 AnCOL0 in SDCR. Tables 7.10 to 7.15 show

the relationship between those settings and the bits output on the address pins. Do not specify

those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.

A25 to A18 are not multiplexed and the original values of address are always output on these pins.

Pin A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to pin A1

of this LSI; pin A1 pin of SDRAM to pin A2 of this LSI, and so on.

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Table 7.10 Relationship between Register Settings and Address Multiplex Output (1)

Conditions: One 16-Mbit product (512 kwords x 16 bits x 2 banks, 8-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 00 (11-bit

row address), and A3COL[1:0] = 00 (8-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A25 A17 Unused

A16 A24 A16

A15 A23 A15

A14 A22 A14

A13 A21 A21

A12 A20*2 A20*2 A11 (BA0) Specifies bank

A11 A19 L/H*1 A10/AP Specifies

address/precharge

A10 A18 A10 A9 Address

A9 A17 A9 A8

A8 A16 A8 A7

A7 A15 A7 A6

A6 A14 A6 A5

A5 A13 A5 A4

A4 A12 A4 A3

A3 A11 A3 A2

A2 A10 A2 A1

A1 A9 A1 A0

A0 A8 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Table 7.11 Relationship between Register Settings and Address Multiplex Output (2)

Conditions: One 64-Mbit product (1 Mword x 16 bits x 4 banks, 8-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 01 (12-bit

row address), and A3COL[1:0] = 00 (8-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A25 A17 Unused

A16 A24 A16

A15 A23 A15

A14 A22*2 A22*2 A13 (BA1) Specifies bank

A13 A21*2 A21*2 A12 (BA0)

A12 A20 A12 A11 Address

A11 A19 L/H*1 A10/AP Specifies

address/precharge

A10 A18 A10 A9 Address

A9 A17 A9 A8

A8 A16 A8 A7

A7 A15 A7 A6

A6 A14 A6 A5

A5 A13 A5 A4

A4 A12 A4 A3

A3 A11 A3 A2

A2 A10 A2 A1

A1 A9 A1 A0

A0 A8 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Table 7.12 Relationship between Register Settings and Address Multiplex Output (3)

Conditions: One 128-Mbit product (2 Mwords x 16 bits x 4 banks, 9-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 01 (12-bit

row address), and A3COL[1:0] = 01 (9-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A26 A17 Unused

A16 A25 A16

A15 A24 A15

A14 A23*2 A23*2 A13 (BA1) Specifies bank

A13 A22*2 A22*2 A12 (BA0)

A12 A21 A12 A11 Address

A11 A20 L/H*1 A10/AP Specifies

address/precharge

A10 A19 A10 A9 Address

A9 A18 A9 A8

A8 A17 A8 A7

A7 A16 A7 A6

A6 A15 A6 A5

A5 A14 A5 A4

A4 A13 A4 A3

A3 A12 A3 A2

A2 A11 A2 A1

A1 A10 A1 A0

A0 A9 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Table 7.13 Relationship between Register Settings and Address Multiplex Output (4)

Conditions: One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 10-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 01 (12-bit

row address), and A3COL[1:0] = 10 (10-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A27 A17 Unused

A16 A26 A16

A15 A25 A15

A14 A24*2 A24*2 A13 (BA1) Specifies bank

A13 A23*2 A23*2 A12 (BA0)

A12 A22 A12 A11 Address

A11 A21 L/H*1 A10/AP Specifies

address/precharge

A10 A20 A10 A9 Address

A9 A19 A9 A8

A8 A18 A8 A7

A7 A17 A7 A6

A6 A16 A6 A5

A5 A15 A5 A4

A4 A14 A4 A3

A3 A13 A3 A2

A2 A12 A2 A1

A1 A11 A1 A0

A0 A10 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Table 7.14 Relationship between Register Settings and Address Multiplex Output (5)

Conditions: One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 9-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 10 (13-bit

row address), and A3COL[1:0] = 01 (9-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A26 A17 Unused

A16 A25 A16

A15 A24*2 A24*2 A14 (BA1) Specifies bank

A14 A23*2 A23*2 A13 (BA0)

A13 A22 A13 A12 Address

A12 A21 A12 A11

A11 A20 L/H*1 A10/AP Specifies

address/precharge

A10 A19 A10 A9 Address

A9 A18 A9 A8

A8 A17 A8 A7

A7 A16 A7 A6

A6 A15 A6 A5

A5 A14 A5 A4

A4 A13 A4 A3

A3 A12 A3 A2

A2 A11 A2 A1

A1 A10 A1 A0

A0 A9 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Table 7.15 Relationship between Register Settings and Address Multiplex Output (6)

Conditions: One 512-Mbit product (8 Mwords x 16 bits x 4 banks, 10-bit column product) is

connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 10 (13-bit

row address), and A3COL[1:0] = 10 (10-bit column address).

Pins of this LSI

Output Row

Address

Output Column

Address Pins of SDRAM Function

A17 A27 A17 Unused

A16 A26 A16

A15 A25*2 A25*2 A14 (BA1) Specifies bank

A14 A24*2 A24*2 A13 (BA0)

A13 A23 A13 A12 Address

A12 A22 A12 A11

A11 A21 L/H*1 A10/AP Specifies

address/precharge

A10 A20 A10 A9 Address

A9 A19 A9 A8

A8 A18 A8 A7

A7 A17 A7 A6

A6 A16 A6 A5

A5 A15 A5 A4

A4 A14 A4 A3

A3 A13 A3 A2

A2 A12 A2 A1

A1 A11 A1 A0

A0 A10 A0 Unused

Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the

access mode.

2. Bank address specification

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Burst Read: A burst read occurs in the following cases with this LSI.

1. Access size in reading is larger than data bus width.

2. 16-byte transfer in cache miss.

This LSI always accesses the SDRAM with burst length 1. For example, read access of burst

length 1 is performed consecutively eight times to read 16-byte consecutive data from the

SDRAM that is connected to a 16-bit data bus.

Table 7.16 shows the relationship between the access size and the number of bursts.

Table 7.16 Relationship between Access Size and Number of Bursts

Bus Width Access Size Number of Bursts

16 bits 8 bits 1

16 bits 1

32 bits 2

16 bytes 8

Figures 7.12 and 7.13 show timing charts in burst read. In burst read, the ACTV command is

output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA

command is issued in the Tc4 cycle, and the read data is latched at the rising edge of the external

clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an

auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new

command will not be issued to the same bank. However, other banks can be accessed. The number

of Tap cycles is specified by bits WTRP1 and WTRP0 in CS3WCR.

In this LSI, wait cycles can be inserted by specifying bits in CSnWCR to connect the SDRAM

with variable frequencies. Figure 7.15 shows an example in which wait cycles are inserted. The

number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where

the READA command is output can be specified using bits WTRCD1 and WTRCD0 in CS3WCR.

When bits WTRCD1 and WTRCD0 is set to one cycle or more, a Trw cycle where the NOP

command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the

Tc1 cycle where the READA command is output to the Td1 cycle where the read data is latched

can be specified by bits A3CL1 and A3CL0 bits in CS3WCR in CS3WCR. This number of cycles

corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous

DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be

specified as one to four cycles. This CAS latency can be achieved by connecting a latch circuit

between this LSI and the synchronous DRAM.

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Tc4

CKIO

A25 to A0

CSn

RD/WR

RAS

DQMxx

D15 to D0

TapTr Tc2 Tc3Tc1

Td4

Tde

Td2 Td3

Td1

A11*

CAS

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.12 Burst Read Basic Timing (Auto Precharge)

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Tc4

CKIO

A25 to A0

CSn

RD/WR

RAS

DQMxx

TapTr Tc2 Tc3Tc1

Td4

Tde

Td2 Td3

Td1

CAS

Trw

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.13 Burst Read Wait Specification Timing (Auto Precharge)

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Single Read: A read access ends in one cycle when data exists in non-cacheable area and the data

bus width is larger than or equal to access size. Since the burst length is set to 1 in synchronous

DRAM burst read/single write mode, only the required data is output. Consequently, no

unnecessary bus cycles are generated even when a cache-through area is accessed.

Figure 7.14 shows the single read basic timing.

A25 to A0

CSn

RD/WR

RAS

DQMxx

TapTr Tc1 TdeTd1

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.14 Basic Timing for Single Read (Auto Precharge)

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Burst Write: A burst write occurs in the following cases in this LSI.

1. Access size in writing is larger than data bus width.

2. Write-back of the cache

This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1

is performed consecutively eight times to write 16-byte consecutive data to the SDRAM that is

connected to a 16-bit data bus. The relationship between the access size and the number of bursts

is shown in table 7.16.

Figure 7.15 shows a timing chart for burst writes. In burst write, the ACTV command is output in

the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA

command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data

is output simultaneously with the write command. After the write command with the auto-

precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the

Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the

SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, other

CS areas and other banks can be accessed. The number of Trw1 cycles is specified by bits

TRWL1 and TRWL0 in CS3WCR. The number of Tap cycles is specified by bits WTRP1 and

WTRP0 in CS3WCR.

Tc4

CKIO

A25 to A0

CSn

RD/WR

RAS

DQMxx

TapTr Tc2 Tc3Tc1 Trwl

CAS

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.15 Basic Timing for Burst Write (Auto Precharge)

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Single Write: A write access ends in one cycle when data is written in non-cacheable area and the

data bus width is larger than or equal to access size.

Figure 7.16 shows the single write basic timing.

A25 to A0

CSn

RD/WR

RAS

DQMxx

TapTr Tc1 Trwl

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.16 Basic Timing for Single Write (Auto-Precharge)

Bank Active: The synchronous DRAM bank function is used to support high-speed accesses to

the same row address. When the BACTV bit in SDCR is 1, accesses are performed using

commands without auto-precharge (READ or WRIT). This function is called bank-active function.

When a bank-active function is used, precharging is not performed when the access ends. When

accessing the same row address in the same bank, it is possible to issue the READ or WRIT

command immediately, without issuing an ACTV command. Since synchronous DRAM is

internally divided into several banks, it is possible to keep one row address in each bank activated.

If the next access is to a different row address, a PRE command is first issued to precharge the

relevant bank, then when precharging is completed, the access is performed by issuing an ACTV

command followed by a READ or WRIT command. If this is followed by an access to a different

row address, the access time will be longer because of the precharging performed after the access

request is issued. The number of cycles between issuance of the PRE command and the ACTV

command is determined by bits WTRP1 and WTRP0 in CSnWCR.

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In a write access, when an auto-precharge is performed, a command cannot be issued to the same

bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active

mode is used, READ or WRIT command can be issued successively if the row address is the

same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write.

There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee

that another row address will be accessed within the period in which this value is maintained by

program execution, it is necessary to set auto-refreshing and set the refresh cycle to no more than

the maximum value of tRAS.

A burst read cycle without auto-precharge is shown in figure 7.17, a burst read cycle for the same

row address in figure 7.18, and a burst read cycle for different row addresses in figure 7.19.

Similarly, a single write cycle without auto-precharge is shown in figure 7.20, a single write cycle

for the same row address in figure 7.21, and a single write cycle for different row addresses in

figure 7.21.

In figure 7.18, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that

issues the READ command. The Tnop cycle is inserted to secure two cycles of CAS latency for

the DQMxx signal that specifies which byte data is read from SDRAM. If the CAS latency is

specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency

can be secured even if the DQMxx signal is asserted after the Tc cycle.

When bank active mode is set, if only accesses to the respective banks in the area 3 are

considered, as long as accesses to the same row address continue, the operation starts with the

cycle in figure 7.17 or 7.20, followed by repetition of the cycle in figure 7.18 or 7.21. An access to

a different area during this time has no effect. When a different row address is accessed in the

bank active state, the bus cycle shown in figure 7.19 or 7.22 is executed instead of that in figure

7.18 or 7.21. In bank active mode, too, all banks become inactive after a refresh cycle.

Section 7 Bus State Controller (BSC)

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Tc4

A25 to A0

CSn

RD/WR

RAS

DQMxx

Tr Tc2 Tc3Tc1

Td4Td2 Td3

Td1

Tde

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.17 Burst Read Timing (No Auto Precharge)

Section 7 Bus State Controller (BSC)

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Tc4

A25 to A0

CSn

RD/WR

RAS

DQMxx

Tc2 Tc3Tc1Tnop

Td4

Tde

Td2 Td3

Td1

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.18 Burst Read Timing (Bank Active, Same Row Address)

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Tc4

CKIO

A25 to A0

CSn

RD/WR

TpwTp Tc2 Tc3Tc1

Td4Td2 Td3

Td1

TdeTr

RAS

DQMxx

CAS

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.19 Burst Read Timing (Bank Active, Different Row Addresses)

Section 7 Bus State Controller (BSC)

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A25 to A0

CSn

RD/WR

Tr Tc1

RAS

DQMxx

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.20 Single Write Timing (No Auto Precharge)

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A25 to A0

CSn

RD/WR

Tnop Tc1

RAS

DQMxx

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.21 Single Write Timing (Bank Active, Same Row Address)

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A25 to A0

CSn

RD/WR

TpwTp Tc1Tr

RAS

DQMxx

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.22 Single Write Timing (Bank Active, Different Row Addresses)

Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Auto-

refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in

SDCR. A consecutive refreshing can be performed by setting bits RRC2 to RRC0 in RTCSR. If

synchronous DRAM is not accessed for a long period, self-refreshing mode, in which the power

consumption for data retention is low, can be activated by setting both the RMODE bit and the

RFSH bit to 1.

1. Auto-refreshing

Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to

CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR

should be set so as to satisfy the given refresh interval for the synchronous DRAM used. First

make the settings for RTCOR, RTCNT, and the RMODE, then make the CKS[2:0] and

RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up

from the value at that time. The RTCNT value is constantly compared with the RTCOR value,

and if the two values are the same, a refresh request is generated and an auto-refreshing is

performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is

cleared to 0 and the count-up is restarted.

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Figure 7.23 shows the auto-refreshing cycle timing. After starting the auto-refreshing, PALL

command is issued in the Tp cycle to make all the banks to precharged state from active state

when some bank is being precharged. Then the REF command is issued in the Trr cycle after

inserting idle cycles of which number is specified by bits WTRP1 and WTRP0 in CSnWCR. A

new command is not issued for the duration of the number of cycles specified by bits WTRC1

and WTRC0 in CSnWCR after the Trr cycle. Bits WTRC1 and WTRC0 in CSnWCR must be

set so as to satisfy the SDRAM refreshing cycle time (tRC). An NOP cycle is inserted between

the Tp cycle and Trr cycle when the setting of bits WTRP1 and WTRP0 in CSnWCR is longer

than or equal to one cycle.

A25 to A0

CSn

RD/WR

TpwTp Trr Trc Trc Trc

Hi-z

RAS

DQMxx

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.23 Auto-Refreshing Timing

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2. Self-refreshing

When self-refreshing mode is selected, the refresh timing and refresh addresses are generated

within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit

and the RFSH bit in SDCR to 1. After starting the self-refreshing, the PALL command is

issued in the Tp cycle after the completion of pre-charging the bank. The SELF command is

then issued after inserting idle cycles of which the number is specified by bits WTRP1 and

WTRP0 in CSnWSR. Synchronous DRAM cannot be accessed while self-refreshing. Self-

refreshing mode is cleared by clearing the RMODE bit to 0. After self-refreshing mode has

been cleared, command issuance is disabled for the number of cycles specified by bits WTRC1

and WTRC0 in CSnWCR.

Self-refreshing timing is shown in figure 7.24. Settings must be made immediately after

clearing self-refreshing mode so that auto-refreshing is performed at the correct intervals.

When self-refreshing is activated from the auto-refreshing mode, only clearing the RMODE bit

to 1 resumes auto-refreshing mode. If it takes long time to start the auto-refreshing, setting

RTCNT to the value of RTCOR − 1 starts the auto-refreshing immediately.

After self-refreshing has been set, the self-refreshing mode continues even in standby mode,

and is maintained even after recovery from standby mode by an interrupt.

Since the BSC registers are initialized at a power-on reset, the self-refreshing mode is cleared.

Section 7 Bus State Controller (BSC)

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CKIO

A25 to A0

CSn

RD/WR

TpwTp Trr Trc Trc Trc

Hi-z

Trc Trc

CKE

RAS

DQMxx

CAS

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.24 Self-Refreshing Timing

Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus

cycle execution, the refresh cycle must wait for the bus cycle to be completed.

If a new refresh request occurs while the previous refresh request is not performed, the previous

refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the

bus busy must be prevented.

Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed

after turning the power on. To perform synchronous DRAM initialization correctly, the BSC

registers must first be set, followed by writing to the synchronous DRAM mode register. When

writing to the synchronous DRAM mode register, the address signal value at that time is latched

by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, write to

the address of X + (H'F8FD5000) in words. In this operation, the data is ignored. To set burst

read/single write, burst read/burst write, CAS latency 2 to 3, wrap type = sequential, and burst

length 1 supported by the LSI, arbitrary data is written to the addresses shown in table 7.17 in

bytes. In this case, 0s are output at the external address pins of A12 or later.

Section 7 Bus State Controller (BSC)

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Table 7.17 Access Address for SDRAM Mode Register Write

• Burst read/single write (burst length 1)

Data Bus Width CAS Latency Access Address External Address Pin

16 bits 2 H'F8FD5440 H'0000440

3 H'F8FD5460 H'0000460

• Burst read/burst write (burst length 1)

Data Bus Width CAS Latency Access Address External Address Pin

16 bits 2 H'F8FD5040 H'0000040

3 H'F8FD5060 H'0000060

Mode register setting timing is shown in figure 7.25. The PALL command (all bank precharge

command) is issued first. The REF command (auto-refreshing command) is then issued eight

times. The MRS command (mode register write command) is finally issued. Idle cycles, of which

number is specified by bits WTRP1 and WTRP0 in CSnWCR, are inserted between the PALL and

the first REF commands. Idle cycles, of which number is specified by bits WTRC1 and WTRC0

in CSnWCR, are inserted between the REF and REF commands, and between the 8th REF and

MRS commands. In addition, one or more idle cycles are inserted between the MRS and the next

command.

It is necessary to keep idle time of certain cycles for SDRAM before issuing the PALL command

after turning the power on. Refer the manual of the SDRAM for the idle time to be needed. When

the pulse width of the reset signal is longer than the idle time, mode register setting can be started

immediately after the reset, but care should be taken when the pulse width of the reset signal is

shorter than the idle time.

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CKIO

A25 to A0

CSn

RD/WR

RAS

DQMxx

D15 to D0

TpwTp Trr

A11*

CAS

Note: * Address pin to be connected to pin A10 of SDRAM.

Trc Trc Tmw

Hi-Z

TnopTrc Trr Trc

REF REF MRS

PALL

Figure 7.25 Write Timing for SDRAM Mode Register (Based on JEDEC)

7.5.6 Byte-Selection SRAM Interface

The byte-selection SRAM interface is for access to SRAM which has a byte-selection pin (WEn

(BEn)). This interface is used to access to SRAM which has 16-bit data pins and upper and lower

byte selection pins, such as UB and LB.

When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-

selection SRAM interface is the same as that for the normal space interface. While in read access

of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,

which is different from that for the normal space interface. The basic access timing is shown in

figure 7.26. In write access, data is written to the memory according to the timing of the byte-

selection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.

If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. The

basic access timing is shown in figure 7.27. In write access, data is written to the memory

according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR

negation to data write must be secured by setting bits HW1 to HW0 in CSnWCR. Figure 7.28

shows the access timing when a software wait is specified.

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CKIO

A25 to A0

CSn

WEn(BEn)

RD/WR

D15 to D0

RD/WR

Read

Write

T1 T2

High

Figure 7.26 Basic Access Timing for Byte-Selection SRAM (BAS = 0)

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CKIO

A25 to A0

CSn

WEn(BEn)

D15 to D0

RD/WR

Read

Write

T1 T2

High

Figure 7.27 Basic Access Timing for Byte-Selection SRAM (BAS = 1)

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CKIO

A25 to A0

CSn

RD/WR

WEn(BEn)

D31 to D0

Read

Write

ThTh T1 Tw

RD/WR

D31 to D0

High

Figure 7.28 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)

Section 7 Bus State Controller (BSC)

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This LSI

A16

CSn

RD/WR

D15

WE1(BE1)

WE0(BE0)

A16

I/O 15

I/O 0

64 kwords x 16 bits

SRAM

...

Figure 7.29 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM

7.5.7 PCMCIA Interface

With this LSI, if address map 2 is selected using the MAP bit in CMNCR, the PCMCIA interface

can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the IC

memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1

Rev. 2.1) by specifying bits TYPE3 to TYPE0 in CSnBCR (n = 5B and 6B) to B'0101. In addition,

bits SA1 and SA0 in CSnWCR (n = 5B and 6B) assign the upper or lower 32 Mbytes of each area

to an IC memory card or I/O card interface. For example, if bits SA1 and SA0 in CS5BWCR are

set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32 Mbytes of area 5B

are used as an IC memory card interface and I/O card interface, respectively.

When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using bits

BSZ1 and BSZ0 in CS5BBCR or CS6BBCR.

Figure 7.30 shows an example of a connection between this LSI and the PCMCIA card. To enable

insertion and removal of the PCMCIA card with the system power turned on, tri-state buffers must

be connected between the LSI and the PCMCIA card.

In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined.

Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI.

Section 7 Bus State Controller (BSC)

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This LSI

PC card

(memory or I/O)

A25 to A0

D7 to D0

CE1

CE2

WE/PGM

IORD

IOWR

REG

A25 to A0

D7 to D0

D15 to D8

RD/WR

CE1A

CE2A

ICIORD

ICIOWR

I/O Port

WAIT

IOIS16

DIR

D15 to D8

WAIT

IOIS16

CD1,CD2

Card

detection

circuit

Figure 7.30 Example of PCMCIA Interface Connection

Basic Timing for Memory Card Interface: Figure 7.31 shows the basic timing of the PCMCIA

IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA

interface, accessing the common memory areas in areas 5 and 6 automatically accesses with the IC

memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold

times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and

write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this

LSI can specify the setup times and hold times for areas 5 and 6 in the physical space

independently, using CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal

space interface, a software wait or hardware wait can be inserted using the WAIT pin. Figure 7.32

shows the PCMCIA memory bus wait timing.

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Tpcm1w

CKIO

A25 to A0

CExx

RD/WR

D15 to D0

Read

Write

Tpcm2Tpcm1 Tpcm1w Tpcm1w

Figure 7.31 Basic Access Timing for PCMCIA Memory Card Interface

Tpcm1w

CKIO

A25 to A0

CExx

RD/WR

D15 to D0

Read

Write

Tpcm2Tpcm0 Tpcm1 Tpcm1wTpcm0w Tpcm2wTpcm1w Tpcm1w

WAIT

Figure 7.32 Wait Timing for PCMCIA Memory Card Interface

(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)

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When 32 Mbytes of the memory space are used as an IC memory card interface, a port is used to

generate the REG signal that switches between the common memory and attribute memory. When

the memory space used for the IC memory card interface is 16 Mbytes or less, pin A24 can be

used as the REG signal by allocating a 16-Mbyte common memory space and a 16-Mbyte attribute

memory space alternatively.

PCMCIA interface area is 32 Mbytes (An I/O port pin is used as the REG)

Area 5 : H'14000000

Attribute memory/common memory

I/O space

Attribute memory/common memory

I/O space

Area 5 : H'16000000

Area 6 : H'18000000

Area 6 : H'1A000000

PCMCIA interface area is 16 Mbytes (A24 is used as the REG)

Area 5 : H'14000000 Attribute memory

I/O space

Area 5 : H'15000000

Area 5 : H'16000000

H'17000000

Area 6 : H'18000000

Area 6 : H'19000000

Area 6 : H'1A000000

H'1B000000

Common memory

Attribute memory

I/O space

Common memory

Figure 7.33 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10,

CS6BWCR.SA[1:0] = B'10)

Basic Timing for I/O Card Interface: Figures 7.34 and 7.35 show the basic timings for the

PCMCIA I/O card interface.

The I/O card and IC memory card interfaces are specified by an address to be accessed. When

area 5 of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS5BWCR

are set to 1, the I/O card interface can automatically be specified by accessing the physical

addresses from H'16000000 to H'17FFFFFF and from H'14000000 to H'15FFFFFF. When area 6

of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS6BWCR are

set to 1, the I/O card interface can automatically be specified by accessing the physical addresses

from H'1A000000 to H'1BFFFFFF and from H'18000000 to H'19FFFFFF.

Note that areas to be accessed as the PCMCIA I/O card must be non-cached (space P2).

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If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the

I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is driven high in a word-size

I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8

bits and data is accessed twice in units of eight bits in the I/O bus cycle to be executed.

The IOIS16 signal is sampled at the falling edge of the CKIO signal in the Tpci0, Tpci0w, and

Tpci1 cycles when bits TED3 to TED0 are specified as 1.5 cycles or more, and is reflected in the

CE2 signal 1.5 cycles after the CKIO sampling point. Bits TED3 to TED0 must be specified

appropriately to satisfy the setup time of the PC card from ICIORD and ICIOWR to CEn.

Figure 7.36 shows the dynamic bus sizing basic timing.

Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the

IOIS16 signal must be fixed low.

Tpci1w

CKIO

A25 to A0

CExx

RD/WR

ICIORD

D15 to D0

ICIOWR

D15 to D0

Read

Write

Tpci2Tpci1 Tpci1w Tpci1w

Figure 7.34 Basic Timing for PCMCIA I/O Card Interface

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Tpci1w

CKIO

A25 to A0

CExx

RD/WR

ICIORD

D15 to D0

ICIOWR

IOIS16

D15 to D0

Read

Write

Tpci2Tpci0 Tpci1 Tpci1wTpci0w Tpci2wTpci1w Tpci1w

WAIT

Figure 7.35 Wait Timing for PCMCIA I/O Card Interface

(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)

Tpci1w

CKIO

A25 to A0

CE1x

RD/WR

ICIORD

D15 to D0

ICIOWR

IOIS16

D15 to D0

Read

Write

Tpci2

CE2x

Tpci0 Tpci1 Tpci1wTpci0w Tpci2wTpci1w Tpci1w

WAIT

Tpci1w Tpci2Tpci0 Tpci1 Tpci1wTpci0w Tpci2wTpci1w Tpci1w

Figure 7.36 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface

(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3)

Section 7 Bus State Controller (BSC)

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7.5.8 Wait between Access Cycles

Data output in the previous cycle may conflict with that in the next cycle because the buffer-off

timing of devices with slow access speed cannot be operated to satisfy the higher operating

frequency of LSIs. As a result of these conflict, the reliability of the device is low and

malfunctions may occur. This LSI has a function that avoids data conflicts by inserting wait cycles

between consecutive access cycles.

The number of wait cycles between access cycles can be set by bits IWW1 and IWW0, bits

IWRWD1 and IWRWD0, bits IWRWS1 and IWRWS0, bits IWRRD1 and IWRRD0, and bits

IWRRS1 and IWRRS0 in CSnBCR. The conditions for setting the wait cycles between access

cycles (idle cycles) are shown below.

1. Consecutive accesses are write-read or write-write

2. Consecutive accesses are read-write for different areas

3. Consecutive accesses are read-write for the same area

4. Consecutive accesses are read-read for different areas

5. Consecutive accesses are read-read for the same area

7.5.9 Others

Reset: The bus state controller (BSC) can be initialized completely only by a power-on reset. At

power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle

state. All control registers are initialized. In standby mode and sleep mode, control registers of the

BSC are not initialized.

Some flash memories may stipulate a minimum time from reset release to the first access. To

ensure this minimum time, the BSC supports a 5-bit counter (RWTCNT). At a power-on reset, the

RWTCNT contents are cleared to 0. After a power-on reset, RWTCNT is counted up in

synchronization with the CKIO signal and an external access will not be generated until

RWTCNT is counted up to H'007F.

Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal

buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to

the cache bus. The BSC is connected to the internal bus. Low-speed peripheral modules are

connected to the peripheral bus. Internal memory other than the cache memory and debugging

modules such as the UBC are connected to both the cache bus and internal bus. Access from the

cache bus to the internal bus is enabled but access from the internal bus to the cache bus is

disabled.

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If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the

CPU latches the data and completes the read access. If the cache does not store data, the CPU

performs four consecutive longword read cycles to perform cache fill operations via the internal

bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary

(4n + 2), the CPU performs four consecutive longword accesses to perform a cache fill operation

on the external interface. For a cache-through area, the CPU performs access according to the

actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs

longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs

word access.

For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first

accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus.

In a write cycle for the cache area, the write cycle operation differs according to the cache write

methods.

In write-back mode, the cache is first searched. If data is detected at the address corresponding to

the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written

until data in the corresponding address is re-written. If data is not detected at the address

corresponding to the cache, the cache is updated. In this case, data to be updated is first saved to

the internal buffer, 16-byte data including the data corresponding to the address is then read, and

data in the corresponding access of the cache is finally updated. Following these operations, a

write-back cycle for the saved 16-byte data is executed.

In write-through mode, the cache is first searched. If data is detected at the address corresponding

to the cache, the data is re-written to the cache simultaneously with the actual write via the internal

bus. If data is not detected at the address corresponding to the cache, the cache is not updated but

an actual write is performed via the internal bus.

Since the BSC incorporates a 1-stage write buffer, the BSC can execute an access via the internal

bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is

read or written after the external low-speed memory is written, the on-chip module can be

accessed before the completion of the external low-speed memory write cycle.

In read cycles, the CPU is placed in the wait cycle until read operation has been completed. To

continue the process after the data write to the device has been completed, perform a dummy read

to the same address to check for completion of the write before the next process to be executed.

The write buffer of the BSC functions in the same way for an access by a bus master other than

the CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers,

the next read cycle is initiated before the previous write cycle is completed. Note, however, that if

Section 7 Bus State Controller (BSC)

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both the DMA source and destination addresses exist in external memory space, the next write

cycle will not be initiated until the previous write cycle is completed.

On-Chip Peripheral Module Access: To access an on-chip module register, two or more

peripheral module clock (Pφ) cycles are required. Care must be taken in system design.

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Section 8 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock

(Pφ), and a bus clock (Bφ). The CPG consists of an oscillator, PLL circuits, and divider circuits.

8.1 Features

• Three clock modes

Selection of three clock modes depending on the frequency of a clock source and whether a

crystal resonator or external clock input is in use.

• Three clocks generated independently

An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip

peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface.

• Frequency change function

Frequencies of the internal clock and peripheral clock can be changed independently using the

PLL circuit and divider circuit within the CPG. Frequencies are changed by software using the

frequency control register (FRQCR).

• Power-down mode control

The clock can be stopped in sleep mode and software standby mode and specific modules can

be stopped using the module standby function.

A block diagram of the CPG is shown in figure 8.1.

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CKIO

PLL circuit 1

(×1, ×2)

PLL circuit 2

(×2, ×4)

×1

×1/2

×1/4

Oscillator unit

Internal clock

(Iφ)

Internal bus

Bus interface

[Legend]

FRQCR: Frequency control register

STBCR: Standby control register

STBCR2: Standby control register 2

STBCR3: Standby control register 3

STBCR4: Standby control register 4

Peripheral clock

(Pφ)

Bus clock

(Bφ = CKIO)

EXTAL

FRQCR STBCR STBCR2 STBCR3 STBCR4

CPG control unit

Clock frequency

control circuit Standby control circuit

Divider 1

MD2

MD1

MD0

XTAL Crystal oscillator

Figure 8.1 Block Diagram of CPG

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The clock pulse generator blocks function as follows:

PLL Circuit 1: PLL circuit 1 leaves the input clock frequency from the PLL circuit 2 unchanged

or doubles it. The multiplication ratio is set by the frequency control register. The phase of the

rising edge of the internal clock is controlled so that it will match the phase of the rising edge of

the CKIO pin.

PLL Circuit 2: PLL circuit 2 doubles or quadruples the clock frequency input from the crystal

oscillator or the EXTAL pin. The multiplication ratio is fixed for each clock operating mode. The

clock operating mode is set with pins MD0, MD1, or MD2.

Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is

connected to the XTAL and EXTAL pins. The crystal oscillator can be used by setting the clock

operating mode.

Divider 1: Divider 1 generates clocks with the frequencies used by the internal clock, peripheral

clock, and bus clock. The frequency output as the internal clock is always the same as that of the

devider1 output. The frequency output as the bus clock is automatically selected so that it is the

same as the frequency of the CKIO signal according to the multiplication ratio of PLL circuit 1.

The frequencies can be 1, 1/2, or 1/4 times the output frequency of PLL circuit 1, as long as it

stays at or above the frequency of the CKIO pin. The division ratio is set in the frequency control

Clock Frequency Control Circuit: The clock frequency control circuit controls the clock

frequency using pins MD0, MD1, and MD2 and the frequency control register.

Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator

circuit and other modules during clock switching and in software standby mode.

Frequency Control Register: The frequency control register has control bits assigned for the

following functions: clock output/non-output from the CKIO pin, the frequency multiplication

ratio of PLL circuit 1, and the frequency division ratio of the peripheral clock.

Standby Control Register: The standby control register has bits for controlling the power-down

modes. For details, see section 10, Power-Down Modes.

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8.2 Input/Output Pins

Table 8.1 shows the CPG pin configuration.

Table 8.1 Pin Configuration

Pin Name Abbr. I/O Description

Mode control pins* MD0 Input Set the clock operating mode.

MD1 Input Set the clock operating mode.

MD2 Input Set the clock operating mode.

Clock input pins XTAL Output Connects a crystal resonator.

EXTAL Input Connects a crystal resonator or an external clock.

Clock output pin CKIO Output Outputs an external clock.

Note: * The values of these mode control pins are sampled only at a power-on reset or in a

software standby with the MDCHG bit in STBCR to 1. This can prevent the erroneous

operation of this LSI.

8.3 Clock Operating Modes

Table 8.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and

the clock operating modes. Table 8.3 shows the usable frequency ranges in the clock operating

modes and the frequency range of the input clock.

Table 8.2 Mode Control Pins and Clock Operating Modes

Pin Values Clock I/O Clock

Operating

Mode MD2 MD1 MD0 Source Output PLL2 PLL1 CKIO Frequency

1 0 0 1 EXTAL CKIO ON (×4) ON (×1, ×2) (EXTAL) × 4

2 0 1 0 Crystal resonator CKIO ON (×4) ON (×1, ×2) (Crystal resonator) ×

5 1 0 1 EXTAL CKIO ON (×2) ON (×1, ×2) (EXTAL) × 2

6 1 1 0 Crystal resonator CKIO ON (×2) ON (×1, ×2) (Crystal resonator) ×

Mode 1: The frequency of the external clock input from the EXTAL pin is quadrupled by PLL

circuit 2, and then the clock is supplied to this LSI. Since the input clock frequency ranging 10

MHz to 12.5 MHz can be used, the CKIO frequency ranges from 40 MHz to 50 MHz.

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Mode 2: The frequency of the on-chip crystal oscillator output is quadrupled by PLL circuit 2, and

then the clock is supplied to this LSI. Since the crystal resonator frequency ranging 10 MHz to

12.5 MHz can be used, the CKIO frequency ranges from 40 MHz to 50 MHz.

Mode 5: The frequency of the external clock from the EXTAL pin is doubled by PLL circuit 2,

and then the clock is supplied to this LSI. Since the input clock frequency ranging 10 MHz to 25

MHz, the CKIO frequency ranges from 20 MHz to 50 MHz.

Mode 6: The frequency of the on-chip crystal oscillator output is doubled by PLL circuit 2, and

then the clock is supplied to the LSI. Since the crystal oscillation frequency ranging 10 MHz to 25

MHz can be used, the CKIO frequency ranges from 20 MHz to 50 MHz.

Table 8.3 Possible Combination of Clock Modes and FRQCR Values

Mode

FRQCR

Value

PLL

Circuit 1

PLL

Circuit 2

Clock Ratio*

(I:B:P)

Input Clock

Frequency Range

CKIO Pin

Frequency

Range

H'1000 ON (×1) ON (×4) 4:4:4 1 or 2

H'1001 ON (×1) ON (×4) 4:4:2

10 MHz to

12.5 MHz

40 MHz to

50 MHz

H'1003 ON (×1) ON (×4) 4:4:1

H'1101 ON (×2) ON (×4) 8:4:4

H'1103 ON (×2) ON (×4) 8:4:2

5 or 6 H'1000 ON (×1) ON (×2) 2:2:2

H'1001 ON (×1) ON (×2) 2:2:1

10 MHz to

25 MHz

20 MHz to

50 MHz

H'1003 ON (×1) ON (×2) 2:2:1/2

H'1101 ON (×2) ON (×2) 4:2:2

H'1103 ON (×2) ON (×2) 4:2:1

Note: * Input clock is assumed to be 1.

Cautions:

1. The internal clock frequency is the product of the frequency of the CKIO pin and the

frequency multiplication ratio of PLL circuit 1.

2. The peripheral clock frequency is the product of the frequency of the CKIO pin, the frequency

multiplication ratio of PLL circuit 1, and the division ratio of divider 1.

Do not set the peripheral clock frequency lower than the CKIO pin frequency.

3. ×1, ×1/2, or ×1/4 can be used as the division ratio of divider 1. Set the rate in the frequency

control register.

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4. The output frequency of PLL circuit 1 is the product of the frequency of the CKIO pin and the

multiplication ratio of PLL circuit 1. It is set by the frequency control register.

5. The bus clock frequency is always set to be equal to the frequency of the CKIO pin.

6. The clock mode, the FRQCR register value, and the frequency of the input clock should be

decided to satisfy the range of operating frequency specified in section 19, Electrical

Characteristics, with referring to table 8.3.

8.4 Register Descriptions

The CPG has the following registers.

For details on the addresses of these registers and the states of these registers in each processing

state, see section 18, List of Registers.

• Frequency control register (FRQCR)

8.4.1 Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register that specifies whether a clock is output from the

CKIO pin in standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency

division ratio of the peripheral clock. Only word access can be used on FRQCR.

FRQCR is initialized by a power-on reset due to the external input signal. However, it is not

initialized by a power-on reset due to a WDT overflow.

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Bit Bit Name

Initial

Value R/W Description

15 to 13  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

12 CKOEN 1 R/W Clock Output Enable

Specifies whether a clock continues to be output from

the CKIO pin or the output level of the CKIO signal is

fixed when leaving software standby mode. The CKIO

output is fixed low when this bit is set to 0. Therefore,

the malfunction of external circuits because of an

unstable CKIO clock when leaving software standby

mode can be prevented.

0: Output level of the CKIO signal is fixed low in

software standby mode.

1: Clock input to the EXTAL pin is output to the CKIO

pin during software standby mode in clock mode 1

or 5. However, the output level of the CKIO pin is

fixed low for two cycles of Pφ when changing from

the normal mode to the standby mode. This

prevents hazard which occurs when the source of

the CKIO signal is changed from the PLL2 output

to the EXTAL signal.

11  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

STC2

STC1

STC0

R/W

PLL Circuit 1 Frequency Multiplication Ratio

000: ×1

001: ×2

Other values: Setting prohibited

7 to 3  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

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Bit Bit Name

Initial

Value R/W Description

PFC2

PFC1

PFC0

R/W

Peripheral Clock Frequency Division Ratio

Specify the division ratio of the peripheral clock

frequency with respect to the output frequency of PLL

circuit 1.

000: ×1

001: ×1/2

011: ×1/4

Other values: Setting prohibited

8.5 Changing Frequency

The internal clock frequency can be changed by changing the multiplication ratio of PLL circuit 1.

The peripheral clock frequency can be changed either by changing the multiplication ratio of PLL

circuit 1 or by changing the division ratio of divider 1. All of these are controlled by software

through the frequency control register. The methods are described below.

8.5.1 Changing Multiplication Ratio

The PLL lock time must be preserved when the multiplication ratio of PLL circuit 1 is changed.

The on-chip WDT counts for preserving the PLL lock time.

1. In the initial state, the multiplication ratio of PLL circuit 1 is 1.

2. Set a value that satisfies the given PLL lock time in the WDT and stop the WDT. The

following must be set.

 TME bit in WTCSR = 0: WDT stops

 Bits CKS2 to CKS0 in WTCSR: Division ratio of WDT count clock

 WTCNT: Initial counter value

3. Set the desired value in bits STC2 to STC0 while the MDCHG bit in STBCR is 0. The division

ratio can also be set in bits PFC2 to PFC0.

4. This LSI pauses internally and the WDT starts incrementing. The internal and peripheral

clocks both stop and only the WDT is supplied with the clock. The clock will continue to be

output on the CKIO pin.

5. Supply of the specified clock starts at a WDT count overflow, and this LSI starts operating

again. The WDT stops after it overflows.

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Notes: 1. When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect

on the operation immediately. For details, see section 8.5.3, Changing Clock Operating

Mode.

2. The multiplication ratio should be changed after completion of the operation, if the on-

chip peripheral module is operating. The internal and peripheral clocks are stopped

during the multiplication ratio is changed. The communication error may occur by the

peripheral module communicating to the external IC, and the time error may occur by

the timer unit (except the WDT). The edge detection of external interrupts (NMI and

IRQ7 to IRQ0) cannot be performed.

8.5.2 Changing Division Ratio

The WDT will not count unless the multiplication ratio is changed simultaneously.

1. In the initial state, PFC2 to PFC0 = 011.

2. Set the desired values in bits PFC2 to PFC0 while the MDCHG bit in STBCR is 0. The values

that can be set are limited by the clock mode and the multiplication ratio of PLL circuit 1. Note

that if the wrong value is set, this LSI will malfunction.

3. The clock is immediately changed to the new division ratio.

Note: When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect on

the operation immediately. For details, see section 8.5.3, Changing Clock Operating

Mode.

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8.5.3 Changing Clock Operating Mode

The values of the mode control pins (MD2 to MD0) that define a clock operating mode are fetched

at a power-on reset and software standby while the MDCHG bit in STBCR is set to 1 register.

Even if changing the FRQCR with the MDCHG bit set to 1, the clock mode cannot immediately

be changed to the specified clock mode. This change can be reflected as a multiplication ratio or a

division ratio after leaving software standby mode to change operating modes. Reducing the PLL

settling time without changing again the multiplication ratio after the operating mode changing is

possible by the use of this.

The procedures for the mode change using software standby mode are described below.

1. Set bits MD2 to MD0 to the desired clock operating mode.

2. Set both the STBY and MDCHG bits in STBCR to 1.

3. Set the adequate value to the WDT so that the given oscillation settling time can be satisfied.

Then stop the WDT.

4. Set FRQCR to the desired mode. Set bits STC2 to STC0 to the desired multiplication ratio. At

this time, a division ratio can be set in bits PFC2 to PFC0. During the operation before the

mode change, the clock cannot be changed to the specified clock.

5. Enter software standby mode using the SLEEP instruction.

6. Leave software standby mode using an interrupt.

7. After leaving software standby mode, this LSI starts the operation with the value of FRQCR

that has been set before the mode change.

Notes: 1. Pins MD2 to MD0 should be set during the operation before the mode change or during

software standby mode before requesting an interrupt.

2. Clear the STBY bit in STBCR in the exception handling routine for the interrupt in

step 6. Otherwise, software standby mode is entered again. For details, see section

10.5.2, Canceling Software Standby Mode.

3. Once bits STC2 to STC0 are changed, the clock is not switched to the specified clock

even if only bits PFC2 to PFC0 are changed. When bits STC2 to STC0 are changed

after the MDCHG bit has been set to 1, the FRQCR setting must not be made until the

clock mode is changed.

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8.6 Notes on Board Design

When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and

CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from

interfering with correct oscillation, use a common grounding point for the capacitors connected to

the resonator, and do not locate a wiring pattern near these components.

EXTAL XTAL

This LSI

Avoid crossing

signal lines

CL1 CL2

Note : Although the recommended value for CL1 and CL2 is

20pF and the recommended value for R is 0Ω, the

values should be determined after consultation with

the crystal manufacturer.

Figure 8.2 Points for Attention When Using Crystal Resonator

Bypass Capacitors: Insert a laminated ceramic capacitor as a bypass capacitor for each VSS/VSSQ

and VCC/VCCQ pair. Mount the bypass capacitors to the power supply pins, and use components

with a frequency characteristic suitable for the operating frequency of the LSI, as well as a suitable

capacitance value.

• Digital power supply pairs for internal logic

A4-B4, B11-A11, D15-D14, E2-E1, G12-G13, H4-H3, J12-J13, M1-M2, M8-N8, P5-R5

• Power supply pairs for input and output

A1-B1, A7-B7, A15-A14, F15-F14, K1-K2, M12-P14, M15-M14, R1-R2, R10-P10

• Power supply pairs for PLL

N13-N14, N13-P15

When Using a PLL Oscillator Circuit: Keep the wiring from the PLL VCC and PLL VSS

connection pattern to the power supply pins short, and make the pattern width large, to minimize

the inductance component.

The analog power supply system of the PLL is sensitive to noise. Therefore, the system

malfunction may occur by the intervention with other power supply. Do not supply the analog

power supply with the same resource as the digital power supply of VCC and VCCQ.

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Section 9 Watchdog Timer (WDT)

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Section 9 Watchdog Timer (WDT)

This LSI includes the watchdog timer (WDT) that can reset this LSI by the overflow of the

counter when the value of the counter has not been updated because of a system runaway.

The WDT is a single-channel timer that uses a peripheral clock as an input and counts the clock

settling time when leaving software standby mode and temporary standby state, such as frequency

changes. It can also be used as an interval timer.

9.1 Features

The WDT has the following features:

• Can be used to ensure the clock settling time.

The WDT can be used when leaving software standby mode and the temporary standby state

which occur when the clock frequency is changed.

• Can switch between watchdog timer mode and interval timer mode.

• Internal resets in watchdog timer mode

Internal resets are generated when the counter overflows.

• Interrupts are generated in interval timer mode

Interval timer interrupts are generated when the counter overflows.

• Choice of eight counter input clocks

Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen.

Figure 9.1 is a block diagram of the WDT.

Section 9 Watchdog Timer (WDT)

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WTCSR

Standby

control

Bus interface

WTCNT

Divider

Clock selector

Clock

Standby

mode

Peripheral

clock (Pφ)

Standby

cancellation

Reset

control

Clock selection

WDT

Overflow

Internal

reset

request

Interrupt

control

Interrupt

request

WTCSR:

WTCNT:

[Legend]

Watchdog timer control/status register

Watchdog timer counter

Figure 9.1 Block Diagram of WDT

9.2 Register Descriptions

The WDT has the following two registers. For details on the addresses of these registers and the

states of these registers in each processing state, see section 18, List of Registers.

• Watchdog timer counter (WTCNT)

• Watchdog timer control/status register (WTCSR)

9.2.1 Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an

overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time

mode. WTCNT is not initialized by an internal power-on reset due to the WDT overflow. WTCNT

is initialized to H'00 by a power-on reset input to the pin and an H-UDI reset.

Use a word access to write to WTCNT, with H'5A in the upper byte. Use a byte access to read

WTCNT.

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Note: The writing method for WTCNT differs from other registers so that the WTCNT value

cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.

9.2.2 Watchdog Timer Control/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the

counting, bits to select the timer mode and overflow flags, and enable bits.

WTCSR holds its value in the internal reset state due to the WDT overflow. WTCSR is initialized

to H'00 by a power-on reset input to the pin and an H-UDI reset. To use it for counting the clock

settling time when leaving software standby mode, WTCSR holds its value after a counter

overflow.

Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read

WTCSR.

Note: The writing method for WTCNT differs from other registers so that the WTCNT value

cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.

Section 9 Watchdog Timer (WDT)

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Bit Bit Name

Initial

Value R/W Description

7 TME 0 R/W Timer Enable

Starts and stops timer operation. Clear this bit to 0

when using the WDT in software standby mode or

when changing the clock frequency.

0: Timer disabled: Count-up stops and WTCNT value

is retained

1: Timer enabled

6 WT/IT 0 R/W Timer Mode Select

Selects whether to use the WDT as a watchdog timer

or an interval timer.

0: Interval timer mode

1: Watchdog timer mode

Note: If WT/IT is modified when the WDT is

operating, the up-count may not be performed

correctly.

5  0 R Reserved

This bit is always red as 0. The write value should

always be 0.

4 WOVF 0 R/W Watchdog Timer Overflow

Indicates that WTCNT has overflowed in watchdog

timer mode. This bit is not set in interval timer mode.

0: No overflow

1: WTCNT has overflowed in watchdog timer mode

3 IOVF 0 R/W Interval Timer Overflow

Indicates that WTCNT has overflowed in interval timer

mode. This bit is not set in watchdog timer mode.

0: No overflow

1: WTCNT has overflowed in interval timer mode

Section 9 Watchdog Timer (WDT)

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Bit Bit Name

Initial

Value R/W Description

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select the clock to be used for the WTCNT

count from the eight types obtainable by dividing the

peripheral clock (Pφ). The overflow period that is

shown inside the parenthesis in the table is the value

when the peripheral clock (Pφ) is 25 MHz.

000: Pφ (10 µs)

001: Pφ /4 (41 µs)

010: Pφ /16 (164 µs)

011: Pφ /32 (328 µs)

100: Pφ /64 (655 µs)

101: Pφ /256 (2.62 ms)

110: Pφ /1024 (10.49 ms)

111: Pφ /4096 (41.94 ms)

Note: If bits CKS2 to CKS0 are modified when the

WDT is operating, the up-count may not be

performed correctly. Ensure that these bits are

modified only when the WDT is not operating.

9.2.3 Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are

more difficult to write to than other registers. The procedure for writing to these registers is given

below.

Writing to WTCNT and WTCSR: These registers must be written by a word transfer

instruction. They cannot be written by a byte or longword transfer instruction. When writing to

WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in

figure 9.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the

write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.

Section 9 Watchdog Timer (WDT)

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15 8 7 0

H'5A Write data

Address: H'F815FF84

WTCNT write

15 8 7 0

H'A5 Write data

Address: H'F815FF86

WTCSR write

Figure 9.2 Writing to WTCNT and WTCSR

9.3 WDT Operation

9.3.1 Canceling Software Standbys

The WDT can be used to cancel software standby mode with an NMI interrupt or external

interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used

for canceling, so keep the RES pin low until the clock stabilizes.)

1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When

the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the

count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. Move to software standby mode by executing a SLEEP instruction to stop the clock.

4. The WDT starts counting by detecting the change of input levels of the NMI or IRQ pin.

5. When the WDT count overflows, the CPG starts supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set when this happens.

6. Since the WDT continues counting from H'00, set the STBY bit in STBCR to 0 in the interrupt

processing program and this will stop the WDT to count. When the STBY bit remains 1, the

LSI again enters software standby mode when the WDT has counted up to H'80. This software

standby mode can be canceled by a power-on reset.

Section 9 Watchdog Timer (WDT)

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9.3.2 Changing Frequency

To change the multiplication ratio of PLL circuit 1, use the WDT. When changing the frequency

only by switching the divider, do not use the WDT.

1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit

is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.

2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for

the counter in WTCNT. These values should ensure that the time till count overflow is longer

than the clock oscillation settling time.

3. When bits STC2 to STC0 in the frequency control register (FRQCR) is written, the processor

stops temporarily. The WDT starts counting.

4. When the WDT count overflows, the CPG resumes supplying the clock and the processor

resumes operation. The WOVF flag in WTCSR is not set when this happens.

5. WTCNT stops at the value of H'00.

6. Before changing WTCNT after the execution of the frequency change instruction, always

confirm that the value of WTCNT is H'00 by reading WTCNT.

9.3.3 Using Watchdog Timer Mode

1. Set the WT/IT bit in WTCSR to 1, set the type of count clock in bits CKS2 to CKS0, and set

the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.

3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent

the counter from overflowing.

4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates a

power-on reset. WTCNT then resumes counting.

Section 9 Watchdog Timer (WDT)

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9.3.4 Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of

the counter. This enables interrupts to be generated at set periods.

1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and

set the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.

3. When the WTCNT overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval

timer interrupt request is sent to the INTC. The WTCNT then resumes counting.

9.4 Usage Note

Note the following when using the WDT.

1. When using the WDT in interval mode, no overflow occurs by the H'00 immediately after

writing H'FF to WDTCNT. (IOVF in WTCSR is not set.) The overflow occurs at a point when

the count reaches H'00 after one cycle.

This does not occur when the WDT is used in watchdog timer mode.

Section 10 Power-Down Modes

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Section 10 Power-Down Modes

This LSI supports the following power-down modes: sleep mode, software standby mode, module

standby mode.

10.1 Features

• Supports sleep mode, software standby mode, and module standby

10.1.1 Types of Power-Down Modes

This LSI has the following power-down modes.

• Sleep mode

• Software standby mode

• Module standby mode (cache, U-memory, UBC, H-UDI, and on-chip peripheral modules)

Table 10.1 shows the methods to make a transition from the program execution state, as well as

the CPU and peripheral module states in each mode and the procedures for canceling each mode.

Section 10 Power-Down Modes

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Table 10.1 States of Power-Down Modes

State

Mode Transition Method CPG CPU

CPU

On-Chip

Memory

On-Chip

Peripheral

Modules Pins

Canceling

Procedure

Sleep Execute SLEEP

instruction with

STBY bit in STBCR

cleared to 0.

Runs Halts Held Halts

(contents

remained)

Run Held

• Interrupt

other than

user break

• Reset

Software

standby

Execute SLEEP

instruction with

STBY bit in STBCR

set to 1.

Halts Halts Held Halts

(contents

remained)

Halt Held

• NMI, IRQ

• Reset

Module

standby

Set MSTP bits in

STBCR2 to STBCR4

to 1.

Runs Runs Held Specified

module halts

(contents

remained)

Specified

module halts

Held • Clear

MSTP bit

to 0

• Power-on

reset

Section 10 Power-Down Modes

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10.2 Input/Output Pins

Table 10.2 lists the pins used for the power-down modes.

Table 10.2 Pin Configuration

Pin Name Abbr. I/O Description

Reset input pin RES Input Reset input signal. Reset by low level.

10.3 Register Descriptions

There are following registers used for the power-down modes. For details on the addresses of

these registers and the states of these registers in each processing state, see section 18, List of

Registers.

• Standby control register (STBCR)

• Standby control register 2 (STBCR2)

• Standby control register 3 (STBCR3)

• Standby control register 4 (STBCR4)

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10.3.1 Standby Control Register (STBCR)

STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode.

Bit Bit Name

Initial

Value R/W Description

7 STBY 0 R/W Standby

Specifies transition to software standby mode.

0: Executing SLEEP instruction makes this LSI

sleep mode

1: Executing SLEEP instruction makes this LSI

software standby mode

6 to 4  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

3 MDCHG 0 R/W MD2 to MD0 Pin Control

Specifies whether or not the values of pins MD2 to

MD0 are reflected in software standby mode. The

values of pins MD2 to MD0 are reflected at returning

from software standby mode by an interrupt when

the MDCHG bit has been set to 1.

0: The values of pins MD2 to MO0 are not reflected

in software standby mode.

1: The values of pins MD2 to MD0 are reflected in

software standby mode.

2 to 0  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

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10.3.2 Standby Control Register 2 (STBCR2)

STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-

down mode.

Bit Bit Name

Initial

Value R/W Description

7 MSTP10 0 R/W Module Stop Bit 10

When this bit is set to 1, the supply of the clock to

the H-UDI is halted.

0: H-UDI operates

1: Clock supply to H-UDI halted

6 MSTP9 0 R/W Module Stop Bit 9

When this bit is set to 1, the supply of the clock to

the UBC is halted.

0: UBC operates

1: Clock supply to UBC halted

5 to 3  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

2 MSTP5 0 R/W Module Stop Bit 5

When this bit is set to 1, the supply of the clock to

the cache memory is halted.

0: Cache memory operates

1: Clock supply to cache memory halted

1 MSTP4 0 R/W Module Stop Bit 4

When this bit is set to 1, the supply of the clock to

the U memory is halted.

0: U memory operates

1: Clock supply to the U memory halted

0  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

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10.3.3 Standby Control Register 3 (STBCR3)

STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-

down mode.

Bit Bit Name

Initial

Value R/W Description

7 to 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

4 MSTP15 0 R/W Module Stop Bit 15

When this bit is set to 1, the supply of the clock to the

CMT is halted.

0: CMT operates

1: Clock supply to CMT halted

3  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

2 MSTP13 0 R/W Module Stop Bit 13

When this bit is set to 1, the supply of the clock to the

SCIF2 is halted.

0: SCIF2 operates

1: Clock supply to SCIF2 halted

1 MSTP12 0 R/W Module Stop Bit 12

When this bit is set to 1, the supply of the clock to the

SCIF1 is halted.

0: SCIF1 operates

1: Clock supply to SCIF1 halted

0 MSTP11 0 R/W Module Stop Bit 11

When this bit is set to 1, the supply of the clock to the

SCIF0 is halted.

0: SCIF0 operates

1: Clock supply to SCIF0 halted

Section 10 Power-Down Modes

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10.3.4 Standby Control Register 4 (STBCR4)

STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-

down mode.

Bit Bit Name

Initial

Value R/W Description

7 to 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

4 MSTP23 0 R/W Module Stop Bit 23

When this bit is set to 1, the supply of the clock to the

HIF is halted.

0: HIF operates

1: Clock supply to HIF halted

3 to 1  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

0 MSTP19 0 R/W Module Stop Bit 19

Setting MSTP19 to1 stops supplying clock to

redundancy logic. Set MSTP19 to 1 immediately after

releasing a power-on reset.

0: Redundancy logic is in operation

1: Stops supplying clock to redundancy logic

Section 10 Power-Down Modes

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10.4 Sleep Mode

10.4.1 Transition to Sleep Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the

program execution state to sleep mode. Although the CPU halts immediately after executing the

SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral

modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.

10.4.2 Canceling Sleep Mode

Sleep mode is canceled by an interrupt other than a user break (NMI, H-UDI, IRQ, and on-chip

peripheral module) or a reset.

Canceling with Interrupt: When a user-break, NMI, H-UDI, IRQ, or on-chip peripheral module

interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the

priority level of an IRQ or on-chip peripheral module interrupt is lower than the interrupt mask

level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing

sleep mode from being canceled.

Canceling with Reset: Sleep mode is canceled by a power-on reset or an H-UDI reset.

10.5 Software Standby Mode

10.5.1 Transition to Software Standby Mode

This LSI switches from a program execution state to software standby mode by executing the

SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the

CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin

also halts.

The contents of the CPU and cache registers remain unchanged. Some registers of on-chip

peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral

modules registers in software standby mode.

Section 10 Power-Down Modes

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Table 10.3 Register States in Software Standby Mode

Module Registers Initialized Registers Retaining Data

Interrupt controller (INTC)  All registers

Clock pulse generator (CPG)  All registers

User break controller (UBC)  All registers

Bus state controller (BSC)  All registers

I/O port  All registers

User debugging interface (H-UDI)  All registers

Serial communication interface with FIFO

(SCIF0 to SCIF2)

 All registers

Compare match timer (CMT0 and CMT1) All registers 

Host interface (HIF)  All registers

The procedure for switching to software standby mode is as follows:

1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.

2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to

appropriate values to secure the specified oscillation settling time.

3. After setting the STBY bit in STBCR to 1, execute the SLEEP instruction.

4. Software standby mode is entered and the clocks within this LSI are halted.

Section 10 Power-Down Modes

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10.5.2 Canceling Software Standby Mode

Software standby mode is canceled by interrupts (NMI, IRQ) or a reset.

Canceling with Interrupt: The WDT can be used for hot starts. When an NMI or IRQ interrupt is

detected, the clock will be supplied to the entire LSI and software standby mode will be canceled

after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception

handling is then executed. After the branch to the interrupt handling routine, clear the STBY bit in

STBCR. WTCNT stops automatically. If the STBY bit is not cleared, WTCNT continues

operation and a transition is made to software standby mode* when it reaches H'80. This function

prevents data destruction due to the voltage rise by an unstable power supply voltage.

IRQ cancels the software standby mode when the input condition matches the specified detect

condition while the IRQn1S and IRQn0S bits in IRQCR are not B'00 (settings other than the low

level detection). When the priority level of an IRQ interrupt is lower than the interrupt mask level

set in the status register (SR) of the CPU, the execution of the instruction following the SLEEP

instruction starts again after the cancellation of software standby mode. When the priority level of

an IRQ interrupt is higher than the interrupt mask level set in the status register (SR) of the CPU,

IRQ interrupt exception handling is executed after the cancellation of software standby mode.

Note: * This software standby mode can be canceled only by a power-on reset.

WTCNT value

H'FF

H'80

Time

Interrupt

request

WDT overflow and branch to

interrupt handling routine

Crystal oscillator settling

time and PLL synchronization time

Clear bit STBCR.STBY before

WTCNT reaches H'80. When

STBCR.STBY is cleared, WTCNT

halts automatically.

Figure 10.1 Canceling Standby Mode with STBY Bit in STBCR

Section 10 Power-Down Modes

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Canceling with Reset: Software standby mode is canceled by a power-on reset. Keep the RES pin

low until the clock oscillation settles. The internal clock will continue to be output to the CKIO

pin.

10.6 Module Standby Mode

10.6.1 Transition to Module Standby Mode

Setting the MSTP bits in the standby control registers (STBCR2 to STBCR4) to 1 halts the supply

of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the

power consumption in normal mode.

In module standby mode, the states of the external pins of the on-chip peripheral modules change

depending on the on-chip peripheral module and port settings. Almost all of the registers retains

its previous state.

10.6.2 Canceling Module Standby Function

The module standby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR4

to 0, or by a power-on reset.

Section 10 Power-Down Modes

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Section 11 Compare Match Timer (CMT)

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Section 11 Compare Match Timer (CMT)

This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The

CMT has a16-bit counter, and can generate interrupts at set intervals.

11.1 Features

CMT has the following features.

• Selection of four counter input clocks

Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently

for each channel.

• Interrupt request on compare match

• When not in use, CMT can be stopped by halting its clock supply to reduce power

consumption.

Figure 11.1 shows a block diagram of CMT.

Control circuit Clock selection

CMSTR0

CMCSR0

CMCOR0

CMCNT0

Channel 0 Channel 1

CMT

Pφ/8

CMCSR1

CMCOR1

CMCNT1

Pφ/32

Pφ/128

Pφ/512

Pφ/8

Pφ/32

Pφ/128

Pφ/512

Clock selectionControl circuit

Comparator

[Legend]

CMSTR: Compare match timer start register

CMCSR: Compare match timer control/status register

CMCOR: Compare match timer constant register

CMCNT: Compare match counter

CMI: Compare match interrupt

Module bus

Bus

interface

Internal bus

CMI0 CMI1

Figure 11.1 Block Diagram of Compare Match Timer

Section 11 Compare Match Timer (CMT)

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11.2 Register Descriptions

The CMT has the following registers.

• Compare match timer start register (CMSTR)

• Compare match timer control/status register_0 (CMCSR_0)

• Compare match counter_0 (CMCNT_0)

• Compare match constant register_0 (CMCOR_0)

• Compare match timer start register_1 (CMSTR_1)

• Compare match timer control/status register_1 (CMCSR_1)

• Compare match counter_1 (CMCNT_1)

• Compare match constant register_1 (CMCOR_1)

11.2.1 Compare Match Timer Start Register (CMSTR)

CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is

stopped.

CMSTR is initialized to H'0000 by a power-on reset and a transition to standby mode.

Bit Bit Name

Initial

value R/W Description

15 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

1 STR1 0 R/W Count Start 1

Specifies whether compare match counter 1 operates

or is stopped.

0: CMCNT_1 count is stopped

1: CMCNT_1 count is started

0 STR0 0 R/W Count Start 0

Specifies whether compare match counter 0 operates

or is stopped.

0: CMCNT_0 count is stopped

1: CMCNT_0 count is started

Section 11 Compare Match Timer (CMT)

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11.2.2 Compare Match Timer Control/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects

the counter input clock.

CMCSR is initialized to H'0000 by a power-on reset and a transition to standby mode.

Bit Bit Name

Initial

value R/W Description

15 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 CMF 0 R/(W)*Compare Match Flag

Indicates whether or not the values of CMCNT and

CMCOR match.

0: CMCNT and CMCOR values do not match

[Clearing condition]

When 0 is written to this bit

1: CMCNT and CMCOR values match

6 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables compare match interrupt (CMI)

generation when CMCNT and CMCOR values match

(CMF=1).

0: Compare match interrupt (CMI) disabled

1: Compare match interrupt (CMI) enabled

5 to 2  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

Section 11 Compare Match Timer (CMT)

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Bit Bit Name

Initial

value R/W Description

CKS1

CKS0

R/W

Clock Select 1 and 0

Select the clock to be input to CMCNT from four

internal clocks obtained by dividing the peripheral

operating clock (Pφ). When the STR bit in CMSTR is

set to 1, CMCNT starts counting on the clock selected

with bits CKS1 and CKS0.

00: Pφ/8

01: Pφ/32

10: Pφ/128

11: Pφ/512

Note: * Only 0 can be written, to clear the flag.

11.2.3 Compare Match Counter (CMCNT)

CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with

bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting

using the selected clock.

When the value in CMCNT and the value in compare match constant register (CMCOR) match,

CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.

CMCNT is initialized to H'0000 by a power-on reset and a transition to standby mode.

11.2.4 Compare Match Constant Register (CMCOR)

CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.

CMCOR is initialized to H'FFFF by a power-on reset and is initialized to H'FFFF in standby

mode.

Section 11 Compare Match Timer (CMT)

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11.3 Operation

11.3.1 Interval Count Operation

When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in

CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in

CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set

to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested.

CMCNT then starts counting up again from H'0000.

Figure 11.2 shows the operation of the compare match counter.

CMCOR1

H'0000

CMCNT1 value

Time

Counter cleared by compare

match with CMCOR1

Figure 11.2 Counter Operation

11.3.2 CMCNT Count Timing

One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock

can be selected with bits CKS1 and CKS0 in CMCSR. Figure 11.3 shows the timing.

Peripheral operating

clock (Pφ)

Nth

clock (N + 1)th

clock

Count clock

CMCNT1 N N + 1

Figure 11.3 Count Timing

Section 11 Compare Match Timer (CMT)

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11.4 Interrupts

11.4.1 Interrupt Sources

The CMT has channels and each of them to which a different vector address is allocated has

compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit

(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to

activate a CPU interrupt, the priority of channels can be changed by the interrupt controller

settings. For details, see section 6, Interrupt Controller (INTC).

11.4.2 Timing of Setting Compare Match Flag

When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in

CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values

match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR

and CMCNT, the compare match signal is not generated until the next CMCNT counter clock

input. Figure 11.4 shows the timing of CMF bit setting.

Peripheral operating

clock (Pφ)

Counter clock

CMCNT1

CMCOR1

Compare match

signal

(N + 1)th

clock

Figure 11.4 Timing of CMF Setting

11.4.3 Timing of Clearing Compare Match Flag

The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0.

Section 11 Compare Match Timer (CMT)

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11.5 Usage Notes

11.5.1 Conflict between Write and Compare-Match Processes of CMCNT

When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing

CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 11.5 shows

the timing to clear the CMCNT counter.

Peripheral operating

clock (Pφ)

Address

Internal write

Counter clear

CMCNT

T1 T2

N H'0000

CMCSR write cycle

CMCNT

Figure 11.5 Conflict between Write and Compare-Match Processes of CMCNT

11.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has

priority over the count-up. In this case, the count-up is not performed. Figure 11.6 shows the

timing to write to CMCNT in words.

Section 11 Compare Match Timer (CMT)

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CMCNT count-up

enable

Peripheral operating

clock (Pφ)

Address

Internal write

CMCNT

T1 T2

CMCSR write cycle

CMCNT

Figure 11.6 Conflict between Word-Write and Count-Up Processes of CMCNT

11.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT

Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing

has priority over the count-up. In this case, the count-up is not performed. The byte data on

another side, which is not written to, is also not counted and the previous contents remain.

Figure 11.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT

in bytes.

Section 11 Compare Match Timer (CMT)

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CMCNTH

CMCNT count-up

enable

CMCNTH

CMCNTL

Peripheral operating

clock (Pφ)

Address

Internal write

T1 T2

CMCSR write cycle

Figure 11.7 Conflict between Byte-Write and Count-Up Processes of CMCNT

11.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and

CMCOR

Writing the same value to CMCNT with the counting stopped and CMCOR is prohibited. If

written, the CMF flag in CMCSR is set to 1 and CMCNT is cleared to H'0000.

Section 11 Compare Match Timer (CMT)

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Section 12 Serial Communication Interface with FIFO (SCIF)

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Section 12 Serial Communication Interface with FIFO

(SCIF)

12.1 Overview

This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both

asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for

both transmission and reception independently for each channel that enable this LSI to perform

efficient high-speed continuous communication.

12.1.1 Features

• Asynchronous serial communication:

 Serial data communication is performed by start-stop in character units. The SCIF can

communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous

communication interface adapter (ACIA), or any other communications chip that employs

a standard asynchronous serial system. There are eight selectable serial data

communication formats.

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2 bits

 Parity: Even, odd, or none

 Receive error detection: Parity, framing, and overrun errors

 Break detection: Break is detected when a framing error is followed by at least one frame at

the space 0 level (low level). It is also detected by reading the RxD level directly from the

port data register when a framing error occurs.

• Synchronous mode:

 Serial data communication is synchronized with a clock signal. The SCIF can communicate

with other chips having a synchronous communication function. There is one serial data

communication format.

 Data length: 8 bits

 Receive error detection: Overrun errors

• Full duplex communication: The transmitting and receiving sections are independent, so the

SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so

high-speed continuous data transfer is possible in both the transmit and receive directions.

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• On-chip baud rate generator with selectable bit rates

• Internal or external transmit/receive clock source: From either baud rate generator (internal) or

SCK pin (external)

• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and

receive-error interrupts are requested independently.

• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving

power.

• In asynchronous, on-chip modem control functions (RTS and CTS) (only for channel 1 and

channel 0).

• The number of data in the transmit and receive FIFO registers and the number of receive errors

of the receive data in the receive FIFO register can be ascertained.

• A time-out error (DR) can be detected when receiving in asynchronous mode.

Figure 12.1 shows a block diagram of the SCIF for each channel.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Module data bus

SCFRDR

(16 stage)

SCRSR

RxD

TxD

SCK

CTS

RTS

SCFTDR

(16 stage)

SCTSR

SCSMR

SCLSR

SCFDR

SCFCR

SCFSR

SCBRRn

Parity generation

Parity check

Transmission/

reception

control

Baud rate

generator

Clock

External clock

Pφ

Pφ/4

Pφ/16

Pφ/64

TXI

RXI

ERI

BRI

SCIF

Bus interface

Internal

data bus

SCSCR

SCSPTR

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

[Legend]

SCFSR:

SCBRR:

SCSPTR:

SCFCR:

SCFDR:

SCLSR:

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial port register

FIFO control register

FIFO data count register

Line status register

Figure 12.1 Block Diagram of SCIF

Section 12 Serial Communication Interface with FIFO (SCIF)

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12.2 Pin Configuration

The SCIF has the serial pins summarized in table 12.1.

Table 12.1 SCIF Pins

Channel Pin Name Abbreviation I/O Function

0 Serial clock pin SCK0 I/O Clock I/O

Receive data pin RxD0 Input Receive data input

Transmit data pin TxD0 Output Transmit data output

Request to send pin RTS0 I/O Request to send

Clear to send pin CTS0 I/O Clear to send

1 Serial clock pin SCK1 I/O Clock I/O

Receive data pin RxD1 Input Receive data input

Transmit data pin TxD1 Output Transmit data output

Request to send RTS1 Output Request to send

Clear to send pin CTS1 Input Clear to send

2 Serial clock pin SCK2 I/O Clock I/O

Receive data pin RxD2 Input Receive data input

Transmit data pin TxD2 Output Transmit data output

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12.3 Register Description

The SCIF has the following registers. These registers specify the data format and bit rate, and

control the transmitter and receiver sections.

• Receive FIFO data register_0 (SCFRDR_0)

• Transmit FIFO data register_0 (SCFTDR_0)

• Serial mode register_0 (SCSMR_0)

• Serial control register_0 (SCSCR_0)

• Serial status register_0 (SCFSR_0)

• Bit rate register_0 (SCBRR_0)

• FIFO control register_0 (SCFCR_0)

• FIFO data count register_0 (SCFDR_0)

• Serial port register_0 (SCSPTR_0)

• Line status register_0 (SCLSR_0)

• Receive FIFO data register_1 (SCFRDR_1)

• Transmit FIFO data register_1 (SCFTDR_1)

• Serial mode register_1 (SCSMR_1)

• Serial control register_1 (SCSCR_1)

• Serial status register_1 (SCFSR_1)

• Bit rate register_1 (SCBRR_1)

• FIFO control register_1 (SCFCR_1)

• FIFO data count register_1 (SCFDR_1)

• Serial port register_1 (SCSPTR_1)

• Line status register_1 (SCLSR_1)

• Receive FIFO data register_2 (SCFRDR_2)

• Transmit FIFO data register_2 (SCFTDR_2)

• Serial mode register_2 (SCSMR_2)

• Serial control register_2 (SCSCR_2)

• Serial status register_2 (SCFSR_2)

• Bit rate register_2 (SCBRR_2)

• FIFO control register_2 (SCFCR_2)

• FIFO data count register_2 (SCFDR_2)

• Serial port register_2 (SCSPTR_2)

• Line status register_2 (SCLSR_2)

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12.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,

LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is

automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or

write to SCRSR directly.

12.3.2 Receive FIFO Data Register (SCFRDR)

SCFRDR is a 16-stage 8-bit FIFO register that stores serial receive data. The SCIF completes the

reception of one byte of serial data by moving the received data from the receive shift register

(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.

The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the

SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data

is lost.

SCFRDR is initialized to undefined value by a power-on reset.

Bit Bit Name

Initial

value R/W Description

7 to 0  Undefined R FIFO for transmits serial data

12.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register

(SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After

transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into

SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly.

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12.3.4 Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF

detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the

SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed

until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU.

When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new

data is attempted, the data is ignored.

SCFTDR is initialized to undefined value by a power-on reset.

Bit Bit Name

Initial

value R/W Description

7 to 0  Undefined W FIFO for transmits serial data

12.3.5 Serial Mode Register (SCSMR)

SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the

clock source for the baud rate generator.

The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on

reset.

Bit Bit Name

Initial

value R/W Description

15 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 C/A 0 R/W Communication Mode

Selects whether the SCIF operates in asynchronous or

synchronous mode.

0: Asynchronous mode

1: Synchronous mode

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Bit Bit Name

Initial

value R/W Description

6 CHR 0 R/W Character Length

Selects 7-bit or 8-bit data in asynchronous mode. In the

synchronous mode, the data length is always eight bits,

regardless of the CHR setting.

0: 8-bit data

1: 7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) of

the transmit FIFO data register is not transmitte

5 PE 0 R/W Parity Enable

Selects whether to add a parity bit to transmit data and

to check the parity of receive data, in asynchronous

mode. In synchronous mode, a parity bit is neither

added nor checked, regardless of the PE setting.

0: Parity bit not added or checked

1: Parity bit added and checked*

Note: * When PE is set to 1, an even or odd parity bit

is added to transmit data, depending on the

parity mode (O/E) setting. Receive data parity

is checked according to the even/odd (O/E)

mode setting.

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Bit Bit Name

Initial

value R/W Description

4 O/E 0 R/W Parity Mode

Selects even or odd parity when parity bits are added

and checked. The O/E setting is used only in

asynchronous mode and only when the parity enable

bit (PE) is set to 1 to enable parity addition and

checking. The O/E setting is ignored in synchronous

mode, or in asynchronous mode when parity addition

and checking is disabled.

0: Even parity*1

1: Odd parity*2

Notes: 1. If even parity is selected, the parity bit is

added to transmit data to make an even

number of 1s in the transmitted character and

parity bit combined. Receive data is checked

to see if it has an even number of 1s in the

received character and parity bit combined.

2. If odd parity is selected, the parity bit is

added to transmit data to make an odd

number of 1s in the transmitted character and

parity bit combined. Receive data is checked

to see if it has an odd number of 1s in the

received character and parity bit combined.

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Bit Bit Name

Initial

value R/W Description

3 STOP 0 R/W Stop Bit Length

Selects one or two bits as the stop bit length in

asynchronous mode. This setting is used only in

asynchronous mode. It is ignored in synchronous

mode because no stop bits are added.

When receiving, only the first stop bit is checked,

regardless of the STOP bit setting. If the second stop

bit is 1, it is treated as a stop bit, but if the second stop

bit is 0, it is treated as the start bit of the next incoming

character.

0: One stop bit

When transmitting, a single 1-bit is added at the end

of each transmitted character.

1: Two stop bits

When transmitting, two 1 bits are added at the end of

each transmitted character.

2  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

CKS1

CKS0

R/W

Clock Select 1 and 0

Select the internal clock source of the on-chip baud rate

generator. Four clock sources are available. Pφ, Pφ/4,

Pφ/16 and Pφ/64. For further information on the clock

source, bit rate register settings, and baud rate, see

section 12.3.8, Bit Rate Register (SCBRR).

00: Pφ

01: Pφ/4

10: Pφ/16

11: Pφ/64

Note: Pφ: Peripheral clock

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12.3.6 Serial Control Register (SCSCR)

SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt

requests, and selects the transmit/receive clock source. The CPU can always read and write to

SCSCR. SCSCR is initialized to H'0000 by a power-on reset.

Bit Bit Name

Initial

value R/W Description

15 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 TIE 0 R/W Transmit Interrupt Enable

Enables or disables the transmit-FIFO-data-empty

interrupt (TXI).

Serial transmit data in the transmit FIFO data register

(SCFTDR) is send to the transmit shift register

(SCTSR). Then, the TDFE flag in the serial status

SCFTDR becomes less than the number of

transmission triggers. At this time, a TXI is requested.

0: Transmit-FIFO-data-empty interrupt request (TXI) is

disabled*

1: Transmit-FIFO-data-empty interrupt request (TXI) is

enabled

Note: * The TXI interrupt request can be cleared by

writing a greater number of transmit data than

the specified transmission trigger number to

SCFTDR and by clearing the TDFE bit to 0

after reading 1 from the TDFE bit, or can be

cleared by clearing this bit to 0.

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Bit Bit Name

Initial

value R/W Description

6 RIE 0 R/W Receive Interrupt Enable

Enables or disables the receive-data-full (RXI)

interrupts requested when the RDF flag or DR flag in

serial status register (SCFSR) is set to1, receive-error

(ERI) interrupts requested when the ER flag in SCFSR

is set to1, and break (BRI) interrupts requested when

the BRK flag in SCFSR or the ORER flag in line status

0: Receive-data-full interrupt (RXI), receive-error

interrupt (ERI), and break interrupt (BRI) requests

are disabled*

1: Receive-data-full interrupt (RXI), receive-error

interrupt (ERI), and break interrupt (BRI) requests

are enabled

Note: * RXI interrupt requests can be cleared by

reading the DR or RDF flag after it has been

set to 1, then clearing the flag to 0, or by

clearing RIE to 0. ERI or BRI interrupt requests

can be cleared by reading the ER, BR or

ORER flag after it has been set to 1, then

clearing the flag to 0, or by clearing RIE and

REIE to 0.

5 TE 0 R/W Transmit Enable

Enables or disables the SCIF serial transmitter.

0: Transmitter disabled

1: Transmitter enabled*

Note: * Serial transmission starts after writing of

transmit data into SCFTDR. Select the transmit

format in SCSMR and SCFCR and reset the

transmit FIFO before setting TE to 1.

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Bit Bit Name

Initial

value R/W Description

4 RE 0 R/W Receive Enable

Enables or disables the SCIF serial receiver.

0:Receiver disabled*1

1: Receiver enabled*2

Notes: 1. Clearing RE to 0 does not affect the receive

flags (DR, ER, BRK, RDF, FER, PER, and

ORER). These flags retain their previous

values.

2. Serial reception starts when a start bit is

detected in asynchronous mode, or

synchronous clock input is detected in

synchronous mode. Select the receive format

in SCSMR and SCFCR and reset the receive

FIFO before setting RE to 1.

3 REIE 0 R Receive Error Interrupt Enable

Enables or disables the receive-error (ERI) interrupts

and break (BRI) interrupts. The setting of REIE bit is

valid only when RIE bit is set to 0.

0: Receive-error interrupt (ERI) and break interrupt

(BRI) requests are disabled*

1: Receive-error interrupt (ERI) and break interrupt

(BRI) requests are enabled

Note: * ERI or BRI interrupt requests can be cleared

by reading the ER, BR or ORER flag after it

has been set to 1, then clearing the flag to 0, or

by clearing RIE and REIE to 0. Even if RIE is

set to 0, when REIE is set to 1, ERI or BRI

interrupt requests are enabled.

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Bit Bit Name

Initial

value R/W Description

2  0 R Reserved

This bit is always read as 0. The write value should

always be 0.

CKE1

CKE0

R/W

Clock Enable 1 and 0

Select the SCIF clock source and enable or disable

clock output from the SCK pin. Depending on the

combination of CKE1 and CKE0, the SCK pin can be

used for serial clock output or serial clock input.

The CKE0 setting is valid only when the SCIF is

operating on the internal clock (CKE1 = 0). The CKE0

setting is ignored when an external clock source is

selected (CKE1 = 1). In synchronous mode, select the

SCIF operating mode in the serial mode register

(SCSMR), then set CKE1 and CKE0.

• Asynchronous mode

00: Internal clock, SCK pin used for input pin (The input

signal is ignored. The state of the SCK pin depends

on both the SCKIO and SCKDT bits.)

01: Internal clock, SCK pin used for clock output

(The output clock frequency is 16 times the bit rate.)

10: External clock, SCK pin used for clock input

(The input clock frequency is 16 times the bit rate.)

11: Setting prohibited

• Synchronous mode

00: Internal clock, SCK pin used for serial clock output

01: Internal clock, SCK pin used for serial clock output

10: External clock, SCK pin used for serial clock input

11: Setting prohibited

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12.3.7 Serial Status Register (SCFSR)

SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR

data, and the lower 8 bits indicate the status flag indicating SCIF operating state.

The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,

TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read

(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is

initialized to H'0060 by a power-on reset.

Bit Bit Name

Initial

value R/W Description

PER3

PER2

PER1

PER0

Number of Parity Errors

Indicate the number of data including a parity error in

the receive data stored in the receive FIFO data

12 represents the number of parity errors in

SCFRDR. When parity errors have occurred in all

16-byte receive data in SCFRDR, PER3 to PER0

show 0.

FER3

FER2

FER1

FER0

Number of Framing Errors

Indicate the number of data including a framing error

in the receive data stored in SCFRDR. The value

indicated by bits 11 to 8 represents the number of

framing errors in SCFRDR. When framing errors have

occurred in all 16-byte receive data in SCFRDR,

FER3 to FER0 show 0.

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Bit Bit Name

Initial

value R/W Description

7 ER 0 R/(W)* Receive Error

Indicates the occurrence of a framing error, or of a

parity error when receiving data that includes parity.*1

0: Receiving is in progress or has ended normally

[Clearing conditions]

• ER is cleared to 0 a power-on reset

• ER is cleared to 0 when the chip is when 0 is

written after 1 is read from ER

1: A framing error or parity error has occurred.

[Setting conditions]

• ER is set to 1 when the stop bit is 0 after checking

whether or not the last stop bit of the received

data is 1 at the end of one data receive

operation*2

• ER is set to 1 when the total number of 1s in the

receive data plus parity bit does not match the

even/odd parity specified by the O/E bit in

SCSMR

Notes: 1. Clearing the RE bit to 0 in SCSCR does not

affect the ER bit, which retains its previous

value. Even if a receive error occurs, the

receive data is transferred to SCFRDR and

the receive operation is continued. Whether

or not the data read from SCRDR includes

a receive error can be detected by the FER

and PER bits in SCFSR.

2. In two stop bits mode, only the first stop bit

is checked; the second stop bit is not

checked.

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Bit Bit Name

Initial

value R/W Description

6 TEND 1 R/(W)* Transmit End

Indicates that when the last bit of a serial character

was transmitted, SCFTDR did not contain valid data,

so transmission has ended.

0: Transmission is in progress

[Clearing condition]

TEND is cleared to 0 when 0 is written after 1 is read

from TEND after transmit data is written in SCFTDR

1: End of transmission

[Setting conditions]

• TEND is set to 1 when the chip is a power-on

reset

• TEND is set to 1 when TE is cleared to 0 in the

serial control register (SCSCR)

• TEND is set to 1 when SCFTDR does not contain

receive data when the last bit of a one-byte serial

character is transmitted

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Bit Bit Name

Initial

value R/W Description

5 TDFE 1 R/(W)* Transmit FIFO Data Empty

Indicates that data has been transferred from the

transmit FIFO data register (SCFTDR) to the transmit

shift register (SCTSR), the number of data in

SCFTDR has become less than the transmission

trigger number specified by the TTRG1 and TTRG0

bits in the FIFO control register (SCFCR), and writing

of transmit data to SCFTDR is enabled.

0: The number of transmit data written to SCFTDR is

greater than the specified transmission trigger

number

[Clearing conditions]

• TDFE is cleared to 0 when data exceeding the

specified transmission trigger number is written to

SCFTDR after 1 is read from the TDFE bit and

then 0 is written

• TDFE is cleared to 0 when DMAC write data

exceeding the specified transmission trigger

number to SCFTDR

1: The number of transmit data in SCFTDR is equal to

or less than the specified transmission trigger

number*

[Setting conditions]

• TDFE is set to 1 by a power-on reset

• TDFE is set to 1 when the number of transmit

data in SCFTDR becomes equal to or less than

the specified transmission trigger number as a

result of transmission

Note: * Since SCFTDR is a 16-byte FIFO register,

the maximum number of data that can be

written when TDFE is 1 is "16 minus the

specified transmission trigger number". If an

attempt is made to write additional data, the

data is ignored. The number of data in

SCFTDR is indicated by the upper 8 bits of

SCFDR.

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Bit Bit Name

Initial

value R/W Description

4 BRK 0 R/(W)* Break Detection

Indicates that a break signal has been detected in

receive data.

0: No break signal received

[Clearing conditions]

• BRK is cleared to 0 when the chip is a power-on

reset

• BRK is cleared to 0 when software reads BRK

after it has been set to 1, then writes 0 to BRK

1: Break signal received*

[Setting condition]

BRK is set to 1 when data including a framing error is

received, and a framing error occurs with space 0 in

the subsequent receive data

Note: * When a break is detected, transfer of the

receive data (H'00) to SCFRDR stops after

detection. When the break ends and the

receive signal becomes mark 1, the transfer

of receive data resumes.

3 FER 0 R Framing Error

Indicates a framing error in the data read from the

next receive FIFO data register (SCFRDR) in

asynchronous mode.

0: No receive framing error occurred in the next data

read from SCFRDR

[Clearing conditions]

• FER is cleared to 0 when the chip undergoes a

power-on reset

• FER is cleared to 0 when no framing error is

present in the next data read from SCFRDR

1: A receive framing error occurred in the next data

read from SCFRDR.

[Setting condition]

FER is set to 1 when a framing error is present in the

next data read from SCFRDR

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Bit Bit Name

Initial

value R/W Description

2 PER 0 R Parity Error

Indicates a parity error in the data read from the next

receive FIFO data register (SCFRDR) in

asynchronous mode.

0: No receive parity error occurred in the next data

read from SCFRDR

[Clearing conditions]

• PER is cleared to 0 when the chip undergoes a

power-on reset

• PER is cleared to 0 when no parity error is

present in the next data read from SCFRDR

1: A receive parity error occurred in the data read

from SCFRDR

[Setting condition]

PER is set to 1 when a parity error is present in the

next data read from SCFRDR

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Bit Bit Name

Initial

value R/W Description

1 RDF 0 R/(W)* Receive FIFO Data Full

Indicates that receive data has been transferred to

the receive FIFO data register (SCFRDR), and the

number of data in SCFRDR has become more than

the receive trigger number specified by the RTRG1

and RTRG0 bits in the FIFO control register

(SCFCR).

0: The number of transmit data written to SCFRDR is

less than the specified receive trigger number

[Clearing conditions]

• RDF is cleared to 0 by a power-on reset

• RDF is cleared to 0 when the SCFRDR is read

until the number of receive data in SCFRDR

becomes less than the specified receive trigger

number after 1 is read from RDF and then 0 is

written

1: The number of receive data in SCFRDR is more

than the specified receive trigger number

[Setting condition]

RDF is set to 1 when a number of receive data more

than the specified receive trigger number is stored in

SCFRDR*

Note: * SCFTDR is a 16-byte FIFO register. When

RDF is 1, the specified receive trigger

number of data can be read at the maximum.

If an attempt is made to read after all the data

in SCFRDR has been read, the data is

undefined. The number of receive data in

SCFRDR is indicated by the lower 8 bits of

SCFDR.

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Bit Bit Name

Initial

value R/W Description

0 DR 0 R/(W)* Receive Data Ready

Indicates that the number of data in the receive FIFO

data register (SCFRDR) is less than the specified

receive trigger number, and that the next data has not

yet been received after the elapse of 15 ETU from the

last stop bit in asynchronous mode. In clock

synchronous mode, this bit is not set to 1.

0: Receiving is in progress, or no receive data

remains in SCFRDR after receiving ended

normally

[Clearing conditions]

• DR is cleared to 0 when the chip undergoes a

power-on reset

• DR is cleared to 0 when all receive data are read

after 1 is read from DR and then 0 is written

1: Next receive data has not been received

[Setting condition]

DR is set to 1 when SCFRDR contains less data than

the specified receive trigger number, and the next

data has not yet been received after the elapse of 15

ETU from the last stop bit.*

Note: * This is equivalent to 1.5 frames with the 8-bit,

1-stop-bit format. (ETU: elementary time unit)

Note: * The only value that can be written is 0 to clear the flag.

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12.3.8 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the

CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive

bit rate.

The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.

Each channel has independent baud rate generator control, so different values can be set in three

channels.

The SCBRR setting is calculated as follows:

• Asynchronous mode:

N = × 10

- 1

64 × 2

2n-1

× B

Pφ

• Synchronous mode:

N = × 106 - 1

8 × 22n-1 × B

Pφ

B: Bit rate (bits/s)

N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)

(The setting value should satisfy the electrical characteristics.)

Pφ: Operating frequency for peripheral modules (MHz)

n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of

n, see table 12.2.)

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Table 12.2 SCSMR Settings

SCSMR Settings

n Clock Source CKS1 CKS0

0 Pφ 0 0

1 Pφ/4 0 1

2 Pφ/16 1 0

3 Pφ/64 1 1

Note: The bit rate error in asynchronous is given by the following formula:

Error (%) = - 1 × 100

(N + 1) × B × 64

2n-1

× 2

Pφ × 10

Table 12.3 lists examples of SCBRR settings in asynchronous mode, and table 12.4 lists examples

of SCBRR settings in synchronous mode.

Table 12.3 Bit Rates and SCBRR Settings in Asynchronous Mode

Pφ (MHz)

5 6 6.144

Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%)

110 2 88 –0.25 2 106 –0.44 2 108 0.08

150 2 64 0.16 2 77 0.16 2 79 0.00

300 1 129 0.16 1 155 0.16 1 159 0.00

600 1 64 0.16 1 77 0.16 1 79 0.00

1200 0 129 0.16 0 155 0.16 0 159 0.00

2400 0 64 0.16 0 77 0.16 0 79 0.00

4800 0 32 –1.36 0 38 0.16 0 39 0.00

9600 0 15 1.73 0 19 –2.34 0 19 0.00

19200 0 7 1.73 0 9 –2.34 0 9 0.00

31250 0 4 0.00 0 5 0.00 0 5 2.40

38400 0 3 1.73 0 4 –2.34 0 4 0.00

Section 12 Serial Communication Interface with FIFO (SCIF)

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Pφ (MHz)

7.3728 8 9.8304

Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%)

110 2 130 –0.07 2 141 0.03 2 174 –0.26

150 2 95 0.00 2 103 0.16 2 127 0.00

300 1 191 0.00 1 207 0.16 1 255 0.00

600 1 95 0.00 1 103 0.16 1 127 0.00

1200 0 191 0.00 0 207 0.16 0 255 0.00

2400 0 95 0.00 0 103 0.16 0 127 0.00

4800 0 47 0.00 0 51 0.16 0 63 0.00

9600 0 23 0.00 0 25 0.16 0 31 0.00

19200 0 11 0.00 0 12 0.16 0 15 0.00

31250 0 6 5.33 0 7 0.00 0 9 –1.70

38400 0 5 0.00 0 6 –6.99 0 7 0.00

Pφ (MHz)

10 12 12.288 14.7456

Bit Rate

(bits/s) n N

Error

(%) n N

Error

(%) n N

Error

(%) n N

Error

(%)

110 2 177 –0.25 2 212 0.03 2 217 0.08 3 64 0.70

150 2 129 0.16 2 155 0.16 2 159 0.00 2 191 0.00

300 2 64 0.16 2 77 0.16 2 79 0.00 2 95 0.00

600 1 129 0.16 1 155 0.16 1 159 0.00 1 191 0.00

1200 1 64 0.16 1 77 0.16 1 79 0.00 1 95 0.00

2400 0 129 0.16 0 155 0.16 0 159 0.00 0 191 0.00

4800 0 64 0.16 0 77 0.16 0 79 0.00 0 95 0.00

9600 0 32 –1.36 0 38 0.16 0 39 0.00 0 47 0.00

19200 0 15 1.73 0 19 0.16 0 19 0.00 0 23 0.00

31250 0 9 0.00 0 11 0.00 0 11 2.40 0 14 –1.70

38400 0 7 1.73 0 9 –2.34 0 9 0.00 0 11 0.00

Section 12 Serial Communication Interface with FIFO (SCIF)

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Pφ (MHz)

16 19.6608 20 24

Bit Rate

(bits/s)

Error

(%)

Error

(%)

Error

(%)

Error

(%)

110 3 70 0.03 3 86 0.31 3 88 –0.25 3 106 –0.44

150 2 207 0.16 2 255 0.00 3 64 0.16 3 77 0.16

300 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16

600 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16

1200 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16

2400 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16

4800 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16

9600 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16

19200 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16

31250 0 15 0.00 0 19 –1.70 0 19 0.00 0 23 0.00

38400 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34

Pφ (MHz)

24.576 28.7 30 33

Bit Rate

(bits/s)

Error

(%)

Error

(%)

Error

(%)

Error

(%)

110 3 108 0.08 3 126 0.31 3 132 0.13 3 145 0.33

150 3 79 0.00 3 92 0.46 3 97 –0.35 3 106 0.39

300 2 159 0.00 2 186 –0.08 2 194 0.16 2 214 -0.07

600 2 79 0.00 2 92 0.46 2 97 –0.35 2 106 0.39

1200 1 159 0.00 1 186 –0.08 1 194 0.16 1 214 -0.07

2400 1 79 0.00 1 92 0.46 1 97 –0.35 1 106 0.39

4800 0 159 0.00 0 186 –0.08 0 194 –1.36 0 214 -0.07

9600 0 79 0.00 0 92 0.46 0 97 –0.35 0 106 0.39

19200 0 39 0.00 0 46 –0.61 0 48 –0.35 0 53 -0.54

31250 0 24 –1.70 0 28 –1.03 0 29 0.00 0 32 0.00

38400 0 19 0.00 0 22 1.55 0 23 1.73 0 26 -0.54

Note: Settings with an error of 1% or less are recommended.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Table 12.4 Bit Rates and SCBRR Settings in Synchronous Mode

Pφ (MHz)

5 8 16 28.7 30 33

Bit Rate

(bits/s) n N n N n N n N n N n N

110            

250 3 77 3 124 3 249      

500 3 38 2 249 3 124 3 223 3 233 3 255

1k 2 77 2 124 2 249 3 111 3 116 3 125

2.5k 1 124 1 199 2 99 2 178 2 187 2 200

5k 0 249 1 99 1 199 2 89 2 93 2 100

10k 0 124 0 199 1 99 1 178 1 187 1 200

25k 0 49 0 79 0 159 1 71 1 74 1 80

50k 0 24 0 39 0 79 0 143 0 149 0 160

100k   0 19 0 39 0 71 0 74 0 80

250k 0 4 0 7 0 15   0 29 0 31

500k   0 3 0 7   0 14 0 15

1M   0 1 0 3     0 7

2M 0 0* 0 1      

[Legend]

Blank: No setting possible

: Setting possible, but error occurs

*: Continuous transmission/reception is disabled.

Note: Settings with an error of 1% or less are recommended.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Table 12.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is

used. Tables 12.6 and 12.7 list the maximum rates for external clock input.

Table 12.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)

Settings

Pφ (MHz) Maximum Bit Rate (bits/s) n N

5 156250 0 0

4.9152 153600 0 0

8 250000 0 0

9.8304 307200 0 0

12 375000 0 0

14.7456 460800 0 0

16 500000 0 0

19.6608 614400 0 0

20 625000 0 0

24 750000 0 0

24.576 768000 0 0

28.7 896875 0 0

30 937500 0 0

33 1031250 0 0

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Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)

Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

5 1.2500 78125

4.9152 1.2288 76800

8 2.0000 125000

9.8304 2.4576 153600

12 3.0000 187500

14.7456 3.6864 230400

16 4.0000 250000

19.6608 4.9152 307200

20 5.0000 312500

24 6.0000 375000

24.576 6.1440 384000

28.7 7.1750 448436

30 7.5000 468750

33 8.25 515625

Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)

Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

5 0.8333 833333.3

8 1.3333 1333333.3

16 2.6667 2666666.7

24 4.0000 4000000.0

28.7 4.7833 4783333.3

30 5.0000 5000000.0

33 5.5000 5500000.0

12.3.9 FIFO Control Register (SCFCR)

SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO

registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR

can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.

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Bit Bit Name

Initial

value R/W Description

15 to 11  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

RSTRG2

RSTRG1

RSTRG0

R/W

RTS Output Active Trigger

When the number of receive data in the receive FIFO

shown below, the RTS signal is set to high.

These bits are available only in SCFCR_0 and

SCFCR_1. In SCFCR_2, these bits are reserved. The

initial value is 0 and the write value should always be 0.

000: 15

001: 1

010: 4

011: 6

100: 8

101: 10

110: 12

111: 14

RTRG1

RTRG0

R/W

Receive FIFO Data Trigger

Set the specified receive trigger number. The receive

data full (RDF) flag in the serial status register (SCFSR)

is set when the number of receive data stored in the

receive FIFO register (SCFRDR) exceeds the specified

trigger number shown below.

• Asynchronous mode

00: 1

01: 4

10: 8

11: 14

• Synchronous mode

00: 1

01: 2

10: 8

11: 14

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Bit Bit Name

Initial

value R/W Description

TTRG1

TTRG0

R/W

Transmit FIFO Data Trigger 1 and 0

Set the specified transmit trigger number. The transmit

FIFO data register empty (TDFE) flag in the serial

status register (SCFSR) is set when the number of

transmit data in the transmit FIFO data register

(SCFTDR) becomes less than the specified trigger

number shown below.

00: 8 (8)*

01: 4 (12)*

10: 2 (14)*

11: 0 (16)*

Note: * Values in parentheses mean the number of

remaining bytes in SCFTDR when the TDFE

flag is set to 1.

3 MCE 0 R/W Modem Control Enable

Enables modem control signals CTS and RTS.

In synchronous mode, clear this bit to 0.

This bit is available only in SCFCR_0 and SCFCR_1. In

SCFCR_2, this bit is reserved. The initial value is 0 and

the write value should always be 0.

0: Modem signal disabled*

1: Modem signal enabled

Note: * The CTS signal is fixed active 0 regardless of

the input value, and the RTS signal is also

fixed 0.

2 TFRST 0 R/W Transmit FIFO Data Register Reset

Disables the transmit data in the transmit FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

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Bit Bit Name

Initial

value R/W Description

1 RFRST 0 R/W Receive FIFO Data Register Reset

Disables the receive data in the receive FIFO data

0: Reset operation disabled*

1: Reset operation enabled

Note: * Reset operation is executed by a power-on

reset.

0 LOOP 0 R/W Loop-Back Test

Internally connects the transmit output pin (TxD) and

receive input pin (RxD) and enables loop-back testing.

0: Loop back test disabled

1: Loop back test enabled

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12.3.10 FIFO Data Count Register (SCFDR)

SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data

transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR

with the lower eight bits. SCFDR can always be read from by the CPU. SCFDR is initialized to

H'0000 by a power on reset.

Bit Bit Name

Initial

value R/W Description

15 to 13  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

Indicate the number of non-transmitted data stored in

SCFTDR. H'00 means no transmit data, and H'10

means that SCFTDR is full of transmit data.

7 to 5  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

Indicate the number of receive data stored in SCFRDR.

H'00 means no receive data, and H'10 means that

SCFRDR full of receive data.

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12.3.11 Serial Port Register (SCSPTR)

SCSPTR is a 16-bit register that controls input/output and data for the pins multiplexed to the

SCIF function. Bits 7 and 6 can control the RTS pin, bits 5 and 4 can control the CTS pin, and bits

3 and 2 can control the SCK pin. Bits 1 and 0 can be used to read the input data from the RxD pin

and to output data to the TxD pin, so they control break of serial transfer. In addition to

descriptions of individual bits shown below, see section 12.6, Serial Port Register (SCSPTR) and

SCIF Pins.

SCSPTR can always be read from or written to by the CPU. Bits 7, 5, 3, and 1 in SCSPTR are

initialized by a power-on reset.

Bit Bit Name

Initial

value R/W Description

15 to 8  All 0 R Reserved

These bits are always read as 0. The write value should

always be 0.

7 RTSIO 0 R/W RTS Port Input/Output Control

Controls the RTS pin in combination with the RTSDT bit

in this register and the MCE bit in SCFCR.

This bit is reserved in SCPTR_2 of SCIF channel 2

since SCIF channel 2 does not support the flow control.

6 RTSDT * R/W RTS Port Data

Controls the RTS pin in combination with the RTSIO bit

in this register and the MCE bit in SCFCR. Select the

RTS pin function in the PFC (pin function controller)

beforehand.

MCE RTSIO RTSDT: RTS pin state

0 0 ×: Input (initial state)

0 1 0: Low level output

0 1 1: High level output

1 × ×: Sequence output according to

modem control logic

×: Don't care

The RTS pin state is read from this bit instead of the set

value. This bit is reserved in SCPTR_2 of SCIF channel

2 since SCIF channel 2 does not support the flow

control.

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Bit Bit Name

Initial

value R/W Description

5 CTSIO 0 R/W CTS Port Input/Output Control

Controls the CTS pin in combination with the CTSDT bit

in this register and the MCE bit in SCFCR.

This bit is reserved in SCPTR_2 of SCIF channel 2

since SCIF channel 2 does not support the flow control.

4 CTSDT * R/W CTS Port Data

Controls the CTS pin in combination with the CTSIO bit

in this register and the MCE bit in SCFCR. Select the

CTS pin function in the PFC (pin function controller)

beforehand.

MCE CTSIO CTSDT: CTS pin state

0 0 ×: Input (initial state)

0 1 0: Low level output

0 1 1: High level output

1 × ×: Input to modem control logic

×: Don't care

The CTS pin state is read from this bit instead of the set

value. This bit is reserved in SCPTR_2 of SCIF channel

2 since SCIF channel 2 does not support the flow

control.

3 SCKIO 0 R/W SCK Port Input/Output Control

Controls the SCK pin in combination with the SCKDT

bit in this register, the C/A bit in SCSMR, and bits CKE1

and CKE0 in SCSCR.

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Bit Bit Name

Initial

value R/W Description

2 SCKDT * R/W SCK Port Data

Controls the SCK pin in combination with the SCKIO bit

in this register, the C/A bit in SCSMR, and bits CKE1

and CKE0 in SCSCR. Select the SCK pin function in

the PFC (pin function controller) beforehand.

C/A CKE1 CKE0 SCKIO SCKDT: SCK pin state

0 0 0 0 ×: Input (initial state)

0 0 0 0 0: Low level output

0 0 0 1 1: High level output

0 0 1 × ×: Internal clock output

according to serial core

logic

0 1 0 × ×: External clock input to

serial core logic

0 1 1 × ×: Setting prohibited

1 0 0 × ×: Internal clock output

according to serial core

logic

1 0 1 × ×: Internal clock output

according to serial core

logic

1 1 0 × ×: External clock input to

serial core logic

1 1 1 × ×: Setting prohibited

×: Don't care

The SCK pin state is read from this bit instead of the

set value.

1 SPBIO 0 R/W Serial Port Break Input/Output Control

Controls the TxD pin in combination with the SPBDT bit

in this register and the TE bit in SCSCR.

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Bit Bit Name

Initial

value R/W Description

0 SPBDT * R/W Serial Port Break Data

Controls the TxD pin in combination with the SPBIO bit

in this register and the TE bit in SCSCR. The RxD pin

state can also be monitored. Select the TxD or RxD pin

function in the PFC (pin function controller) beforehand.

TE SPBIO SPBDT: TxD pin state

0 0 ×: Input (initial state)

0 1 0: Low level output

0 1 1: High level output

0 × ×: Transmit data output according

to serial core logic

×: Don't care

The RxD pin state is read from this bit instead of the set

value.

Note: * This bit is read as an undefined value and the setting value is 0.

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12.3.12 Line Status Register (SCLSR)

SCLSR is a 16-bit readable/writable register which can always be read from and written to by the

CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has

first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset.

Bit Bit Name

Initial

value R/W Description

15 to 1  All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

0 ORER 0 R/(W)* Overrun Error

Indicates the occurrence of an overrun error.

0: Receiving is in progress or has ended normally *1

[Clearing conditions]

• ORER is cleared to 0 when the chip is a power-on

reset

• ORER is cleared to 0 when 0 is written after 1 is

read from ORER.

1: An overrun error has occurred *2

[Setting condition]

ORER is set to 1 when the next serial receiving is

finished while receive FIFO data are full.

Notes: 1. Clearing the RE bit to 0 in SCSCR does

not affect the ORER bit, which retains its

previous value.

2. The receive FIFO data register (SCFRDR)

hold the data before an overrun error is

occurred, and the next receive data is

extinguished. When ORER is set to 1,

SCIF can not continue the next serial

receiving.

Note: * The only value that can be written is 0 to clear the flag.

Section 12 Serial Communication Interface with FIFO (SCIF)

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12.4 Operation

12.4.1 Overview

For serial communication, the SCIF has an asynchronous mode in which characters are

synchronized individually, and a synchronous mode in which communication is synchronized with

clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations,

reducing the overhead of the CPU, and enabling continuous high-speed communication.

Moreover, it has RTS and CTS signals as modem control signals (only for channel 0). The

transmission format is selected in the serial mode register (SCSMR). The SCIF clock source is

selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR).

Asynchronous Mode:

• Data length is selectable: 7 or 8 bits.

• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding

selections constitutes the communication format and character length.

• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,

overrun errors, receive data ready, and breaks.

• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.

• An internal or external clock can be selected as the SCIF clock source.

 When an internal clock is selected, the SCIF operates using the on-chip baud rate

generator.

 When an external clock is selected, the external clock input must have a frequency 16 times

the bit rate. (The on-chip baud rate generator is not used.)

Synchronous Mode:

• The transmission/reception format has a fixed 8-bit data length.

• In receiving, it is possible to detect overrun errors (ORER).

• An internal or external clock can be selected as the SCIF clock source.

 When an internal clock is selected, the SCIF operates using the on-chip baud rate

generator, and outputs a serial clock signal to external devices.

 When an external clock is selected, the SCIF operates on the input serial clock. The on-

chip baud rate generator is not used.

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Table 12.8 SCSMR Settings and SCIF Communication Formats

SCSMR Settings SCIF Communication Format

Bit 7

C/A

Bit 6

CHR

Bit 5

Bit 3

STOP Mode Data Length Parity Bit Stop Bit Length

0 0 0 0 8-bit Not set 1 bit

1 2 bits

1 0 Set 1 bit

1 2 bits

1 0 0 7-bit Not set 1 bit

1 2 bits

1 0 Set 1 bit

Asynchronous

2 bits

1 * * * Synchronous 8-bit Not set None

Note: * : Don't care

Table 12.9 SCSMR and SCSCR Settings and SCIF Clock Source Selection

SCSMR SCSCR Settings SCIF Transmit/Receive Clock

Bit 7

C/A

Bit 1

CKE1

Bit 0

CKE0 Mode

Clock

Source SCK Pin Function

0 0 0 Asynchronous Internal SCIF does not use the SCK pin. The state

of the SCK pin depends on both the SCKIO

and SCKDT bits.

1 Clock with a frequency 16 times the bit rate

is output.

1 0 External Input a clock with frequency 16 times the bit

rate.

1  Setting prohibited.

1 0 * Synchronous Internal Serial clock is output.

1 0 External Input the serial clock.

1  Setting prohibited.

Note: * : Don't care

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12.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with

a stop bit. Serial communication is synchronized one character at a time.

The transmitting and receiving sections of the SCIF are independent, so full duplex

communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be

written and read while transmitting and receiving are in progress, enabling continuous transmitting

and receiving.

Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous

serial communication, the communication line is normally held in the mark (high) state. The SCIF

monitors the line and starts serial communication when the line goes to the space (low) state,

indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit

(high or low), and stop bit (high), in that order.

When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit.

The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit

rate. Receive data is latched at the center of each bit.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Serial

data

Parity

bit

1 bit 1 or 2 bits7 or 8 bits 1 bit or

none

One unit of transfer data (character or frame)

Figure 12.2 Example of Data Format in Asynchronous Communication

(8-Bit Data with Parity and Two Stop Bits)

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Transmit/Receive Formats: Table 12.10 lists the eight communication formats that can be

selected in asynchronous mode. The format is selected by settings in the serial mode register

(SCSMR).

Table 12.10 Serial Communication Formats (Asynchronous Mode)

SCSMR Bits Serial Transmit/Receive Format and Frame Length

CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12

0 0 0 START 8-bit data STOP

0 0 1 START 8-bit data STOP STOP

0 1 0 START 8-bit data P STOP

0 1 1 START 8-bit data P STOP STOP

1 0 0 START 7-bit data STOP

1 0 1 START 7-bit data STOP STOP

1 1 0 START 7-bit data P STOP

1 1 1 START 7-bit data P STOP STOP

[Legend]

START: Start bit

STOP: Stop bit

P: Parity bit

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected

by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control

When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to 16 times the desired bit rate.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Transmitting and Receiving Data: SCIF Initialization (Asynchronous Mode):

Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register

(SCSCR), then initialize the SCIF as follows.

When changing the operation mode or the communication format, always clear the TE and RE bits

to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift

(SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which

retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the

TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the

transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1

and reset SCFTDR before TE is set again to start transmission.

When an external clock is used, the clock should not be stopped during initialization or subsequent

operation. SCIF operation becomes unreliable if the clock is stopped.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Figure 12.3 shows a sample flowchart for initializing the SCIF.

Start of initialization

Clear TE and RE bits in SCSCR to 0

Set TFRST and RFRST bits

in SCFCR to 1

Set CKE1 and CKE0 bits

in SCSCR (leaving TE, RE, TIE,

and RIE bits cleared to 0)

Set data transfer format in SCSMR

Set value in SCBRR

1-bit interval elapsed?

Set RTRG1-0 and TTRG1-0 bits

in SCFCR, and clear TFRST

and RFRST bits to 0

Set TE and RE bits in SCSCR to 1,

and set TIE, RIE, and REIE bits

End of initialization

Wait

Yes

Set the clock selection in SCSCR.

Be sure to clear bits TIE, RIE, TE,

and RE to 0.

Set the data transfer format in

SCSMR.

Write a value corresponding to the

bit rate into SCBRR. (Not

necessary if an external clock is

used.)

Wait at least one bit interval, then

set the TE bit or RE bit in SCSCR

to 1. Also set the RIE, REIE, and

TIE bits.

Setting the TE bit enables the TxD

and RxD pins to be used.

When transmitting, the SCIF will go

to the mark state; when receiving,

it will go to the idle state, waiting for

a start bit.

[1]

[2]

[3]

[4]

[2]

[3]

[4]

After reading BRK, DR, and ER flags

in SCFSR, and each flag in SCLSR,

write 0 to clear them

Figure 12.3 Sample Flowchart for SCIF Initialization

Section 12 Serial Communication Interface with FIFO (SCIF)

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Transmitting Serial Data (Asynchronous Mode):

Figure 12.4 shows a sample flowchart for serial transmission.

Use the following procedure for serial data transmission after enabling the SCIF for transmission.

Start of transmission

Read TDFE flag in SCFSR

TDFE = 1?

Write transmit data in SCFTDR,

and read 1 from TDFE flag

and TEND flag in SCFSR,

then clear to 0

All data transmitted?

Read TEND flag in SCFSR

TEND = 1?

Break output?

Clear SPBDT to 0 and

set SPBIO to 1

Clear TE bit in SCSCR to 0

End of transmission

Yes

[1] SCIF status check and transmit data

write:

Read SCFSR and check that the

TDFE flag is set to 1, then write

transmit data to SCFTDR, and read 1

from the TDFE and TEND flags, then

clear to 0.

The number of transmit data bytes

that can be written is 16 - (transmit

trigger set number).

[2] Serial transmission continuation

procedure:

To continue serial transmission, read

1 from the TDFE flag to confirm that

writing is possible, then write data to

SCFTDR, and then clear the TDFE

flag to 0.

[3] Break output at the end of serial

transmission:

To output a break in serial

transmission, clear the SPBDT bit to

0 and set the SPBIO bit to 1 in

SCSPTR, then clear the TE bit in

SCSCR to 0.

In [1] and [2], it is possible to

ascertain the number of data bytes

that can be written from the number

of transmit data bytes in SCFTDR

indicated by the upper 8 bits of

SCFDR.

[1]

[2]

[3]

Figure 12.4 Sample Flowchart for Transmitting Serial Data

Section 12 Serial Communication Interface with FIFO (SCIF)

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In serial transmission, the SCIF operates as described below.

1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the

data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that

the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to

SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).

2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive

transmit operations are performed until there is no transmit data left in SCFTDR. When the

number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the

FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register

(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is

generated.

The serial transmit data is sent from the TxD pin in the following order.

A. Start bit: One-bit 0 is output.

B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.

C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is

not output can also be selected.)

D. Stop bit(s): One or two 1 bits (stop bits) are output.

E. Mark state: 1 is output continuously until the start bit that starts the next transmission is

sent.

3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is

present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial

transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR

is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output

continuously.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Figure 12.5 shows an example of the operation for transmission.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

TDFE

TEND

Serial

data

Start

bit

Data Parity

bit

Stop

bit

Start

bit

Idle state

(mark state)

Data Parity

bit

Stop

bit

TXI interrupt

request Data written to SCFTDR

and TDFE flag read as 1

then cleared to 0 by TXI

interrupt handler

One frame

TXI interrupt

request

Figure 12.5 Example of Transmit Operation

(8-Bit Data, Parity, One Stop Bit)

4. When modem control is enabled, transmission can be stopped and restarted in accordance with

the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the

mark state after transmission of one frame. When CTS is set to 0, the next transmit data is

output starting from the start bit.

Figure 12.6 shows an example of the operation when modem control is used (only for

channel 0).

Serial data

TxD 0 D0 D1 D7 0/1 01 D0 D1 D7 0/1

CTS

Drive high before stop bit

Start

bit

Parity

bit

Stop

bit

Start

bit

Figure 12.6 Example of Operation Using Modem Control (CTS)

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Receiving Serial Data (Asynchronous Mode):

Figures 12.7 and 12.8 show a sample flowchart for serial reception.

Use the following procedure for serial data reception after enabling the SCIF for reception.

Start of reception

Read ER, DR, BRK flags in

SCFSR and ORER

flag in SCLSR

ER, DR, BRK or ORER = 1?

Read RDF flag in SCFSR

RDF = 1?

Read receive data in

SCFRDR, and clear RDF

flag in SCFSR to 0

All data received?

Clear RE bit in SCSCR to 0

End of reception

Yes

Error handling

[1] Receive error handling and

break detection:

Read the DR, ER, and BRK

flags in SCFSR, and the

ORER flag in SCLSR, to

identify any error, perform the

appropriate error handling,

then clear the DR, ER, BRK,

and ORER flags to 0. In the

case of a framing error, a

break can also be detected by

reading the value of the RxD

pin.

[2] SCIF status check and receive

data read:

Read SCFSR and check that

RDF = 1, then read the receive

data in SCFRDR, read 1 from

the RDF flag, and then clear

the RDF flag to 0. The

transition of the RDF flag from

0 to 1 can also be identified by

an RXI interrupt.

[3] Serial reception continuation

procedure:

To continue serial reception,

read at least the receive

trigger set number of receive

data bytes from SCFRDR,

read 1 from the RDF flag, then

clear the RDF flag to 0. The

number of receive data bytes

in SCFRDR can be

ascertained by reading from

SCRFDR.

[1]

[2]

[3]

Figure 12.7 Sample Flowchart for Receiving Serial Data

Section 12 Serial Communication Interface with FIFO (SCIF)

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REJ09B0239-0400

Error handling

Receive error handling

ER = 1?

BRK = 1?

Break handling

DR = 1?

Read receive data in SCFRDR

Clear DR, ER, BRK flags

in SCFSR,

and ORER flag in SCLSR, to 0

End

Yes

Overrun error handling

ORER = 1?

Yes

[1] Whether a framing error or parity error

has occurred in the receive data that

is to be read from SCFRDR can be

ascertained from the FER and PER

bits in SCFSR.

[2] When a break signal is received,

receive data is not transferred to

SCFRDR while the BRK flag is set.

However, note that the last data in

SCFRDR is H'00, and the break data

in which a framing error occurred is

stored.

Figure 12.8 Sample Flowchart for Receiving Serial Data (cont)

Section 12 Serial Communication Interface with FIFO (SCIF)

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In serial reception, the SCIF operates as described below.

1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal

synchronization and starts reception.

2. The received data is stored in SCRSR in LSB-to-MSB order.

3. The parity bit and stop bit are received.

After receiving these bits, the SCIF carries out the following checks.

A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only

the first is checked.

B. The SCIF checks whether receive data can be transferred from the receive shift register

(SCRSR) to SCFRDR.

C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error

has not occurred.

D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not

set.

If all the above checks are passed, the receive data is stored in SCFRDR.

Note: When a parity error or a framing error occurs, reception is not suspended.

4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-

data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to

1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the

RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a

break reception interrupt (BRI) request is generated.

Figure 12.9 shows an example of the operation for reception.

Section 12 Serial Communication Interface with FIFO (SCIF)

Rev. 4.00 Sep. 13, 2007 Page 285 of 502

REJ09B0239-0400

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/10

RDF

FER

Serial

data

Start

bit

Data Parity

bit

Stop

bit

Start

bit

Data Parity

bit

Stop

bit

RXI interrupt

request

One frame

Data read and RDF flag

read as 1 then cleared to

0 by RXI interrupt handler

ERI interrupt request

generated by receive

error

Figure 12.9 Example of SCIF Receive Operation

(8-Bit Data, Parity, One Stop Bit)

5. When modem control is enabled, the RTS signal is output depending on the empty status of

SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that the

SCFRDR is full and no extra data can be received. (Only for channel 0 and channel 1)

Figure 12.10 shows an example of the operation when modem control is used.

D0 D1 D2 D7 0/1 D0 D1 D7 0/1100

RTS

Serial data

RxD

Start

bit

Parity

bit

Stop

bit

Start

bit

Figure 12.10 Example of Operation Using Modem Control (RTS)

Section 12 Serial Communication Interface with FIFO (SCIF)

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12.4.3 Synchronous Mode

In synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses.

This mode is suitable for high-speed serial communication.

The SCIF transmitter and receiver are independent, so full-duplex communication is possible

while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so

continuous transmitting or receiving is possible by reading or writing data while transmitting or

receiving is in progress.

Figure 12.11 shows the general format in synchronous serial communication.

Don’t

care

Don’t

care

One unit of transfer data (character or frame)

Bit 0

Serial data

Synchronization

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 12.11 Data Format in Synchronous Communication

In synchronous serial communication, each data bit is output on the communication line from one

falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial

clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the

MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In

synchronous mode, the SCIF transmits data by synchronizing with the falling edge of the serial

clock, and receives data by synchronizing with the rising edge of the serial clock.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Communication Format: The data length is fixed at eight bits. No parity bit can be added.

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCIF transmit/receive clock.

When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight

clock pulses are output per transmitted or received character. When the SCIF is not transmitting or

receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs

while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive

FIFO data trigger number. In this case, 8 × (16 + 1) = 136 pulses of synchronous clock are output.

To perform reception of n characters of data, select an external clock as the clock source. If an

internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data

simultaneously with the transmission of n characters of dummy data.

Transmitting and Receiving Data SCIF Initialization (Synchronous Mode): Before

transmitting, receiving, or changing the mode or communication format, the software must clear

the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing

TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not

initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain

their previous contents.

Section 12 Serial Communication Interface with FIFO (SCIF)

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Figure 12.12 shows a sample flowchart for initializing the SCIF. The procedure for initializing the

SCIF is:

Start of initialization

Clear TE and RE bits

in SCSCR to 0

Set TFRST and RFRST bits

in SCFCR to 1 to clear

the FIFO buffer

After reading BRK, DR,

and ER flags in SCFSR

and a flag in SCLSR,

write 0 to clear them

Set CKE1 and CKE0 bits

in SCSCR (leaving TE, RE, TIE,

and RIE bits cleared to 0)

Set data transfer format

in SCSMR

Set value in SCBRR

1-bit interval elapsed?

Set RTRG1-0 and TTRG1-0 bits

in SCFCR, and clear TFRST

and RFRST bits to 0

Set TE and RE bits in SCSCR

to 1, and set TIE, RIE,

and REIE bits

End of initialization

Wait

Yes

Leave the TE and RE bits cleared

to 0 until the initialization almost

ends. Be sure to clear the TIE,

RIE, TE, and RE bits to 0.

Set the CKE1 and CKE0 bits.

Set the data transfer format in

SCSMR.

Write a value corresponding to

the bit rate into SCBRR. This

is not necessary if an external

clock is used. Wait at least one

bit interval after this write before

moving to the next step.

Set the TE or RE bit in SCSCR

to 1. Also set the TEI, RIE, and

REIE bits to enable the TxD,

RxD, and SCK pins to be used.

When transmitting, the TxD pin

will go to the mark state.

When receiving in clocked

synchronous mode with the

synchronization clock output (clock

master) selected, a clock starts to

be output from the SCIF_CLK pin

at this point.

[1]

[2]

[3]

[4]

[5]

[2]

[3]

[4]

[5]

Figure 12.12 Sample Flowchart for SCIF Initialization

Section 12 Serial Communication Interface with FIFO (SCIF)

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Transmitting Serial Data (Synchronous Mode): Figure 12.13 shows a sample flowchart for

transmitting serial data.

Start of transmission

Read TDFE flag in SCFSR

TDFE = 1?

Write transmit data to SCFTDR

Read TDFE and TEND flags

in SCFSR while they are 1, then

clear them to 0

All data transmitted?

Read TEND flag in SCFSR

TEND = 1?

Clear TE bit in SCSCR to 0

End of transmission

Yes

[1] SCIF status check and transmit data

write:

Read SCFSR and check that the

TDFE flag is set to 1, then write

transmit data to SCFTDR. Read the

TDFE and TEND flags while they are

1, then clear them to 0.

[2] Serial transmission continuation

procedeure:

To continue serial transmission, read

1 from the TDFE flag to confirm that

writing is possible, then write data to

SCFTDR, and then clear the TDFE

flag to 0.

[1]

[2]

Figure 12.13 Sample Flowchart for Transmitting Serial Data

Section 12 Serial Communication Interface with FIFO (SCIF)

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In transmitting serial data, the SCIF operates as follows: