LH28F800BVE IT TL9O 8M Flas M em ory M odelNo.: LH F80V01) Spec No.: EL1L09037 Isvie D ate: Septem ber14,1998SHARP LHF80VO1 @Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. @When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). eOffice electronics eInstrumentation and measuring equipment Machine tools eAudiovisual equipment eHome appliance eCommunication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. eControl and safety devices for airplanes, trains, automobiles, and other transportation equipment Mainframe computers Traffic control systems eGas leak detectors and automatic cutoff devices Rescue and security equipment eOther safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. e Aerospace equipment eCommunications equipment for trunk lines eControl equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. @Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 1.01SHARP LHF80V01 1 CONTENTS PAGE PAGE 1 INTRODUCTION D1 Features occ ececcsecsesessececeeceseesseessssesesseseveasesenserenes 1.2 Product OVErViGW 2.00... ccccecceceseteetetseeeceeeseeesesssseneeseeene 3 2 PRINCIPLES OF OPERATION ....W.00...20.0:csceeeteeeeee 7 2.1 Data Protection... .scsescseseessersesseereneeseeeresecseeessenes 8 3 BUS OPERATION os ceecccseseeeresseseeeecensesseeeesneeranesenees 8 BL ROAG eee eecereeceeeteeceeeeteecossecerenseseeasseneetsneeseessonetaeses 8 3.2 Output Disable... cee eeeceeneeseseesesseenseerseeesssssseene 8 3.3 Standby... ee eeeeeenessenencesesetsssseesevenecsenensesessssaseeees 8 3.4 Deep Power-DOown ..........:scscescesecesceeceteeeevenseteneesceavacees 8 3.5 Read Identifier Codes Operation... ec eeeeeeteees 9 3.6 WH... cee ceteeteneeteneesenenseeenseeesssenesensesenenseensaseseeees 9 4 COMMAND DEFINITIONS ...............2::ccceeeceeeeeceeeeeeneeeeees 9 4.1 Read Array Command... cece 12 4.2 Read Identifier Codes Command ............0.0.0...0000 12 4.3 Read Status Register Command 4.4 Clear Status Register Command.............csecsesseenees 12 4.5 Block Erase Command... ccc cecesesseseeeseesersesererees 12 4.6 Word/Byte Write Command... eee eee cere rereecee 13 4.7 Block Erase Suspend Command ..........::ccssesessveeees 13 4.8 Word/Byte Write Suspend Command ......sscs.sssessee 14 4.9 Considerations of Suspend ...0...... eee ceeeeeeteeneeeenees 14 4.10 Block Locking ........cccccccstcssessecesseeseseseesesessenetseeas 14 4.10.1 Vpp=Vy, for Complete Protection..................... 14 4.10.2 WP#=V,, for Block Locking.............0.:.:cc0 14 4.10.3 WP#=V},; for Block Unlocking............0...c00 14 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control 5.2 RY/BY# and Block Erase and Word/Byte Write Polling... ee ce cece ees ceceeceesecaeeaceesseeeseeneeeees 20 5.3 Power Supply Decoupling 0.0.00... eens 20 5.4 Vpp Trace on Printed Circuit Boards 0.0.0.0... 20 5.5 Vec, Vpp, RP# Tramsitions ......... cerca 21 5.6 Power-Up/Down Protection...........cccccceseesetseesseeees 21 5.7 Power Dissipation ...........ccceceseeesecsecseeeeesetsenseteeenes 21 6 ELECTRICAL SPECIFICATIONS ...... ce ceeeeeeeeneeeeere 22 6.1 Absolute Maximum Ratings .0..... ccc eeseeeeeeneene 22 6.2 Operating Conditions... cece seeeceseeeeseeeereneens 22 6.2.1 Capacitance 0... eee ce ceseteeeceeesenseeeteeeetenees 22 6.2.2 AC Input/Output Test Conditions .......0.0.0.02...... 23 6.2.3 DC Characteristics 200... ecececeetereeeeeeeeeeaeenee 24 6.2.4 AC Characteristics - Read-Only Operations ....... 26 6.2.5 AC Characteristics - Write Operations ............... 29 6.2.6 Alternative CE#-Controlled Writes... 31 6.2.7 Reset Operations 0.00... eee renee neseseeeseneens 33 6.2.8 Block Erase and Word/Byte Write Performance 34 7 PACKAGE AND PACKING SPECIFICATIONS......... 35 Rev. 1.0SHARP LHF80VOlL 2 LH28F800B VE-TTL90 8M-BIT (1Mbit x 8 /512Kbit x 16) Smart3 Flash MEMORY WM Smart3 Technology @ Enhanced Data Protection Features 2.7V-3.6V Vcc Absolute Protection with Vpp=GND 2.7V-3.6V or 11.4V-12.6V Vpp Block Erase and Word/Byte Write Lockout during Power Transitions M User-Configurable x8 or x16 Operation Boot Blocks Protection with WP#=Vy,_ @ High-Performance Access Time @ Automated Word/Byte Write and Block Erase 90ns(2.7V-3.6V) Command User Interface ; Status Register M@ Operating Temperature 0C to +70C @ Low Power Management i. . . Deep Power-Down Mode M Optimized Array Blocking Architecture Automatic Power Savings Mode Decreases Two 4k-word Boot Blocks Icc in Static Mode Six 4k-word Parameter Blocks Fifteen 32k-word Main Blocks M@ SRAM-Compatible Write Interface Top Boot Location M Industry-Standard Packaging M@ Extended Cycling Capability 48-Lead TSOP 100,000 Block Erase Cycles . M@ ETOXT* Nonvolatile Flash Technology M@ Enhanced Automated Suspend Options Word/Byte Write Suspend to Read mM CMOS Process (P-type silicon substrate) Block Erase Suspend to Word/Byte Write . . Block Erase Suspend to Read M@ Not designed or rated as radiation hardened SHARPs LH28F800B VE-TTL90 Flash memory with Smart3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800B VE-TTL90 can operate at Voc=2.7V-3.6V and Vpp=2.7V-3.6V. Its low voltage operation capability realize battery life and suits for cellular phone application. Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BVE-TTL90 offers two levels of protection: absolute protection with Vpp at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their code security needs. The LH28F800BVE-TTL90 is manufactured on SHARPs 0.35um ETOX process technology. [t come in industry- standard package: the 48-lead TSOP ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. Rev. 1.01SHARP LHF80V01 3 1 INTRODUCTION This datasheet contains LH28F800B VE-TTL90 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of LH28F800BVE-TTL90 Smart3 Flash memory are: eSmart3 Technology eEnhanced Suspend Capabilities eBoot Block Architecture Please note following important differences: VpprK has been lowered to 1.5V to support 2.7V-3.6V block erase and word/byte write operations. Designs that switch Vpp off during read operations should make sure that the Vpp voltage transitions to GND. *To take advantage of Smart3 technology, allow Voc and Vpp connection to 2.7V-3.6V. 1.2 Product Overview The LH28F800B VE-TTL90 is a high-performance 8-Mbit Smart3 Flash memory organized as 1M-byte of 8 bits or 12K-word of 16 bits. The 1M-byte/512K-word of data is arranged in two 8K-byte/4K-word boot blocks, six 8K-~- byte/4K-word parameter blocks and fifteen 64K-byte/32K- word main blocks which are individually erasable in- system. The memory map is shown in Figure 3. Smart3 technology provides a choice of Vcc and Vpp combinations, as shown in Table 1, to meet system performance and power expectations. Vpp at 2.7V-3.6V eliminates theneed for a separate 12V converter, while Vpp=12V maximizes block erase and word/byte write performance. In addition to flexible erase and program voltages, the dedicated Vpp pin gives complete data protection when Vpp S$ Vppr x. Table 1. Vcc and Vpp Voltage Combinations Offered by Smart3 Technology Vcc Voltage 2.7V-3.6V Vpp Voltage 2.7V-3.6V, L14V-12.6V Internal Vcc and Vpp detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUD serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and word/byte write operations. A block erase operation erases one of the devices 32K- word blocks typically within 0.51s (2.7V-3.6V Vee, 11.4V-12.6V Vpp), 4K-word blocks typically within 0.31s (2.7V-3.6V Vec, 11.4V-12.6V Vpp) independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word/byte increments of the devices 32K-word blocks typically within 12.6us (2.7V-3.6V Voc, 11.4V-12.6V Vpp), 4K- word blocks typically within 24.5us (2.7V-3.6V Vcc, 11.4V-12.6V Vpp). Word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. Rev. 1.0SHARP LHF80V01 4 The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried out by WP# to Low and RP# to Vy. The status register indicates when the WSMs block erase or word/byte write operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/B Y# indicates that the WSM is performing a block erase or word/byte write. RY/BY#-high Z indicates that the WSM is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode. The access time is 90 ns (tayoy) over the commercial temperature range (OC to +I0C) and Vcc supply voltage range of 2.7V-3.6V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical Iccp current is 3 mA at 2.7V Vcc. When CE# and RP# pins are at Voc, the Ip CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tpygy) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tpyy,) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2. Rev. 1.0SHARP LHF80VO1 ArAig DQo-DQis AL BYTE# Vee Identifier Register Command Output Multiplexer WE# OE# RP# WP# Status User Register Interface Data Comparator RY/BY# Y Decoder Program/Erase Vpp Voltage Switch ol ne x 3 4 15 x Vee Decoder /= 32K-Word 2 | 2 a mls q GND : s Main blocks |2|@ s/= sls Figure 1. Block Diagram CT 1 48 Ce Ate , C) 47 F-= > = BYTE# cH 3 46 [7 ~=GND C=) 4 45 7 DQ)5/A1 C5 44 To 7 Cc 6 43 [= -~DQiy co) 7 ae Dds co 8 4. DQ)3 Cc 9 40 7 =ODQ; = 10 48-LEAD TSOP 39 = 4 DAN Cc 1 3) COD 12 STANDARD PINOUT 37 ven cr 13 36 Fo) DQ a 12mm x 20mm 35 EDO; co 15 TOP VIEW 34s DQ I] 16 3374 DQ c 17 32 [DQ c is 31-7 S~DQ ci] 19 30 = DQ; Cc} 20 29 E) ~DQ ee | 28 [1_ OFF cc 22 27 -=:~GND CZ 23 26 (= _SCE# Cc 24 25 [Ao Figure 2. TSOP 48-Lead Pinout Rev. 1.0SHARP LHF80VOl1 6 Table 2. Pin Descriptions Symbol Type Name and Function Ag-Aig INPUT ADDRESS INPUTS: Addresses are internally latched during a write cycle. A : Byte Select Address. Not used in x16 mode. Ag-Aig : Row Address. Selects 1 of 2048 word lines. Ayy-Ay4 : Column Address. Selects | of 16 bit lines. A)s5-A)g_: Main Block Address. (Boot and Parameter block Addresses are Aj>-Ajg.) DQo-DQis INPUT/ OUTPUT DATA INPUT/OUTPUTS: DQp-DQ,:Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ,-DQ,,:Inputs data during CUI write cycles in x16 mode; outputs data during memory array read cycles in x16 mode; not used for status register and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode (Byte#=V jy ). Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the devices control logic, input buffers, decoders and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. INPUT RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. With RP#=Vjy4,, block erase or word/byte write can operate to all blocks without WP# state. Block erase or word/byte write with Vj.<RP#<Vj}4, produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. WP# INPUT WRITE PROTECT: Master control for boot blocks locking. When Vj, , locked boot blocks cannot be erased and programmed. BYTE# INPUT BYTE ENABLE: BYTE# Vj, places device in x8 mode. All data is then input or output on DQp_7, and DQ, |; float. BYTE# Vy, places the device in x16 mode , and turns off the A_, input buffer. RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active. SUPPLY BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or writing words/bytes. With Vpp<Vpp; x. memory contents cannot be altered. Block erase and word/byte write with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. With VcSVj xo, all write attempts to the flash memory are inhibited. Device operations at invalid Voc voltage (see DC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internal connected; it may be driven or floated. Rev. 1.0SHARP LHF80V01 2 PRINCIPLES OF OPERATION The LH28F800BVE-TTL90 Smart3 Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the Vpp voltage. High voltage on Vpp enables successful block erasure and word/byte writing. All functions associated with altering memory contentsblock erase, word/byte write, status and identifier codes-are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase and word/byte write. The internal algorithms are regulated by the WSM, including pulse repetition, internal] verification and margining of data. Addresses and data are internally latch during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. Interface software that initiates and polls progress of block erase and word/byte write can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. TFFFF 7FO00 TJEFFF TEOOO 7DFFF 7D000 7CFFF 7C000 7BEFF 7B000 7AFFF 7A000 79FFF 79000 78FFF 78000 TTFFF 70000 6FFFF 68000 67FFF 60000 SFFFF 58000 57FFF 50000 AFFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 OFFFF 27FFF 20000 1FFFF 18000 17 FFF 10000 OFFFF 08000 O7FFF Top Boot 4K-word Boot Block 0 4K-word Boot Block 1 4K-word Parameter Block 0 4K-word Parameter Block 1 4K-word Parameter Block 2 4K-word Parameter Block 3 4K-word Parameter Block 4 4K-word Parameter Block 5 32K-word Main Block 0 32K-word Main Block 1 32K-word Main Block 2 32K-word Main Block 3 32K-word Main Block 4 32K-word Main Block 5 32K-word Main Block 6 32K-word Main Block 7 32K-word Main Block 8 32K-word Main Block 9 32K-word Main Block 10 32K-word Main Block 11 32K-word Main Block 12 32K-word Main Block 13 32K-word Main Block 14 Figure 3. Memory Map Rev. 1.0SHARP LHF80V01 8 2.1 Data Protection Depending on the application, the system designer may choose to make the Vpp power supply switchable (available only when memory block erases or word/byte writes are required) or hardwired to Vppyyj/. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VppSVppy x, Memory contents cannot be altered. The CUI, with two-step block erase or word/byte write command sequences, provides protection from unwanted operations even when high voltage is applied to Vpp. All write functions are disabled when Vcc is below the write lockout voltage V; xo or when RP# is at Vj. The device's boot blocks locking capability for WP# provides. additional protection from inadvertent code or data alteration by block erase and word/byte write operations. Refer to Table 6 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the Vpp voltage. RP# can be at either Vy, or Vip. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Six control pins dictate the data flow in and out of the component: CE#, OE#, WE#, RP#, WP# and BYTE#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQp-DQ;5) control and when active drives the selected memory data onto the I/O bus. WE# must be at V,,, and RP# must be at Vy or Veqy. Figure 11, 12 illustrates read cycle. 3.2 Output Disable With OE# at a logic-high level (Vj), the device outputs are disabled. Output pins (DQ9-DQ)5) are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (Vy;) places the device in standby mode which substantially reduces device power consumption. DQ)-DQ,5 outputs are placed in a high- impedance state independent of OE#. If deselected during block erase or word/byte write, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at Vj, initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tpypy is required after return from power- down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase or word/byte write modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tpyywy, is required after RP# goes to logic-high (Vj) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word/byte write modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARPs flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. Rev. 1.0SHARP LHF80V01 9 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. [Ais-Ag] TFFFF 00001 Device Code 00000 Manufacturer Code Figure 4. Device Identifier Code Memory Map 3.6 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When V-c=2.7V-3.6V and Vpp=VppHi2, the CUI additionally controls block erasure and word/byte write. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/Byte Write command requires the command and address of the location to be written. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 13 and 14 illustrate WE# and CE# controlled write operations. 4 COMMAND DEFINITIONS When the Vpp voltage < Vppy x, Read operations from the status register, identifier codes, or blocks are enabled. Placing Vppyj/2 0M Vpp enables successful block erase and word/byte write operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Rev. 1.0SHARP LHF80V01 10 Table 3.1. Bus Operations(B YTE#=V,4)(1-2) Mode Notes RP# CE# OE# WE# Address Vpp DQo.15_ |[RY/BY#?) Viyq OF Read 8 TH Vv Vv V x xX D xX Van IL IL IH OUT . Vin oF . Output Disable Vv Vit Vin Vin Xx Xx High Z x HH Ving oF . Standby 10 Vv Vig X X x Xx High Z x HH Deep Power-Down 4,10 Vin Xx x Xx xX x High Z High Z . Vin OF See . Read Identifier Codes 8 Van Vit Vit Vin Figure 4 x Note 5 High Z Write 678] EH | va | Vay | Va x x Din x Vy Table 3.2. Bus Operations(BYTE#=V, )!-2) Mode Notes| RP# | CE# | OE# | WE# | Address | Vpp | DQo.7 | DQg.j5 |RY/BY#0) Read 8 ve Vi | Va) Van Xx X | Dour | Highz]} Xx Output Disable yee Vo | Vi | Vu X X | HighZ | HighZ X Standby 10 | YAS | ve | x | Xx x X |HighZ|Highz| x HH Deep Power-Down 4,10 Vit Xx x Xx x Xx High Z | HighZ | HighZ . Vig oF See . . Read Identifier Codes 8,9 Van Vin Vit Vin Figure 4 Xx Note 5 | HighZ | High Z Write 6,7,8 ye Vo | Vin | Vic x x Din x x NOTES: 1. Refer to DC Characteristics. When VppSVpp; x, Memory contents can be read, but not altered. 2. Xcan be Vy or Vyqy for control pins and addresses, and Vppy x OF Vppyy1/7 for Vpp. See DC Characteristics for Vpp; x and VppHi2 Voltages. 3. RY/BY# is Vo, when the WSM is executing internal block erase or word/byte write algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or deep power-down mode. 4. RP# at GND+0.2V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. Command writes involving block erase or word/byte write are reliably executed when Vpp=Vppyy/2 and Vec=2.7V-3.6V. Block erase or word/byte write with Vyy<RP#<V jy, produce spurious results and should not be attempted. 7. Refer to Table 4 for valid Djy during a write operation. 8. Never hold OE# low and WE# low at the same timing. 9. A, setto Vy or Vyy in byte mode (BYTE#=V, ). 10. WP# set to Vy or Voy. Rev. 1.0SHARP LHF80V01 11 Table 4. Command Definitions) Bus Cycles First Bus Cycle Second Bus Cycle Command Reqd. Notes | Oper) | Addr2) | Data) | Oper(l) | Addr | Data) Read Array/Reset 1 Write Xx FFH Read Identifier Codes 22 4 Write X 90H Read IA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write x 50H Block Erase 2 5 Write BA 20H Write BA DOH Word/Byte Write 2 5,6 | Write | WA oe Write | WA WD Block Erase and Word/Byte 1 5 Wate x BOH Write Suspend Block Erase and Word/Byte 1 5 Write x DOH Write Resume NOTES: 1. BUS operations are defined in Table 3.1 and Table 3.2, 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. A_, set to Vy, or Vyq in Byte Mode (BYTE#=V,, ). BA=Address within the block being erased. The each block can select by the address pin Ay, through Aj, combination. WAz=Address of memory location to be written. 3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID=Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for read identifier code data. 5. If the block is boot block, WP# must be at Vy, or RP# must be at Vy, to enable block erase or word/byte write operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is Vj, or RP# is Vy. 6. Either 40H or 10H are recognized by the WSM as the word/byte write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 1.0SHARP LHF80VO1 12 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has Started a block erase or word/byte write, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word/Byte Write Suspend command. The Read Array command functions independently of the Vpp voltage and RP# can be Vy; or Vig. 42 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer and device codes (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the Vpp voltage and RP# can be Vyy or Vun- Following the Read Identifier Codes command, the following information can be read: Table 5. Identifier Codes Code Address Data [Ayg-Ag] | [DQ,-DQo] Manufacture Code 00000H BOH Device Code 00001H 4AH 4.3 Read Status Register Command The status register may be read to determine when a block erase or word/byte write is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to Vy, before further reads to update the status register latch. The Read Status Register command functions independently of the Vpp voltage. RP# can be Vy; or Vig. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "L"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied Vpp Voltage. RP# can be Vyjy or Vuqy. This command is not functional during block erase or word/byte write suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when Vec=2-7V-3.6V and Vpp=Vppy1/2- In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VppSVpp, x. SR.3 and SR.5 will be set to "1". Successful block erase for boot blocks requires that the corresponding if set, that WP#=Viy or RP#=Viy. If block erase is attempted to boot block when the corresponding WP#=V) or RP#=V14;, SR.1 and SR.5 will be set to "1". Block erase operations with V}4y<RP#<Vjy,4 produce spurious results and should not be attempted. Rev. 1.0SHARP LHF80V01 13 4.6 Word/Byte Write Command Word/byte write is executed by a two-cycle command sequence. Word/byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word/byte write event by analyzing the RY/BY# pin or Status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when Voec=2.7V-3.6V and Vpp=Vppy1/2- In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while VppSV pp x, Status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write for boot blocks requires that the corresponding if set, that WP#=V),, or RP#=V yp. If word/byte write is attempted to boot block when the corresponding WP#=V,, or RP#=Vjyq, SR.1 and SR.4 will be set to 1". Word/byte write operations with Vig<RP#<Vyy7y produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in another block of memory. Once the block-erase process starts, writing the Block Erase Suspend command requests that the WSM_ suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification twuRz? defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word/Byte Write Suspend command (see Section 4.8), a word/byte write operation can also be suspended. During a word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to Vo, . However, SR.6 will remain "1" to indicate block erase suspend Status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to Voy. After the Erase Resume command is wnitten, the device automatically outputs status register data when read (see Figure 7). Vpp must remain at Vppyyj/2 (the same Vpp level used for block erase) while block erase is suspended. RP# must also remain at Vjy or Viqy (the same RP# level used for block erase), WP# must also remain at Vy or Vy (the same WP# level used for block erase). Block erase cannot resume until word/byte write operations initiated during block erase suspend have completed. Rev. 1.0SHARP LHF80V0O1 14 4.8 Word/Byte Write Suspend Command The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash memory locations. Once the word/byte write process starts, writing the Word/Byte Write Suspend command Tequests that the WSM suspend the word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to High Z. Specification tyyyp7, defines the word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word/byte write is suspended are Read Status Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to Vo. After the Word/Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 8). Vpp must remain at Vppyy/. (the same Vpp level used for word/byte write) while in word/byte write suspend mode. RP# must also remain at Vy, or Vig (the same RP# level used for word/byte write). WP# must also remain at Vy or Viq (the same WP# level used for word/byte write). 4.9 Considerations of Suspend After the suspend command write to the CUI, read status register command has to write to CUI, then status register bit SR.6 or SR.2 should be checked for places the device in suspend mode. 4.10 Block Locking This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. 4.10.1 Vpp=Vy_ for Complete Protection The Vpp programming voltage can be held low for complete write protection of all blocks in the flash device. 4.10.2 WP#=Vy, for Block Locking The lockable blocks are locked when WP#=Vy; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable. For the bottom configuration, the bottom tow boot blocks are lockable. Unlocked blocks can be programmed or erased normally (Unless Vpp is below Vppy x). 4.10.3) WP#=V 1 for Block Unlocking WP#=V ,, unlocks all lockable blocks. These blocks can now be programmed or erased. WP# controls 2 boot blocks locking and Vpp provides protection against spurious writes. Table 6 defines the write protection methods. Table 6. Write Protection Alternatives Operation Vpp RP# WP# Effect Vin xX x All Blocks Locked. Block Erase Vin X All Blocks Locked. or >VppLK Vun xX All Blocks Unlocked. Word/Byte Write Vin Vin 2 Boot Blocks Locked. Vin All Blocks Unlocked. Rev. 1.0SHARP LHF80V01 15 Table 7. Status Register Definition WwsMS | _ ESS ES WBWS VPPS WBWSS DPS R 7 6 5 4 3 2 1 0 SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = WORD/BYTE WRITE STATUS (WBWS) 1 = Error in Word/Byte Write 0 = Successful Word/Byte Write SR.3 = Vpp STATUS (VPPS) 1 = Vpp Low Detect, Operation Abort SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = WP# or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTES: Check RY/BY# or SR.7 to determine block erase or word/byte write completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of Vpp level. The WSM interrogates and indicates the Vpp level only after Block Erase or Word/Byte Write command sequences. SR.3 is not guaranteed to reports accurate feedback only when Vpp#V ppHt2- The WSM interrogates the WP# and RP# only after Block Erase or Word/Byte Write command sequences. It informs the system, depending on the attempted operation, if the WP# is not Vy RP# is not Vig. SR.O is reserved for future use and should be masked out when polling the status register. Rev. 1.0SHARP LHF80V01 16 Com) ot Command Comment ration Data=20H Write 20H, Write Erase Setuy rite 20H 8 weweuP Addr=Within Block to be Etased Block Address v . Erase Data=DOH Write a. 5 Confirm Addr=Withia Block to be Erased Write DOH, Block Address Read Status Register Data Read Status Regist _ Suspend Block Check SR.7 eee i Standby 1=WSM Ready oor 0=WSM Busy Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode. Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Bus . Command Comments Data(See Above) Operation Check SR.3 Standby ee 1=Vpp Error Detect VppR: Erre Check SR.1 Standby 1=Device Protect Detect Check SR.4.5 Standby . Both 1=Command Sequence Error Check SR.5 Standby ee " 1=Block Erase Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Command Sequence Error Block Erase Error Block Erase Successful Figure 5. Automated Block Erase Flowchart Rev. 1.0SHARP LHF80V01 17 Write 40H or 10H. Address v White Word/Byte Data and Address Read Status Register Suspend Word/Byte Write Loop > te Word/Byte Write Full Status Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Word/Byte Write Error Word/Byte Write Successful Bi " Command Comments Operation Write . Data=40H or 10H Setup Word/Byte Write | 4 turat ocation to Be Written Write | Data=Data to Be Written " Word/Byte Write | addr-Location to Be Written Read Status Register Data Check SR.7 Standby 1=WSM Ready 0=WSM Busy Repeat for subsequent byte writes. SR full stats check can be done after each Word/Byte write, or after a sequence of Word/Byte writes. Write FFH after the last Word/Byte write operation to place device in tead array mode. Bus Cc id C it: Operation omman omments SR.3 Standby Check l=Vpp Error Detect Check SR.1 Standby ee . t=Device Protect Detect 4 Standby Check SR. | 1=Data Write Error SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Word/Byte Write Flowchart Rev. 1.0Read Read Array Data No Yes Word/Byte Write Loop Bi Operation Command Comments . Erase Data=BOH Write Suspend Addr=X Status Register Data Read Addr=X Check SR.7 Standby 1=WSM Ready 0=WSM Busy Check SR.6 Standby 1=Block Erase Suspended 0=Block Erase Completed . Erase Data=DOH Write Resume Addr=X Block Erase Completed Word/Byte Write | Write DOH | v (Bost Erase Resumed ) | Read Array Data | v Write FFH | Figure 7. Block Erase Suspend/Resume Flowchart Rev. 1.0SHARP Bus Command Comments Operation Write Word/Byte Write Data=BOH Write BOH Suspend Addr=X v Read a = Data Read 7 Status Register Check SR.7 Standby 1=WSM Ready Q=WSM Busy Check SR.2 Standby 1=Word/Byte Write Suspended 0=Word/B yte Write Completed Write Read Array Daa=FFH Addr=X Word/Byte Write Completed Read Read Array locations other than that being written. i Data=DOH Write Word/Byte Write a= White FFH Resume Addr=X | Write DOH | | Write FFH | Word/Byte Write Read Array Data Resumed Figure 8. Word/Byte Write Suspend/Resume Flowchart Rev. 1.0SHARP LHF80V01 20 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the systems READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY#, Block Erase and Word/Byte Write Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase and word/byte write completion. It transitions low after block erase or word/byte write commands and returns to High Z when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also High Z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 pF ceramic capacitor connected between its Vcc and GND and between its Vpp and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 wF electrolytic capacitor should be placed at the arrays power supply connection between Vc, and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4. Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the Vpp Power supply trace. The Vpp pin supplies the memory cell current for word/byte writing and block erasing. Use similar trace widths and layout considerations given to the V-- power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots. Rev. 1.0SHARP LHF80V01 21 5.5 Vcc, Vpp, RP# Transitions Block erase and word/byte write are not guaranteed if Vpp falls outside of a valid Vppy)/> range, Vcc falls outside of a valid 2.7V-3.6V range, or RP##V),; or Vij. If Vpp error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to Vy during block erase or word/byte write, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to Vj, clear the status register. The CUI latches commands issued by system software and is not altered by Vpp or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Voc transitions below V; xo. After block erase or word/byte write, even after Vpp transitions down to Vppy x, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure or word/byte writing during power transitions. Upon power-up, the device is indifferent as to which power supply (Vpp or Voc) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for Vcc voltages above V, x9 when Vpp is active. Since both WE# and CE# must be low for a command write, driving either to Vy, will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. WP# provide additional protection from inadvertent code or data alteration. The device is disabled while RP#=Vy,_ regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memorys nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering RP# to Vj, standby or sleep modes. If access is again needed, the devices can be read following the tpyoy and tpywr Wake-up cycles required after RP# is first raised to Vp. See AC Characteristics Read Only and Write Operations and Figures 11, 12, 13 and 14 for more information. Rev. 1.0SHARP LHF80V01 22 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Rating. Operating Temperature During Read, Block Erase and st Word/Byte Write... cee 0C to +70C) Temperature under Bias................06 -10C to +80C Storage Temperature .........0.0.0. eee -65C to +125C Voltage On Any Pin (except Voc, Vpp, and RP#) ........... -0.5V to +7.0V) Voc Supply Voltage... -0.2V to +7.0V2) Vpp Update Voltage during Block Erase and Word/Byte Write.........-0.2V to +14.0V@23) RP# Voltage .....ccccccecccseeeesseeteeetees -0.5V to +14.0V(2.3) Output Short Circuit Current.........:ceccseeceseeeees 100mA 6.2 Operating Conditions *WARNING: Stressing the device beyond the Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Vcc and Vpp pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and Voc is Vect0.5V which, during transitions, may overshoot to Voct2.0V for periods <20ns. 3. Maximum DC voltage on Vpp and RP# may overshoot to +14.0V for periods <20ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. Temperature and V.- Operating Conditions Symbol Parameter Min. Max. Unit Test Condition Ta Operating Temperature 0 +70 C Ambient Temperature Vcc Vcc Supply Voltage (2.7V-3.6V) 2.7 3.6 Vv 6.2.1 CAPACITANCE] T,=+25C, f=IMHz Symbol Parameter Typ. Max. Unit Condition Cin Input Capacitance 7 10 pF Vin=0.0V Cour Output Capacitance 9 12 pF Vout=0.0V NOTE: 1. Sampled, not 100% tested. Rev. 1.0SHARP LHF80VO1 23 6.2.2, AC INPUT/OUTPUT TEST CONDITIONS 27 fs INPUT 1.35 <j TEST POINTS _> _ 1.35 OUTPUT 0.0 SS AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns. Figure 9. Transient Input/Output Reference Waveform for Vo=2.7V-3.6V Test Configuration Capacitance Loading Value Test Configuration C, (pF) Voc=2.7V-3.6V 30 DEVICE UNDER TEST Cy Includes Jig Cc. Capacitance OUT Figure 10. Transient Equivalent Testing Load Circuit Rev. 1.01SHARP LHF80V01 24 6.2.3. DC CHARACTERISTICS DC Characteristics Vec=2.7V-3.6V Test Sym. Parameter Notes Typ. Max. Unit Conditions ly Input Load Current 1 +05 uA Vec=VccMax. lo Output Leakage Current 1 Vec=VccMax. +0.5 HA Vout=Ycc or GND lecs Vcc Standby Current 1,3,6, CMOS Inputs CE#=RP#=Vc#0.2V 1,3,6 TTL Inputs 0.2 2 Voc=VccMax. CE#=RP#=V yy lecp Vcc Deep Power-Down Current 1,10 5 10 uA Revie ouT(RY/BY#)=OmA Iecr Voc Read Current 1,5,6 CMOS Inputs 15 25 Vec=VccMax., CE#=GND f=5MHz. Ipyp=OmA TTL Inputs f=5MHz., [oy 7=0mA Iccw | Voc Word/Byte Write Current 1,7 5 17 mA | Vpp=2.7V-3.6V 5 12 mA | Vpp=11.4V-12.6V lece Vcc Block Erase Current 1,7 4 17 mA | Vpp=2.7V-3.6V 4 12 mA | Vpp=11.4V-12.6V Iccws | Vcc Word/Byte Write or 1,2 _ Icces _| Block Erase Suspend Current 6 mA | CEHEV iy Ipps Vpp Standby or Read Current 1 +2 +15 uA | VppSVoc Ippp Vpp Deep Power-Down Current 1 0.1 5 pA RP#=GND+0.2V Ippw Vpp Word/Byte Write Current 1,7 12 40 mA | Vpp=2.7V-3.6V 30 mA | Vpp=11.4V-12.6V IppR Vpp Block Erase Current 1,7 8 25 mA | Vpp=2.7V-3.6V ; 20 mA | Vpp=11.4V-12.6V Ippws Vpp Word/Byte Write or 1 _ IppEs Block Erase Suspend Current 10 200 pA | Ver=Vepni2 Rev. 1.0SHARP LHF80V01 25 DC Characteristics (Continued) Vec=2.7V-3.6V Sym. Parameter Notes Min. Max. Unit Test Conditions Vi Input Low Voltage 7 -0.5 0.8 Vv Vin Input High Voitage 7 20 Vec V +0.5 Vor Output Low Voltage 37 0 4 Vv Vec=Vcc Min. . IQ =2. (TTL) . Ioq=-1.5mA Vor Output High Voltage 3,7 0.85 V Voc=Vec Min. (CMOS) Vec Igq=-2-0mA Vec Vv Vec=Vcc Min. -0.4 Top=-100NA Vppix | Vpp Lockout Voltage during Normal 47 Ls Vv Operations Vppy1 | Vpp Voltage during Word/Byte Write 27 36 Vv or Block Erase Operations Vppy2 | Vpp Voltage during Word/Byte Write or Block Erase Operations i4 12.6 v ViKxo Voc Lockout Voltage 2.0 Vv Vuy RP# Unlock Voltage 8,9 11.4 12.6 Vv Unavailable WP# NOTES: i. All currents are in RMS unless otherwise noted. Typical values at nominal Vcc voltage and T,y=+25C. 2. Iecws and Iecgs are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the devices current draw is the sum of Icews or Iecgs and Iecp oF Iecw. respectively. 3. Includes RY/BY#. 4. Block erases and word/byte writes are inhibited when VppS$Vpp; x. and not guaranteed in the range between Vpp; ,.(max.) and Vppy)(min.), between Vppy,(max.) and Vppy.(min.), between Vppy(max.) and Vppy,(min.), and above Vppy3(max.). 5. Automatic Power Savings (APS) reduces typical Iccp to 3mA at 2.7V Vog in static operation. 6. CMOS inputs are either V-+0.2V or GND+0.2V. TTL inputs are either Vy or Vy). 7. Sampled, not 100% tested. 8. Boot block erases and word/byte writes are inhibited when the corresponding RP#=V},, and WP#=V,, . Block erase and word/byte write operations are not guaranteed with V),,<RP#<V,,,, and should not be attempted. 9. RP# connection to a Vy; supply is allowed for a maximum cumulative period of 80 hours. 10. BY TE# input level is Veo+0.2V in word mode or GND+0.2V in byte mode. WP# input level is Vao+0.2V or GND+0.2V. Rev. 1.01SHARP LHF80V01 26 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS() Vec=2.7V-3.6V, T,=0C to +70C Sym. Parameter Notes Min. Max Unit tavay __| Read Cycle Time 90 ns tavov _| Address to Output Delay 90 ns teLov CE# to Output Delay 2 90 ns tppyov _| RP# High to Output Delay 600 ns tgtov__| OE# to Output Delay 2 50 ns te_ox | CE# to Output in Low Z 3 0 ns tepoz CE# High to Output in High Z 3 55 ns tsLox OE# to Output in Low Z 3 0 ns tcHoz _| OE# High to Output in High Z 3 20 ns ton Output Hold from Address, CE# or OE# Change, Whichever 3 0 ns Occurs First tevov BYTE# and A_, to Output Delay 3 90 ns teLoz BYTE# Low to Output in High Z 3 30 ns teLEV CE# to BYTE# High or Low 3,4 5 ns NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. OE# may be delayed up to thy gy-tgigv after the falling edge of CE# without impact on tgy gy- 2. 3. Sampled, not 100% tested. 4, If BY TE# transfer during reading cycle, exist the regulations separately. Rev. 1.01SHARP LHF80V01 27 Device ; Vv Standby Address Selection Data Valid 1H Lb ; rons XX KX OX Address Stable XXX KK Vit h ae tavav Vin ; CEE) fo | \ New = \. Vi K eg HOZ Vin ; vw | \ Iho) \ Vi. h {GHOZ Vin wee) / 1 (GLOV Vit teLov > \ TGLQX| tox tELOx Mig HIGH Z V Wk uicHz DATA(D/Q) # , (DQo-DQi5) { Valid Ourput yy You le tavov | Vec / \ le tpHoV. Vin RP#(P) Vi \ Figure 11. AC Waveform for Read Operations Rev. 1.0SHARP LHF80VO1 28 Device ; Standby Address Selection Data Valid V; ADDRESSES(A) Address Stable Vn. Vin CE#(E) ViL Vin OE#(G) Vit V; BYTE#(F) VIL Vou DATA(DIQ) (DQo-DQ7) Voi Data Output Vou DATA(D/Q) (DQs-DQi5) Vou Figure 12. BYTE# timing Waveform Rev. 1.0SHARP LHF80V01 29 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS() Vcc=2.7V-3.6V, T,=0C to +70C Sym. Parameter Notes Min. Max Unit tavay | Write Cycle Time 90 ns tpuwi _| RP# High Recovery to WE# Going Low 2 1 us terwi | CE# Setup to WE# Going Low 10 ns twowH | WE# Pulse Width 50 ns tprpwe_ | RP# Vi Setup to WE# Going High 2 100 ns touwH | WP# Vy Setup to WE# Going High 2 100 ns typwH | Vpp Setup to WE# Going High 2 100 ns tavwy___| Address Setup to WE# Going High 3 50 ns tovwn ___| Data Setup to WE# Going High 3 50 ns twHpx _| Data Hold from WE# High 0 ns twHax | Address Hold from WE# High 0 ns twHen | CE# Hold from WE# High 10 ns twiw i | WE# Pulse Width High 30 ns twure | WE# High to RY/BY# Going Low 100 ns twuG_ | Write Recovery before Read 0 ns tovvL _| Vpp Hold from Valid SRD, RY/BY# High Z 2,4 0 ns tovey | RP# Vy Hold from Valid SRD, RY/BY# High Z 2,4 0 ns tovs. WP# Vi Hold from Valid SRD, RY/BY# High Z 2,4 0 ns tevwy | BYTE# Setup to WE# Going High 5 50 ns twury | BYTE# Hold from WE# High 5 90 ns 2 3. 4. Vpp should be held at Vppy1/. (and if necessary RP# should be held at Vip) until determination of block erase or NOTES: 1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. . Sampled, not 100% tested. Refer to Table 4 for valid Aj, and D,, for block erase or word/byte write. word/byte write success (SR.1/3/4/5=0). If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.01SHARP LHF80V01 30 a. 47. -4 4 SE rooresses "WUE AROOOTRENOOROOOCE TROOOOOON t tavav TAVWH WHAX Vin CE#(E) I\ / \ Vit Lf a text +h 'WHEH twHGL Vin OE#(G) / \ / VIL J WH, twHovi234 Vin 1 OF L WEa(W) / \ \ | Vu. | twewu 7 QywH Vin ou. WHDX High Z i ann (Ox Gs) ) Vi b pawL levwH twHEy Vin lb L BYTE#(E) Mt Mt VL t HighZ A twure k RY/BY#(R) | 1 Vor i {sHWH VSL Vin WPA(S) i 4 Vi VPH Vu cereeebeeeeeeeee] RPA#(P) Vin + 4 Vit J {vpw tow ver ome UU 1. Vec power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Figure 13. AC Waveform for WE#-Controlled Write Operations Rey. 1.0SHARP LHF80V01 31 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES() Voc=2.7V-3.6V, T,=0C to +70C Sym. Parameter Notes Min. Max. Unit tavay | Write Cycle Time 90 ns tpHEL RP# High Recovery to CE# Going Low 2 1 ps twreL WE# Setup to CE# Going Low 0 ns teLEH CE# Pulse Width 50 ns tpuneH | RP# Viy Setup to CE# Going High 2 100 os toHEH WP# Vj, Setup to CE# Going High 2 100 ns typEH Vpp Setup to CE# Going High 2 100 ns tAVEH Address Setup to CE# Going High 3 50 ns toven Data Setup to CE# Going High 3 50 ns teypx Data Hold from CE# High 0 ns teyax | Address Hold from CE# High 0 ns teywo | WE# Hold from CE# High 0 ns teHEL CE# Pulse Width High 30 ns teuR CE# High to RY/B Y# Going Low 100 ns teHoL Write Recovery before Read 0 ns tovv_ _| Vpp Hold from Valid SRD, RY/BY# High Z 2,4 0 ns toveH RP# Vii Hold from Valid SRD, RY/BY# High Z 2,4 0 ns tovsr WP# Vj}; Hold from Valid SRD, RY/BY# High Z 2,4 0 ns tevEH BYTE# Setup to CE# Going High 5 30 ns teHFV BYTE# Hold from CE# High 5 90 ns NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A; and Dyy for block erase or word/byte write. 4 . Vpp should be held at Vppyy/. (and if necessary RP# should be held at Vyy) until determination of block erase or word/byte write success (SR.1/3/4/5=0). 5. If BYTE# switch during reading cycle, exist the regulations separately. Rev. 1.01SHARP LHF80VOl 32 NOTES: RAuw pwn _. H_/~-. 4 SH SS Vin ADDRESSES(A) AN An Vit tavav (AVEH Vin CE#(E) Vit Vin OE#G) Vi Vin WE#(W) Vit Vin DATA(/Q) Van Vin BYTEHP) Vit High Z RY/BY#) Vou Vin WP#(S) Vun RPH(P) Vin Vit VppH?,1 Vpp(V) VppLiK Vi . Ver power-up and standby. . Write block erase or word/byte write setup. . Write block erase confirm or valid address and data. . Automated erase or program delay. . Read status register data. . Write Read Array command. Figure 14. AC Waveform for CE#-Controlled Write Operations Rev. 1.0SHARP LHF80V01 33 6.2.7 RESET OPERATIONS HighZ RY/BY#(R) Vor Vin RP#(P) vu kf tpLPH (A)Reset During Read Array Mode High Z RY/BY#(R) VoL PLRz Vig RPA(P) \ Vit _ I* tPLPH (B)Resct During Block Erase or Word/Byte Write 27V fb Vcc Vit t*- ovPH Vin lr RPA(P) L Va 4 (C)RP# rising Timing Figure 15. AC Waveform for Reset Operation Reset AC Specifications Vec=2.7V-3.6V Sym. Parameter Notes Min. Max. Unit t RP# Pulse Low Time 100 ns PLPH (If RP# is tied to Vcc, this specification is not applicable) tptRz RP# Low to Reset during Block Erase or Word/Byte Write 1,2 22 us boven Vor 2.7V to RP# High 3 100 ns NOTES: 2. A reset time, tpyay, is required from the later of RY/BY# going High Z or RP# going high until outputs are valid. has been in stable there. 1. If RP# is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns. 3. When the device power-up, holding RP# low minimum 100ns is required after Vcc has been in predefined range and also Rev. 1.0SHARP LHF80V01 34 6.2.8 BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCES) Vec=2.7V-3.6V, Ta=0C to +70C Sym. Parameter Notes | Typ.()) Max. Typ.) Max. Unit 'wHQVI Word/Byte Write Time | 32K word Block 2 44.6 12.6 us teHevi 4K word Block 2 45.9 24.5 us Block Write Time 32K word Block 2,4 1.46 0.42 s 4K word Block 2,4 0.19 0.11 s 'WHOV? | Block Erase Time 32K word Block 2 1.14 0.51 s teHov2 4K word Block 2 0.38 0.31 s twyrz |Word/Byte Write Suspend Latency Time to 7 8 6 7 us teurzi |Read WHRZ2_|Erase Suspend Latency Time to Read 18 22 il 14 Us tenRrz2 NOTES: 1. Typical values measured at T,=+25C and nominal voltages. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. All values are in word mode (BYTE#=V)j;,). At byte mode (BYTE#=V), ), those values are double. Rev. 1.0SHARP LHF80V01 35 7 Package and packing specification | 1. Package Outline Specification Refer to drawing No. AA1142 2. Markings 2-1. Marking contents (1) Product name : LH28F800BVE-TTL9IYO (2) Company name : SHARP (3) Date code (Example) Y Y WW xx xX Indicates the product was manufactured in the WWth week of 19YY. L_. Denotes the production ref.code (1~3) Denotes the production week. (01,02,03, > s+: 52,53) Denotes the production year. (Lower two digits of the year.) (4) The marking of JAPAN indicates the country of origin. 22, Marking layout Refer drawing No. AA114 2 (This layout does not define the dimensions of marking character and marking position.) 3, Packing Specification (Dry packing for surface mount packages) Dry packing is used for the purpose of maintaining IC quality after mount ing packages on the PCB (Printed Circuit Board). When the epoxy resin which is used for plastic packages is stored at high humidity, it may absorb 0.15% or more of its weight in moisture. If the surface mount type package for a relatively large chip absorbs a large amount of moisture between the epoxy resin and insert material (e.g. chip, lead frame) this moisture may suddenly vaporize into steam when the entire package is heated during the soldering process (e.g. VPS). This causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. This dry packing is designed to prevent the above problem from occurring in surface mount packages. 31.,. Packing Materials Material Name Material Specificaiton Purpose Tray Conductive plastic (50devices/tray)| Fixing of device Upper cover tray Conductive plastic (Itray/case) | Fixing of device Laminated aluminum bag Aluminum polyethylene (1bag/case) Drying of device Desiccant Silica gel Drying of device P P band Polypropylene (3pces/case) Fixing of tray Inner case Card board (500device/case) | Packaging of device Label Paper Indicates part number, quantity| and date of manufacture Outer case Card board Quter packing of tray (Devices shall be placed into a tray in the same direction.)SHARP LHF80VOl1 36 32, Outline dimension of tray Refer to attached drawing 4, Storage and Opening of Dry Packing 41, Store under conditions shown below before opening the dry packing (1) Temperature range : 5~40 (2) Humidity : 80% RH or less 42, Notes on opening the dry packing (1) Before opening the dry packing, prepare a working table which is grounded against ESD and use a grounding strap. (2) The tray has been treated to be conductive or anti-static. If the device is transferred to another tray, use a equivalent tray. 43. Storage after opening the dry packing Perform the following to prevent absorption of moisture after opening. (1) After opening the dry packing, store the ICs in an environment with a temperature of 5~25 and a relative humidity of 60% or less and mount ICs within 72 hours after opening dry packing. 44., Baking (drying) before mounting (1) Baking is necessary (A) If the humidity indicator in the desiccant becomes pink (B) If the procedure in section 4~3 could not be performed (2) Recommended baking conditions If the above conditions (A) and (B) are applicable, bake it before mounting. The recommended conditions are 16~24 hours at 120. Heat resistance tray is used for shipping tray. 5. Surface Mount Conditions Please perform the following conditions when mounting ICs not to deteriorate IC quality. 5 1 Soldering conditions(The following conditions are valid only for one time soldering.) Mounting Method | Temperature and Duration Measurement Point Reflow soldering | Peak temperature of 230C or less, IC package (air) duration of less than 15 seconds. surface 200C or over,duration of less than 40 seconds. Temperature increase rate of 1~4C/second Manual soldering | 260C or less, duration of less IC outer lead (soldering iron) | than 10 seconds. surface 5-2. Conditions for removal of residual flux (1) Ultrasonic washing power : 25 Watts/liter or less (2) Washing time : Total 1 minute maximum (3) Solvent temperature > 15~40CSHARP HF80V L Ol 31 48-0. 2 +0. 08 O P-0. STYP. ZN o. 1 LH28F800BVE-TTL30 a SHARP -= + * o JAPAN S YYWW Xxx = 24 - 20. 0 +0. 3 nN + = s 18. 4 +0. 2 19) | % 3) 3 ol * nN o DS I ) 1 Y PXG. BASE PLANE a 4 3 19. 0 +0. 1 + SEE DETAIL A 3 DETAIL A PKG. BASE PLANE BM D-RELE | TIN-LEAD (HBS 75 AF Sy TATE 10) ESET NAME | TSOP48-P-1220 | LEAD FINISH | PLATING | NOTE Plastic body dimensions do not include burr BIZ of resin. DRAWING NO. AAL142 UNIT mm38 LHF8OVOl1 SHARP 315.8 33 21.040. 3*9=279, 010.5 j P- OO & p | SS re re re Ie tS. ap ees ier ik (es ree tease ot co) IL IFS Ltr 1S eS tee & { ota oy eee eer (err es = =. i. FA Oo Ly 79 3 \ = = = ad o ro o IC TT yee eer a| to PIE yt CS easy Rea TEST x a = a 2 a a zz a A es ty Mm Ww try = xi . my HP & . to ele ete ek Lie = S yoo 7FY Fra fer) Lt. iT TEST Hh tet est Tie} wn T =. = a 2 = i. =a = = =. ow & a . r ee ee if f f 1 a BS) eS tie 3} == EE} ES} (3) ; O = = = = pa =. pa a aa a a. = Ra & apr Qe n Ss - N \50 $4 \4 aa\ mo om a | Oo a uy | tf ji oe} | 200 A, S Ww = tH} al = us| &SHARP LHF80VO0l1 39 (Supplementary data) Recommended mount ing LHF8OVOl1 conditions for two time reflow soldering . Product name(Package) LH28F800BVE-TTL90_ (TSOP48-P-1220) Packing specification Tray (Dry packing) Mounting method Reflow soldering (Air) Reflow soldering conditions Peak temperature of 230C or less. 200C or over, duration of less than 40 seconds. Preheat temperature of 125~150C, duration of less than 180 seconds. Temperature increase rate of 1~4C/second. Measurement point IC package surface Storage conditions After opening the dry packing, store the ICs in an environment with a temperature of 5~25C and a relative humidity of 60% or less. If doing reflow soldering twice,do the first reflow soldering within 72 hours after opening dry packing and do the second reflow soldering within 72 hours after the first reflow soldering. Note If the above storage conditions are not applicable, bake it before reflow soldering. The recommended conditions are 16~24 hours at 120C. (Heat resistance tray is used for shipping tray.) Recommended Reflaw Soldering (Air) Temperature Profile ey Package surface temperature Preheating Peak temperature i 230 MAX. (Less than 180 seconds): 200C (Less than 40 seconds) Temperature increase rate 1~4C / second Time __ (NO. 980803-X14)SHARP LHF80V01 40 Flash memory LHF8OVXX family Data Protection (TSOP package, CSP package) Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block By setting a WP# to low, only the boot block can be protected against overwriting. Parameter and main blocks cannot be locked. System program, etc., can be locked by storing them in the boot block. When a high voltage is applied to RP#, overwrite operation is enabled for all blocks. For further information on controlling of WP# and RP#, refer to the specification. (See chapter 4.10) 2) Data protection through Vpp When the level of Vpp is lower than VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the specification. (See chapter 4.10 and 6.2.3.) 3) Data protection through RP# When the RP# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting al! blocks. For the details of RP# control, refer to the specification. (See chapter 5.6 and 6. 2. 7. ) 4) Noise rejection of WE# Consider noise rejection of WE4 in order to prevent false write command input. Rev 1.01LH28F800B VE-TTL90, FLASH MEMORY, FLASH, NON-VOLATILE MEMORY, FLASH ROM READ ONLY MEMORY, ETOX, LH28F800BVE-TTL90, Boot Block