CM1215-02SO - ON Semiconductor

July, 2011 − Rev. 3

1Publication Order Number:

CM1215/D

CM1215

1, 2 and 4-Channel

Low Capacitance

ESD Arrays

Product Description

The CM1215 family of diode arrays provides ESD protection for

electronic components or sub−systems requiring minimal capacitive

loading. These devices are ideal for protecting systems with high data

and clock rates or for circuits requiring low capacitive loading. Each

ESD channel consists of a pair of diodes in series which steer the

positive or negative ESD current pulse to either the positive (VP) or

negative (VN) supply rail. The CM1215 protects against ESD pulses

up to ±15 kV per the IEC 61000−4−2 standard.

This device is particularly well−suited for protecting systems using

high−speed ports such as USB2.0, IEEE1394 (Firewire®, iLinkt),

Serial ATA, DVI, HDMI and corresponding ports in removable

storage, digital camcorders, DVD−RW drives and other applications

where extremely low loading capacitance with ESD protection are

required in a small package footprint.

Features

•One, two, and four channels of ESD Protection

•Provides ±15 kV ESD Protection on Each Channel Per the IEC

61000−4−2 ESD Requirements

•Channel Loading Capacitance of 1.6 pF Typical

•Channel I/O to GND Capacitance Difference of 0.04 pF Typical

•Mutual Capacitance of 0.13 pF Typical

•Minimal Capacitance Change with Temperature and Voltage

•Each I/O Pin Can Withstand Over 1000 ESD Strikes

•SOT Packages

•These Devices are Pb−Free and are RoHS Compliant

Applications

•IEEE1394 Firewire® Ports at 400 Mbps / 800 Mbps

•DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

LCD Displays

•Serial ATA Ports in Desktop PCs and Hard Disk Drives

•PCI Express Ports

•General Purpose High−Speed Data Line ESD Protection

SOT23−5

(Pb−Free)

MARKING DIAGRAM

Device Package Shipping†

ORDERING INFORMATION

SOT23−3

SO SUFFIX

CASE 419AH

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CM1215−01SO SOT23−3

(Pb−Free)

3000/Tape & Reel

SOT143

(Pb−Free)

3000/Tape & ReelCM1215−02SR

3000/Tape & ReelCM1215−02SO

SOT23−6

(Pb−Free)

3000/Tape & ReelCM1215−04SO

E151 MG

XXXX = Specific Device Code

M = Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

SOT23−6

SO SUFFIX

CASE 527AJ

SOT23−5

SO SUFFIX

CASE 527AH

SOT143

SR SUFFIX

CASE 527AF

E153 MG

E152 MG

E154 MG

CM1215

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CH4 VP

CH3

CH1 CH2

CM1215−04SO

CH1

CM1215−02SO

CM1215−02SR

CH2

BLOCK DIAGRAM

CH1

CM1215−01SO

PACKAGE / PINOUT DIAGRAMS

Top View

CH1

E151

3−Pin SOT23−3

Top View

CH1

E152

4−Pin SOT143

CH2

Top View

CH1

E153

5−Lead SOT23−5

CH2

NC 1

Top View

CH2

E154

6−Pin SOT23−6

CH3

CH1 1

6 CH4

Table 1. PACKAGE PIN DESCRIPTIONS

Pin Name

SOT23−3 SOT143 SOT23−5 SOT23−6

Type Description

Pin No. Pin No. Pin No. Pin No.

CH1 1 2 3 1 I/O ESD Channel

VN3 1 2 2 GND Negative voltage supply rail

CH2 −3 4 3 I/O ESD Channel

CH3 − − − 4 I/O ESD Channel

VP2 4 5 5 PWR Positive voltage supply rail

CH4 − − − 6 I/O ESD Channel

N/C − − 1− − No Connection

CM1215

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SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Supply Voltage (VP−VN) 6 V

Diode Forward DC Current (Note 1) 20 mA

DC Voltage at any Channel Input (VN−0.5) to (VP+0.5) V

Operating Temperature Range

Ambient −40 to +85 °C

Junction −40 to +125 °C

Storage Temperature Range −40 to +150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 3. STANDARD OPERATING CONDITIONS

Parameter Rating Units

Operating Temperature Range –40 to +85 °C

Package Power Rating

SOT23−3 Package (CM1215−01SO)

SOT143 Package (CM1215−02SR)

SOT23−5 Package (CM1215−02SO)

SOT23−6 Package (CM1215−04SO)

225

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)

Symbol Parameter Conditions Min Typ Max Unit

VPOperating Supply Voltage (VP−VN) 3.3 5.5 V

IPOperating Supply Current (VP−VN) = 3.3 V 8mA

VFDiode Forward Voltage

Top Diode

Bottom Diode

IF = 20 mA; TA = 25°C

0.6

0.8

0.95

ILEAK Channel Leakage Current TA = 25°C; VP = 5 V, VN = 0 V ±0.1 ±1.0 mA

CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V,

VN = 0 V, VIN = 1.65V;

1.6 2.0 pF

ΔCIN Channel I/O to GND Capacitance Difference 0.04 pF

CMUTUAL Mutual Capacitance (VP−VN) = 3.3 V 0.13 pF

VESD ESD Protection

Peak Discharge Voltage at any channel input,

in system, contact discharge

per IEC 61000−4−2 standard

TA = 25°C

(Notes 2 and 3)

±15

VCL Channel Clamp Voltage

Positive Transients

Negative Transients

IPP = 1 A, tP = 8/20 mS;

TA = 25°C; VP+1.5

VN−1.5

RDYN Dynamic Resistance

Positive transients

Negative transients

IPP = 1 A, tP = 8/20 mS;

TA = 25°C; 0.4

0.4

1. All parameters specified at TA = −40°C to +85°C unless otherwise noted.

2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.

3. From I/O pins to VP or VN only. VP bypassed to VN with low ESR 0.2 mF ceramic capacitor.

CM1215

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PERFORMANCE INFORMATION

Input Channel Capacitance Performance Curves

Figure 1. Typical Variation of CIN vs. VIN

(f = 1 MHz, VP= 3.3 V, VN = 0 V, 0.1 mF Chip Capacitor between VP and VN, TA =

255C)

Figure 2. Typical Filter Performance (Nominal Conditions unless

Specified Otherwise, 50 Ohm Environment)

CM1215

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APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking

an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on

the line being protected is:

VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt

where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be

approximated by d(ESD)/dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V

increment in VCL!

Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.

Figure 3. Application of Positive ESD Pulse between Input Channel and Ground

POSITIVE SUPPLY

PATH OF ESD CURRENT

PULSE (IESD)

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

CHANNEL

IMPUT

LINE BEING

PROTECTED

ONE

CHANNEL

GROUND RAIL

CHASSI‘S GROUND

CM1215

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PACKAGE DIMENSIONS

SOT−23 3−Lead (TO−236AA)

CASE 419AH−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH

THICKNESS. MINIMUM LEAD THICKNESS IS THE

MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR GATE BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT

EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE

DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE IN-

DICATED ZONE.

DETAIL Z

E1 E

DETAIL Z

DIM

MIN MAX

MILLIMETERS

0.75 1.17

A1 0.05 0.15

b0.30 0.50

c0.08 0.20

D2.80 3.05

E1 1.20 1.40

L0.40 0.60

2.10 2.64

M°°

0.95 BSC

L2 0.25 BSC

2.74

0.95

PITCH

DIMENSIONS: MILLIMETERS

0.82

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

0.56

CSEATING

PLANE

0.05

CSEATING

PLANE

GAUGE

PLANE

CM1215

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PACKAGE DIMENSIONS

SOT−143, 4 Lead

CASE 527AF−01

ISSUE A

E1 E

e1 b

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC TO-253.

SYMBOL

MIN NOM MAX

0° 8°

0.05

0.75

0.30

0.76

0.40

0.08

2.80

2.10

1.92 BSC

0.54 REF

1.22

0.15

1.07

0.50

0.89

0.60

0.20

3.04

2.64

0.50

0.90

2.90

e1 0.20 BSC

E1 1.20 1.401.30

L2 0.25

0.80

CM1215

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PACKAGE DIMENSIONS

SOT−23, 5 Lead

CASE 527AH−01

ISSUE O

TOP VIEW

SIDE VIEW END VIEW

E1 E

PIN #1 IDENTIFICATION

L1 L

Notes:

(1) All dimensions in millimeters. Angles in degrees.

(2) Complies with JEDEC standard MO-178.

θ2

θ1

SYMBOL MIN NOM MAX

θ2 5° 15°

0.00

0.90

0.30

0.08

2.90 BSC

1.60 BSC

0.45

1.45

0.15

1.30

0.50

0.22

0.25 REF

1.15

2.80 BSC

L1 0.60 REF

0.30 0.60

0.95 BSC

0.90

10°

θ1 5° 15°10°

θ0° 8°4°

CM1215

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PACKAGE DIMENSIONS

SOT−23, 6 Lead

CASE 527AJ−01

ISSUE A

DETAIL A

DIM MIN MAX

MILLIMETERS

A1 0.00 0.15

A2 0.90 1.30

b0.20 0.50

c0.08 0.26

D2.70 3.00

E2.50 3.10

E1 1.30 1.80

e0.95 BSC

L2 0.25 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DATUM C IS THE SEATING PLANE.

0.20 0.60

A--- 1.45

SIDE VIEW

TOP VIEW

END VIEW

0.20

SEATING

PLANE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

3.30

0.95

0.85

DIMENSIONS: MILLIMETERS

0.56

PITCH

RECOMMENDED

0.10 C

SEATING

PLANE

GAGE

PLANE

FireWire is a registered trademark of Apple Computer, Inc.

iLink is a trademark of S. J. Electro Systems, Inc.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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CM1215/D

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